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Commit | Line | Data |
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2488514c RH |
1 | /* |
2 | * Calxeda Highbank SoC emulation | |
3 | * | |
4 | * Copyright (c) 2010-2012 Calxeda | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | */ | |
19 | ||
12b16722 | 20 | #include "qemu/osdep.h" |
a8d25326 | 21 | #include "qemu-common.h" |
da34e65c | 22 | #include "qapi/error.h" |
83c9f4ca | 23 | #include "hw/sysbus.h" |
d6454270 | 24 | #include "migration/vmstate.h" |
12ec8bd5 | 25 | #include "hw/arm/boot.h" |
83c9f4ca | 26 | #include "hw/loader.h" |
1422e32d | 27 | #include "net/net.h" |
40340e5f | 28 | #include "sysemu/kvm.h" |
54d31236 | 29 | #include "sysemu/runstate.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
83c9f4ca | 31 | #include "hw/boards.h" |
022c62cb | 32 | #include "exec/address-spaces.h" |
f282f296 | 33 | #include "qemu/error-report.h" |
f0d1d2c1 | 34 | #include "hw/char/pl011.h" |
c2de81e2 PMD |
35 | #include "hw/ide/ahci.h" |
36 | #include "hw/cpu/a9mpcore.h" | |
37 | #include "hw/cpu/a15mpcore.h" | |
c5c752af | 38 | #include "qemu/log.h" |
2488514c | 39 | |
e2cddeeb PC |
40 | #define SMP_BOOT_ADDR 0x100 |
41 | #define SMP_BOOT_REG 0x40 | |
42 | #define MPCORE_PERIPHBASE 0xfff10000 | |
2488514c | 43 | |
40340e5f | 44 | #define MVBAR_ADDR 0x200 |
716536a9 | 45 | #define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t)) |
40340e5f | 46 | |
e2cddeeb | 47 | #define NIRQ_GIC 160 |
2488514c RH |
48 | |
49 | /* Board init. */ | |
2488514c | 50 | |
40340e5f PC |
51 | static void hb_write_board_setup(ARMCPU *cpu, |
52 | const struct arm_boot_info *info) | |
53 | { | |
716536a9 | 54 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); |
40340e5f PC |
55 | } |
56 | ||
9543b0cd | 57 | static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) |
2488514c RH |
58 | { |
59 | int n; | |
60 | uint32_t smpboot[] = { | |
61 | 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */ | |
62 | 0xe210000f, /* ands r0, r0, #0x0f */ | |
63 | 0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */ | |
64 | 0xe0830200, /* add r0, r3, r0, lsl #4 */ | |
bf471f79 | 65 | 0xe59f2024, /* ldr r2, privbase */ |
2488514c | 66 | 0xe3a01001, /* mov r1, #1 */ |
bf471f79 PM |
67 | 0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */ |
68 | 0xe3a010ff, /* mov r1, #0xff */ | |
69 | 0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */ | |
70 | 0xf57ff04f, /* dsb */ | |
2488514c RH |
71 | 0xe320f003, /* wfi */ |
72 | 0xe5901000, /* ldr r1, [r0] */ | |
73 | 0xe1110001, /* tst r1, r1 */ | |
74 | 0x0afffffb, /* beq <wfi> */ | |
75 | 0xe12fff11, /* bx r1 */ | |
e2cddeeb | 76 | MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */ |
2488514c RH |
77 | }; |
78 | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { | |
79 | smpboot[n] = tswap32(smpboot[n]); | |
80 | } | |
81 | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR); | |
82 | } | |
83 | ||
5d309320 | 84 | static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) |
2488514c | 85 | { |
5d309320 AF |
86 | CPUARMState *env = &cpu->env; |
87 | ||
2488514c RH |
88 | switch (info->nb_cpus) { |
89 | case 4: | |
42874d3a PM |
90 | address_space_stl_notdirty(&address_space_memory, |
91 | SMP_BOOT_REG + 0x30, 0, | |
92 | MEMTXATTRS_UNSPECIFIED, NULL); | |
2488514c | 93 | case 3: |
42874d3a PM |
94 | address_space_stl_notdirty(&address_space_memory, |
95 | SMP_BOOT_REG + 0x20, 0, | |
96 | MEMTXATTRS_UNSPECIFIED, NULL); | |
2488514c | 97 | case 2: |
42874d3a PM |
98 | address_space_stl_notdirty(&address_space_memory, |
99 | SMP_BOOT_REG + 0x10, 0, | |
100 | MEMTXATTRS_UNSPECIFIED, NULL); | |
2488514c RH |
101 | env->regs[15] = SMP_BOOT_ADDR; |
102 | break; | |
103 | default: | |
104 | break; | |
105 | } | |
106 | } | |
107 | ||
108 | #define NUM_REGS 0x200 | |
a8170e5e | 109 | static void hb_regs_write(void *opaque, hwaddr offset, |
2488514c RH |
110 | uint64_t value, unsigned size) |
111 | { | |
112 | uint32_t *regs = opaque; | |
113 | ||
114 | if (offset == 0xf00) { | |
115 | if (value == 1 || value == 2) { | |
cf83f140 | 116 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
2488514c | 117 | } else if (value == 3) { |
cf83f140 | 118 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
2488514c RH |
119 | } |
120 | } | |
121 | ||
c5c752af PP |
122 | if (offset / 4 >= NUM_REGS) { |
123 | qemu_log_mask(LOG_GUEST_ERROR, | |
124 | "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); | |
125 | return; | |
126 | } | |
127 | regs[offset / 4] = value; | |
2488514c RH |
128 | } |
129 | ||
a8170e5e | 130 | static uint64_t hb_regs_read(void *opaque, hwaddr offset, |
2488514c RH |
131 | unsigned size) |
132 | { | |
c5c752af | 133 | uint32_t value; |
2488514c | 134 | uint32_t *regs = opaque; |
c5c752af PP |
135 | |
136 | if (offset / 4 >= NUM_REGS) { | |
137 | qemu_log_mask(LOG_GUEST_ERROR, | |
138 | "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); | |
139 | return 0; | |
140 | } | |
141 | value = regs[offset / 4]; | |
2488514c RH |
142 | |
143 | if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { | |
144 | value |= 0x30000000; | |
145 | } | |
146 | ||
147 | return value; | |
148 | } | |
149 | ||
150 | static const MemoryRegionOps hb_mem_ops = { | |
151 | .read = hb_regs_read, | |
152 | .write = hb_regs_write, | |
153 | .endianness = DEVICE_NATIVE_ENDIAN, | |
154 | }; | |
155 | ||
426533fa AF |
156 | #define TYPE_HIGHBANK_REGISTERS "highbank-regs" |
157 | #define HIGHBANK_REGISTERS(obj) \ | |
158 | OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS) | |
159 | ||
2488514c | 160 | typedef struct { |
426533fa AF |
161 | /*< private >*/ |
162 | SysBusDevice parent_obj; | |
163 | /*< public >*/ | |
164 | ||
112f2ac9 | 165 | MemoryRegion iomem; |
2488514c RH |
166 | uint32_t regs[NUM_REGS]; |
167 | } HighbankRegsState; | |
168 | ||
169 | static VMStateDescription vmstate_highbank_regs = { | |
170 | .name = "highbank-regs", | |
171 | .version_id = 0, | |
172 | .minimum_version_id = 0, | |
2488514c RH |
173 | .fields = (VMStateField[]) { |
174 | VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS), | |
175 | VMSTATE_END_OF_LIST(), | |
176 | }, | |
177 | }; | |
178 | ||
179 | static void highbank_regs_reset(DeviceState *dev) | |
180 | { | |
426533fa | 181 | HighbankRegsState *s = HIGHBANK_REGISTERS(dev); |
2488514c RH |
182 | |
183 | s->regs[0x40] = 0x05F20121; | |
184 | s->regs[0x41] = 0x2; | |
185 | s->regs[0x42] = 0x05F30121; | |
186 | s->regs[0x43] = 0x05F40121; | |
187 | } | |
188 | ||
ff7a27c1 | 189 | static void highbank_regs_init(Object *obj) |
2488514c | 190 | { |
ff7a27c1 XZ |
191 | HighbankRegsState *s = HIGHBANK_REGISTERS(obj); |
192 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
2488514c | 193 | |
ff7a27c1 | 194 | memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs, |
64bde0f3 | 195 | "highbank_regs", 0x1000); |
112f2ac9 | 196 | sysbus_init_mmio(dev, &s->iomem); |
2488514c RH |
197 | } |
198 | ||
999e12bb AL |
199 | static void highbank_regs_class_init(ObjectClass *klass, void *data) |
200 | { | |
39bffca2 | 201 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 202 | |
39bffca2 AL |
203 | dc->desc = "Calxeda Highbank registers"; |
204 | dc->vmsd = &vmstate_highbank_regs; | |
205 | dc->reset = highbank_regs_reset; | |
999e12bb AL |
206 | } |
207 | ||
8c43a6f0 | 208 | static const TypeInfo highbank_regs_info = { |
426533fa | 209 | .name = TYPE_HIGHBANK_REGISTERS, |
39bffca2 AL |
210 | .parent = TYPE_SYS_BUS_DEVICE, |
211 | .instance_size = sizeof(HighbankRegsState), | |
ff7a27c1 | 212 | .instance_init = highbank_regs_init, |
39bffca2 | 213 | .class_init = highbank_regs_class_init, |
2488514c RH |
214 | }; |
215 | ||
83f7d43a | 216 | static void highbank_regs_register_types(void) |
2488514c | 217 | { |
39bffca2 | 218 | type_register_static(&highbank_regs_info); |
2488514c RH |
219 | } |
220 | ||
83f7d43a | 221 | type_init(highbank_regs_register_types) |
2488514c RH |
222 | |
223 | static struct arm_boot_info highbank_binfo; | |
224 | ||
574f66bc AP |
225 | enum cxmachines { |
226 | CALXEDA_HIGHBANK, | |
b25a83f0 | 227 | CALXEDA_MIDWAY, |
574f66bc AP |
228 | }; |
229 | ||
2488514c RH |
230 | /* ram_size must be set to match the upper bound of memory in the |
231 | * device tree (linux/arch/arm/boot/dts/highbank.dts), which is | |
232 | * normally 0xff900000 or -m 4089. When running this board on a | |
233 | * 32-bit host, set the reg value of memory to 0xf7ff00000 in the | |
234 | * device tree and pass -m 2047 to QEMU. | |
235 | */ | |
3ef96221 | 236 | static void calxeda_init(MachineState *machine, enum cxmachines machine_id) |
2488514c | 237 | { |
3ef96221 | 238 | ram_addr_t ram_size = machine->ram_size; |
574f66bc | 239 | DeviceState *dev = NULL; |
2488514c | 240 | SysBusDevice *busdev; |
2488514c RH |
241 | qemu_irq pic[128]; |
242 | int n; | |
cc7d44c2 | 243 | unsigned int smp_cpus = machine->smp.cpus; |
2488514c | 244 | qemu_irq cpu_irq[4]; |
5ae79fe8 | 245 | qemu_irq cpu_fiq[4]; |
582c8f75 PM |
246 | qemu_irq cpu_virq[4]; |
247 | qemu_irq cpu_vfiq[4]; | |
2488514c RH |
248 | MemoryRegion *sysram; |
249 | MemoryRegion *dram; | |
250 | MemoryRegion *sysmem; | |
251 | char *sysboot_filename; | |
252 | ||
dca6eeed PC |
253 | switch (machine_id) { |
254 | case CALXEDA_HIGHBANK: | |
ba1ba5cc | 255 | machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
dca6eeed PC |
256 | break; |
257 | case CALXEDA_MIDWAY: | |
ba1ba5cc | 258 | machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
dca6eeed | 259 | break; |
ba1ba5cc IM |
260 | default: |
261 | assert(0); | |
2488514c RH |
262 | } |
263 | ||
264 | for (n = 0; n < smp_cpus; n++) { | |
d097696e | 265 | Object *cpuobj; |
c5fad12f | 266 | ARMCPU *cpu; |
f282f296 | 267 | |
ba1ba5cc | 268 | cpuobj = object_new(machine->cpu_type); |
d097696e | 269 | cpu = ARM_CPU(cpuobj); |
f282f296 | 270 | |
40340e5f PC |
271 | object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC, |
272 | "psci-conduit", &error_abort); | |
273 | ||
274 | if (n) { | |
275 | /* Secondary CPUs start in PSCI powered-down state */ | |
276 | object_property_set_bool(cpuobj, true, | |
277 | "start-powered-off", &error_abort); | |
61e2f352 GB |
278 | } |
279 | ||
d097696e PM |
280 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { |
281 | object_property_set_int(cpuobj, MPCORE_PERIPHBASE, | |
282 | "reset-cbar", &error_abort); | |
c0f1ead9 | 283 | } |
007b0657 | 284 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
9188dbf7 | 285 | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ); |
5ae79fe8 | 286 | cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ); |
582c8f75 PM |
287 | cpu_virq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VIRQ); |
288 | cpu_vfiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_VFIQ); | |
2488514c RH |
289 | } |
290 | ||
291 | sysmem = get_system_memory(); | |
292 | dram = g_new(MemoryRegion, 1); | |
c8623c02 | 293 | memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); |
2488514c RH |
294 | /* SDRAM at address zero. */ |
295 | memory_region_add_subregion(sysmem, 0, dram); | |
296 | ||
297 | sysram = g_new(MemoryRegion, 1); | |
eb7d1f17 | 298 | memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, |
f8ed85ac | 299 | &error_fatal); |
2488514c RH |
300 | memory_region_add_subregion(sysmem, 0xfff88000, sysram); |
301 | if (bios_name != NULL) { | |
302 | sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
303 | if (sysboot_filename != NULL) { | |
60ff4e63 | 304 | if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) { |
c525436e MA |
305 | error_report("Unable to load %s", bios_name); |
306 | exit(1); | |
2488514c | 307 | } |
6e05a12f | 308 | g_free(sysboot_filename); |
2488514c | 309 | } else { |
c525436e MA |
310 | error_report("Unable to find %s", bios_name); |
311 | exit(1); | |
2488514c RH |
312 | } |
313 | } | |
314 | ||
3ef96221 | 315 | switch (machine_id) { |
574f66bc | 316 | case CALXEDA_HIGHBANK: |
b25a83f0 AP |
317 | dev = qdev_create(NULL, "l2x0"); |
318 | qdev_init_nofail(dev); | |
319 | busdev = SYS_BUS_DEVICE(dev); | |
320 | sysbus_mmio_map(busdev, 0, 0xfff12000); | |
321 | ||
c2de81e2 | 322 | dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); |
574f66bc | 323 | break; |
b25a83f0 | 324 | case CALXEDA_MIDWAY: |
c2de81e2 | 325 | dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV); |
b25a83f0 | 326 | break; |
574f66bc | 327 | } |
2488514c RH |
328 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
329 | qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC); | |
330 | qdev_init_nofail(dev); | |
1356b98d | 331 | busdev = SYS_BUS_DEVICE(dev); |
e2cddeeb | 332 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
2488514c RH |
333 | for (n = 0; n < smp_cpus; n++) { |
334 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
5ae79fe8 | 335 | sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]); |
582c8f75 PM |
336 | sysbus_connect_irq(busdev, n + 2 * smp_cpus, cpu_virq[n]); |
337 | sysbus_connect_irq(busdev, n + 3 * smp_cpus, cpu_vfiq[n]); | |
2488514c RH |
338 | } |
339 | ||
340 | for (n = 0; n < 128; n++) { | |
341 | pic[n] = qdev_get_gpio_in(dev, n); | |
342 | } | |
343 | ||
2488514c RH |
344 | dev = qdev_create(NULL, "sp804"); |
345 | qdev_prop_set_uint32(dev, "freq0", 150000000); | |
346 | qdev_prop_set_uint32(dev, "freq1", 150000000); | |
347 | qdev_init_nofail(dev); | |
1356b98d | 348 | busdev = SYS_BUS_DEVICE(dev); |
2488514c RH |
349 | sysbus_mmio_map(busdev, 0, 0xfff34000); |
350 | sysbus_connect_irq(busdev, 0, pic[18]); | |
9bca0edb | 351 | pl011_create(0xfff36000, pic[20], serial_hd(0)); |
2488514c | 352 | |
c2de81e2 | 353 | dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS); |
2488514c | 354 | qdev_init_nofail(dev); |
1356b98d | 355 | busdev = SYS_BUS_DEVICE(dev); |
2488514c RH |
356 | sysbus_mmio_map(busdev, 0, 0xfff3c000); |
357 | ||
358 | sysbus_create_simple("pl061", 0xfff30000, pic[14]); | |
359 | sysbus_create_simple("pl061", 0xfff31000, pic[15]); | |
360 | sysbus_create_simple("pl061", 0xfff32000, pic[16]); | |
361 | sysbus_create_simple("pl061", 0xfff33000, pic[17]); | |
362 | sysbus_create_simple("pl031", 0xfff35000, pic[19]); | |
363 | sysbus_create_simple("pl022", 0xfff39000, pic[23]); | |
364 | ||
c2de81e2 | 365 | sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]); |
2488514c | 366 | |
a005d073 | 367 | if (nd_table[0].used) { |
2488514c RH |
368 | qemu_check_nic_model(&nd_table[0], "xgmac"); |
369 | dev = qdev_create(NULL, "xgmac"); | |
370 | qdev_set_nic_properties(dev, &nd_table[0]); | |
371 | qdev_init_nofail(dev); | |
1356b98d AF |
372 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000); |
373 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]); | |
374 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]); | |
375 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]); | |
2488514c RH |
376 | |
377 | qemu_check_nic_model(&nd_table[1], "xgmac"); | |
378 | dev = qdev_create(NULL, "xgmac"); | |
379 | qdev_set_nic_properties(dev, &nd_table[1]); | |
380 | qdev_init_nofail(dev); | |
1356b98d AF |
381 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000); |
382 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]); | |
383 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]); | |
384 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]); | |
2488514c RH |
385 | } |
386 | ||
2a7ae4ee MA |
387 | /* TODO create and connect IDE devices for ide_drive_get() */ |
388 | ||
2488514c | 389 | highbank_binfo.ram_size = ram_size; |
2488514c RH |
390 | /* highbank requires a dtb in order to boot, and the dtb will override |
391 | * the board ID. The following value is ignored, so set it to -1 to be | |
392 | * clear that the value is meaningless. | |
393 | */ | |
394 | highbank_binfo.board_id = -1; | |
395 | highbank_binfo.nb_cpus = smp_cpus; | |
396 | highbank_binfo.loader_start = 0; | |
397 | highbank_binfo.write_secondary_boot = hb_write_secondary; | |
398 | highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary; | |
40340e5f PC |
399 | if (!kvm_enabled()) { |
400 | highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR; | |
401 | highbank_binfo.write_board_setup = hb_write_board_setup; | |
402 | highbank_binfo.secure_board_setup = true; | |
403 | } else { | |
3dc6f869 AF |
404 | warn_report("cannot load built-in Monitor support " |
405 | "if KVM is enabled. Some guests (such as Linux) " | |
406 | "may not boot."); | |
40340e5f PC |
407 | } |
408 | ||
2744ece8 | 409 | arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo); |
2488514c RH |
410 | } |
411 | ||
3ef96221 | 412 | static void highbank_init(MachineState *machine) |
574f66bc | 413 | { |
3ef96221 | 414 | calxeda_init(machine, CALXEDA_HIGHBANK); |
574f66bc AP |
415 | } |
416 | ||
3ef96221 | 417 | static void midway_init(MachineState *machine) |
b25a83f0 | 418 | { |
3ef96221 | 419 | calxeda_init(machine, CALXEDA_MIDWAY); |
b25a83f0 AP |
420 | } |
421 | ||
8a661aea | 422 | static void highbank_class_init(ObjectClass *oc, void *data) |
e264d29d | 423 | { |
8a661aea AF |
424 | MachineClass *mc = MACHINE_CLASS(oc); |
425 | ||
e264d29d EH |
426 | mc->desc = "Calxeda Highbank (ECX-1000)"; |
427 | mc->init = highbank_init; | |
2a7ae4ee MA |
428 | mc->block_default_type = IF_IDE; |
429 | mc->units_per_default_bus = 1; | |
e264d29d | 430 | mc->max_cpus = 4; |
4672cbd7 | 431 | mc->ignore_memory_transaction_failures = true; |
e264d29d | 432 | } |
2488514c | 433 | |
8a661aea AF |
434 | static const TypeInfo highbank_type = { |
435 | .name = MACHINE_TYPE_NAME("highbank"), | |
436 | .parent = TYPE_MACHINE, | |
437 | .class_init = highbank_class_init, | |
438 | }; | |
b25a83f0 | 439 | |
8a661aea | 440 | static void midway_class_init(ObjectClass *oc, void *data) |
2488514c | 441 | { |
8a661aea AF |
442 | MachineClass *mc = MACHINE_CLASS(oc); |
443 | ||
e264d29d EH |
444 | mc->desc = "Calxeda Midway (ECX-2000)"; |
445 | mc->init = midway_init; | |
2a7ae4ee MA |
446 | mc->block_default_type = IF_IDE; |
447 | mc->units_per_default_bus = 1; | |
e264d29d | 448 | mc->max_cpus = 4; |
4672cbd7 | 449 | mc->ignore_memory_transaction_failures = true; |
2488514c RH |
450 | } |
451 | ||
8a661aea AF |
452 | static const TypeInfo midway_type = { |
453 | .name = MACHINE_TYPE_NAME("midway"), | |
454 | .parent = TYPE_MACHINE, | |
455 | .class_init = midway_class_init, | |
456 | }; | |
457 | ||
458 | static void calxeda_machines_init(void) | |
459 | { | |
460 | type_register_static(&highbank_type); | |
461 | type_register_static(&midway_type); | |
462 | } | |
463 | ||
0e6aac87 | 464 | type_init(calxeda_machines_init) |