[mirror_qemu.git] / hw / arm / highbank.c

/*
 * Calxeda Highbank SoC emulation
 *
 * Copyright (c) 2010-2012 Calxeda
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "hw/loader.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"

#define SMP_BOOT_ADDR           0x100
#define SMP_BOOT_REG            0x40
#define MPCORE_PERIPHBASE       0xfff10000

#define NIRQ_GIC                160

/* Board init.  */

static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
        0xe210000f, /* ands r0, r0, #0x0f */
        0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
        0xe0830200, /* add r0, r3, r0, lsl #4 */
        0xe59f2024, /* ldr r2, privbase */
        0xe3a01001, /* mov r1, #1 */
        0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
    };
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}

static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    CPUARMState *env = &cpu->env;

    switch (info->nb_cpus) {
    case 4:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x30, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
    case 3:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x20, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
    case 2:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x10, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
        env->regs[15] = SMP_BOOT_ADDR;
        break;
    default:
        break;
    }
}

#define NUM_REGS      0x200
static void hb_regs_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    uint32_t *regs = opaque;

    if (offset == 0xf00) {
        if (value == 1 || value == 2) {
            qemu_system_reset_request();
        } else if (value == 3) {
            qemu_system_shutdown_request();
        }
    }

    regs[offset/4] = value;
}

static uint64_t hb_regs_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    uint32_t *regs = opaque;
    uint32_t value = regs[offset/4];

    if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
        value |= 0x30000000;
    }

    return value;
}

static const MemoryRegionOps hb_mem_ops = {
    .read = hb_regs_read,
    .write = hb_regs_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
#define HIGHBANK_REGISTERS(obj) \
    OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)

typedef struct {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    uint32_t regs[NUM_REGS];
} HighbankRegsState;

static VMStateDescription vmstate_highbank_regs = {
    .name = "highbank-regs",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
        VMSTATE_END_OF_LIST(),
    },
};

static void highbank_regs_reset(DeviceState *dev)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(dev);

    s->regs[0x40] = 0x05F20121;
    s->regs[0x41] = 0x2;
    s->regs[0x42] = 0x05F30121;
    s->regs[0x43] = 0x05F40121;
}

static int highbank_regs_init(SysBusDevice *dev)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
                          "highbank_regs", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);

    return 0;
}

static void highbank_regs_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = highbank_regs_init;
    dc->desc = "Calxeda Highbank registers";
    dc->vmsd = &vmstate_highbank_regs;
    dc->reset = highbank_regs_reset;
}

static const TypeInfo highbank_regs_info = {
    .name          = TYPE_HIGHBANK_REGISTERS,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(HighbankRegsState),
    .class_init    = highbank_regs_class_init,
};

static void highbank_regs_register_types(void)
{
    type_register_static(&highbank_regs_info);
}

type_init(highbank_regs_register_types)

static struct arm_boot_info highbank_binfo;

enum cxmachines {
    CALXEDA_HIGHBANK,
    CALXEDA_MIDWAY,
};

/* ram_size must be set to match the upper bound of memory in the
 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 * normally 0xff900000 or -m 4089. When running this board on a
 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 * device tree and pass -m 2047 to QEMU.
 */
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    DeviceState *dev = NULL;
    SysBusDevice *busdev;
    qemu_irq pic[128];
    int n;
    qemu_irq cpu_irq[4];
    qemu_irq cpu_fiq[4];
    MemoryRegion *sysram;
    MemoryRegion *dram;
    MemoryRegion *sysmem;
    char *sysboot_filename;

    if (!cpu_model) {
        switch (machine_id) {
        case CALXEDA_HIGHBANK:
            cpu_model = "cortex-a9";
            break;
        case CALXEDA_MIDWAY:
            cpu_model = "cortex-a15";
            break;
        }
    }

    for (n = 0; n < smp_cpus; n++) {
        ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
        Object *cpuobj;
        ARMCPU *cpu;
        Error *err = NULL;

        if (!oc) {
            error_report("Unable to find CPU definition");
            exit(1);
        }

        cpuobj = object_new(object_class_get_name(oc));
        cpu = ARM_CPU(cpuobj);

        /* By default A9 and A15 CPUs have EL3 enabled.  This board does not
         * currently support EL3 so the CPU EL3 property is disabled before
         * realization.
         */
        if (object_property_find(cpuobj, "has_el3", NULL)) {
            object_property_set_bool(cpuobj, false, "has_el3", &err);
            if (err) {
                error_report_err(err);
                exit(1);
            }
        }

        if (object_property_find(cpuobj, "reset-cbar", NULL)) {
            object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
                                    "reset-cbar", &error_abort);
        }
        object_property_set_bool(cpuobj, true, "realized", &err);
        if (err) {
            error_report_err(err);
            exit(1);
        }
        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
        cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
    }

    sysmem = get_system_memory();
    dram = g_new(MemoryRegion, 1);
    memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, dram);

    sysram = g_new(MemoryRegion, 1);
    memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
                           &error_fatal);
    memory_region_add_subregion(sysmem, 0xfff88000, sysram);
    if (bios_name != NULL) {
        sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (sysboot_filename != NULL) {
            if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
                hw_error("Unable to load %s\n", bios_name);
            }
            g_free(sysboot_filename);
        } else {
           hw_error("Unable to find %s\n", bios_name);
        }
    }

    switch (machine_id) {
    case CALXEDA_HIGHBANK:
        dev = qdev_create(NULL, "l2x0");
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, 0xfff12000);

        dev = qdev_create(NULL, "a9mpcore_priv");
        break;
    case CALXEDA_MIDWAY:
        dev = qdev_create(NULL, "a15mpcore_priv");
        break;
    }
    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
    qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    for (n = 0; n < smp_cpus; n++) {
        sysbus_connect_irq(busdev, n, cpu_irq[n]);
        sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
    }

    for (n = 0; n < 128; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    dev = qdev_create(NULL, "sp804");
    qdev_prop_set_uint32(dev, "freq0", 150000000);
    qdev_prop_set_uint32(dev, "freq1", 150000000);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff34000);
    sysbus_connect_irq(busdev, 0, pic[18]);
    sysbus_create_simple("pl011", 0xfff36000, pic[20]);

    dev = qdev_create(NULL, "highbank-regs");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff3c000);

    sysbus_create_simple("pl061", 0xfff30000, pic[14]);
    sysbus_create_simple("pl061", 0xfff31000, pic[15]);
    sysbus_create_simple("pl061", 0xfff32000, pic[16]);
    sysbus_create_simple("pl061", 0xfff33000, pic[17]);
    sysbus_create_simple("pl031", 0xfff35000, pic[19]);
    sysbus_create_simple("pl022", 0xfff39000, pic[23]);

    sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);

    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[0]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);

        qemu_check_nic_model(&nd_table[1], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[1]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
    }

    highbank_binfo.ram_size = ram_size;
    highbank_binfo.kernel_filename = kernel_filename;
    highbank_binfo.kernel_cmdline = kernel_cmdline;
    highbank_binfo.initrd_filename = initrd_filename;
    /* highbank requires a dtb in order to boot, and the dtb will override
     * the board ID. The following value is ignored, so set it to -1 to be
     * clear that the value is meaningless.
     */
    highbank_binfo.board_id = -1;
    highbank_binfo.nb_cpus = smp_cpus;
    highbank_binfo.loader_start = 0;
    highbank_binfo.write_secondary_boot = hb_write_secondary;
    highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
    arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
}

static void highbank_init(MachineState *machine)
{
    calxeda_init(machine, CALXEDA_HIGHBANK);
}

static void midway_init(MachineState *machine)
{
    calxeda_init(machine, CALXEDA_MIDWAY);
}

static void highbank_machine_init(MachineClass *mc)
{
    mc->desc = "Calxeda Highbank (ECX-1000)";
    mc->init = highbank_init;
    mc->block_default_type = IF_SCSI;
    mc->max_cpus = 4;
}

DEFINE_MACHINE("highbank", highbank_machine_init)

static void midway_machine_init(MachineClass *mc)
{
    mc->desc = "Calxeda Midway (ECX-2000)";
    mc->init = midway_init;
    mc->block_default_type = IF_SCSI;
    mc->max_cpus = 4;
}

DEFINE_MACHINE("midway", midway_machine_init)
Commit	Line	Data
2488514c RH	1	/*
	2	* Calxeda Highbank SoC emulation
	3	*
	4	* Copyright (c) 2010-2012 Calxeda
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	*/
	19
83c9f4ca	20	#include "hw/sysbus.h"
bd2be150 PM	21	#include "hw/arm/arm.h"
bd2be150 PM	22	#include "hw/devices.h"
83c9f4ca	23	#include "hw/loader.h"
1422e32d	24	#include "net/net.h"
9c17d615	25	#include "sysemu/sysemu.h"
83c9f4ca	26	#include "hw/boards.h"
4be74634	27	#include "sysemu/block-backend.h"
022c62cb	28	#include "exec/address-spaces.h"
f282f296	29	#include "qemu/error-report.h"
2488514c	30
e2cddeeb PC	31	#define SMP_BOOT_ADDR 0x100
	32	#define SMP_BOOT_REG 0x40
	33	#define MPCORE_PERIPHBASE 0xfff10000
2488514c	34
e2cddeeb	35	#define NIRQ_GIC 160
2488514c RH	36
2488514c RH	37	/* Board init. */
2488514c	38
9543b0cd	39	static void hb_write_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c RH	40	{
	41	int n;
	42	uint32_t smpboot[] = {
	43	0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
	44	0xe210000f, /* ands r0, r0, #0x0f */
	45	0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
	46	0xe0830200, /* add r0, r3, r0, lsl #4 */
bf471f79	47	0xe59f2024, /* ldr r2, privbase */
2488514c	48	0xe3a01001, /* mov r1, #1 */
bf471f79 PM	49	0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
	50	0xe3a010ff, /* mov r1, #0xff */
	51	0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
	52	0xf57ff04f, /* dsb */
2488514c RH	53	0xe320f003, /* wfi */
	54	0xe5901000, /* ldr r1, [r0] */
	55	0xe1110001, /* tst r1, r1 */
	56	0x0afffffb, /* beq <wfi> */
	57	0xe12fff11, /* bx r1 */
e2cddeeb	58	MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
2488514c RH	59	};
	60	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	61	smpboot[n] = tswap32(smpboot[n]);
	62	}
	63	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
	64	}
	65
5d309320	66	static void hb_reset_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c	67	{
5d309320 AF	68	CPUARMState *env = &cpu->env;
5d309320 AF	69
2488514c RH	70	switch (info->nb_cpus) {
2488514c RH	71	case 4:
42874d3a PM	72	address_space_stl_notdirty(&address_space_memory,
	73	SMP_BOOT_REG + 0x30, 0,
	74	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c	75	case 3:
42874d3a PM	76	address_space_stl_notdirty(&address_space_memory,
	77	SMP_BOOT_REG + 0x20, 0,
	78	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c	79	case 2:
42874d3a PM	80	address_space_stl_notdirty(&address_space_memory,
	81	SMP_BOOT_REG + 0x10, 0,
	82	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c RH	83	env->regs[15] = SMP_BOOT_ADDR;
	84	break;
	85	default:
	86	break;
	87	}
	88	}
	89
	90	#define NUM_REGS 0x200
a8170e5e	91	static void hb_regs_write(void *opaque, hwaddr offset,
2488514c RH	92	uint64_t value, unsigned size)
	93	{
	94	uint32_t *regs = opaque;
	95
	96	if (offset == 0xf00) {
	97	if (value == 1 \|\| value == 2) {
	98	qemu_system_reset_request();
	99	} else if (value == 3) {
	100	qemu_system_shutdown_request();
	101	}
	102	}
	103
	104	regs[offset/4] = value;
	105	}
	106
a8170e5e	107	static uint64_t hb_regs_read(void *opaque, hwaddr offset,
2488514c RH	108	unsigned size)
	109	{
	110	uint32_t *regs = opaque;
	111	uint32_t value = regs[offset/4];
	112
	113	if ((offset == 0x100) \|\| (offset == 0x108) \|\| (offset == 0x10C)) {
	114	value \|= 0x30000000;
	115	}
	116
	117	return value;
	118	}
	119
	120	static const MemoryRegionOps hb_mem_ops = {
	121	.read = hb_regs_read,
	122	.write = hb_regs_write,
	123	.endianness = DEVICE_NATIVE_ENDIAN,
	124	};
	125
426533fa AF	126	#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
	127	#define HIGHBANK_REGISTERS(obj) \
	128	OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
	129
2488514c	130	typedef struct {
426533fa AF	131	/< private >/
	132	SysBusDevice parent_obj;
	133	/< public >/
	134
112f2ac9	135	MemoryRegion iomem;
2488514c RH	136	uint32_t regs[NUM_REGS];
	137	} HighbankRegsState;
	138
	139	static VMStateDescription vmstate_highbank_regs = {
	140	.name = "highbank-regs",
	141	.version_id = 0,
	142	.minimum_version_id = 0,
2488514c RH	143	.fields = (VMStateField[]) {
	144	VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
	145	VMSTATE_END_OF_LIST(),
	146	},
	147	};
	148
	149	static void highbank_regs_reset(DeviceState *dev)
	150	{
426533fa	151	HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
2488514c RH	152
	153	s->regs[0x40] = 0x05F20121;
	154	s->regs[0x41] = 0x2;
	155	s->regs[0x42] = 0x05F30121;
	156	s->regs[0x43] = 0x05F40121;
	157	}
	158
	159	static int highbank_regs_init(SysBusDevice *dev)
	160	{
426533fa	161	HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
2488514c	162
112f2ac9	163	memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
64bde0f3	164	"highbank_regs", 0x1000);
112f2ac9	165	sysbus_init_mmio(dev, &s->iomem);
2488514c RH	166
	167	return 0;
	168	}
	169
999e12bb AL	170	static void highbank_regs_class_init(ObjectClass klass, void data)
	171	{
	172	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	173	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	174
999e12bb AL	175	sbc->init = highbank_regs_init;
39bffca2 AL	176	dc->desc = "Calxeda Highbank registers";
	177	dc->vmsd = &vmstate_highbank_regs;
	178	dc->reset = highbank_regs_reset;
999e12bb AL	179	}
999e12bb AL	180
8c43a6f0	181	static const TypeInfo highbank_regs_info = {
426533fa	182	.name = TYPE_HIGHBANK_REGISTERS,
39bffca2 AL	183	.parent = TYPE_SYS_BUS_DEVICE,
	184	.instance_size = sizeof(HighbankRegsState),
	185	.class_init = highbank_regs_class_init,
2488514c RH	186	};
2488514c RH	187
83f7d43a	188	static void highbank_regs_register_types(void)
2488514c	189	{
39bffca2	190	type_register_static(&highbank_regs_info);
2488514c RH	191	}
2488514c RH	192
83f7d43a	193	type_init(highbank_regs_register_types)
2488514c RH	194
	195	static struct arm_boot_info highbank_binfo;
	196
574f66bc AP	197	enum cxmachines {
574f66bc AP	198	CALXEDA_HIGHBANK,
b25a83f0	199	CALXEDA_MIDWAY,
574f66bc AP	200	};
574f66bc AP	201
2488514c RH	202	/* ram_size must be set to match the upper bound of memory in the
	203	* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
	204	* normally 0xff900000 or -m 4089. When running this board on a
	205	* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
	206	* device tree and pass -m 2047 to QEMU.
	207	*/
3ef96221	208	static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
2488514c	209	{
3ef96221 MA	210	ram_addr_t ram_size = machine->ram_size;
	211	const char *cpu_model = machine->cpu_model;
	212	const char *kernel_filename = machine->kernel_filename;
	213	const char *kernel_cmdline = machine->kernel_cmdline;
	214	const char *initrd_filename = machine->initrd_filename;
574f66bc	215	DeviceState *dev = NULL;
2488514c	216	SysBusDevice *busdev;
2488514c RH	217	qemu_irq pic[128];
	218	int n;
	219	qemu_irq cpu_irq[4];
5ae79fe8	220	qemu_irq cpu_fiq[4];
2488514c RH	221	MemoryRegion *sysram;
	222	MemoryRegion *dram;
	223	MemoryRegion *sysmem;
	224	char *sysboot_filename;
	225
	226	if (!cpu_model) {
3ef96221	227	switch (machine_id) {
574f66bc AP	228	case CALXEDA_HIGHBANK:
	229	cpu_model = "cortex-a9";
	230	break;
b25a83f0 AP	231	case CALXEDA_MIDWAY:
	232	cpu_model = "cortex-a15";
	233	break;
574f66bc	234	}
2488514c RH	235	}
	236
	237	for (n = 0; n < smp_cpus; n++) {
f282f296	238	ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
d097696e	239	Object *cpuobj;
c5fad12f	240	ARMCPU *cpu;
f282f296 PC	241	Error *err = NULL;
f282f296 PC	242
3b418d0c PM	243	if (!oc) {
	244	error_report("Unable to find CPU definition");
	245	exit(1);
	246	}
	247
d097696e PM	248	cpuobj = object_new(object_class_get_name(oc));
d097696e PM	249	cpu = ARM_CPU(cpuobj);
f282f296	250
61e2f352 GB	251	/* By default A9 and A15 CPUs have EL3 enabled. This board does not
	252	* currently support EL3 so the CPU EL3 property is disabled before
	253	* realization.
	254	*/
	255	if (object_property_find(cpuobj, "has_el3", NULL)) {
	256	object_property_set_bool(cpuobj, false, "has_el3", &err);
	257	if (err) {
565f65d2	258	error_report_err(err);
61e2f352 GB	259	exit(1);
	260	}
	261	}
	262
d097696e PM	263	if (object_property_find(cpuobj, "reset-cbar", NULL)) {
	264	object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
	265	"reset-cbar", &error_abort);
c0f1ead9	266	}
d097696e	267	object_property_set_bool(cpuobj, true, "realized", &err);
f282f296	268	if (err) {
565f65d2	269	error_report_err(err);
2488514c RH	270	exit(1);
2488514c RH	271	}
9188dbf7	272	cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
5ae79fe8	273	cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
2488514c RH	274	}
	275
	276	sysmem = get_system_memory();
	277	dram = g_new(MemoryRegion, 1);
c8623c02	278	memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
2488514c RH	279	/* SDRAM at address zero. */
	280	memory_region_add_subregion(sysmem, 0, dram);
	281
	282	sysram = g_new(MemoryRegion, 1);
49946538	283	memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
f8ed85ac	284	&error_fatal);
2488514c RH	285	memory_region_add_subregion(sysmem, 0xfff88000, sysram);
	286	if (bios_name != NULL) {
	287	sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	288	if (sysboot_filename != NULL) {
60ff4e63	289	if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
2488514c RH	290	hw_error("Unable to load %s\n", bios_name);
2488514c RH	291	}
6e05a12f	292	g_free(sysboot_filename);
2488514c RH	293	} else {
	294	hw_error("Unable to find %s\n", bios_name);
	295	}
	296	}
	297
3ef96221	298	switch (machine_id) {
574f66bc	299	case CALXEDA_HIGHBANK:
b25a83f0 AP	300	dev = qdev_create(NULL, "l2x0");
	301	qdev_init_nofail(dev);
	302	busdev = SYS_BUS_DEVICE(dev);
	303	sysbus_mmio_map(busdev, 0, 0xfff12000);
	304
574f66bc AP	305	dev = qdev_create(NULL, "a9mpcore_priv");
574f66bc AP	306	break;
b25a83f0 AP	307	case CALXEDA_MIDWAY:
	308	dev = qdev_create(NULL, "a15mpcore_priv");
	309	break;
574f66bc	310	}
2488514c RH	311	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	312	qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
	313	qdev_init_nofail(dev);
1356b98d	314	busdev = SYS_BUS_DEVICE(dev);
e2cddeeb	315	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
2488514c RH	316	for (n = 0; n < smp_cpus; n++) {
2488514c RH	317	sysbus_connect_irq(busdev, n, cpu_irq[n]);
5ae79fe8	318	sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
2488514c RH	319	}
	320
	321	for (n = 0; n < 128; n++) {
	322	pic[n] = qdev_get_gpio_in(dev, n);
	323	}
	324
2488514c RH	325	dev = qdev_create(NULL, "sp804");
	326	qdev_prop_set_uint32(dev, "freq0", 150000000);
	327	qdev_prop_set_uint32(dev, "freq1", 150000000);
	328	qdev_init_nofail(dev);
1356b98d	329	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	330	sysbus_mmio_map(busdev, 0, 0xfff34000);
	331	sysbus_connect_irq(busdev, 0, pic[18]);
	332	sysbus_create_simple("pl011", 0xfff36000, pic[20]);
	333
	334	dev = qdev_create(NULL, "highbank-regs");
	335	qdev_init_nofail(dev);
1356b98d	336	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	337	sysbus_mmio_map(busdev, 0, 0xfff3c000);
	338
	339	sysbus_create_simple("pl061", 0xfff30000, pic[14]);
	340	sysbus_create_simple("pl061", 0xfff31000, pic[15]);
	341	sysbus_create_simple("pl061", 0xfff32000, pic[16]);
	342	sysbus_create_simple("pl061", 0xfff33000, pic[17]);
	343	sysbus_create_simple("pl031", 0xfff35000, pic[19]);
	344	sysbus_create_simple("pl022", 0xfff39000, pic[23]);
	345
	346	sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
	347
a005d073	348	if (nd_table[0].used) {
2488514c RH	349	qemu_check_nic_model(&nd_table[0], "xgmac");
	350	dev = qdev_create(NULL, "xgmac");
	351	qdev_set_nic_properties(dev, &nd_table[0]);
	352	qdev_init_nofail(dev);
1356b98d AF	353	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
	354	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
	355	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
	356	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
2488514c RH	357
	358	qemu_check_nic_model(&nd_table[1], "xgmac");
	359	dev = qdev_create(NULL, "xgmac");
	360	qdev_set_nic_properties(dev, &nd_table[1]);
	361	qdev_init_nofail(dev);
1356b98d AF	362	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
	363	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
	364	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
	365	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
2488514c RH	366	}
	367
	368	highbank_binfo.ram_size = ram_size;
	369	highbank_binfo.kernel_filename = kernel_filename;
	370	highbank_binfo.kernel_cmdline = kernel_cmdline;
	371	highbank_binfo.initrd_filename = initrd_filename;
	372	/* highbank requires a dtb in order to boot, and the dtb will override
	373	* the board ID. The following value is ignored, so set it to -1 to be
	374	* clear that the value is meaningless.
	375	*/
	376	highbank_binfo.board_id = -1;
	377	highbank_binfo.nb_cpus = smp_cpus;
	378	highbank_binfo.loader_start = 0;
	379	highbank_binfo.write_secondary_boot = hb_write_secondary;
	380	highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
182735ef	381	arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
2488514c RH	382	}
2488514c RH	383
3ef96221	384	static void highbank_init(MachineState *machine)
574f66bc	385	{
3ef96221	386	calxeda_init(machine, CALXEDA_HIGHBANK);
574f66bc AP	387	}
574f66bc AP	388
3ef96221	389	static void midway_init(MachineState *machine)
b25a83f0	390	{
3ef96221	391	calxeda_init(machine, CALXEDA_MIDWAY);
b25a83f0 AP	392	}
b25a83f0 AP	393
e264d29d EH	394	static void highbank_machine_init(MachineClass *mc)
	395	{
	396	mc->desc = "Calxeda Highbank (ECX-1000)";
	397	mc->init = highbank_init;
	398	mc->block_default_type = IF_SCSI;
	399	mc->max_cpus = 4;
	400	}
2488514c	401
e264d29d	402	DEFINE_MACHINE("highbank", highbank_machine_init)
b25a83f0	403
e264d29d	404	static void midway_machine_init(MachineClass *mc)
2488514c	405	{
e264d29d EH	406	mc->desc = "Calxeda Midway (ECX-2000)";
	407	mc->init = midway_init;
	408	mc->block_default_type = IF_SCSI;
	409	mc->max_cpus = 4;
2488514c RH	410	}
2488514c RH	411
e264d29d	412	DEFINE_MACHINE("midway", midway_machine_init)