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5fafdf24 | 1 | /* |
b5ff1b31 FB |
2 | * ARM Integrator CP System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
b5ff1b31 FB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL |
b5ff1b31 FB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
4771d756 | 12 | #include "cpu.h" |
83c9f4ca | 13 | #include "hw/sysbus.h" |
83c9f4ca | 14 | #include "hw/boards.h" |
12ec8bd5 | 15 | #include "hw/arm/boot.h" |
b8616055 | 16 | #include "hw/misc/arm_integrator_debug.h" |
437cc27d | 17 | #include "hw/net/smc91c111.h" |
1422e32d | 18 | #include "net/net.h" |
022c62cb | 19 | #include "exec/address-spaces.h" |
9c17d615 | 20 | #include "sysemu/sysemu.h" |
223a72f1 | 21 | #include "qemu/error-report.h" |
f0d1d2c1 | 22 | #include "hw/char/pl011.h" |
b5ff1b31 | 23 | |
257ec289 AF |
24 | #define TYPE_INTEGRATOR_CM "integrator_core" |
25 | #define INTEGRATOR_CM(obj) \ | |
26 | OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) | |
27 | ||
28 | typedef struct IntegratorCMState { | |
29 | /*< private >*/ | |
30 | SysBusDevice parent_obj; | |
31 | /*< public >*/ | |
32 | ||
71d9bc50 | 33 | MemoryRegion iomem; |
ee6847d1 | 34 | uint32_t memsz; |
211adf4d | 35 | MemoryRegion flash; |
b5ff1b31 FB |
36 | uint32_t cm_osc; |
37 | uint32_t cm_ctrl; | |
38 | uint32_t cm_lock; | |
39 | uint32_t cm_auxosc; | |
40 | uint32_t cm_sdram; | |
41 | uint32_t cm_init; | |
42 | uint32_t cm_flags; | |
43 | uint32_t cm_nvflags; | |
f53977f7 | 44 | uint32_t cm_refcnt_offset; |
b5ff1b31 FB |
45 | uint32_t int_level; |
46 | uint32_t irq_enabled; | |
47 | uint32_t fiq_enabled; | |
257ec289 | 48 | } IntegratorCMState; |
b5ff1b31 FB |
49 | |
50 | static uint8_t integrator_spd[128] = { | |
51 | 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, | |
52 | 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 | |
53 | }; | |
54 | ||
26d32022 PD |
55 | static const VMStateDescription vmstate_integratorcm = { |
56 | .name = "integratorcm", | |
57 | .version_id = 1, | |
58 | .minimum_version_id = 1, | |
59 | .fields = (VMStateField[]) { | |
60 | VMSTATE_UINT32(cm_osc, IntegratorCMState), | |
61 | VMSTATE_UINT32(cm_ctrl, IntegratorCMState), | |
62 | VMSTATE_UINT32(cm_lock, IntegratorCMState), | |
63 | VMSTATE_UINT32(cm_auxosc, IntegratorCMState), | |
64 | VMSTATE_UINT32(cm_sdram, IntegratorCMState), | |
65 | VMSTATE_UINT32(cm_init, IntegratorCMState), | |
66 | VMSTATE_UINT32(cm_flags, IntegratorCMState), | |
67 | VMSTATE_UINT32(cm_nvflags, IntegratorCMState), | |
68 | VMSTATE_UINT32(int_level, IntegratorCMState), | |
69 | VMSTATE_UINT32(irq_enabled, IntegratorCMState), | |
70 | VMSTATE_UINT32(fiq_enabled, IntegratorCMState), | |
71 | VMSTATE_END_OF_LIST() | |
72 | } | |
73 | }; | |
74 | ||
a8170e5e | 75 | static uint64_t integratorcm_read(void *opaque, hwaddr offset, |
71d9bc50 | 76 | unsigned size) |
b5ff1b31 | 77 | { |
257ec289 | 78 | IntegratorCMState *s = opaque; |
b5ff1b31 FB |
79 | if (offset >= 0x100 && offset < 0x200) { |
80 | /* CM_SPD */ | |
81 | if (offset >= 0x180) | |
82 | return 0; | |
83 | return integrator_spd[offset >> 2]; | |
84 | } | |
85 | switch (offset >> 2) { | |
86 | case 0: /* CM_ID */ | |
87 | return 0x411a3001; | |
88 | case 1: /* CM_PROC */ | |
89 | return 0; | |
90 | case 2: /* CM_OSC */ | |
91 | return s->cm_osc; | |
92 | case 3: /* CM_CTRL */ | |
93 | return s->cm_ctrl; | |
94 | case 4: /* CM_STAT */ | |
95 | return 0x00100000; | |
96 | case 5: /* CM_LOCK */ | |
97 | if (s->cm_lock == 0xa05f) { | |
98 | return 0x1a05f; | |
99 | } else { | |
100 | return s->cm_lock; | |
101 | } | |
102 | case 6: /* CM_LMBUSCNT */ | |
103 | /* ??? High frequency timer. */ | |
2ac71179 | 104 | hw_error("integratorcm_read: CM_LMBUSCNT"); |
b5ff1b31 FB |
105 | case 7: /* CM_AUXOSC */ |
106 | return s->cm_auxosc; | |
107 | case 8: /* CM_SDRAM */ | |
108 | return s->cm_sdram; | |
109 | case 9: /* CM_INIT */ | |
110 | return s->cm_init; | |
f53977f7 JP |
111 | case 10: /* CM_REFCNT */ |
112 | /* This register, CM_REFCNT, provides a 32-bit count value. | |
113 | * The count increments at the fixed reference clock frequency of 24MHz | |
114 | * and can be used as a real-time counter. | |
115 | */ | |
116 | return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, | |
117 | 1000) - s->cm_refcnt_offset; | |
b5ff1b31 FB |
118 | case 12: /* CM_FLAGS */ |
119 | return s->cm_flags; | |
120 | case 14: /* CM_NVFLAGS */ | |
121 | return s->cm_nvflags; | |
122 | case 16: /* CM_IRQ_STAT */ | |
123 | return s->int_level & s->irq_enabled; | |
124 | case 17: /* CM_IRQ_RSTAT */ | |
125 | return s->int_level; | |
126 | case 18: /* CM_IRQ_ENSET */ | |
127 | return s->irq_enabled; | |
128 | case 20: /* CM_SOFT_INTSET */ | |
129 | return s->int_level & 1; | |
130 | case 24: /* CM_FIQ_STAT */ | |
131 | return s->int_level & s->fiq_enabled; | |
132 | case 25: /* CM_FIQ_RSTAT */ | |
133 | return s->int_level; | |
134 | case 26: /* CM_FIQ_ENSET */ | |
135 | return s->fiq_enabled; | |
136 | case 32: /* CM_VOLTAGE_CTL0 */ | |
137 | case 33: /* CM_VOLTAGE_CTL1 */ | |
138 | case 34: /* CM_VOLTAGE_CTL2 */ | |
139 | case 35: /* CM_VOLTAGE_CTL3 */ | |
140 | /* ??? Voltage control unimplemented. */ | |
141 | return 0; | |
142 | default: | |
2ac71179 PB |
143 | hw_error("integratorcm_read: Unimplemented offset 0x%x\n", |
144 | (int)offset); | |
b5ff1b31 FB |
145 | return 0; |
146 | } | |
147 | } | |
148 | ||
257ec289 | 149 | static void integratorcm_do_remap(IntegratorCMState *s) |
b5ff1b31 | 150 | { |
563c2bf3 PM |
151 | /* Sync memory region state with CM_CTRL REMAP bit: |
152 | * bit 0 => flash at address 0; bit 1 => RAM | |
153 | */ | |
154 | memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); | |
b5ff1b31 FB |
155 | } |
156 | ||
257ec289 | 157 | static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) |
b5ff1b31 FB |
158 | { |
159 | if (value & 8) { | |
cf83f140 | 160 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
b5ff1b31 | 161 | } |
df3f457b PM |
162 | if ((s->cm_ctrl ^ value) & 1) { |
163 | /* (value & 1) != 0 means the green "MISC LED" is lit. | |
164 | * We don't have any nice place to display LEDs. printf is a bad | |
165 | * idea because Linux uses the LED as a heartbeat and the output | |
166 | * will swamp anything else on the terminal. | |
167 | */ | |
b5ff1b31 | 168 | } |
df3f457b PM |
169 | /* Note that the RESET bit [3] always reads as zero */ |
170 | s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); | |
563c2bf3 | 171 | integratorcm_do_remap(s); |
b5ff1b31 FB |
172 | } |
173 | ||
257ec289 | 174 | static void integratorcm_update(IntegratorCMState *s) |
b5ff1b31 FB |
175 | { |
176 | /* ??? The CPU irq/fiq is raised when either the core module or base PIC | |
177 | are active. */ | |
178 | if (s->int_level & (s->irq_enabled | s->fiq_enabled)) | |
2ac71179 | 179 | hw_error("Core module interrupt\n"); |
b5ff1b31 FB |
180 | } |
181 | ||
a8170e5e | 182 | static void integratorcm_write(void *opaque, hwaddr offset, |
71d9bc50 | 183 | uint64_t value, unsigned size) |
b5ff1b31 | 184 | { |
257ec289 | 185 | IntegratorCMState *s = opaque; |
b5ff1b31 FB |
186 | switch (offset >> 2) { |
187 | case 2: /* CM_OSC */ | |
188 | if (s->cm_lock == 0xa05f) | |
189 | s->cm_osc = value; | |
190 | break; | |
191 | case 3: /* CM_CTRL */ | |
192 | integratorcm_set_ctrl(s, value); | |
193 | break; | |
194 | case 5: /* CM_LOCK */ | |
195 | s->cm_lock = value & 0xffff; | |
196 | break; | |
197 | case 7: /* CM_AUXOSC */ | |
198 | if (s->cm_lock == 0xa05f) | |
199 | s->cm_auxosc = value; | |
200 | break; | |
201 | case 8: /* CM_SDRAM */ | |
202 | s->cm_sdram = value; | |
203 | break; | |
204 | case 9: /* CM_INIT */ | |
205 | /* ??? This can change the memory bus frequency. */ | |
206 | s->cm_init = value; | |
207 | break; | |
208 | case 12: /* CM_FLAGSS */ | |
209 | s->cm_flags |= value; | |
210 | break; | |
211 | case 13: /* CM_FLAGSC */ | |
212 | s->cm_flags &= ~value; | |
213 | break; | |
214 | case 14: /* CM_NVFLAGSS */ | |
215 | s->cm_nvflags |= value; | |
216 | break; | |
217 | case 15: /* CM_NVFLAGSS */ | |
218 | s->cm_nvflags &= ~value; | |
219 | break; | |
220 | case 18: /* CM_IRQ_ENSET */ | |
221 | s->irq_enabled |= value; | |
222 | integratorcm_update(s); | |
223 | break; | |
224 | case 19: /* CM_IRQ_ENCLR */ | |
225 | s->irq_enabled &= ~value; | |
226 | integratorcm_update(s); | |
227 | break; | |
228 | case 20: /* CM_SOFT_INTSET */ | |
229 | s->int_level |= (value & 1); | |
230 | integratorcm_update(s); | |
231 | break; | |
232 | case 21: /* CM_SOFT_INTCLR */ | |
233 | s->int_level &= ~(value & 1); | |
234 | integratorcm_update(s); | |
235 | break; | |
236 | case 26: /* CM_FIQ_ENSET */ | |
237 | s->fiq_enabled |= value; | |
238 | integratorcm_update(s); | |
239 | break; | |
240 | case 27: /* CM_FIQ_ENCLR */ | |
241 | s->fiq_enabled &= ~value; | |
242 | integratorcm_update(s); | |
243 | break; | |
244 | case 32: /* CM_VOLTAGE_CTL0 */ | |
245 | case 33: /* CM_VOLTAGE_CTL1 */ | |
246 | case 34: /* CM_VOLTAGE_CTL2 */ | |
247 | case 35: /* CM_VOLTAGE_CTL3 */ | |
248 | /* ??? Voltage control unimplemented. */ | |
249 | break; | |
250 | default: | |
2ac71179 PB |
251 | hw_error("integratorcm_write: Unimplemented offset 0x%x\n", |
252 | (int)offset); | |
b5ff1b31 FB |
253 | break; |
254 | } | |
255 | } | |
256 | ||
257 | /* Integrator/CM control registers. */ | |
258 | ||
71d9bc50 BC |
259 | static const MemoryRegionOps integratorcm_ops = { |
260 | .read = integratorcm_read, | |
261 | .write = integratorcm_write, | |
262 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
263 | }; |
264 | ||
a1f42e0c | 265 | static void integratorcm_init(Object *obj) |
b5ff1b31 | 266 | { |
a1f42e0c | 267 | IntegratorCMState *s = INTEGRATOR_CM(obj); |
b5ff1b31 | 268 | |
b5ff1b31 FB |
269 | s->cm_osc = 0x01000048; |
270 | /* ??? What should the high bits of this value be? */ | |
271 | s->cm_auxosc = 0x0007feff; | |
272 | s->cm_sdram = 0x00011122; | |
e9d9ee23 JJ |
273 | memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); |
274 | s->cm_init = 0x00000112; | |
275 | s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, | |
276 | 1000); | |
e9d9ee23 | 277 | |
e9d9ee23 JJ |
278 | /* ??? Save/restore. */ |
279 | } | |
280 | ||
281 | static void integratorcm_realize(DeviceState *d, Error **errp) | |
282 | { | |
283 | IntegratorCMState *s = INTEGRATOR_CM(d); | |
8720daad TH |
284 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
285 | Error *local_err = NULL; | |
286 | ||
287 | memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, | |
288 | &local_err); | |
289 | if (local_err) { | |
290 | error_propagate(errp, local_err); | |
291 | return; | |
292 | } | |
293 | ||
294 | memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, | |
295 | "integratorcm", 0x00800000); | |
296 | sysbus_init_mmio(dev, &s->iomem); | |
297 | ||
298 | integratorcm_do_remap(s); | |
e9d9ee23 | 299 | |
ee6847d1 | 300 | if (s->memsz >= 256) { |
b5ff1b31 FB |
301 | integrator_spd[31] = 64; |
302 | s->cm_sdram |= 0x10; | |
ee6847d1 | 303 | } else if (s->memsz >= 128) { |
b5ff1b31 FB |
304 | integrator_spd[31] = 32; |
305 | s->cm_sdram |= 0x0c; | |
ee6847d1 | 306 | } else if (s->memsz >= 64) { |
b5ff1b31 FB |
307 | integrator_spd[31] = 16; |
308 | s->cm_sdram |= 0x08; | |
ee6847d1 | 309 | } else if (s->memsz >= 32) { |
b5ff1b31 FB |
310 | integrator_spd[31] = 4; |
311 | s->cm_sdram |= 0x04; | |
312 | } else { | |
313 | integrator_spd[31] = 2; | |
314 | } | |
b5ff1b31 FB |
315 | } |
316 | ||
317 | /* Integrator/CP hardware emulation. */ | |
318 | /* Primary interrupt controller. */ | |
319 | ||
91b64626 AF |
320 | #define TYPE_INTEGRATOR_PIC "integrator_pic" |
321 | #define INTEGRATOR_PIC(obj) \ | |
322 | OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) | |
323 | ||
324 | typedef struct icp_pic_state { | |
325 | /*< private >*/ | |
326 | SysBusDevice parent_obj; | |
327 | /*< public >*/ | |
328 | ||
329 | MemoryRegion iomem; | |
330 | uint32_t level; | |
331 | uint32_t irq_enabled; | |
332 | uint32_t fiq_enabled; | |
333 | qemu_irq parent_irq; | |
334 | qemu_irq parent_fiq; | |
b5ff1b31 FB |
335 | } icp_pic_state; |
336 | ||
26d32022 PD |
337 | static const VMStateDescription vmstate_icp_pic = { |
338 | .name = "icp_pic", | |
339 | .version_id = 1, | |
340 | .minimum_version_id = 1, | |
341 | .fields = (VMStateField[]) { | |
342 | VMSTATE_UINT32(level, icp_pic_state), | |
343 | VMSTATE_UINT32(irq_enabled, icp_pic_state), | |
344 | VMSTATE_UINT32(fiq_enabled, icp_pic_state), | |
345 | VMSTATE_END_OF_LIST() | |
346 | } | |
347 | }; | |
348 | ||
b5ff1b31 FB |
349 | static void icp_pic_update(icp_pic_state *s) |
350 | { | |
cdbdb648 | 351 | uint32_t flags; |
b5ff1b31 | 352 | |
d537cf6c PB |
353 | flags = (s->level & s->irq_enabled); |
354 | qemu_set_irq(s->parent_irq, flags != 0); | |
355 | flags = (s->level & s->fiq_enabled); | |
356 | qemu_set_irq(s->parent_fiq, flags != 0); | |
b5ff1b31 FB |
357 | } |
358 | ||
cdbdb648 | 359 | static void icp_pic_set_irq(void *opaque, int irq, int level) |
b5ff1b31 | 360 | { |
80337b66 | 361 | icp_pic_state *s = (icp_pic_state *)opaque; |
b5ff1b31 | 362 | if (level) |
80337b66 | 363 | s->level |= 1 << irq; |
b5ff1b31 | 364 | else |
80337b66 | 365 | s->level &= ~(1 << irq); |
b5ff1b31 FB |
366 | icp_pic_update(s); |
367 | } | |
368 | ||
a8170e5e | 369 | static uint64_t icp_pic_read(void *opaque, hwaddr offset, |
61074e46 | 370 | unsigned size) |
b5ff1b31 FB |
371 | { |
372 | icp_pic_state *s = (icp_pic_state *)opaque; | |
373 | ||
b5ff1b31 FB |
374 | switch (offset >> 2) { |
375 | case 0: /* IRQ_STATUS */ | |
376 | return s->level & s->irq_enabled; | |
377 | case 1: /* IRQ_RAWSTAT */ | |
378 | return s->level; | |
379 | case 2: /* IRQ_ENABLESET */ | |
380 | return s->irq_enabled; | |
381 | case 4: /* INT_SOFTSET */ | |
382 | return s->level & 1; | |
383 | case 8: /* FRQ_STATUS */ | |
384 | return s->level & s->fiq_enabled; | |
385 | case 9: /* FRQ_RAWSTAT */ | |
386 | return s->level; | |
387 | case 10: /* FRQ_ENABLESET */ | |
388 | return s->fiq_enabled; | |
389 | case 3: /* IRQ_ENABLECLR */ | |
390 | case 5: /* INT_SOFTCLR */ | |
391 | case 11: /* FRQ_ENABLECLR */ | |
392 | default: | |
29bfb117 | 393 | printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
394 | return 0; |
395 | } | |
396 | } | |
397 | ||
a8170e5e | 398 | static void icp_pic_write(void *opaque, hwaddr offset, |
61074e46 | 399 | uint64_t value, unsigned size) |
b5ff1b31 FB |
400 | { |
401 | icp_pic_state *s = (icp_pic_state *)opaque; | |
b5ff1b31 FB |
402 | |
403 | switch (offset >> 2) { | |
404 | case 2: /* IRQ_ENABLESET */ | |
405 | s->irq_enabled |= value; | |
406 | break; | |
407 | case 3: /* IRQ_ENABLECLR */ | |
408 | s->irq_enabled &= ~value; | |
409 | break; | |
410 | case 4: /* INT_SOFTSET */ | |
411 | if (value & 1) | |
d537cf6c | 412 | icp_pic_set_irq(s, 0, 1); |
b5ff1b31 FB |
413 | break; |
414 | case 5: /* INT_SOFTCLR */ | |
415 | if (value & 1) | |
d537cf6c | 416 | icp_pic_set_irq(s, 0, 0); |
b5ff1b31 FB |
417 | break; |
418 | case 10: /* FRQ_ENABLESET */ | |
419 | s->fiq_enabled |= value; | |
420 | break; | |
421 | case 11: /* FRQ_ENABLECLR */ | |
422 | s->fiq_enabled &= ~value; | |
423 | break; | |
424 | case 0: /* IRQ_STATUS */ | |
425 | case 1: /* IRQ_RAWSTAT */ | |
426 | case 8: /* FRQ_STATUS */ | |
427 | case 9: /* FRQ_RAWSTAT */ | |
428 | default: | |
29bfb117 | 429 | printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); |
b5ff1b31 FB |
430 | return; |
431 | } | |
432 | icp_pic_update(s); | |
433 | } | |
434 | ||
61074e46 BC |
435 | static const MemoryRegionOps icp_pic_ops = { |
436 | .read = icp_pic_read, | |
437 | .write = icp_pic_write, | |
438 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
439 | }; |
440 | ||
a1f42e0c | 441 | static void icp_pic_init(Object *obj) |
b5ff1b31 | 442 | { |
a1f42e0c XZ |
443 | DeviceState *dev = DEVICE(obj); |
444 | icp_pic_state *s = INTEGRATOR_PIC(obj); | |
445 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
b5ff1b31 | 446 | |
91b64626 AF |
447 | qdev_init_gpio_in(dev, icp_pic_set_irq, 32); |
448 | sysbus_init_irq(sbd, &s->parent_irq); | |
449 | sysbus_init_irq(sbd, &s->parent_fiq); | |
a1f42e0c | 450 | memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, |
64bde0f3 | 451 | "icp-pic", 0x00800000); |
91b64626 | 452 | sysbus_init_mmio(sbd, &s->iomem); |
b5ff1b31 FB |
453 | } |
454 | ||
b5ff1b31 | 455 | /* CP control registers. */ |
0c36493e | 456 | |
ffc8542a JK |
457 | #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" |
458 | #define ICP_CONTROL_REGS(obj) \ | |
459 | OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) | |
460 | ||
461 | typedef struct ICPCtrlRegsState { | |
462 | /*< private >*/ | |
463 | SysBusDevice parent_obj; | |
464 | /*< public >*/ | |
465 | ||
466 | MemoryRegion iomem; | |
83d0cf89 JK |
467 | |
468 | qemu_irq mmc_irq; | |
469 | uint32_t intreg_state; | |
ffc8542a JK |
470 | } ICPCtrlRegsState; |
471 | ||
83d0cf89 JK |
472 | #define ICP_GPIO_MMC_WPROT "mmc-wprot" |
473 | #define ICP_GPIO_MMC_CARDIN "mmc-cardin" | |
474 | ||
475 | #define ICP_INTREG_WPROT (1 << 0) | |
476 | #define ICP_INTREG_CARDIN (1 << 3) | |
477 | ||
26d32022 PD |
478 | static const VMStateDescription vmstate_icp_control = { |
479 | .name = "icp_control", | |
480 | .version_id = 1, | |
481 | .minimum_version_id = 1, | |
482 | .fields = (VMStateField[]) { | |
483 | VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), | |
484 | VMSTATE_END_OF_LIST() | |
485 | } | |
486 | }; | |
487 | ||
a8170e5e | 488 | static uint64_t icp_control_read(void *opaque, hwaddr offset, |
0c36493e | 489 | unsigned size) |
b5ff1b31 | 490 | { |
83d0cf89 JK |
491 | ICPCtrlRegsState *s = opaque; |
492 | ||
b5ff1b31 FB |
493 | switch (offset >> 2) { |
494 | case 0: /* CP_IDFIELD */ | |
495 | return 0x41034003; | |
496 | case 1: /* CP_FLASHPROG */ | |
497 | return 0; | |
498 | case 2: /* CP_INTREG */ | |
83d0cf89 | 499 | return s->intreg_state; |
b5ff1b31 FB |
500 | case 3: /* CP_DECODE */ |
501 | return 0x11; | |
502 | default: | |
2ac71179 | 503 | hw_error("icp_control_read: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
504 | return 0; |
505 | } | |
506 | } | |
507 | ||
a8170e5e | 508 | static void icp_control_write(void *opaque, hwaddr offset, |
0c36493e | 509 | uint64_t value, unsigned size) |
b5ff1b31 | 510 | { |
83d0cf89 JK |
511 | ICPCtrlRegsState *s = opaque; |
512 | ||
b5ff1b31 | 513 | switch (offset >> 2) { |
b5ff1b31 | 514 | case 2: /* CP_INTREG */ |
83d0cf89 JK |
515 | s->intreg_state &= ~(value & ICP_INTREG_CARDIN); |
516 | qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); | |
517 | break; | |
518 | case 1: /* CP_FLASHPROG */ | |
b5ff1b31 FB |
519 | case 3: /* CP_DECODE */ |
520 | /* Nothing interesting implemented yet. */ | |
521 | break; | |
522 | default: | |
2ac71179 | 523 | hw_error("icp_control_write: Bad offset %x\n", (int)offset); |
b5ff1b31 FB |
524 | } |
525 | } | |
b5ff1b31 | 526 | |
0c36493e BC |
527 | static const MemoryRegionOps icp_control_ops = { |
528 | .read = icp_control_read, | |
529 | .write = icp_control_write, | |
530 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b5ff1b31 FB |
531 | }; |
532 | ||
83d0cf89 JK |
533 | static void icp_control_mmc_wprot(void *opaque, int line, int level) |
534 | { | |
535 | ICPCtrlRegsState *s = opaque; | |
536 | ||
537 | s->intreg_state &= ~ICP_INTREG_WPROT; | |
538 | if (level) { | |
539 | s->intreg_state |= ICP_INTREG_WPROT; | |
540 | } | |
541 | } | |
542 | ||
543 | static void icp_control_mmc_cardin(void *opaque, int line, int level) | |
544 | { | |
545 | ICPCtrlRegsState *s = opaque; | |
546 | ||
547 | /* line is released by writing to CP_INTREG */ | |
548 | if (level) { | |
549 | s->intreg_state |= ICP_INTREG_CARDIN; | |
550 | qemu_set_irq(s->mmc_irq, 1); | |
551 | } | |
552 | } | |
553 | ||
ffc8542a | 554 | static void icp_control_init(Object *obj) |
b5ff1b31 | 555 | { |
ffc8542a JK |
556 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
557 | ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); | |
83d0cf89 | 558 | DeviceState *dev = DEVICE(obj); |
b5ff1b31 | 559 | |
ffc8542a JK |
560 | memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, |
561 | "icp_ctrl_regs", 0x00800000); | |
562 | sysbus_init_mmio(sbd, &s->iomem); | |
83d0cf89 JK |
563 | |
564 | qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); | |
565 | qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, | |
566 | ICP_GPIO_MMC_CARDIN, 1); | |
567 | sysbus_init_irq(sbd, &s->mmc_irq); | |
b5ff1b31 FB |
568 | } |
569 | ||
570 | ||
b5ff1b31 FB |
571 | /* Board init. */ |
572 | ||
f93eb9ff AZ |
573 | static struct arm_boot_info integrator_binfo = { |
574 | .loader_start = 0x0, | |
575 | .board_id = 0x113, | |
576 | }; | |
577 | ||
3ef96221 | 578 | static void integratorcp_init(MachineState *machine) |
b5ff1b31 | 579 | { |
3ef96221 | 580 | ram_addr_t ram_size = machine->ram_size; |
3ef96221 MA |
581 | const char *kernel_filename = machine->kernel_filename; |
582 | const char *kernel_cmdline = machine->kernel_cmdline; | |
583 | const char *initrd_filename = machine->initrd_filename; | |
223a72f1 | 584 | Object *cpuobj; |
393a9eab | 585 | ARMCPU *cpu; |
211adf4d AK |
586 | MemoryRegion *address_space_mem = get_system_memory(); |
587 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
588 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | |
a7086888 | 589 | qemu_irq pic[32]; |
83d0cf89 | 590 | DeviceState *dev, *sic, *icp; |
a7086888 | 591 | int i; |
b5ff1b31 | 592 | |
ba1ba5cc | 593 | cpuobj = object_new(machine->cpu_type); |
223a72f1 | 594 | |
61e2f352 GB |
595 | /* By default ARM1176 CPUs have EL3 enabled. This board does not |
596 | * currently support EL3 so the CPU EL3 property is disabled before | |
597 | * realization. | |
598 | */ | |
599 | if (object_property_find(cpuobj, "has_el3", NULL)) { | |
007b0657 | 600 | object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); |
61e2f352 GB |
601 | } |
602 | ||
007b0657 | 603 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
223a72f1 GB |
604 | |
605 | cpu = ARM_CPU(cpuobj); | |
606 | ||
c8623c02 DM |
607 | memory_region_allocate_system_memory(ram, NULL, "integrator.ram", |
608 | ram_size); | |
b5ff1b31 | 609 | /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ |
1235fc06 | 610 | /* ??? RAM should repeat to fill physical memory space. */ |
b5ff1b31 | 611 | /* SDRAM at address zero*/ |
211adf4d | 612 | memory_region_add_subregion(address_space_mem, 0, ram); |
b5ff1b31 | 613 | /* And again at address 0x80000000 */ |
2c9b15ca | 614 | memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); |
211adf4d | 615 | memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); |
b5ff1b31 | 616 | |
257ec289 | 617 | dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); |
ee6847d1 | 618 | qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); |
e23a1b33 | 619 | qdev_init_nofail(dev); |
a7086888 PB |
620 | sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); |
621 | ||
91b64626 | 622 | dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, |
99d228d6 PM |
623 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), |
624 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), | |
625 | NULL); | |
a7086888 | 626 | for (i = 0; i < 32; i++) { |
067a3ddc | 627 | pic[i] = qdev_get_gpio_in(dev, i); |
a7086888 | 628 | } |
83d0cf89 | 629 | sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); |
6a824ec3 PB |
630 | sysbus_create_varargs("integrator_pit", 0x13000000, |
631 | pic[5], pic[6], pic[7], NULL); | |
a63bdb31 | 632 | sysbus_create_simple("pl031", 0x15000000, pic[8]); |
9bca0edb PM |
633 | pl011_create(0x16000000, pic[1], serial_hd(0)); |
634 | pl011_create(0x17000000, pic[2], serial_hd(1)); | |
83d0cf89 JK |
635 | icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, |
636 | qdev_get_gpio_in(sic, 3)); | |
86394e96 PB |
637 | sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); |
638 | sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); | |
b8616055 | 639 | sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); |
83d0cf89 JK |
640 | |
641 | dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); | |
642 | qdev_connect_gpio_out(dev, 0, | |
643 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); | |
644 | qdev_connect_gpio_out(dev, 1, | |
645 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); | |
646 | ||
a005d073 | 647 | if (nd_table[0].used) |
0ae18cee | 648 | smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); |
2e9bdce5 PB |
649 | |
650 | sysbus_create_simple("pl110", 0xc0000000, pic[22]); | |
b5ff1b31 | 651 | |
f93eb9ff AZ |
652 | integrator_binfo.ram_size = ram_size; |
653 | integrator_binfo.kernel_filename = kernel_filename; | |
654 | integrator_binfo.kernel_cmdline = kernel_cmdline; | |
655 | integrator_binfo.initrd_filename = initrd_filename; | |
3aaa8dfa | 656 | arm_load_kernel(cpu, &integrator_binfo); |
b5ff1b31 FB |
657 | } |
658 | ||
e264d29d | 659 | static void integratorcp_machine_init(MachineClass *mc) |
f80f9ec9 | 660 | { |
e264d29d EH |
661 | mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; |
662 | mc->init = integratorcp_init; | |
4672cbd7 | 663 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 664 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
f80f9ec9 AL |
665 | } |
666 | ||
e264d29d | 667 | DEFINE_MACHINE("integratorcp", integratorcp_machine_init) |
f80f9ec9 | 668 | |
999e12bb | 669 | static Property core_properties[] = { |
257ec289 | 670 | DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), |
999e12bb AL |
671 | DEFINE_PROP_END_OF_LIST(), |
672 | }; | |
673 | ||
674 | static void core_class_init(ObjectClass *klass, void *data) | |
675 | { | |
39bffca2 | 676 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 677 | |
39bffca2 | 678 | dc->props = core_properties; |
e9d9ee23 | 679 | dc->realize = integratorcm_realize; |
26d32022 PD |
680 | dc->vmsd = &vmstate_integratorcm; |
681 | } | |
682 | ||
683 | static void icp_pic_class_init(ObjectClass *klass, void *data) | |
684 | { | |
685 | DeviceClass *dc = DEVICE_CLASS(klass); | |
686 | ||
687 | dc->vmsd = &vmstate_icp_pic; | |
688 | } | |
689 | ||
690 | static void icp_control_class_init(ObjectClass *klass, void *data) | |
691 | { | |
692 | DeviceClass *dc = DEVICE_CLASS(klass); | |
693 | ||
694 | dc->vmsd = &vmstate_icp_control; | |
999e12bb AL |
695 | } |
696 | ||
8c43a6f0 | 697 | static const TypeInfo core_info = { |
257ec289 | 698 | .name = TYPE_INTEGRATOR_CM, |
39bffca2 | 699 | .parent = TYPE_SYS_BUS_DEVICE, |
257ec289 | 700 | .instance_size = sizeof(IntegratorCMState), |
a1f42e0c | 701 | .instance_init = integratorcm_init, |
39bffca2 | 702 | .class_init = core_class_init, |
999e12bb AL |
703 | }; |
704 | ||
8c43a6f0 | 705 | static const TypeInfo icp_pic_info = { |
91b64626 | 706 | .name = TYPE_INTEGRATOR_PIC, |
39bffca2 AL |
707 | .parent = TYPE_SYS_BUS_DEVICE, |
708 | .instance_size = sizeof(icp_pic_state), | |
a1f42e0c | 709 | .instance_init = icp_pic_init, |
26d32022 | 710 | .class_init = icp_pic_class_init, |
ee6847d1 GH |
711 | }; |
712 | ||
ffc8542a JK |
713 | static const TypeInfo icp_ctrl_regs_info = { |
714 | .name = TYPE_ICP_CONTROL_REGS, | |
715 | .parent = TYPE_SYS_BUS_DEVICE, | |
716 | .instance_size = sizeof(ICPCtrlRegsState), | |
717 | .instance_init = icp_control_init, | |
26d32022 | 718 | .class_init = icp_control_class_init, |
ffc8542a JK |
719 | }; |
720 | ||
83f7d43a | 721 | static void integratorcp_register_types(void) |
a7086888 | 722 | { |
39bffca2 AL |
723 | type_register_static(&icp_pic_info); |
724 | type_register_static(&core_info); | |
ffc8542a | 725 | type_register_static(&icp_ctrl_regs_info); |
a7086888 PB |
726 | } |
727 | ||
83f7d43a | 728 | type_init(integratorcp_register_types) |