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5aff1c07 PM |
1 | /* |
2 | * ARM V2M MPS2 board emulation, trustzone aware FPGA images | |
3 | * | |
4 | * Copyright (c) 2017 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | |
13 | * FPGA but is otherwise the same as the 2). Since the CPU itself | |
14 | * and most of the devices are in the FPGA, the details of the board | |
15 | * as seen by the guest depend significantly on the FPGA image. | |
16 | * This source file covers the following FPGA images, for TrustZone cores: | |
17 | * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 | |
23f92423 | 18 | * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 |
5aff1c07 PM |
19 | * |
20 | * Links to the TRM for the board itself and to the various Application | |
21 | * Notes which document the FPGA images can be found here: | |
22 | * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 | |
23 | * | |
24 | * Board TRM: | |
25 | * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf | |
26 | * Application Note AN505: | |
27 | * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html | |
23f92423 PM |
28 | * Application Note AN521: |
29 | * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html | |
5aff1c07 PM |
30 | * |
31 | * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide | |
32 | * (ARM ECM0601256) for the details of some of the device layout: | |
33 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html | |
23f92423 PM |
34 | * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines |
35 | * most of the device layout: | |
36 | * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf | |
37 | * | |
5aff1c07 PM |
38 | */ |
39 | ||
40 | #include "qemu/osdep.h" | |
41 | #include "qapi/error.h" | |
42 | #include "qemu/error-report.h" | |
43 | #include "hw/arm/arm.h" | |
44 | #include "hw/arm/armv7m.h" | |
45 | #include "hw/or-irq.h" | |
46 | #include "hw/boards.h" | |
47 | #include "exec/address-spaces.h" | |
48 | #include "sysemu/sysemu.h" | |
49 | #include "hw/misc/unimp.h" | |
50 | #include "hw/char/cmsdk-apb-uart.h" | |
51 | #include "hw/timer/cmsdk-apb-timer.h" | |
52 | #include "hw/misc/mps2-scc.h" | |
53 | #include "hw/misc/mps2-fpgaio.h" | |
665670aa | 54 | #include "hw/misc/tz-mpc.h" |
28e56f05 | 55 | #include "hw/misc/tz-msc.h" |
6eee5d24 | 56 | #include "hw/arm/armsse.h" |
28e56f05 | 57 | #include "hw/dma/pl080.h" |
0d49759b | 58 | #include "hw/ssi/pl022.h" |
5aff1c07 PM |
59 | #include "net/net.h" |
60 | #include "hw/core/split-irq.h" | |
61 | ||
4a30dc1c PM |
62 | #define MPS2TZ_NUMIRQ 92 |
63 | ||
5aff1c07 PM |
64 | typedef enum MPS2TZFPGAType { |
65 | FPGA_AN505, | |
4a30dc1c | 66 | FPGA_AN521, |
5aff1c07 PM |
67 | } MPS2TZFPGAType; |
68 | ||
69 | typedef struct { | |
70 | MachineClass parent; | |
71 | MPS2TZFPGAType fpga_type; | |
72 | uint32_t scc_id; | |
23f92423 | 73 | const char *armsse_type; |
5aff1c07 PM |
74 | } MPS2TZMachineClass; |
75 | ||
76 | typedef struct { | |
77 | MachineState parent; | |
78 | ||
93dbd103 | 79 | ARMSSE iotkit; |
5aff1c07 | 80 | MemoryRegion psram; |
665670aa | 81 | MemoryRegion ssram[3]; |
5aff1c07 | 82 | MemoryRegion ssram1_m; |
5aff1c07 PM |
83 | MPS2SCC scc; |
84 | MPS2FPGAIO fpgaio; | |
85 | TZPPC ppc[5]; | |
665670aa | 86 | TZMPC ssram_mpc[3]; |
0d49759b | 87 | PL022State spi[5]; |
5aff1c07 PM |
88 | UnimplementedDeviceState i2c[4]; |
89 | UnimplementedDeviceState i2s_audio; | |
519655e6 | 90 | UnimplementedDeviceState gpio[4]; |
5aff1c07 | 91 | UnimplementedDeviceState gfx; |
28e56f05 PM |
92 | PL080State dma[4]; |
93 | TZMSC msc[4]; | |
5aff1c07 PM |
94 | CMSDKAPBUART uart[5]; |
95 | SplitIRQ sec_resp_splitter; | |
96 | qemu_or_irq uart_irq_orgate; | |
519655e6 | 97 | DeviceState *lan9118; |
4a30dc1c | 98 | SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; |
5aff1c07 PM |
99 | } MPS2TZMachineState; |
100 | ||
101 | #define TYPE_MPS2TZ_MACHINE "mps2tz" | |
102 | #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") | |
23f92423 | 103 | #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") |
5aff1c07 PM |
104 | |
105 | #define MPS2TZ_MACHINE(obj) \ | |
106 | OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE) | |
107 | #define MPS2TZ_MACHINE_GET_CLASS(obj) \ | |
108 | OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE) | |
109 | #define MPS2TZ_MACHINE_CLASS(klass) \ | |
110 | OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE) | |
111 | ||
112 | /* Main SYSCLK frequency in Hz */ | |
113 | #define SYSCLK_FRQ 20000000 | |
114 | ||
5aff1c07 PM |
115 | /* Create an alias of an entire original MemoryRegion @orig |
116 | * located at @base in the memory map. | |
117 | */ | |
118 | static void make_ram_alias(MemoryRegion *mr, const char *name, | |
119 | MemoryRegion *orig, hwaddr base) | |
120 | { | |
121 | memory_region_init_alias(mr, NULL, name, orig, 0, | |
122 | memory_region_size(orig)); | |
123 | memory_region_add_subregion(get_system_memory(), base, mr); | |
124 | } | |
125 | ||
4a30dc1c PM |
126 | static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) |
127 | { | |
128 | /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ | |
129 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | |
130 | ||
131 | assert(irqno < MPS2TZ_NUMIRQ); | |
132 | ||
133 | switch (mmc->fpga_type) { | |
134 | case FPGA_AN505: | |
135 | return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); | |
136 | case FPGA_AN521: | |
137 | return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); | |
138 | default: | |
139 | g_assert_not_reached(); | |
140 | } | |
141 | } | |
142 | ||
5aff1c07 PM |
143 | /* Most of the devices in the AN505 FPGA image sit behind |
144 | * Peripheral Protection Controllers. These data structures | |
145 | * define the layout of which devices sit behind which PPCs. | |
146 | * The devfn for each port is a function which creates, configures | |
147 | * and initializes the device, returning the MemoryRegion which | |
148 | * needs to be plugged into the downstream end of the PPC port. | |
149 | */ | |
150 | typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, | |
151 | const char *name, hwaddr size); | |
152 | ||
153 | typedef struct PPCPortInfo { | |
154 | const char *name; | |
155 | MakeDevFn *devfn; | |
156 | void *opaque; | |
157 | hwaddr addr; | |
158 | hwaddr size; | |
159 | } PPCPortInfo; | |
160 | ||
161 | typedef struct PPCInfo { | |
162 | const char *name; | |
163 | PPCPortInfo ports[TZ_NUM_PORTS]; | |
164 | } PPCInfo; | |
165 | ||
166 | static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | |
167 | void *opaque, | |
168 | const char *name, hwaddr size) | |
169 | { | |
170 | /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, | |
171 | * and return a pointer to its MemoryRegion. | |
172 | */ | |
173 | UnimplementedDeviceState *uds = opaque; | |
174 | ||
fcf13ca5 TH |
175 | sysbus_init_child_obj(OBJECT(mms), name, uds, |
176 | sizeof(UnimplementedDeviceState), | |
177 | TYPE_UNIMPLEMENTED_DEVICE); | |
5aff1c07 PM |
178 | qdev_prop_set_string(DEVICE(uds), "name", name); |
179 | qdev_prop_set_uint64(DEVICE(uds), "size", size); | |
180 | object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | |
181 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); | |
182 | } | |
183 | ||
184 | static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | |
185 | const char *name, hwaddr size) | |
186 | { | |
187 | CMSDKAPBUART *uart = opaque; | |
188 | int i = uart - &mms->uart[0]; | |
5aff1c07 PM |
189 | int rxirqno = i * 2; |
190 | int txirqno = i * 2 + 1; | |
191 | int combirqno = i + 10; | |
192 | SysBusDevice *s; | |
5aff1c07 PM |
193 | DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); |
194 | ||
fcf13ca5 TH |
195 | sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), |
196 | TYPE_CMSDK_APB_UART); | |
fc38a112 | 197 | qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); |
5aff1c07 PM |
198 | qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); |
199 | object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | |
200 | s = SYS_BUS_DEVICE(uart); | |
4a30dc1c PM |
201 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); |
202 | sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); | |
5aff1c07 PM |
203 | sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); |
204 | sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | |
4a30dc1c | 205 | sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); |
5aff1c07 PM |
206 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); |
207 | } | |
208 | ||
209 | static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, | |
210 | const char *name, hwaddr size) | |
211 | { | |
212 | MPS2SCC *scc = opaque; | |
213 | DeviceState *sccdev; | |
214 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); | |
215 | ||
216 | object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); | |
217 | sccdev = DEVICE(scc); | |
218 | qdev_set_parent_bus(sccdev, sysbus_get_default()); | |
219 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | |
cb159db9 | 220 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
5aff1c07 PM |
221 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
222 | object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); | |
223 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); | |
224 | } | |
225 | ||
226 | static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | |
227 | const char *name, hwaddr size) | |
228 | { | |
229 | MPS2FPGAIO *fpgaio = opaque; | |
230 | ||
231 | object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); | |
232 | qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); | |
233 | object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); | |
234 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | |
235 | } | |
236 | ||
519655e6 PM |
237 | static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, |
238 | const char *name, hwaddr size) | |
239 | { | |
240 | SysBusDevice *s; | |
519655e6 PM |
241 | NICInfo *nd = &nd_table[0]; |
242 | ||
243 | /* In hardware this is a LAN9220; the LAN9118 is software compatible | |
244 | * except that it doesn't support the checksum-offload feature. | |
245 | */ | |
246 | qemu_check_nic_model(nd, "lan9118"); | |
247 | mms->lan9118 = qdev_create(NULL, "lan9118"); | |
248 | qdev_set_nic_properties(mms->lan9118, nd); | |
249 | qdev_init_nofail(mms->lan9118); | |
250 | ||
251 | s = SYS_BUS_DEVICE(mms->lan9118); | |
4a30dc1c | 252 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); |
519655e6 PM |
253 | return sysbus_mmio_get_region(s, 0); |
254 | } | |
255 | ||
665670aa PM |
256 | static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, |
257 | const char *name, hwaddr size) | |
258 | { | |
259 | TZMPC *mpc = opaque; | |
260 | int i = mpc - &mms->ssram_mpc[0]; | |
261 | MemoryRegion *ssram = &mms->ssram[i]; | |
262 | MemoryRegion *upstream; | |
263 | char *mpcname = g_strdup_printf("%s-mpc", name); | |
264 | static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; | |
265 | static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; | |
266 | ||
267 | memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); | |
268 | ||
fcf13ca5 TH |
269 | sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), |
270 | TYPE_TZ_MPC); | |
665670aa PM |
271 | object_property_set_link(OBJECT(mpc), OBJECT(ssram), |
272 | "downstream", &error_fatal); | |
273 | object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); | |
274 | /* Map the upstream end of the MPC into system memory */ | |
275 | upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); | |
276 | memory_region_add_subregion(get_system_memory(), rambase[i], upstream); | |
277 | /* and connect its interrupt to the IoTKit */ | |
278 | qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, | |
279 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), | |
280 | "mpcexp_status", i)); | |
281 | ||
282 | /* The first SSRAM is a special case as it has an alias; accesses to | |
283 | * the alias region at 0x00400000 must also go to the MPC upstream. | |
284 | */ | |
285 | if (i == 0) { | |
286 | make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); | |
287 | } | |
288 | ||
289 | g_free(mpcname); | |
290 | /* Return the register interface MR for our caller to map behind the PPC */ | |
291 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); | |
292 | } | |
293 | ||
28e56f05 PM |
294 | static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, |
295 | const char *name, hwaddr size) | |
296 | { | |
297 | PL080State *dma = opaque; | |
298 | int i = dma - &mms->dma[0]; | |
299 | SysBusDevice *s; | |
300 | char *mscname = g_strdup_printf("%s-msc", name); | |
301 | TZMSC *msc = &mms->msc[i]; | |
302 | DeviceState *iotkitdev = DEVICE(&mms->iotkit); | |
303 | MemoryRegion *msc_upstream; | |
304 | MemoryRegion *msc_downstream; | |
305 | ||
306 | /* | |
307 | * Each DMA device is a PL081 whose transaction master interface | |
308 | * is guarded by a Master Security Controller. The downstream end of | |
309 | * the MSC connects to the IoTKit AHB Slave Expansion port, so the | |
310 | * DMA devices can see all devices and memory that the CPU does. | |
311 | */ | |
312 | sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); | |
313 | msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); | |
314 | object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), | |
315 | "downstream", &error_fatal); | |
316 | object_property_set_link(OBJECT(msc), OBJECT(mms), | |
317 | "idau", &error_fatal); | |
318 | object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); | |
319 | ||
320 | qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, | |
321 | qdev_get_gpio_in_named(iotkitdev, | |
322 | "mscexp_status", i)); | |
323 | qdev_connect_gpio_out_named(iotkitdev, "mscexp_clear", i, | |
324 | qdev_get_gpio_in_named(DEVICE(msc), | |
325 | "irq_clear", 0)); | |
326 | qdev_connect_gpio_out_named(iotkitdev, "mscexp_ns", i, | |
327 | qdev_get_gpio_in_named(DEVICE(msc), | |
328 | "cfg_nonsec", 0)); | |
329 | qdev_connect_gpio_out(DEVICE(&mms->sec_resp_splitter), | |
330 | ARRAY_SIZE(mms->ppc) + i, | |
331 | qdev_get_gpio_in_named(DEVICE(msc), | |
332 | "cfg_sec_resp", 0)); | |
333 | msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); | |
334 | ||
335 | sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); | |
336 | object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), | |
337 | "downstream", &error_fatal); | |
338 | object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); | |
339 | ||
340 | s = SYS_BUS_DEVICE(dma); | |
341 | /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ | |
4a30dc1c PM |
342 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); |
343 | sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); | |
344 | sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); | |
28e56f05 | 345 | |
7081e9b6 | 346 | g_free(mscname); |
28e56f05 PM |
347 | return sysbus_mmio_get_region(s, 0); |
348 | } | |
349 | ||
0d49759b PM |
350 | static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, |
351 | const char *name, hwaddr size) | |
352 | { | |
353 | /* | |
354 | * The AN505 has five PL022 SPI controllers. | |
355 | * One of these should have the LCD controller behind it; the others | |
356 | * are connected only to the FPGA's "general purpose SPI connector" | |
357 | * or "shield" expansion connectors. | |
358 | * Note that if we do implement devices behind SPI, the chip select | |
359 | * lines are set via the "MISC" register in the MPS2 FPGAIO device. | |
360 | */ | |
361 | PL022State *spi = opaque; | |
362 | int i = spi - &mms->spi[0]; | |
0d49759b PM |
363 | SysBusDevice *s; |
364 | ||
365 | sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(mms->spi[0]), | |
366 | TYPE_PL022); | |
367 | object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); | |
368 | s = SYS_BUS_DEVICE(spi); | |
4a30dc1c | 369 | sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); |
0d49759b PM |
370 | return sysbus_mmio_get_region(s, 0); |
371 | } | |
372 | ||
5aff1c07 PM |
373 | static void mps2tz_common_init(MachineState *machine) |
374 | { | |
375 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | |
4a30dc1c | 376 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); |
5aff1c07 PM |
377 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
378 | MemoryRegion *system_memory = get_system_memory(); | |
379 | DeviceState *iotkitdev; | |
380 | DeviceState *dev_splitter; | |
381 | int i; | |
382 | ||
383 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | |
384 | error_report("This board can only be used with CPU %s", | |
385 | mc->default_cpu_type); | |
386 | exit(1); | |
387 | } | |
388 | ||
fcf13ca5 | 389 | sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, |
23f92423 | 390 | sizeof(mms->iotkit), mmc->armsse_type); |
5aff1c07 PM |
391 | iotkitdev = DEVICE(&mms->iotkit); |
392 | object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | |
393 | "memory", &error_abort); | |
4a30dc1c | 394 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); |
5aff1c07 PM |
395 | qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); |
396 | object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", | |
397 | &error_fatal); | |
398 | ||
4a30dc1c PM |
399 | /* |
400 | * The AN521 needs us to create splitters to feed the IRQ inputs | |
401 | * for each CPU in the SSE-200 from each device in the board. | |
402 | */ | |
403 | if (mmc->fpga_type == FPGA_AN521) { | |
404 | for (i = 0; i < MPS2TZ_NUMIRQ; i++) { | |
405 | char *name = g_strdup_printf("mps2-irq-splitter%d", i); | |
406 | SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; | |
407 | ||
408 | object_initialize_child(OBJECT(machine), name, | |
409 | splitter, sizeof(*splitter), | |
410 | TYPE_SPLIT_IRQ, &error_fatal, NULL); | |
411 | g_free(name); | |
412 | ||
413 | object_property_set_int(OBJECT(splitter), 2, "num-lines", | |
414 | &error_fatal); | |
415 | object_property_set_bool(OBJECT(splitter), true, "realized", | |
416 | &error_fatal); | |
417 | qdev_connect_gpio_out(DEVICE(splitter), 0, | |
418 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), | |
419 | "EXP_IRQ", i)); | |
420 | qdev_connect_gpio_out(DEVICE(splitter), 1, | |
421 | qdev_get_gpio_in_named(DEVICE(&mms->iotkit), | |
422 | "EXP_CPU1_IRQ", i)); | |
423 | } | |
424 | } | |
425 | ||
5aff1c07 | 426 | /* The sec_resp_cfg output from the IoTKit must be split into multiple |
28e56f05 | 427 | * lines, one for each of the PPCs we create here, plus one per MSC. |
5aff1c07 PM |
428 | */ |
429 | object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter), | |
430 | TYPE_SPLIT_IRQ); | |
431 | object_property_add_child(OBJECT(machine), "sec-resp-splitter", | |
432 | OBJECT(&mms->sec_resp_splitter), &error_abort); | |
28e56f05 PM |
433 | object_property_set_int(OBJECT(&mms->sec_resp_splitter), |
434 | ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc), | |
5aff1c07 PM |
435 | "num-lines", &error_fatal); |
436 | object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true, | |
437 | "realized", &error_fatal); | |
438 | dev_splitter = DEVICE(&mms->sec_resp_splitter); | |
439 | qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, | |
440 | qdev_get_gpio_in(dev_splitter, 0)); | |
441 | ||
442 | /* The IoTKit sets up much of the memory layout, including | |
443 | * the aliases between secure and non-secure regions in the | |
444 | * address space. The FPGA itself contains: | |
445 | * | |
446 | * 0x00000000..0x003fffff SSRAM1 | |
447 | * 0x00400000..0x007fffff alias of SSRAM1 | |
448 | * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 | |
449 | * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices | |
450 | * 0x80000000..0x80ffffff 16MB PSRAM | |
451 | */ | |
452 | ||
453 | /* The FPGA images have an odd combination of different RAMs, | |
454 | * because in hardware they are different implementations and | |
455 | * connected to different buses, giving varying performance/size | |
456 | * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | |
457 | * call the 16MB our "system memory", as it's the largest lump. | |
458 | */ | |
459 | memory_region_allocate_system_memory(&mms->psram, | |
460 | NULL, "mps.ram", 0x01000000); | |
461 | memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); | |
462 | ||
5aff1c07 PM |
463 | /* The overflow IRQs for all UARTs are ORed together. |
464 | * Tx, Rx and "combined" IRQs are sent to the NVIC separately. | |
465 | * Create the OR gate for this. | |
466 | */ | |
467 | object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate), | |
468 | TYPE_OR_IRQ); | |
469 | object_property_add_child(OBJECT(mms), "uart-irq-orgate", | |
470 | OBJECT(&mms->uart_irq_orgate), &error_abort); | |
471 | object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines", | |
472 | &error_fatal); | |
473 | object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true, | |
474 | "realized", &error_fatal); | |
475 | qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, | |
4a30dc1c | 476 | get_sse_irq_in(mms, 15)); |
5aff1c07 PM |
477 | |
478 | /* Most of the devices in the FPGA are behind Peripheral Protection | |
479 | * Controllers. The required order for initializing things is: | |
480 | * + initialize the PPC | |
481 | * + initialize, configure and realize downstream devices | |
482 | * + connect downstream device MemoryRegions to the PPC | |
483 | * + realize the PPC | |
484 | * + map the PPC's MemoryRegions to the places in the address map | |
485 | * where the downstream devices should appear | |
486 | * + wire up the PPC's control lines to the IoTKit object | |
487 | */ | |
488 | ||
489 | const PPCInfo ppcs[] = { { | |
490 | .name = "apb_ppcexp0", | |
491 | .ports = { | |
665670aa PM |
492 | { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, |
493 | { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, | |
494 | { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, | |
5aff1c07 PM |
495 | }, |
496 | }, { | |
497 | .name = "apb_ppcexp1", | |
498 | .ports = { | |
0d49759b PM |
499 | { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, |
500 | { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, | |
501 | { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, | |
502 | { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, | |
503 | { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, | |
5aff1c07 PM |
504 | { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, |
505 | { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, | |
506 | { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | |
507 | { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | |
508 | { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | |
509 | { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | |
510 | { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | |
511 | { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | |
512 | { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | |
513 | }, | |
514 | }, { | |
515 | .name = "apb_ppcexp2", | |
516 | .ports = { | |
517 | { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 }, | |
518 | { "i2s-audio", make_unimp_dev, &mms->i2s_audio, | |
519 | 0x40301000, 0x1000 }, | |
520 | { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 }, | |
521 | }, | |
522 | }, { | |
523 | .name = "ahb_ppcexp0", | |
524 | .ports = { | |
525 | { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 }, | |
526 | { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 }, | |
527 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | |
528 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | |
529 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | |
519655e6 | 530 | { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, |
5aff1c07 PM |
531 | }, |
532 | }, { | |
533 | .name = "ahb_ppcexp1", | |
534 | .ports = { | |
28e56f05 PM |
535 | { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, |
536 | { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, | |
537 | { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, | |
538 | { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, | |
5aff1c07 PM |
539 | }, |
540 | }, | |
541 | }; | |
542 | ||
543 | for (i = 0; i < ARRAY_SIZE(ppcs); i++) { | |
544 | const PPCInfo *ppcinfo = &ppcs[i]; | |
545 | TZPPC *ppc = &mms->ppc[i]; | |
546 | DeviceState *ppcdev; | |
547 | int port; | |
548 | char *gpioname; | |
549 | ||
fcf13ca5 TH |
550 | sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, |
551 | sizeof(TZPPC), TYPE_TZ_PPC); | |
5aff1c07 PM |
552 | ppcdev = DEVICE(ppc); |
553 | ||
554 | for (port = 0; port < TZ_NUM_PORTS; port++) { | |
555 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | |
556 | MemoryRegion *mr; | |
557 | char *portname; | |
558 | ||
559 | if (!pinfo->devfn) { | |
560 | continue; | |
561 | } | |
562 | ||
563 | mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); | |
564 | portname = g_strdup_printf("port[%d]", port); | |
565 | object_property_set_link(OBJECT(ppc), OBJECT(mr), | |
566 | portname, &error_fatal); | |
567 | g_free(portname); | |
568 | } | |
569 | ||
570 | object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); | |
571 | ||
572 | for (port = 0; port < TZ_NUM_PORTS; port++) { | |
573 | const PPCPortInfo *pinfo = &ppcinfo->ports[port]; | |
574 | ||
575 | if (!pinfo->devfn) { | |
576 | continue; | |
577 | } | |
578 | sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr); | |
579 | ||
580 | gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name); | |
581 | qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | |
582 | qdev_get_gpio_in_named(ppcdev, | |
583 | "cfg_nonsec", | |
584 | port)); | |
585 | g_free(gpioname); | |
586 | gpioname = g_strdup_printf("%s_ap", ppcinfo->name); | |
587 | qdev_connect_gpio_out_named(iotkitdev, gpioname, port, | |
588 | qdev_get_gpio_in_named(ppcdev, | |
589 | "cfg_ap", port)); | |
590 | g_free(gpioname); | |
591 | } | |
592 | ||
593 | gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name); | |
594 | qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | |
595 | qdev_get_gpio_in_named(ppcdev, | |
596 | "irq_enable", 0)); | |
597 | g_free(gpioname); | |
598 | gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name); | |
599 | qdev_connect_gpio_out_named(iotkitdev, gpioname, 0, | |
600 | qdev_get_gpio_in_named(ppcdev, | |
601 | "irq_clear", 0)); | |
602 | g_free(gpioname); | |
603 | gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name); | |
604 | qdev_connect_gpio_out_named(ppcdev, "irq", 0, | |
605 | qdev_get_gpio_in_named(iotkitdev, | |
606 | gpioname, 0)); | |
607 | g_free(gpioname); | |
608 | ||
609 | qdev_connect_gpio_out(dev_splitter, i, | |
610 | qdev_get_gpio_in_named(ppcdev, | |
611 | "cfg_sec_resp", 0)); | |
612 | } | |
613 | ||
5aff1c07 PM |
614 | create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); |
615 | ||
616 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | |
617 | } | |
618 | ||
28e56f05 PM |
619 | static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, |
620 | int *iregion, bool *exempt, bool *ns, bool *nsc) | |
621 | { | |
622 | /* | |
623 | * The MPS2 TZ FPGA images have IDAUs in them which are connected to | |
624 | * the Master Security Controllers. Thes have the same logic as | |
625 | * is used by the IoTKit for the IDAU connected to the CPU, except | |
626 | * that MSCs don't care about the NSC attribute. | |
627 | */ | |
628 | int region = extract32(address, 28, 4); | |
629 | ||
630 | *ns = !(region & 1); | |
631 | *nsc = false; | |
632 | /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */ | |
633 | *exempt = (address & 0xeff00000) == 0xe0000000; | |
634 | *iregion = region; | |
635 | } | |
636 | ||
5aff1c07 PM |
637 | static void mps2tz_class_init(ObjectClass *oc, void *data) |
638 | { | |
639 | MachineClass *mc = MACHINE_CLASS(oc); | |
28e56f05 | 640 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); |
5aff1c07 PM |
641 | |
642 | mc->init = mps2tz_common_init; | |
28e56f05 | 643 | iic->check = mps2_tz_idau_check; |
5aff1c07 PM |
644 | } |
645 | ||
646 | static void mps2tz_an505_class_init(ObjectClass *oc, void *data) | |
647 | { | |
648 | MachineClass *mc = MACHINE_CLASS(oc); | |
649 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | |
650 | ||
651 | mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33"; | |
23f92423 PM |
652 | mc->default_cpus = 1; |
653 | mc->min_cpus = mc->default_cpus; | |
654 | mc->max_cpus = mc->default_cpus; | |
5aff1c07 PM |
655 | mmc->fpga_type = FPGA_AN505; |
656 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | |
cb159db9 | 657 | mmc->scc_id = 0x41045050; |
23f92423 PM |
658 | mmc->armsse_type = TYPE_IOTKIT; |
659 | } | |
660 | ||
661 | static void mps2tz_an521_class_init(ObjectClass *oc, void *data) | |
662 | { | |
663 | MachineClass *mc = MACHINE_CLASS(oc); | |
664 | MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | |
665 | ||
666 | mc->desc = "ARM MPS2 with AN521 FPGA image for dual Cortex-M33"; | |
667 | mc->default_cpus = 2; | |
668 | mc->min_cpus = mc->default_cpus; | |
669 | mc->max_cpus = mc->default_cpus; | |
670 | mmc->fpga_type = FPGA_AN521; | |
671 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); | |
672 | mmc->scc_id = 0x41045210; | |
673 | mmc->armsse_type = TYPE_SSE200; | |
5aff1c07 PM |
674 | } |
675 | ||
676 | static const TypeInfo mps2tz_info = { | |
677 | .name = TYPE_MPS2TZ_MACHINE, | |
678 | .parent = TYPE_MACHINE, | |
679 | .abstract = true, | |
680 | .instance_size = sizeof(MPS2TZMachineState), | |
681 | .class_size = sizeof(MPS2TZMachineClass), | |
682 | .class_init = mps2tz_class_init, | |
28e56f05 PM |
683 | .interfaces = (InterfaceInfo[]) { |
684 | { TYPE_IDAU_INTERFACE }, | |
685 | { } | |
686 | }, | |
5aff1c07 PM |
687 | }; |
688 | ||
689 | static const TypeInfo mps2tz_an505_info = { | |
690 | .name = TYPE_MPS2TZ_AN505_MACHINE, | |
691 | .parent = TYPE_MPS2TZ_MACHINE, | |
692 | .class_init = mps2tz_an505_class_init, | |
693 | }; | |
694 | ||
23f92423 PM |
695 | static const TypeInfo mps2tz_an521_info = { |
696 | .name = TYPE_MPS2TZ_AN521_MACHINE, | |
697 | .parent = TYPE_MPS2TZ_MACHINE, | |
698 | .class_init = mps2tz_an521_class_init, | |
699 | }; | |
700 | ||
5aff1c07 PM |
701 | static void mps2tz_machine_init(void) |
702 | { | |
703 | type_register_static(&mps2tz_info); | |
704 | type_register_static(&mps2tz_an505_info); | |
23f92423 | 705 | type_register_static(&mps2tz_an521_info); |
5aff1c07 PM |
706 | } |
707 | ||
708 | type_init(mps2tz_machine_init); |