[mirror_qemu.git] / hw / arm / mps2.c

/*
 * ARM V2M MPS2 board emulation.
 *
 * Copyright (c) 2017 Linaro Limited
 * Written by Peter Maydell
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 or
 *  (at your option) any later version.
 */

/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
 * FPGA but is otherwise the same as the 2). Since the CPU itself
 * and most of the devices are in the FPGA, the details of the board
 * as seen by the guest depend significantly on the FPGA image.
 * We model the following FPGA images:
 *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
 *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
 *
 * Links to the TRM for the board itself and to the various Application
 * Notes which document the FPGA images can be found here:
 *   https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/arm/arm.h"
#include "hw/arm/armv7m.h"
#include "hw/or-irq.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/misc/unimp.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/timer/cmsdk-apb-timer.h"
#include "hw/misc/mps2-scc.h"
#include "hw/devices.h"
#include "net/net.h"

typedef enum MPS2FPGAType {
    FPGA_AN385,
    FPGA_AN511,
} MPS2FPGAType;

typedef struct {
    MachineClass parent;
    MPS2FPGAType fpga_type;
    const char *cpu_model;
    uint32_t scc_id;
} MPS2MachineClass;

typedef struct {
    MachineState parent;

    ARMv7MState armv7m;
    MemoryRegion psram;
    MemoryRegion ssram1;
    MemoryRegion ssram1_m;
    MemoryRegion ssram23;
    MemoryRegion ssram23_m;
    MemoryRegion blockram;
    MemoryRegion blockram_m1;
    MemoryRegion blockram_m2;
    MemoryRegion blockram_m3;
    MemoryRegion sram;
    MPS2SCC scc;
} MPS2MachineState;

#define TYPE_MPS2_MACHINE "mps2"
#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")

#define MPS2_MACHINE(obj)                                       \
    OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
#define MPS2_MACHINE_GET_CLASS(obj) \
    OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
#define MPS2_MACHINE_CLASS(klass) \
    OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)

/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 25000000

/* Initialize the auxiliary RAM region @mr and map it into
 * the memory map at @base.
 */
static void make_ram(MemoryRegion *mr, const char *name,
                     hwaddr base, hwaddr size)
{
    memory_region_init_ram(mr, NULL, name, size, &error_fatal);
    memory_region_add_subregion(get_system_memory(), base, mr);
}

/* Create an alias of an entire original MemoryRegion @orig
 * located at @base in the memory map.
 */
static void make_ram_alias(MemoryRegion *mr, const char *name,
                           MemoryRegion *orig, hwaddr base)
{
    memory_region_init_alias(mr, NULL, name, orig, 0,
                             memory_region_size(orig));
    memory_region_add_subregion(get_system_memory(), base, mr);
}

static void mps2_common_init(MachineState *machine)
{
    MPS2MachineState *mms = MPS2_MACHINE(machine);
    MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
    MemoryRegion *system_memory = get_system_memory();
    DeviceState *armv7m, *sccdev;

    if (!machine->cpu_model) {
        machine->cpu_model = mmc->cpu_model;
    }

    if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
        error_report("This board can only be used with CPU %s", mmc->cpu_model);
        exit(1);
    }

    /* The FPGA images have an odd combination of different RAMs,
     * because in hardware they are different implementations and
     * connected to different buses, giving varying performance/size
     * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
     * call the 16MB our "system memory", as it's the largest lump.
     *
     * Common to both boards:
     *  0x21000000..0x21ffffff : PSRAM (16MB)
     * AN385 only:
     *  0x00000000 .. 0x003fffff : ZBT SSRAM1
     *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
     *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
     *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
     *  0x01000000 .. 0x01003fff : block RAM (16K)
     *  0x01004000 .. 0x01007fff : mirror of above
     *  0x01008000 .. 0x0100bfff : mirror of above
     *  0x0100c000 .. 0x0100ffff : mirror of above
     * AN511 only:
     *  0x00000000 .. 0x0003ffff : FPGA block RAM
     *  0x00400000 .. 0x007fffff : ZBT SSRAM1
     *  0x20000000 .. 0x2001ffff : SRAM
     *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
     *
     * The AN385 has a feature where the lowest 16K can be mapped
     * either to the bottom of the ZBT SSRAM1 or to the block RAM.
     * This is of no use for QEMU so we don't implement it (as if
     * zbt_boot_ctrl is always zero).
     */
    memory_region_allocate_system_memory(&mms->psram,
                                         NULL, "mps.ram", 0x1000000);
    memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);

    switch (mmc->fpga_type) {
    case FPGA_AN385:
        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
                       &mms->ssram23, 0x20400000);
        make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
        make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
                       &mms->blockram, 0x01004000);
        make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
                       &mms->blockram, 0x01008000);
        make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
                       &mms->blockram, 0x0100c000);
        break;
    case FPGA_AN511:
        make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
        make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
        make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
        make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
        break;
    default:
        g_assert_not_reached();
    }

    object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M);
    armv7m = DEVICE(&mms->armv7m);
    qdev_set_parent_bus(armv7m, sysbus_get_default());
    switch (mmc->fpga_type) {
    case FPGA_AN385:
        qdev_prop_set_uint32(armv7m, "num-irq", 32);
        break;
    case FPGA_AN511:
        qdev_prop_set_uint32(armv7m, "num-irq", 64);
        break;
    default:
        g_assert_not_reached();
    }
    qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
    object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
                             "memory", &error_abort);
    object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
                             &error_fatal);

    create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
    create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
    create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
    create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
    create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
    create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
    /* These three ranges all cover multiple devices; we may implement
     * some of them below (in which case the real device takes precedence
     * over the unimplemented-region mapping).
     */
    create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
                                0x40000000, 0x00010000);
    create_unimplemented_device("CMSDK peripheral region @0x40010000",
                                0x40010000, 0x00010000);
    create_unimplemented_device("Extra peripheral region @0x40020000",
                                0x40020000, 0x00010000);
    create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
    create_unimplemented_device("VGA", 0x41000000, 0x0200000);

    switch (mmc->fpga_type) {
    case FPGA_AN385:
    {
        /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
         * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
         */
        Object *orgate;
        DeviceState *orgate_dev;
        int i;

        orgate = object_new(TYPE_OR_IRQ);
        object_property_set_int(orgate, 6, "num-lines", &error_fatal);
        object_property_set_bool(orgate, true, "realized", &error_fatal);
        orgate_dev = DEVICE(orgate);
        qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));

        for (i = 0; i < 5; i++) {
            static const hwaddr uartbase[] = {0x40004000, 0x40005000,
                                              0x40006000, 0x40007000,
                                              0x40009000};
            Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
            /* RX irq number; TX irq is always one greater */
            static const int uartirq[] = {0, 2, 4, 18, 20};
            qemu_irq txovrint = NULL, rxovrint = NULL;

            if (i < 3) {
                txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
                rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
            }

            cmsdk_apb_uart_create(uartbase[i],
                                  qdev_get_gpio_in(armv7m, uartirq[i] + 1),
                                  qdev_get_gpio_in(armv7m, uartirq[i]),
                                  txovrint, rxovrint,
                                  NULL,
                                  uartchr, SYSCLK_FRQ);
        }
        break;
    }
    case FPGA_AN511:
    {
        /* The overflow IRQs for all UARTs are ORed together.
         * Tx and Rx IRQs for each UART are ORed together.
         */
        Object *orgate;
        DeviceState *orgate_dev;
        int i;

        orgate = object_new(TYPE_OR_IRQ);
        object_property_set_int(orgate, 10, "num-lines", &error_fatal);
        object_property_set_bool(orgate, true, "realized", &error_fatal);
        orgate_dev = DEVICE(orgate);
        qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));

        for (i = 0; i < 5; i++) {
            /* system irq numbers for the combined tx/rx for each UART */
            static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
            static const hwaddr uartbase[] = {0x40004000, 0x40005000,
                                              0x4002c000, 0x4002d000,
                                              0x4002e000};
            Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
            Object *txrx_orgate;
            DeviceState *txrx_orgate_dev;

            txrx_orgate = object_new(TYPE_OR_IRQ);
            object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
            object_property_set_bool(txrx_orgate, true, "realized",
                                     &error_fatal);
            txrx_orgate_dev = DEVICE(txrx_orgate);
            qdev_connect_gpio_out(txrx_orgate_dev, 0,
                                  qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
            cmsdk_apb_uart_create(uartbase[i],
                                  qdev_get_gpio_in(txrx_orgate_dev, 0),
                                  qdev_get_gpio_in(txrx_orgate_dev, 1),
                                  qdev_get_gpio_in(orgate_dev, i * 2),
                                  qdev_get_gpio_in(orgate_dev, i * 2 + 1),
                                  NULL,
                                  uartchr, SYSCLK_FRQ);
        }
        break;
    }
    default:
        g_assert_not_reached();
    }

    cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
    cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);

    object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
    sccdev = DEVICE(&mms->scc);
    qdev_set_parent_bus(sccdev, sysbus_get_default());
    qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
    qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
    qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
    object_property_set_bool(OBJECT(&mms->scc), true, "realized",
                             &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);

    /* In hardware this is a LAN9220; the LAN9118 is software compatible
     * except that it doesn't support the checksum-offload feature.
     */
    lan9118_init(&nd_table[0], 0x40200000,
                 qdev_get_gpio_in(armv7m,
                                  mmc->fpga_type == FPGA_AN385 ? 13 : 47));

    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;

    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
                       0x400000);
}

static void mps2_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->init = mps2_common_init;
    mc->max_cpus = 1;
}

static void mps2_an385_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);
    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);

    mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
    mmc->fpga_type = FPGA_AN385;
    mmc->cpu_model = "cortex-m3";
    mmc->scc_id = 0x41040000 | (385 << 4);
}

static void mps2_an511_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);
    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);

    mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
    mmc->fpga_type = FPGA_AN511;
    mmc->cpu_model = "cortex-m3";
    mmc->scc_id = 0x4104000 | (511 << 4);
}

static const TypeInfo mps2_info = {
    .name = TYPE_MPS2_MACHINE,
    .parent = TYPE_MACHINE,
    .abstract = true,
    .instance_size = sizeof(MPS2MachineState),
    .class_size = sizeof(MPS2MachineClass),
    .class_init = mps2_class_init,
};

static const TypeInfo mps2_an385_info = {
    .name = TYPE_MPS2_AN385_MACHINE,
    .parent = TYPE_MPS2_MACHINE,
    .class_init = mps2_an385_class_init,
};

static const TypeInfo mps2_an511_info = {
    .name = TYPE_MPS2_AN511_MACHINE,
    .parent = TYPE_MPS2_MACHINE,
    .class_init = mps2_an511_class_init,
};

static void mps2_machine_init(void)
{
    type_register_static(&mps2_info);
    type_register_static(&mps2_an385_info);
    type_register_static(&mps2_an511_info);
}

type_init(mps2_machine_init);
Commit	Line	Data
2eb5578b PM	1	/*
	2	* ARM V2M MPS2 board emulation.
	3	*
	4	* Copyright (c) 2017 Linaro Limited
	5	* Written by Peter Maydell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 or
	9	* (at your option) any later version.
	10	*/
	11
	12	/* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
	13	* FPGA but is otherwise the same as the 2). Since the CPU itself
	14	* and most of the devices are in the FPGA, the details of the board
	15	* as seen by the guest depend significantly on the FPGA image.
	16	* We model the following FPGA images:
	17	* "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
	18	* "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
	19	*
	20	* Links to the TRM for the board itself and to the various Application
	21	* Notes which document the FPGA images can be found here:
	22	* https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system
	23	*/
	24
	25	#include "qemu/osdep.h"
	26	#include "qapi/error.h"
	27	#include "qemu/error-report.h"
	28	#include "hw/arm/arm.h"
	29	#include "hw/arm/armv7m.h"
977a15f4	30	#include "hw/or-irq.h"
2eb5578b PM	31	#include "hw/boards.h"
2eb5578b PM	32	#include "exec/address-spaces.h"
977a15f4	33	#include "sysemu/sysemu.h"
2eb5578b	34	#include "hw/misc/unimp.h"
977a15f4	35	#include "hw/char/cmsdk-apb-uart.h"
3d53904a	36	#include "hw/timer/cmsdk-apb-timer.h"
6dbdf4ec	37	#include "hw/misc/mps2-scc.h"
35873939 PM	38	#include "hw/devices.h"
35873939 PM	39	#include "net/net.h"
2eb5578b PM	40
	41	typedef enum MPS2FPGAType {
	42	FPGA_AN385,
	43	FPGA_AN511,
	44	} MPS2FPGAType;
	45
	46	typedef struct {
	47	MachineClass parent;
	48	MPS2FPGAType fpga_type;
	49	const char *cpu_model;
6dbdf4ec	50	uint32_t scc_id;
2eb5578b PM	51	} MPS2MachineClass;
	52
	53	typedef struct {
	54	MachineState parent;
	55
	56	ARMv7MState armv7m;
	57	MemoryRegion psram;
	58	MemoryRegion ssram1;
	59	MemoryRegion ssram1_m;
	60	MemoryRegion ssram23;
	61	MemoryRegion ssram23_m;
	62	MemoryRegion blockram;
	63	MemoryRegion blockram_m1;
	64	MemoryRegion blockram_m2;
	65	MemoryRegion blockram_m3;
	66	MemoryRegion sram;
6dbdf4ec	67	MPS2SCC scc;
2eb5578b PM	68	} MPS2MachineState;
	69
	70	#define TYPE_MPS2_MACHINE "mps2"
	71	#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
	72	#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
	73
	74	#define MPS2_MACHINE(obj) \
	75	OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE)
	76	#define MPS2_MACHINE_GET_CLASS(obj) \
	77	OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE)
	78	#define MPS2_MACHINE_CLASS(klass) \
	79	OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE)
	80
	81	/* Main SYSCLK frequency in Hz */
	82	#define SYSCLK_FRQ 25000000
	83
	84	/* Initialize the auxiliary RAM region @mr and map it into
	85	* the memory map at @base.
	86	*/
	87	static void make_ram(MemoryRegion mr, const char name,
	88	hwaddr base, hwaddr size)
	89	{
	90	memory_region_init_ram(mr, NULL, name, size, &error_fatal);
	91	memory_region_add_subregion(get_system_memory(), base, mr);
	92	}
	93
	94	/* Create an alias of an entire original MemoryRegion @orig
	95	* located at @base in the memory map.
	96	*/
	97	static void make_ram_alias(MemoryRegion mr, const char name,
	98	MemoryRegion *orig, hwaddr base)
	99	{
	100	memory_region_init_alias(mr, NULL, name, orig, 0,
	101	memory_region_size(orig));
	102	memory_region_add_subregion(get_system_memory(), base, mr);
	103	}
	104
	105	static void mps2_common_init(MachineState *machine)
	106	{
	107	MPS2MachineState *mms = MPS2_MACHINE(machine);
	108	MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);
	109	MemoryRegion *system_memory = get_system_memory();
6dbdf4ec	110	DeviceState armv7m, sccdev;
2eb5578b PM	111
	112	if (!machine->cpu_model) {
	113	machine->cpu_model = mmc->cpu_model;
	114	}
	115
	116	if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {
	117	error_report("This board can only be used with CPU %s", mmc->cpu_model);
	118	exit(1);
	119	}
	120
	121	/* The FPGA images have an odd combination of different RAMs,
	122	* because in hardware they are different implementations and
	123	* connected to different buses, giving varying performance/size
	124	* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
	125	* call the 16MB our "system memory", as it's the largest lump.
	126	*
	127	* Common to both boards:
	128	* 0x21000000..0x21ffffff : PSRAM (16MB)
	129	* AN385 only:
	130	* 0x00000000 .. 0x003fffff : ZBT SSRAM1
	131	* 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
	132	* 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
	133	* 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
	134	* 0x01000000 .. 0x01003fff : block RAM (16K)
	135	* 0x01004000 .. 0x01007fff : mirror of above
	136	* 0x01008000 .. 0x0100bfff : mirror of above
	137	* 0x0100c000 .. 0x0100ffff : mirror of above
	138	* AN511 only:
	139	* 0x00000000 .. 0x0003ffff : FPGA block RAM
	140	* 0x00400000 .. 0x007fffff : ZBT SSRAM1
	141	* 0x20000000 .. 0x2001ffff : SRAM
	142	* 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
	143	*
	144	* The AN385 has a feature where the lowest 16K can be mapped
	145	* either to the bottom of the ZBT SSRAM1 or to the block RAM.
	146	* This is of no use for QEMU so we don't implement it (as if
	147	* zbt_boot_ctrl is always zero).
	148	*/
	149	memory_region_allocate_system_memory(&mms->psram,
	150	NULL, "mps.ram", 0x1000000);
	151	memory_region_add_subregion(system_memory, 0x21000000, &mms->psram);
	152
	153	switch (mmc->fpga_type) {
	154	case FPGA_AN385:
	155	make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
	156	make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
	157	make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
	158	make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
	159	&mms->ssram23, 0x20400000);
	160	make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
	161	make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
	162	&mms->blockram, 0x01004000);
	163	make_ram_alias(&mms->blockram_m2, "mps.blockram_m2",
	164	&mms->blockram, 0x01008000);
	165	make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
	166	&mms->blockram, 0x0100c000);
	167	break;
	168	case FPGA_AN511:
	169	make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
	170	make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000);
	171	make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000);
	172	make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000);
	173	break;
	174	default:
175	g_assert_not_reached();
176	}
177
178	object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M);
179	armv7m = DEVICE(&mms->armv7m);
180	qdev_set_parent_bus(armv7m, sysbus_get_default());
181	switch (mmc->fpga_type) {
182	case FPGA_AN385:
183	qdev_prop_set_uint32(armv7m, "num-irq", 32);
184	break;
185	case FPGA_AN511:
186	qdev_prop_set_uint32(armv7m, "num-irq", 64);
187	break;
188	default:
189	g_assert_not_reached();
190	}
191	qdev_prop_set_string(armv7m, "cpu-model", machine->cpu_model);
192	object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
193	"memory", &error_abort);
194	object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
195	&error_fatal);
196
197	create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000);
198	create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000);
199	create_unimplemented_device("Block RAM", 0x01000000, 0x00010000);
200	create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000);
201	create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000);
202	create_unimplemented_device("PSRAM", 0x21000000, 0x01000000);
203	/* These three ranges all cover multiple devices; we may implement
204	* some of them below (in which case the real device takes precedence
205	* over the unimplemented-region mapping).
206	*/
207	create_unimplemented_device("CMSDK APB peripheral region @0x40000000",
208	0x40000000, 0x00010000);
209	create_unimplemented_device("CMSDK peripheral region @0x40010000",
210	0x40010000, 0x00010000);
211	create_unimplemented_device("Extra peripheral region @0x40020000",
212	0x40020000, 0x00010000);
213	create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000);
2eb5578b PM	214	create_unimplemented_device("VGA", 0x41000000, 0x0200000);
2eb5578b PM	215
977a15f4 PM	216	switch (mmc->fpga_type) {
	217	case FPGA_AN385:
	218	{
	219	/* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
	220	* Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
	221	*/
	222	Object *orgate;
	223	DeviceState *orgate_dev;
	224	int i;
	225
	226	orgate = object_new(TYPE_OR_IRQ);
	227	object_property_set_int(orgate, 6, "num-lines", &error_fatal);
	228	object_property_set_bool(orgate, true, "realized", &error_fatal);
	229	orgate_dev = DEVICE(orgate);
	230	qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
	231
	232	for (i = 0; i < 5; i++) {
	233	static const hwaddr uartbase[] = {0x40004000, 0x40005000,
	234	0x40006000, 0x40007000,
	235	0x40009000};
	236	Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
	237	/* RX irq number; TX irq is always one greater */
	238	static const int uartirq[] = {0, 2, 4, 18, 20};
	239	qemu_irq txovrint = NULL, rxovrint = NULL;
	240
	241	if (i < 3) {
	242	txovrint = qdev_get_gpio_in(orgate_dev, i * 2);
	243	rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
	244	}
	245
	246	cmsdk_apb_uart_create(uartbase[i],
	247	qdev_get_gpio_in(armv7m, uartirq[i] + 1),
	248	qdev_get_gpio_in(armv7m, uartirq[i]),
	249	txovrint, rxovrint,
	250	NULL,
	251	uartchr, SYSCLK_FRQ);
	252	}
	253	break;
	254	}
	255	case FPGA_AN511:
	256	{
	257	/* The overflow IRQs for all UARTs are ORed together.
	258	* Tx and Rx IRQs for each UART are ORed together.
	259	*/
	260	Object *orgate;
	261	DeviceState *orgate_dev;
	262	int i;
	263
	264	orgate = object_new(TYPE_OR_IRQ);
	265	object_property_set_int(orgate, 10, "num-lines", &error_fatal);
	266	object_property_set_bool(orgate, true, "realized", &error_fatal);
	267	orgate_dev = DEVICE(orgate);
	268	qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
	269
	270	for (i = 0; i < 5; i++) {
	271	/* system irq numbers for the combined tx/rx for each UART */
	272	static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56};
	273	static const hwaddr uartbase[] = {0x40004000, 0x40005000,
	274	0x4002c000, 0x4002d000,
	275	0x4002e000};
	276	Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL;
	277	Object *txrx_orgate;
	278	DeviceState *txrx_orgate_dev;
	279
280	txrx_orgate = object_new(TYPE_OR_IRQ);
281	object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal);
282	object_property_set_bool(txrx_orgate, true, "realized",
283	&error_fatal);
284	txrx_orgate_dev = DEVICE(txrx_orgate);
285	qdev_connect_gpio_out(txrx_orgate_dev, 0,
286	qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
287	cmsdk_apb_uart_create(uartbase[i],
288	qdev_get_gpio_in(txrx_orgate_dev, 0),
289	qdev_get_gpio_in(txrx_orgate_dev, 1),
ce3bc112 PM	290	qdev_get_gpio_in(orgate_dev, i * 2),
ce3bc112 PM	291	qdev_get_gpio_in(orgate_dev, i * 2 + 1),
977a15f4 PM	292	NULL,
	293	uartchr, SYSCLK_FRQ);
	294	}
	295	break;
	296	}
	297	default:
	298	g_assert_not_reached();
	299	}
	300
3d53904a PM	301	cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
	302	cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
	303
6dbdf4ec PM	304	object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
6dbdf4ec PM	305	sccdev = DEVICE(&mms->scc);
3d75007e	306	qdev_set_parent_bus(sccdev, sysbus_get_default());
6dbdf4ec PM	307	qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
	308	qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
	309	qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
	310	object_property_set_bool(OBJECT(&mms->scc), true, "realized",
	311	&error_fatal);
	312	sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
	313
35873939 PM	314	/* In hardware this is a LAN9220; the LAN9118 is software compatible
	315	* except that it doesn't support the checksum-offload feature.
	316	*/
	317	lan9118_init(&nd_table[0], 0x40200000,
	318	qdev_get_gpio_in(armv7m,
	319	mmc->fpga_type == FPGA_AN385 ? 13 : 47));
	320
2eb5578b PM	321	system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
	322
	323	armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
	324	0x400000);
	325	}
	326
	327	static void mps2_class_init(ObjectClass oc, void data)
	328	{
	329	MachineClass *mc = MACHINE_CLASS(oc);
	330
	331	mc->init = mps2_common_init;
	332	mc->max_cpus = 1;
	333	}
	334
	335	static void mps2_an385_class_init(ObjectClass oc, void data)
	336	{
	337	MachineClass *mc = MACHINE_CLASS(oc);
	338	MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
	339
	340	mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
	341	mmc->fpga_type = FPGA_AN385;
	342	mmc->cpu_model = "cortex-m3";
6dbdf4ec	343	mmc->scc_id = 0x41040000 \| (385 << 4);
2eb5578b PM	344	}
	345
	346	static void mps2_an511_class_init(ObjectClass oc, void data)
	347	{
	348	MachineClass *mc = MACHINE_CLASS(oc);
	349	MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
	350
	351	mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
	352	mmc->fpga_type = FPGA_AN511;
	353	mmc->cpu_model = "cortex-m3";
6dbdf4ec	354	mmc->scc_id = 0x4104000 \| (511 << 4);
2eb5578b PM	355	}
	356
	357	static const TypeInfo mps2_info = {
	358	.name = TYPE_MPS2_MACHINE,
	359	.parent = TYPE_MACHINE,
	360	.abstract = true,
	361	.instance_size = sizeof(MPS2MachineState),
	362	.class_size = sizeof(MPS2MachineClass),
	363	.class_init = mps2_class_init,
	364	};
	365
	366	static const TypeInfo mps2_an385_info = {
	367	.name = TYPE_MPS2_AN385_MACHINE,
	368	.parent = TYPE_MPS2_MACHINE,
	369	.class_init = mps2_an385_class_init,
	370	};
	371
	372	static const TypeInfo mps2_an511_info = {
	373	.name = TYPE_MPS2_AN511_MACHINE,
	374	.parent = TYPE_MPS2_MACHINE,
	375	.class_init = mps2_an511_class_init,
	376	};
	377
	378	static void mps2_machine_init(void)
	379	{
	380	type_register_static(&mps2_info);
	381	type_register_static(&mps2_an385_info);
	382	type_register_static(&mps2_an511_info);
	383	}
	384
	385	type_init(mps2_machine_init);