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2eb5578b PM |
1 | /* |
2 | * ARM V2M MPS2 board emulation. | |
3 | * | |
4 | * Copyright (c) 2017 Linaro Limited | |
5 | * Written by Peter Maydell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger | |
13 | * FPGA but is otherwise the same as the 2). Since the CPU itself | |
14 | * and most of the devices are in the FPGA, the details of the board | |
15 | * as seen by the guest depend significantly on the FPGA image. | |
16 | * We model the following FPGA images: | |
17 | * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 | |
18 | * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 | |
19 | * | |
20 | * Links to the TRM for the board itself and to the various Application | |
21 | * Notes which document the FPGA images can be found here: | |
22 | * https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
eba59997 | 26 | #include "qemu/units.h" |
68637c3a | 27 | #include "qemu/cutils.h" |
2eb5578b PM |
28 | #include "qapi/error.h" |
29 | #include "qemu/error-report.h" | |
12ec8bd5 | 30 | #include "hw/arm/boot.h" |
2eb5578b | 31 | #include "hw/arm/armv7m.h" |
977a15f4 | 32 | #include "hw/or-irq.h" |
2eb5578b PM |
33 | #include "hw/boards.h" |
34 | #include "exec/address-spaces.h" | |
977a15f4 | 35 | #include "sysemu/sysemu.h" |
2eb5578b | 36 | #include "hw/misc/unimp.h" |
977a15f4 | 37 | #include "hw/char/cmsdk-apb-uart.h" |
3d53904a | 38 | #include "hw/timer/cmsdk-apb-timer.h" |
595c786b | 39 | #include "hw/timer/cmsdk-apb-dualtimer.h" |
6dbdf4ec | 40 | #include "hw/misc/mps2-scc.h" |
66b03dce | 41 | #include "hw/net/lan9118.h" |
35873939 | 42 | #include "net/net.h" |
2eb5578b PM |
43 | |
44 | typedef enum MPS2FPGAType { | |
45 | FPGA_AN385, | |
46 | FPGA_AN511, | |
47 | } MPS2FPGAType; | |
48 | ||
49 | typedef struct { | |
50 | MachineClass parent; | |
51 | MPS2FPGAType fpga_type; | |
6dbdf4ec | 52 | uint32_t scc_id; |
2eb5578b PM |
53 | } MPS2MachineClass; |
54 | ||
55 | typedef struct { | |
56 | MachineState parent; | |
57 | ||
58 | ARMv7MState armv7m; | |
2eb5578b PM |
59 | MemoryRegion ssram1; |
60 | MemoryRegion ssram1_m; | |
61 | MemoryRegion ssram23; | |
62 | MemoryRegion ssram23_m; | |
63 | MemoryRegion blockram; | |
64 | MemoryRegion blockram_m1; | |
65 | MemoryRegion blockram_m2; | |
66 | MemoryRegion blockram_m3; | |
67 | MemoryRegion sram; | |
6dbdf4ec | 68 | MPS2SCC scc; |
595c786b | 69 | CMSDKAPBDualTimer dualtimer; |
2eb5578b PM |
70 | } MPS2MachineState; |
71 | ||
72 | #define TYPE_MPS2_MACHINE "mps2" | |
73 | #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") | |
74 | #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") | |
75 | ||
76 | #define MPS2_MACHINE(obj) \ | |
77 | OBJECT_CHECK(MPS2MachineState, obj, TYPE_MPS2_MACHINE) | |
78 | #define MPS2_MACHINE_GET_CLASS(obj) \ | |
79 | OBJECT_GET_CLASS(MPS2MachineClass, obj, TYPE_MPS2_MACHINE) | |
80 | #define MPS2_MACHINE_CLASS(klass) \ | |
81 | OBJECT_CLASS_CHECK(MPS2MachineClass, klass, TYPE_MPS2_MACHINE) | |
82 | ||
83 | /* Main SYSCLK frequency in Hz */ | |
84 | #define SYSCLK_FRQ 25000000 | |
85 | ||
86 | /* Initialize the auxiliary RAM region @mr and map it into | |
87 | * the memory map at @base. | |
88 | */ | |
89 | static void make_ram(MemoryRegion *mr, const char *name, | |
90 | hwaddr base, hwaddr size) | |
91 | { | |
92 | memory_region_init_ram(mr, NULL, name, size, &error_fatal); | |
93 | memory_region_add_subregion(get_system_memory(), base, mr); | |
94 | } | |
95 | ||
96 | /* Create an alias of an entire original MemoryRegion @orig | |
97 | * located at @base in the memory map. | |
98 | */ | |
99 | static void make_ram_alias(MemoryRegion *mr, const char *name, | |
100 | MemoryRegion *orig, hwaddr base) | |
101 | { | |
102 | memory_region_init_alias(mr, NULL, name, orig, 0, | |
103 | memory_region_size(orig)); | |
104 | memory_region_add_subregion(get_system_memory(), base, mr); | |
105 | } | |
106 | ||
107 | static void mps2_common_init(MachineState *machine) | |
108 | { | |
109 | MPS2MachineState *mms = MPS2_MACHINE(machine); | |
110 | MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); | |
111 | MemoryRegion *system_memory = get_system_memory(); | |
ba1ba5cc | 112 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
6dbdf4ec | 113 | DeviceState *armv7m, *sccdev; |
2eb5578b | 114 | |
ba1ba5cc IM |
115 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { |
116 | error_report("This board can only be used with CPU %s", | |
117 | mc->default_cpu_type); | |
2eb5578b PM |
118 | exit(1); |
119 | } | |
120 | ||
68637c3a IM |
121 | if (machine->ram_size != mc->default_ram_size) { |
122 | char *sz = size_to_str(mc->default_ram_size); | |
123 | error_report("Invalid RAM size, should be %s", sz); | |
124 | g_free(sz); | |
125 | exit(EXIT_FAILURE); | |
126 | } | |
127 | ||
2eb5578b PM |
128 | /* The FPGA images have an odd combination of different RAMs, |
129 | * because in hardware they are different implementations and | |
130 | * connected to different buses, giving varying performance/size | |
131 | * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily | |
132 | * call the 16MB our "system memory", as it's the largest lump. | |
133 | * | |
134 | * Common to both boards: | |
135 | * 0x21000000..0x21ffffff : PSRAM (16MB) | |
136 | * AN385 only: | |
137 | * 0x00000000 .. 0x003fffff : ZBT SSRAM1 | |
138 | * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 | |
139 | * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 | |
140 | * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 | |
141 | * 0x01000000 .. 0x01003fff : block RAM (16K) | |
142 | * 0x01004000 .. 0x01007fff : mirror of above | |
143 | * 0x01008000 .. 0x0100bfff : mirror of above | |
144 | * 0x0100c000 .. 0x0100ffff : mirror of above | |
145 | * AN511 only: | |
146 | * 0x00000000 .. 0x0003ffff : FPGA block RAM | |
147 | * 0x00400000 .. 0x007fffff : ZBT SSRAM1 | |
148 | * 0x20000000 .. 0x2001ffff : SRAM | |
149 | * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 | |
150 | * | |
151 | * The AN385 has a feature where the lowest 16K can be mapped | |
152 | * either to the bottom of the ZBT SSRAM1 or to the block RAM. | |
153 | * This is of no use for QEMU so we don't implement it (as if | |
154 | * zbt_boot_ctrl is always zero). | |
155 | */ | |
68637c3a | 156 | memory_region_add_subregion(system_memory, 0x21000000, machine->ram); |
2eb5578b PM |
157 | |
158 | switch (mmc->fpga_type) { | |
159 | case FPGA_AN385: | |
160 | make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); | |
161 | make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); | |
162 | make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); | |
163 | make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", | |
164 | &mms->ssram23, 0x20400000); | |
165 | make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); | |
166 | make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", | |
167 | &mms->blockram, 0x01004000); | |
168 | make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", | |
169 | &mms->blockram, 0x01008000); | |
170 | make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", | |
171 | &mms->blockram, 0x0100c000); | |
172 | break; | |
173 | case FPGA_AN511: | |
174 | make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); | |
175 | make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); | |
176 | make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); | |
177 | make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); | |
178 | break; | |
179 | default: | |
180 | g_assert_not_reached(); | |
181 | } | |
182 | ||
0074fce6 | 183 | object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); |
2eb5578b | 184 | armv7m = DEVICE(&mms->armv7m); |
2eb5578b PM |
185 | switch (mmc->fpga_type) { |
186 | case FPGA_AN385: | |
187 | qdev_prop_set_uint32(armv7m, "num-irq", 32); | |
188 | break; | |
189 | case FPGA_AN511: | |
190 | qdev_prop_set_uint32(armv7m, "num-irq", 64); | |
191 | break; | |
192 | default: | |
193 | g_assert_not_reached(); | |
194 | } | |
ba1ba5cc | 195 | qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); |
a1c5a062 | 196 | qdev_prop_set_bit(armv7m, "enable-bitband", true); |
2eb5578b PM |
197 | object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), |
198 | "memory", &error_abort); | |
0074fce6 | 199 | sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); |
2eb5578b PM |
200 | |
201 | create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); | |
202 | create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); | |
203 | create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); | |
204 | create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); | |
205 | create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); | |
206 | create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); | |
207 | /* These three ranges all cover multiple devices; we may implement | |
208 | * some of them below (in which case the real device takes precedence | |
209 | * over the unimplemented-region mapping). | |
210 | */ | |
211 | create_unimplemented_device("CMSDK APB peripheral region @0x40000000", | |
212 | 0x40000000, 0x00010000); | |
213 | create_unimplemented_device("CMSDK peripheral region @0x40010000", | |
214 | 0x40010000, 0x00010000); | |
215 | create_unimplemented_device("Extra peripheral region @0x40020000", | |
216 | 0x40020000, 0x00010000); | |
217 | create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); | |
2eb5578b PM |
218 | create_unimplemented_device("VGA", 0x41000000, 0x0200000); |
219 | ||
977a15f4 PM |
220 | switch (mmc->fpga_type) { |
221 | case FPGA_AN385: | |
222 | { | |
223 | /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. | |
224 | * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. | |
225 | */ | |
226 | Object *orgate; | |
227 | DeviceState *orgate_dev; | |
228 | int i; | |
229 | ||
230 | orgate = object_new(TYPE_OR_IRQ); | |
231 | object_property_set_int(orgate, 6, "num-lines", &error_fatal); | |
ce189ab2 | 232 | qdev_realize(DEVICE(orgate), NULL, &error_fatal); |
977a15f4 PM |
233 | orgate_dev = DEVICE(orgate); |
234 | qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); | |
235 | ||
236 | for (i = 0; i < 5; i++) { | |
237 | static const hwaddr uartbase[] = {0x40004000, 0x40005000, | |
238 | 0x40006000, 0x40007000, | |
239 | 0x40009000}; | |
977a15f4 PM |
240 | /* RX irq number; TX irq is always one greater */ |
241 | static const int uartirq[] = {0, 2, 4, 18, 20}; | |
242 | qemu_irq txovrint = NULL, rxovrint = NULL; | |
243 | ||
244 | if (i < 3) { | |
245 | txovrint = qdev_get_gpio_in(orgate_dev, i * 2); | |
246 | rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); | |
247 | } | |
248 | ||
249 | cmsdk_apb_uart_create(uartbase[i], | |
250 | qdev_get_gpio_in(armv7m, uartirq[i] + 1), | |
251 | qdev_get_gpio_in(armv7m, uartirq[i]), | |
252 | txovrint, rxovrint, | |
253 | NULL, | |
fc38a112 | 254 | serial_hd(i), SYSCLK_FRQ); |
977a15f4 PM |
255 | } |
256 | break; | |
257 | } | |
258 | case FPGA_AN511: | |
259 | { | |
260 | /* The overflow IRQs for all UARTs are ORed together. | |
261 | * Tx and Rx IRQs for each UART are ORed together. | |
262 | */ | |
263 | Object *orgate; | |
264 | DeviceState *orgate_dev; | |
265 | int i; | |
266 | ||
267 | orgate = object_new(TYPE_OR_IRQ); | |
268 | object_property_set_int(orgate, 10, "num-lines", &error_fatal); | |
ce189ab2 | 269 | qdev_realize(DEVICE(orgate), NULL, &error_fatal); |
977a15f4 PM |
270 | orgate_dev = DEVICE(orgate); |
271 | qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); | |
272 | ||
273 | for (i = 0; i < 5; i++) { | |
274 | /* system irq numbers for the combined tx/rx for each UART */ | |
275 | static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; | |
276 | static const hwaddr uartbase[] = {0x40004000, 0x40005000, | |
277 | 0x4002c000, 0x4002d000, | |
278 | 0x4002e000}; | |
977a15f4 PM |
279 | Object *txrx_orgate; |
280 | DeviceState *txrx_orgate_dev; | |
281 | ||
282 | txrx_orgate = object_new(TYPE_OR_IRQ); | |
283 | object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal); | |
ce189ab2 | 284 | qdev_realize(DEVICE(txrx_orgate), NULL, &error_fatal); |
977a15f4 PM |
285 | txrx_orgate_dev = DEVICE(txrx_orgate); |
286 | qdev_connect_gpio_out(txrx_orgate_dev, 0, | |
287 | qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); | |
288 | cmsdk_apb_uart_create(uartbase[i], | |
289 | qdev_get_gpio_in(txrx_orgate_dev, 0), | |
290 | qdev_get_gpio_in(txrx_orgate_dev, 1), | |
ce3bc112 PM |
291 | qdev_get_gpio_in(orgate_dev, i * 2), |
292 | qdev_get_gpio_in(orgate_dev, i * 2 + 1), | |
977a15f4 | 293 | NULL, |
fc38a112 | 294 | serial_hd(i), SYSCLK_FRQ); |
977a15f4 PM |
295 | } |
296 | break; | |
297 | } | |
298 | default: | |
299 | g_assert_not_reached(); | |
300 | } | |
301 | ||
3d53904a PM |
302 | cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); |
303 | cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); | |
304 | ||
0074fce6 MA |
305 | object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, |
306 | TYPE_CMSDK_APB_DUALTIMER); | |
595c786b | 307 | qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); |
0074fce6 | 308 | sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); |
595c786b PM |
309 | sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, |
310 | qdev_get_gpio_in(armv7m, 10)); | |
311 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); | |
312 | ||
0074fce6 | 313 | object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); |
6dbdf4ec | 314 | sccdev = DEVICE(&mms->scc); |
6dbdf4ec | 315 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); |
239cb6fe | 316 | qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); |
6dbdf4ec | 317 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); |
0074fce6 | 318 | sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); |
6dbdf4ec PM |
319 | sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); |
320 | ||
35873939 PM |
321 | /* In hardware this is a LAN9220; the LAN9118 is software compatible |
322 | * except that it doesn't support the checksum-offload feature. | |
323 | */ | |
324 | lan9118_init(&nd_table[0], 0x40200000, | |
325 | qdev_get_gpio_in(armv7m, | |
326 | mmc->fpga_type == FPGA_AN385 ? 13 : 47)); | |
327 | ||
2eb5578b PM |
328 | system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; |
329 | ||
330 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, | |
331 | 0x400000); | |
332 | } | |
333 | ||
334 | static void mps2_class_init(ObjectClass *oc, void *data) | |
335 | { | |
336 | MachineClass *mc = MACHINE_CLASS(oc); | |
337 | ||
338 | mc->init = mps2_common_init; | |
339 | mc->max_cpus = 1; | |
68637c3a IM |
340 | mc->default_ram_size = 16 * MiB; |
341 | mc->default_ram_id = "mps.ram"; | |
2eb5578b PM |
342 | } |
343 | ||
344 | static void mps2_an385_class_init(ObjectClass *oc, void *data) | |
345 | { | |
346 | MachineClass *mc = MACHINE_CLASS(oc); | |
347 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); | |
348 | ||
349 | mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3"; | |
350 | mmc->fpga_type = FPGA_AN385; | |
ba1ba5cc | 351 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
239cb6fe | 352 | mmc->scc_id = 0x41043850; |
2eb5578b PM |
353 | } |
354 | ||
355 | static void mps2_an511_class_init(ObjectClass *oc, void *data) | |
356 | { | |
357 | MachineClass *mc = MACHINE_CLASS(oc); | |
358 | MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc); | |
359 | ||
360 | mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3"; | |
361 | mmc->fpga_type = FPGA_AN511; | |
ba1ba5cc | 362 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
239cb6fe | 363 | mmc->scc_id = 0x41045110; |
2eb5578b PM |
364 | } |
365 | ||
366 | static const TypeInfo mps2_info = { | |
367 | .name = TYPE_MPS2_MACHINE, | |
368 | .parent = TYPE_MACHINE, | |
369 | .abstract = true, | |
370 | .instance_size = sizeof(MPS2MachineState), | |
371 | .class_size = sizeof(MPS2MachineClass), | |
372 | .class_init = mps2_class_init, | |
373 | }; | |
374 | ||
375 | static const TypeInfo mps2_an385_info = { | |
376 | .name = TYPE_MPS2_AN385_MACHINE, | |
377 | .parent = TYPE_MPS2_MACHINE, | |
378 | .class_init = mps2_an385_class_init, | |
379 | }; | |
380 | ||
381 | static const TypeInfo mps2_an511_info = { | |
382 | .name = TYPE_MPS2_AN511_MACHINE, | |
383 | .parent = TYPE_MPS2_MACHINE, | |
384 | .class_init = mps2_an511_class_init, | |
385 | }; | |
386 | ||
387 | static void mps2_machine_init(void) | |
388 | { | |
389 | type_register_static(&mps2_info); | |
390 | type_register_static(&mps2_an385_info); | |
391 | type_register_static(&mps2_an511_info); | |
392 | } | |
393 | ||
394 | type_init(mps2_machine_init); |