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6d262dcb SS |
1 | /* |
2 | * SmartFusion2 SOM starter kit(from Emcraft) emulation. | |
3 | * | |
a7f16aed PMD |
4 | * M2S-FG484 SOM hardware architecture specification: |
5 | * https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf | |
6 | * | |
6d262dcb SS |
7 | * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | */ | |
27 | ||
28 | #include "qemu/osdep.h" | |
fc6b3cf9 | 29 | #include "qemu/units.h" |
6d262dcb SS |
30 | #include "qapi/error.h" |
31 | #include "qemu/error-report.h" | |
32 | #include "hw/boards.h" | |
a27bd6c7 | 33 | #include "hw/qdev-properties.h" |
12ec8bd5 | 34 | #include "hw/arm/boot.h" |
9bfaf375 | 35 | #include "hw/qdev-clock.h" |
6d262dcb | 36 | #include "exec/address-spaces.h" |
6d262dcb | 37 | #include "hw/arm/msf2-soc.h" |
6d262dcb SS |
38 | |
39 | #define DDR_BASE_ADDRESS 0xA0000000 | |
d23b6caa | 40 | #define DDR_SIZE (64 * MiB) |
6d262dcb | 41 | |
d23b6caa PMD |
42 | #define M2S010_ENVM_SIZE (256 * KiB) |
43 | #define M2S010_ESRAM_SIZE (64 * KiB) | |
6d262dcb SS |
44 | |
45 | static void emcraft_sf2_s2s010_init(MachineState *machine) | |
46 | { | |
47 | DeviceState *dev; | |
48 | DeviceState *spi_flash; | |
49 | MSF2State *soc; | |
64eaa820 | 50 | DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); |
6d262dcb | 51 | qemu_irq cs_line; |
57d479c9 | 52 | BusState *spi_bus; |
6d262dcb SS |
53 | MemoryRegion *sysmem = get_system_memory(); |
54 | MemoryRegion *ddr = g_new(MemoryRegion, 1); | |
9bfaf375 | 55 | Clock *m3clk; |
6d262dcb | 56 | |
6d262dcb SS |
57 | memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE, |
58 | &error_fatal); | |
59 | memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr); | |
60 | ||
3e80f690 | 61 | dev = qdev_new(TYPE_MSF2_SOC); |
f503bc4b | 62 | object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); |
6d262dcb | 63 | qdev_prop_set_string(dev, "part-name", "M2S010"); |
6d262dcb SS |
64 | qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); |
65 | qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); | |
66 | ||
67 | /* | |
68 | * CPU clock and peripheral clocks(APB0, APB1)are configurable | |
69 | * in Libero. CPU clock is divided by APB0 and APB1 divisors for | |
70 | * peripherals. Emcraft's SoM kit comes with these settings by default. | |
71 | */ | |
9bfaf375 PM |
72 | /* This clock doesn't need migration because it is fixed-frequency */ |
73 | m3clk = clock_new(OBJECT(machine), "m3clk"); | |
74 | clock_set_hz(m3clk, 142 * 1000000); | |
75 | qdev_connect_clock_in(dev, "m3clk", m3clk); | |
6d262dcb SS |
76 | qdev_prop_set_uint32(dev, "apb0div", 2); |
77 | qdev_prop_set_uint32(dev, "apb1div", 2); | |
78 | ||
3c6ef471 | 79 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
6d262dcb SS |
80 | |
81 | soc = MSF2_SOC(dev); | |
82 | ||
83 | /* Attach SPI flash to SPI0 controller */ | |
57d479c9 | 84 | spi_bus = qdev_get_child_bus(dev, "spi0"); |
a7f16aed | 85 | spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */ |
6d262dcb SS |
86 | qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1); |
87 | if (dinfo) { | |
934df912 MA |
88 | qdev_prop_set_drive_err(spi_flash, "drive", |
89 | blk_by_legacy_dinfo(dinfo), &error_fatal); | |
6d262dcb | 90 | } |
57d479c9 | 91 | qdev_realize_and_unref(spi_flash, spi_bus, &error_fatal); |
6d262dcb SS |
92 | cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0); |
93 | sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line); | |
94 | ||
95 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, | |
761c532a | 96 | 0, soc->envm_size); |
6d262dcb SS |
97 | } |
98 | ||
99 | static void emcraft_sf2_machine_init(MachineClass *mc) | |
100 | { | |
3e71f4a7 GS |
101 | static const char * const valid_cpu_types[] = { |
102 | ARM_CPU_TYPE_NAME("cortex-m3"), | |
103 | NULL | |
104 | }; | |
105 | ||
6d262dcb SS |
106 | mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; |
107 | mc->init = emcraft_sf2_s2s010_init; | |
3e71f4a7 | 108 | mc->valid_cpu_types = valid_cpu_types; |
6d262dcb SS |
109 | } |
110 | ||
111 | DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init) |