[mirror_qemu.git] / hw / arm / npcm7xx_boards.c

/*
 * Machine definitions for boards featuring an NPCM7xx SoC.
 *
 * Copyright 2020 Google LLC
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"

#include "hw/arm/npcm7xx.h"
#include "hw/core/cpu.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/loader.h"
#include "hw/nvram/eeprom_at24c.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "sysemu/blockdev.h"
#include "sysemu/sysemu.h"
#include "sysemu/block-backend.h"
#include "qemu/error-report.h"


#define NPCM7XX_POWER_ON_STRAPS_DEFAULT (           \
        NPCM7XX_PWRON_STRAP_SPI0F18 |               \
        NPCM7XX_PWRON_STRAP_SFAB |                  \
        NPCM7XX_PWRON_STRAP_BSPA |                  \
        NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) |   \
        NPCM7XX_PWRON_STRAP_SECEN |                 \
        NPCM7XX_PWRON_STRAP_HIZ |                   \
        NPCM7XX_PWRON_STRAP_ECC |                   \
        NPCM7XX_PWRON_STRAP_RESERVE1 |              \
        NPCM7XX_PWRON_STRAP_J2EN |                  \
        NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))

#define NPCM750_EVB_POWER_ON_STRAPS ( \
        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
#define QUANTA_GBS_POWER_ON_STRAPS ( \
        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT

static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";

static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
{
    const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
    g_autofree char *filename = NULL;
    int ret;

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    if (!filename) {
        error_report("Could not find ROM image '%s'", bios_name);
        if (!machine->kernel_filename) {
            /* We can't boot without a bootrom or a kernel image. */
            exit(1);
        }
        return;
    }
    ret = load_image_mr(filename, &soc->irom);
    if (ret < 0) {
        error_report("Failed to load ROM image '%s'", filename);
        exit(1);
    }
}

static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
                                  const char *flash_type, DriveInfo *dinfo)
{
    DeviceState *flash;
    qemu_irq flash_cs;

    flash = qdev_new(flash_type);
    if (dinfo) {
        qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
    }
    qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);

    flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
    qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
}

static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
{
    memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);

    object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
                             &error_abort);
}

static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
{
        DriveInfo *di = drive_get(IF_SD, 0, unit);
        BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;

        BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus");
        if (bus == NULL) {
            error_report("No SD bus found in SOC object");
            exit(1);
        }

        DeviceState *carddev = qdev_new(TYPE_SD_CARD);
        qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
        qdev_realize_and_unref(carddev, bus, &error_fatal);
}

static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
                                        uint32_t hw_straps)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
    Object *obj;

    obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
                                &error_abort, NULL);
    object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);

    return NPCM7XX(obj);
}

static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
{
    g_assert(num < ARRAY_SIZE(soc->smbus));
    return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
}

static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
                                      NPCM7xxState *soc, const int *fan_counts)
{
    SplitIRQ *splitters = machine->fan_splitter;

    /*
     * PWM 0~3 belong to module 0 output 0~3.
     * PWM 4~7 belong to module 1 output 0~3.
     */
    for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
        for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
            int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
            DeviceState *splitter;

            if (fan_counts[splitter_no] < 1) {
                continue;
            }
            object_initialize_child(OBJECT(machine), "fan-splitter[*]",
                                    &splitters[splitter_no], TYPE_SPLIT_IRQ);
            splitter = DEVICE(&splitters[splitter_no]);
            qdev_prop_set_uint16(splitter, "num-lines",
                                 fan_counts[splitter_no]);
            qdev_realize(splitter, NULL, &error_abort);
            qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
                                        j, qdev_get_gpio_in(splitter, 0));
        }
    }
}

static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,
                                    int fan_no, int output_no)
{
    DeviceState *fan;
    int fan_input;
    qemu_irq fan_duty_gpio;

    g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
    /*
     * Fan 0~1 belong to module 0 input 0~1.
     * Fan 2~3 belong to module 1 input 0~1.
     * ...
     * Fan 14~15 belong to module 7 input 0~1.
     * Fan 16~17 belong to module 0 input 2~3.
     * Fan 18~19 belong to module 1 input 2~3.
     */
    if (fan_no < 16) {
        fan = DEVICE(&soc->mft[fan_no / 2]);
        fan_input = fan_no % 2;
    } else {
        fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
        fan_input = fan_no % 2 + 2;
    }

    /* Connect the Fan to PWM module */
    fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
    qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
}

static void npcm750_evb_i2c_init(NPCM7xxState *soc)
{
    /* lm75 temperature sensor on SVB, tmp105 is compatible */
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48);
    /* lm75 temperature sensor on EB, tmp105 is compatible */
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48);
    /* tmp100 temperature sensor on EB, tmp105 is compatible */
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48);
    /* tmp100 temperature sensor on SVB, tmp105 is compatible */
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
}

static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
{
    SplitIRQ *splitter = machine->fan_splitter;
    static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};

    npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
    npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
}

static void quanta_gsj_i2c_init(NPCM7xxState *soc)
{
    /* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c);
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c);
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);

    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);

    /*
     * i2c-11:
     * - power-brick@36: delta,dps800
     * - hotswap@15: ti,lm5066i
     */

    /*
     * i2c-12:
     * - ucd90160@6b
     */

    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75);
}

static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)
{
    SplitIRQ *splitter = machine->fan_splitter;
    static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};

    npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
    npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
    npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
    npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
}

static void quanta_gbs_i2c_init(NPCM7xxState *soc)
{
    /*
     * i2c-0:
     *     pca9546@71
     *
     * i2c-1:
     *     pca9535@24
     *     pca9535@20
     *     pca9535@21
     *     pca9535@22
     *     pca9535@23
     *     pca9535@25
     *     pca9535@26
     *
     * i2c-2:
     *     sbtsi@4c
     *
     * i2c-5:
     *     atmel,24c64@50 mb_fru
     *     pca9546@71
     *         - channel 0: max31725@54
     *         - channel 1: max31725@55
     *         - channel 2: max31725@5d
     *                      atmel,24c64@51 fan_fru
     *         - channel 3: atmel,24c64@52 hsbp_fru
     *
     * i2c-6:
     *     pca9545@73
     *
     * i2c-7:
     *     pca9545@72
     *
     * i2c-8:
     *     adi,adm1272@10
     *
     * i2c-9:
     *     pca9546@71
     *         - channel 0: isil,isl68137@60
     *         - channel 1: isil,isl68137@61
     *         - channel 2: isil,isl68137@63
     *         - channel 3: isil,isl68137@45
     *
     * i2c-10:
     *     pca9545@71
     *
     * i2c-11:
     *     pca9545@76
     *
     * i2c-12:
     *     maxim,max34451@4e
     *     isil,isl68137@5d
     *     isil,isl68137@5e
     *
     * i2c-14:
     *     pca9545@70
     */
}

static void kudo_bmc_i2c_init(NPCM7xxState *soc)
{
    I2CSlave *i2c_mux;

    i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1),
                                      TYPE_PCA9548, 0x75);

    /* tmp105 is compatible with the lm75 */
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x5c);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "tmp105", 0x5c);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), "tmp105", 0x5c);

    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77);

    i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);

    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */

    i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
                                      TYPE_PCA9548, 0x77);

    /* tmp105 is compatible with the lm75 */
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "tmp105", 0x48);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "tmp105", 0x49);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
    i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);

    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */

    /* TODO: Add remaining i2c devices. */
}

static void npcm750_evb_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_fatal);

    npcm7xx_load_bootrom(machine, soc);
    npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
    npcm750_evb_i2c_init(soc);
    npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
    npcm7xx_load_kernel(machine, soc);
}

static void quanta_gsj_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_fatal);

    npcm7xx_load_bootrom(machine, soc);
    npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
                          drive_get(IF_MTD, 0, 0));
    quanta_gsj_i2c_init(soc);
    quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
    npcm7xx_load_kernel(machine, soc);
}

static void quanta_gbs_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_fatal);

    npcm7xx_load_bootrom(machine, soc);

    npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
                          drive_get(IF_MTD, 0, 0));

    quanta_gbs_i2c_init(soc);
    sdhci_attach_drive(&soc->mmc.sdhci, 0);
    npcm7xx_load_kernel(machine, soc);
}

static void kudo_bmc_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_fatal);

    npcm7xx_load_bootrom(machine, soc);
    npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
                          drive_get(IF_MTD, 0, 0));
    npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
                          drive_get(IF_MTD, 3, 0));

    kudo_bmc_i2c_init(soc);
    sdhci_attach_drive(&soc->mmc.sdhci, 0);
    npcm7xx_load_kernel(machine, soc);
}

static void mori_bmc_init(MachineState *machine)
{
    NPCM7xxState *soc;

    soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS);
    npcm7xx_connect_dram(soc, machine->ram);
    qdev_realize(DEVICE(soc), NULL, &error_fatal);

    npcm7xx_load_bootrom(machine, soc);
    npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
                          drive_get(IF_MTD, 3, 0));

    npcm7xx_load_kernel(machine, soc);
}

static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
{
    NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
    MachineClass *mc = MACHINE_CLASS(nmc);

    nmc->soc_type = type;
    mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
}

static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);
    static const char * const valid_cpu_types[] = {
        ARM_CPU_TYPE_NAME("cortex-a9"),
        NULL
    };

    mc->no_floppy = 1;
    mc->no_cdrom = 1;
    mc->no_parallel = 1;
    mc->default_ram_id = "ram";
    mc->valid_cpu_types = valid_cpu_types;
}

/*
 * Schematics:
 * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
 */
static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    npcm7xx_set_soc_type(nmc, TYPE_NPCM750);

    mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)";
    mc->init = npcm750_evb_init;
    mc->default_ram_size = 512 * MiB;
};

static void gsj_machine_class_init(ObjectClass *oc, void *data)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);

    mc->desc = "Quanta GSJ (Cortex-A9)";
    mc->init = quanta_gsj_init;
    mc->default_ram_size = 512 * MiB;
};

static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);

    mc->desc = "Quanta GBS (Cortex-A9)";
    mc->init = quanta_gbs_init;
    mc->default_ram_size = 1 * GiB;
}

static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);

    mc->desc = "Kudo BMC (Cortex-A9)";
    mc->init = kudo_bmc_init;
    mc->default_ram_size = 1 * GiB;
};

static void mori_bmc_machine_class_init(ObjectClass *oc, void *data)
{
    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
    MachineClass *mc = MACHINE_CLASS(oc);

    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);

    mc->desc = "Mori BMC (Cortex-A9)";
    mc->init = mori_bmc_init;
    mc->default_ram_size = 1 * GiB;
}

static const TypeInfo npcm7xx_machine_types[] = {
    {
        .name           = TYPE_NPCM7XX_MACHINE,
        .parent         = TYPE_MACHINE,
        .instance_size  = sizeof(NPCM7xxMachine),
        .class_size     = sizeof(NPCM7xxMachineClass),
        .class_init     = npcm7xx_machine_class_init,
        .abstract       = true,
    }, {
        .name           = MACHINE_TYPE_NAME("npcm750-evb"),
        .parent         = TYPE_NPCM7XX_MACHINE,
        .class_init     = npcm750_evb_machine_class_init,
    }, {
        .name           = MACHINE_TYPE_NAME("quanta-gsj"),
        .parent         = TYPE_NPCM7XX_MACHINE,
        .class_init     = gsj_machine_class_init,
    }, {
        .name           = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
        .parent         = TYPE_NPCM7XX_MACHINE,
        .class_init     = gbs_bmc_machine_class_init,
    }, {
        .name           = MACHINE_TYPE_NAME("kudo-bmc"),
        .parent         = TYPE_NPCM7XX_MACHINE,
        .class_init     = kudo_bmc_machine_class_init,
    }, {
        .name           = MACHINE_TYPE_NAME("mori-bmc"),
        .parent         = TYPE_NPCM7XX_MACHINE,
        .class_init     = mori_bmc_machine_class_init,
    },
};

DEFINE_TYPES(npcm7xx_machine_types)
Commit	Line	Data
b773acf4 HS	1	/*
	2	* Machine definitions for boards featuring an NPCM7xx SoC.
	3	*
	4	* Copyright 2020 Google LLC
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*/
	16
	17	#include "qemu/osdep.h"
	18
b773acf4 HS	19	#include "hw/arm/npcm7xx.h"
b773acf4 HS	20	#include "hw/core/cpu.h"
6229659e	21	#include "hw/i2c/i2c_mux_pca954x.h"
2ef1e0d7	22	#include "hw/i2c/smbus_eeprom.h"
4e89ccd6	23	#include "hw/loader.h"
9618ebae	24	#include "hw/nvram/eeprom_at24c.h"
a9d3d7b1	25	#include "hw/qdev-core.h"
0eb73f23	26	#include "hw/qdev-properties.h"
b773acf4	27	#include "qapi/error.h"
2c65db5e	28	#include "qemu/datadir.h"
b773acf4	29	#include "qemu/units.h"
2cb06d49 SM	30	#include "sysemu/blockdev.h"
	31	#include "sysemu/sysemu.h"
	32	#include "sysemu/block-backend.h"
cc37d98b RH	33	#include "qemu/error-report.h"
cc37d98b RH	34
b773acf4	35
5b415dd6 HW	36	#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \
	37	NPCM7XX_PWRON_STRAP_SPI0F18 \| \
	38	NPCM7XX_PWRON_STRAP_SFAB \| \
	39	NPCM7XX_PWRON_STRAP_BSPA \| \
	40	NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) \| \
	41	NPCM7XX_PWRON_STRAP_SECEN \| \
	42	NPCM7XX_PWRON_STRAP_HIZ \| \
	43	NPCM7XX_PWRON_STRAP_ECC \| \
	44	NPCM7XX_PWRON_STRAP_RESERVE1 \| \
	45	NPCM7XX_PWRON_STRAP_J2EN \| \
	46	NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
	47
	48	#define NPCM750_EVB_POWER_ON_STRAPS ( \
	49	NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
	50	#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
	51	#define QUANTA_GBS_POWER_ON_STRAPS ( \
	52	NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
	53	#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
	54	#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
b773acf4	55
4e89ccd6 HS	56	static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
	57
	58	static void npcm7xx_load_bootrom(MachineState machine, NPCM7xxState soc)
	59	{
0ad3b5d3	60	const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
4e89ccd6 HS	61	g_autofree char *filename = NULL;
	62	int ret;
	63
4e89ccd6 HS	64	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	65	if (!filename) {
	66	error_report("Could not find ROM image '%s'", bios_name);
	67	if (!machine->kernel_filename) {
	68	/* We can't boot without a bootrom or a kernel image. */
	69	exit(1);
	70	}
	71	return;
	72	}
	73	ret = load_image_mr(filename, &soc->irom);
	74	if (ret < 0) {
	75	error_report("Failed to load ROM image '%s'", filename);
	76	exit(1);
	77	}
	78	}
	79
0eb73f23 HS	80	static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
	81	const char flash_type, DriveInfo dinfo)
	82	{
	83	DeviceState *flash;
	84	qemu_irq flash_cs;
	85
	86	flash = qdev_new(flash_type);
	87	if (dinfo) {
	88	qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
	89	}
	90	qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
	91
	92	flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
	93	qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
	94	}
	95
b773acf4 HS	96	static void npcm7xx_connect_dram(NPCM7xxState soc, MemoryRegion dram)
	97	{
	98	memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
	99
	100	object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
	101	&error_abort);
	102	}
	103
93d8bc8f	104	static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
2cb06d49	105	{
93d8bc8f	106	DriveInfo *di = drive_get(IF_SD, 0, unit);
2cb06d49 SM	107	BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
	108
	109	BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus");
	110	if (bus == NULL) {
	111	error_report("No SD bus found in SOC object");
	112	exit(1);
	113	}
	114
	115	DeviceState *carddev = qdev_new(TYPE_SD_CARD);
	116	qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
	117	qdev_realize_and_unref(carddev, bus, &error_fatal);
	118	}
	119
b773acf4 HS	120	static NPCM7xxState npcm7xx_create_soc(MachineState machine,
	121	uint32_t hw_straps)
	122	{
	123	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
b773acf4 HS	124	Object *obj;
b773acf4 HS	125
b773acf4 HS	126	obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
	127	&error_abort, NULL);
	128	object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
	129
	130	return NPCM7XX(obj);
	131	}
	132
86248f53 HW	133	static I2CBus npcm7xx_i2c_get_bus(NPCM7xxState soc, uint32_t num)
	134	{
	135	g_assert(num < ARRAY_SIZE(soc->smbus));
	136	return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
	137	}
	138
a9d3d7b1 HW	139	static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
	140	NPCM7xxState soc, const int fan_counts)
	141	{
	142	SplitIRQ *splitters = machine->fan_splitter;
	143
	144	/*
	145	* PWM 0~3 belong to module 0 output 0~3.
	146	* PWM 4~7 belong to module 1 output 0~3.
	147	*/
	148	for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {
	149	for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {
	150	int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;
	151	DeviceState *splitter;
	152
	153	if (fan_counts[splitter_no] < 1) {
	154	continue;
	155	}
	156	object_initialize_child(OBJECT(machine), "fan-splitter[*]",
	157	&splitters[splitter_no], TYPE_SPLIT_IRQ);
	158	splitter = DEVICE(&splitters[splitter_no]);
	159	qdev_prop_set_uint16(splitter, "num-lines",
	160	fan_counts[splitter_no]);
	161	qdev_realize(splitter, NULL, &error_abort);
	162	qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",
	163	j, qdev_get_gpio_in(splitter, 0));
	164	}
	165	}
	166	}
	167
	168	static void npcm7xx_connect_pwm_fan(NPCM7xxState soc, SplitIRQ splitter,
	169	int fan_no, int output_no)
	170	{
	171	DeviceState *fan;
	172	int fan_input;
	173	qemu_irq fan_duty_gpio;
	174
	175	g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);
	176	/*
	177	* Fan 0~1 belong to module 0 input 0~1.
	178	* Fan 2~3 belong to module 1 input 0~1.
	179	* ...
	180	* Fan 14~15 belong to module 7 input 0~1.
	181	* Fan 16~17 belong to module 0 input 2~3.
	182	* Fan 18~19 belong to module 1 input 2~3.
	183	*/
	184	if (fan_no < 16) {
	185	fan = DEVICE(&soc->mft[fan_no / 2]);
	186	fan_input = fan_no % 2;
	187	} else {
	188	fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);
	189	fan_input = fan_no % 2 + 2;
	190	}
	191
	192	/* Connect the Fan to PWM module */
	193	fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);
	194	qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);
	195	}
	196
86248f53 HW	197	static void npcm750_evb_i2c_init(NPCM7xxState *soc)
	198	{
	199	/* lm75 temperature sensor on SVB, tmp105 is compatible */
	200	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 0), "tmp105", 0x48);
	201	/* lm75 temperature sensor on EB, tmp105 is compatible */
	202	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x48);
	203	/* tmp100 temperature sensor on EB, tmp105 is compatible */
	204	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x48);
	205	/* tmp100 temperature sensor on SVB, tmp105 is compatible */
	206	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 6), "tmp105", 0x48);
	207	}
	208
a9d3d7b1 HW	209	static void npcm750_evb_fan_init(NPCM7xxMachine machine, NPCM7xxState soc)
	210	{
	211	SplitIRQ *splitter = machine->fan_splitter;
	212	static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};
	213
	214	npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
	215	npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
	216	npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
	217	npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
	218	npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
	219	npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
	220	npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
	221	npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);
	222	npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);
	223	npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);
	224	npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);
	225	npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);
	226	npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);
	227	npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);
	228	npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);
	229	npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);
	230	npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);
	231	}
	232
2ef1e0d7 HW	233	static void quanta_gsj_i2c_init(NPCM7xxState *soc)
	234	{
	235	/* GSJ machine have 4 max31725 temperature sensors, tmp105 is compatible. */
	236	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), "tmp105", 0x5c);
	237	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 2), "tmp105", 0x5c);
	238	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
	239	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
	240
9618ebae PD	241	at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
9618ebae PD	242	at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
2ef1e0d7	243
31946687 PV	244	/*
	245	* i2c-11:
	246	* - power-brick@36: delta,dps800
	247	* - hotswap@15: ti,lm5066i
	248	*/
	249
	250	/*
	251	* i2c-12:
	252	* - ucd90160@6b
	253	*/
	254
6229659e	255	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75);
2ef1e0d7 HW	256	}
2ef1e0d7 HW	257
a9d3d7b1 HW	258	static void quanta_gsj_fan_init(NPCM7xxMachine machine, NPCM7xxState soc)
	259	{
	260	SplitIRQ *splitter = machine->fan_splitter;
	261	static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};
	262
	263	npcm7xx_init_pwm_splitter(machine, soc, fan_counts);
	264	npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);
	265	npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);
	266	npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);
	267	npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);
	268	npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);
	269	npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);
	270	}
	271
1c7f3e24 PV	272	static void quanta_gbs_i2c_init(NPCM7xxState *soc)
	273	{
	274	/*
	275	* i2c-0:
	276	* pca9546@71
	277	*
	278	* i2c-1:
	279	* pca9535@24
	280	* pca9535@20
	281	* pca9535@21
	282	* pca9535@22
	283	* pca9535@23
	284	* pca9535@25
	285	* pca9535@26
	286	*
	287	* i2c-2:
	288	* sbtsi@4c
	289	*
	290	* i2c-5:
	291	* atmel,24c64@50 mb_fru
	292	* pca9546@71
	293	* - channel 0: max31725@54
	294	* - channel 1: max31725@55
	295	* - channel 2: max31725@5d
	296	* atmel,24c64@51 fan_fru
	297	* - channel 3: atmel,24c64@52 hsbp_fru
	298	*
	299	* i2c-6:
	300	* pca9545@73
	301	*
	302	* i2c-7:
	303	* pca9545@72
	304	*
	305	* i2c-8:
	306	* adi,adm1272@10
	307	*
	308	* i2c-9:
	309	* pca9546@71
	310	* - channel 0: isil,isl68137@60
	311	* - channel 1: isil,isl68137@61
	312	* - channel 2: isil,isl68137@63
	313	* - channel 3: isil,isl68137@45
	314	*
	315	* i2c-10:
	316	* pca9545@71
	317	*
	318	* i2c-11:
	319	* pca9545@76
	320	*
	321	* i2c-12:
	322	* maxim,max34451@4e
	323	* isil,isl68137@5d
	324	* isil,isl68137@5e
	325	*
	326	* i2c-14:
	327	* pca9545@70
	328	*/
	329	}
	330
560223dc CR	331	static void kudo_bmc_i2c_init(NPCM7xxState *soc)
560223dc CR	332	{
b8905cc2 PV	333	I2CSlave *i2c_mux;
b8905cc2 PV	334
0419e6a8 PV	335	i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1),
	336	TYPE_PCA9548, 0x75);
	337
	338	/* tmp105 is compatible with the lm75 */
	339	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x5c);
	340	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x5c);
	341	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), "tmp105", 0x5c);
	342	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), "tmp105", 0x5c);
	343
5b0829d3 PV	344	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 1), TYPE_PCA9548, 0x77);
	345
	346	i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
	347
9618ebae	348	at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
5b0829d3	349
b8905cc2 PV	350	i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
	351	TYPE_PCA9548, 0x77);
	352
	353	/* tmp105 is compatible with the lm75 */
	354	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 2), "tmp105", 0x48);
	355	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 3), "tmp105", 0x49);
	356	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
	357	i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
5b0829d3	358
9618ebae	359	at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
5b0829d3	360
560223dc CR	361	/* TODO: Add remaining i2c devices. */
	362	}
	363
b773acf4 HS	364	static void npcm750_evb_init(MachineState *machine)
	365	{
	366	NPCM7xxState *soc;
	367
	368	soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
	369	npcm7xx_connect_dram(soc, machine->ram);
	370	qdev_realize(DEVICE(soc), NULL, &error_fatal);
	371
4e89ccd6	372	npcm7xx_load_bootrom(machine, soc);
0eb73f23	373	npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
86248f53	374	npcm750_evb_i2c_init(soc);
a9d3d7b1	375	npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);
b773acf4 HS	376	npcm7xx_load_kernel(machine, soc);
	377	}
	378
	379	static void quanta_gsj_init(MachineState *machine)
	380	{
	381	NPCM7xxState *soc;
	382
	383	soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
	384	npcm7xx_connect_dram(soc, machine->ram);
	385	qdev_realize(DEVICE(soc), NULL, &error_fatal);
	386
4e89ccd6	387	npcm7xx_load_bootrom(machine, soc);
0eb73f23 HS	388	npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
0eb73f23 HS	389	drive_get(IF_MTD, 0, 0));
2ef1e0d7	390	quanta_gsj_i2c_init(soc);
a9d3d7b1	391	quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);
b773acf4 HS	392	npcm7xx_load_kernel(machine, soc);
	393	}
	394
a8b3ddde PV	395	static void quanta_gbs_init(MachineState *machine)
	396	{
	397	NPCM7xxState *soc;
	398
	399	soc = npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS);
	400	npcm7xx_connect_dram(soc, machine->ram);
	401	qdev_realize(DEVICE(soc), NULL, &error_fatal);
	402
	403	npcm7xx_load_bootrom(machine, soc);
	404
	405	npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
	406	drive_get(IF_MTD, 0, 0));
	407
1c7f3e24	408	quanta_gbs_i2c_init(soc);
93d8bc8f	409	sdhci_attach_drive(&soc->mmc.sdhci, 0);
a8b3ddde PV	410	npcm7xx_load_kernel(machine, soc);
	411	}
	412
3b8a4733 CR	413	static void kudo_bmc_init(MachineState *machine)
	414	{
	415	NPCM7xxState *soc;
	416
	417	soc = npcm7xx_create_soc(machine, KUDO_BMC_POWER_ON_STRAPS);
	418	npcm7xx_connect_dram(soc, machine->ram);
	419	qdev_realize(DEVICE(soc), NULL, &error_fatal);
	420
	421	npcm7xx_load_bootrom(machine, soc);
	422	npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f",
	423	drive_get(IF_MTD, 0, 0));
	424	npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
	425	drive_get(IF_MTD, 3, 0));
	426
560223dc	427	kudo_bmc_i2c_init(soc);
b27de2c5	428	sdhci_attach_drive(&soc->mmc.sdhci, 0);
3b8a4733 CR	429	npcm7xx_load_kernel(machine, soc);
	430	}
	431
ca6d63c2 PV	432	static void mori_bmc_init(MachineState *machine)
	433	{
	434	NPCM7xxState *soc;
	435
	436	soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS);
	437	npcm7xx_connect_dram(soc, machine->ram);
	438	qdev_realize(DEVICE(soc), NULL, &error_fatal);
	439
	440	npcm7xx_load_bootrom(machine, soc);
	441	npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f",
	442	drive_get(IF_MTD, 3, 0));
	443
	444	npcm7xx_load_kernel(machine, soc);
	445	}
	446
b773acf4 HS	447	static void npcm7xx_set_soc_type(NPCM7xxMachineClass nmc, const char type)
	448	{
	449	NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
	450	MachineClass *mc = MACHINE_CLASS(nmc);
	451
	452	nmc->soc_type = type;
	453	mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
	454	}
	455
	456	static void npcm7xx_machine_class_init(ObjectClass oc, void data)
	457	{
	458	MachineClass *mc = MACHINE_CLASS(oc);
3e71f4a7 GS	459	static const char * const valid_cpu_types[] = {
	460	ARM_CPU_TYPE_NAME("cortex-a9"),
	461	NULL
	462	};
b773acf4 HS	463
	464	mc->no_floppy = 1;
	465	mc->no_cdrom = 1;
	466	mc->no_parallel = 1;
	467	mc->default_ram_id = "ram";
3e71f4a7	468	mc->valid_cpu_types = valid_cpu_types;
b773acf4 HS	469	}
	470
	471	/*
	472	* Schematics:
	473	* https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
	474	*/
	475	static void npcm750_evb_machine_class_init(ObjectClass oc, void data)
	476	{
	477	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
	478	MachineClass *mc = MACHINE_CLASS(oc);
	479
	480	npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
	481
f548f201	482	mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)";
b773acf4 HS	483	mc->init = npcm750_evb_init;
	484	mc->default_ram_size = 512 * MiB;
	485	};
	486
	487	static void gsj_machine_class_init(ObjectClass oc, void data)
	488	{
	489	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
	490	MachineClass *mc = MACHINE_CLASS(oc);
	491
	492	npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
	493
f548f201	494	mc->desc = "Quanta GSJ (Cortex-A9)";
b773acf4 HS	495	mc->init = quanta_gsj_init;
	496	mc->default_ram_size = 512 * MiB;
	497	};
	498
a8b3ddde PV	499	static void gbs_bmc_machine_class_init(ObjectClass oc, void data)
	500	{
	501	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
	502	MachineClass *mc = MACHINE_CLASS(oc);
	503
	504	npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
	505
	506	mc->desc = "Quanta GBS (Cortex-A9)";
	507	mc->init = quanta_gbs_init;
	508	mc->default_ram_size = 1 * GiB;
	509	}
	510
3b8a4733 CR	511	static void kudo_bmc_machine_class_init(ObjectClass oc, void data)
	512	{
	513	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
	514	MachineClass *mc = MACHINE_CLASS(oc);
	515
	516	npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
	517
	518	mc->desc = "Kudo BMC (Cortex-A9)";
	519	mc->init = kudo_bmc_init;
	520	mc->default_ram_size = 1 * GiB;
	521	};
	522
ca6d63c2 PV	523	static void mori_bmc_machine_class_init(ObjectClass oc, void data)
	524	{
	525	NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
	526	MachineClass *mc = MACHINE_CLASS(oc);
	527
	528	npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
	529
	530	mc->desc = "Mori BMC (Cortex-A9)";
	531	mc->init = mori_bmc_init;
	532	mc->default_ram_size = 1 * GiB;
	533	}
	534
b773acf4 HS	535	static const TypeInfo npcm7xx_machine_types[] = {
	536	{
	537	.name = TYPE_NPCM7XX_MACHINE,
	538	.parent = TYPE_MACHINE,
	539	.instance_size = sizeof(NPCM7xxMachine),
	540	.class_size = sizeof(NPCM7xxMachineClass),
	541	.class_init = npcm7xx_machine_class_init,
	542	.abstract = true,
	543	}, {
	544	.name = MACHINE_TYPE_NAME("npcm750-evb"),
	545	.parent = TYPE_NPCM7XX_MACHINE,
	546	.class_init = npcm750_evb_machine_class_init,
	547	}, {
	548	.name = MACHINE_TYPE_NAME("quanta-gsj"),
	549	.parent = TYPE_NPCM7XX_MACHINE,
	550	.class_init = gsj_machine_class_init,
a8b3ddde PV	551	}, {
	552	.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
	553	.parent = TYPE_NPCM7XX_MACHINE,
	554	.class_init = gbs_bmc_machine_class_init,
3b8a4733 CR	555	}, {
	556	.name = MACHINE_TYPE_NAME("kudo-bmc"),
	557	.parent = TYPE_NPCM7XX_MACHINE,
	558	.class_init = kudo_bmc_machine_class_init,
ca6d63c2 PV	559	}, {
	560	.name = MACHINE_TYPE_NAME("mori-bmc"),
	561	.parent = TYPE_NPCM7XX_MACHINE,
	562	.class_init = mori_bmc_machine_class_init,
b773acf4 HS	563	},
	564	};
	565
	566	DEFINE_TYPES(npcm7xx_machine_types)