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673b2d42 JS |
1 | /* |
2 | * Nordic Semiconductor nRF51 SoC | |
3 | * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf | |
4 | * | |
5 | * Copyright 2018 Joel Stanley <joel@jms.id.au> | |
6 | * | |
7 | * This code is licensed under the GPL version 2 or later. See | |
8 | * the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
11 | #include "qemu/osdep.h" | |
12 | #include "qapi/error.h" | |
12ec8bd5 | 13 | #include "hw/arm/boot.h" |
673b2d42 | 14 | #include "hw/sysbus.h" |
c08e6126 | 15 | #include "hw/qdev-clock.h" |
673b2d42 | 16 | #include "hw/misc/unimp.h" |
673b2d42 | 17 | #include "qemu/log.h" |
673b2d42 | 18 | |
659b85e4 | 19 | #include "hw/arm/nrf51.h" |
673b2d42 JS |
20 | #include "hw/arm/nrf51_soc.h" |
21 | ||
673b2d42 JS |
22 | /* |
23 | * The size and base is for the NRF51822 part. If other parts | |
24 | * are supported in the future, add a sub-class of NRF51SoC for | |
25 | * the specific variants | |
26 | */ | |
4d744b25 SG |
27 | #define NRF51822_FLASH_PAGES 256 |
28 | #define NRF51822_SRAM_PAGES 16 | |
29 | #define NRF51822_FLASH_SIZE (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE) | |
30 | #define NRF51822_SRAM_SIZE (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE) | |
673b2d42 | 31 | |
b0014913 JS |
32 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) |
33 | ||
ce4f70e8 PM |
34 | /* HCLK (the main CPU clock) on this SoC is always 16MHz */ |
35 | #define HCLK_FRQ 16000000 | |
36 | ||
b39dced6 SG |
37 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) |
38 | { | |
39 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | |
40 | __func__, addr, size); | |
41 | return 1; | |
42 | } | |
43 | ||
44 | static void clock_write(void *opaque, hwaddr addr, uint64_t data, | |
45 | unsigned int size) | |
46 | { | |
47 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | |
48 | __func__, addr, data, size); | |
49 | } | |
50 | ||
51 | static const MemoryRegionOps clock_ops = { | |
52 | .read = clock_read, | |
53 | .write = clock_write | |
54 | }; | |
55 | ||
56 | ||
673b2d42 JS |
57 | static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) |
58 | { | |
59 | NRF51State *s = NRF51_SOC(dev_soc); | |
b0014913 | 60 | MemoryRegion *mr; |
673b2d42 | 61 | Error *err = NULL; |
60facd90 SG |
62 | uint8_t i = 0; |
63 | hwaddr base_addr = 0; | |
673b2d42 JS |
64 | |
65 | if (!s->board_memory) { | |
66 | error_setg(errp, "memory property was not set"); | |
67 | return; | |
68 | } | |
69 | ||
c08e6126 PM |
70 | /* |
71 | * HCLK on this SoC is fixed, so we set up sysclk ourselves and | |
72 | * the board shouldn't connect it. | |
73 | */ | |
74 | if (clock_has_source(s->sysclk)) { | |
75 | error_setg(errp, "sysclk clock must not be wired up by the board code"); | |
76 | return; | |
77 | } | |
78 | /* This clock doesn't need migration because it is fixed-frequency */ | |
79 | clock_set_hz(s->sysclk, HCLK_FRQ); | |
80 | qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk); | |
81 | /* | |
82 | * This SoC has no systick device, so don't connect refclk. | |
83 | * TODO: model the lack of systick (currently the armv7m object | |
84 | * will always provide one). | |
85 | */ | |
86 | ||
5325cc34 | 87 | object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container), |
c24d9716 | 88 | &error_abort); |
668f62ec | 89 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) { |
673b2d42 JS |
90 | return; |
91 | } | |
92 | ||
93 | memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | |
94 | ||
287a7f6e | 95 | memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, |
96 | &err); | |
673b2d42 JS |
97 | if (err) { |
98 | error_propagate(errp, err); | |
99 | return; | |
100 | } | |
659b85e4 | 101 | memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); |
673b2d42 | 102 | |
b0014913 | 103 | /* UART */ |
668f62ec | 104 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { |
b0014913 JS |
105 | return; |
106 | } | |
107 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); | |
659b85e4 | 108 | memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); |
b0014913 JS |
109 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, |
110 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
659b85e4 | 111 | BASE_TO_IRQ(NRF51_UART_BASE))); |
b0014913 | 112 | |
f30890de | 113 | /* RNG */ |
668f62ec | 114 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rng), errp)) { |
f30890de SG |
115 | return; |
116 | } | |
117 | ||
118 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); | |
119 | memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); | |
120 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, | |
121 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
122 | BASE_TO_IRQ(NRF51_RNG_BASE))); | |
123 | ||
4d744b25 | 124 | /* UICR, FICR, NVMC, FLASH */ |
778a2dc5 | 125 | if (!object_property_set_uint(OBJECT(&s->nvm), "flash-size", |
668f62ec | 126 | s->flash_size, errp)) { |
4d744b25 SG |
127 | return; |
128 | } | |
129 | ||
668f62ec | 130 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->nvm), errp)) { |
4d744b25 SG |
131 | return; |
132 | } | |
133 | ||
134 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); | |
135 | memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0); | |
136 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); | |
137 | memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0); | |
138 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); | |
139 | memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0); | |
140 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3); | |
141 | memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0); | |
142 | ||
bb42c4cb | 143 | /* GPIO */ |
668f62ec | 144 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
bb42c4cb SG |
145 | return; |
146 | } | |
147 | ||
148 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); | |
149 | memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); | |
150 | ||
151 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
152 | qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); | |
153 | ||
60facd90 SG |
154 | /* TIMER */ |
155 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { | |
668f62ec | 156 | if (!object_property_set_uint(OBJECT(&s->timer[i]), "id", i, errp)) { |
27d6dea3 PMD |
157 | return; |
158 | } | |
668f62ec | 159 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { |
60facd90 SG |
160 | return; |
161 | } | |
162 | ||
54595a57 | 163 | base_addr = NRF51_TIMER_BASE + i * NRF51_PERIPHERAL_SIZE; |
60facd90 SG |
164 | |
165 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); | |
166 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, | |
167 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
168 | BASE_TO_IRQ(base_addr))); | |
169 | } | |
170 | ||
b39dced6 | 171 | /* STUB Peripherals */ |
32b9523a | 172 | memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL, |
54595a57 | 173 | "nrf51_soc.clock", NRF51_PERIPHERAL_SIZE); |
b39dced6 SG |
174 | memory_region_add_subregion_overlap(&s->container, |
175 | NRF51_IOMEM_BASE, &s->clock, -1); | |
176 | ||
659b85e4 SG |
177 | create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, |
178 | NRF51_IOMEM_SIZE); | |
673b2d42 | 179 | create_unimplemented_device("nrf51_soc.private", |
659b85e4 | 180 | NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); |
673b2d42 JS |
181 | } |
182 | ||
183 | static void nrf51_soc_init(Object *obj) | |
184 | { | |
60facd90 SG |
185 | uint8_t i = 0; |
186 | ||
673b2d42 JS |
187 | NRF51State *s = NRF51_SOC(obj); |
188 | ||
189 | memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); | |
190 | ||
db873cc5 | 191 | object_initialize_child(OBJECT(s), "armv6m", &s->cpu, TYPE_ARMV7M); |
673b2d42 JS |
192 | qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", |
193 | ARM_CPU_TYPE_NAME("cortex-m0")); | |
194 | qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); | |
b0014913 | 195 | |
db873cc5 | 196 | object_initialize_child(obj, "uart", &s->uart, TYPE_NRF51_UART); |
d2623129 | 197 | object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev"); |
f30890de | 198 | |
db873cc5 | 199 | object_initialize_child(obj, "rng", &s->rng, TYPE_NRF51_RNG); |
bb42c4cb | 200 | |
db873cc5 | 201 | object_initialize_child(obj, "nvm", &s->nvm, TYPE_NRF51_NVM); |
4d744b25 | 202 | |
db873cc5 | 203 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_NRF51_GPIO); |
60facd90 SG |
204 | |
205 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { | |
db873cc5 MA |
206 | object_initialize_child(obj, "timer[*]", &s->timer[i], |
207 | TYPE_NRF51_TIMER); | |
60facd90 SG |
208 | |
209 | } | |
c08e6126 PM |
210 | |
211 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); | |
673b2d42 JS |
212 | } |
213 | ||
214 | static Property nrf51_soc_properties[] = { | |
215 | DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, | |
216 | MemoryRegion *), | |
217 | DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), | |
218 | DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, | |
219 | NRF51822_FLASH_SIZE), | |
220 | DEFINE_PROP_END_OF_LIST(), | |
221 | }; | |
222 | ||
223 | static void nrf51_soc_class_init(ObjectClass *klass, void *data) | |
224 | { | |
225 | DeviceClass *dc = DEVICE_CLASS(klass); | |
226 | ||
227 | dc->realize = nrf51_soc_realize; | |
4f67d30b | 228 | device_class_set_props(dc, nrf51_soc_properties); |
673b2d42 JS |
229 | } |
230 | ||
231 | static const TypeInfo nrf51_soc_info = { | |
232 | .name = TYPE_NRF51_SOC, | |
233 | .parent = TYPE_SYS_BUS_DEVICE, | |
234 | .instance_size = sizeof(NRF51State), | |
235 | .instance_init = nrf51_soc_init, | |
236 | .class_init = nrf51_soc_class_init, | |
237 | }; | |
238 | ||
239 | static void nrf51_soc_types(void) | |
240 | { | |
241 | type_register_static(&nrf51_soc_info); | |
242 | } | |
243 | type_init(nrf51_soc_types) |