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673b2d42 JS |
1 | /* |
2 | * Nordic Semiconductor nRF51 SoC | |
3 | * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf | |
4 | * | |
5 | * Copyright 2018 Joel Stanley <joel@jms.id.au> | |
6 | * | |
7 | * This code is licensed under the GPL version 2 or later. See | |
8 | * the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
11 | #include "qemu/osdep.h" | |
12 | #include "qapi/error.h" | |
13 | #include "qemu-common.h" | |
14 | #include "hw/arm/arm.h" | |
15 | #include "hw/sysbus.h" | |
16 | #include "hw/boards.h" | |
17 | #include "hw/devices.h" | |
18 | #include "hw/misc/unimp.h" | |
19 | #include "exec/address-spaces.h" | |
20 | #include "sysemu/sysemu.h" | |
21 | #include "qemu/log.h" | |
22 | #include "cpu.h" | |
23 | ||
659b85e4 | 24 | #include "hw/arm/nrf51.h" |
673b2d42 JS |
25 | #include "hw/arm/nrf51_soc.h" |
26 | ||
673b2d42 JS |
27 | /* |
28 | * The size and base is for the NRF51822 part. If other parts | |
29 | * are supported in the future, add a sub-class of NRF51SoC for | |
30 | * the specific variants | |
31 | */ | |
659b85e4 SG |
32 | #define NRF51822_FLASH_SIZE (256 * NRF51_PAGE_SIZE) |
33 | #define NRF51822_SRAM_SIZE (16 * NRF51_PAGE_SIZE) | |
673b2d42 | 34 | |
b0014913 JS |
35 | #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F) |
36 | ||
b39dced6 SG |
37 | static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) |
38 | { | |
39 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", | |
40 | __func__, addr, size); | |
41 | return 1; | |
42 | } | |
43 | ||
44 | static void clock_write(void *opaque, hwaddr addr, uint64_t data, | |
45 | unsigned int size) | |
46 | { | |
47 | qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n", | |
48 | __func__, addr, data, size); | |
49 | } | |
50 | ||
51 | static const MemoryRegionOps clock_ops = { | |
52 | .read = clock_read, | |
53 | .write = clock_write | |
54 | }; | |
55 | ||
56 | ||
673b2d42 JS |
57 | static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) |
58 | { | |
59 | NRF51State *s = NRF51_SOC(dev_soc); | |
b0014913 | 60 | MemoryRegion *mr; |
673b2d42 | 61 | Error *err = NULL; |
60facd90 SG |
62 | uint8_t i = 0; |
63 | hwaddr base_addr = 0; | |
673b2d42 JS |
64 | |
65 | if (!s->board_memory) { | |
66 | error_setg(errp, "memory property was not set"); | |
67 | return; | |
68 | } | |
69 | ||
70 | object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory", | |
71 | &err); | |
72 | if (err) { | |
73 | error_propagate(errp, err); | |
74 | return; | |
75 | } | |
76 | object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); | |
77 | if (err) { | |
78 | error_propagate(errp, err); | |
79 | return; | |
80 | } | |
81 | ||
82 | memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); | |
83 | ||
84 | memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size, | |
85 | &err); | |
86 | if (err) { | |
87 | error_propagate(errp, err); | |
88 | return; | |
89 | } | |
659b85e4 | 90 | memory_region_add_subregion(&s->container, NRF51_FLASH_BASE, &s->flash); |
673b2d42 | 91 | |
287a7f6e | 92 | memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, |
93 | &err); | |
673b2d42 JS |
94 | if (err) { |
95 | error_propagate(errp, err); | |
96 | return; | |
97 | } | |
659b85e4 | 98 | memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); |
673b2d42 | 99 | |
b0014913 JS |
100 | /* UART */ |
101 | object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); | |
102 | if (err) { | |
103 | error_propagate(errp, err); | |
104 | return; | |
105 | } | |
106 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); | |
659b85e4 | 107 | memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0); |
b0014913 JS |
108 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, |
109 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
659b85e4 | 110 | BASE_TO_IRQ(NRF51_UART_BASE))); |
b0014913 | 111 | |
f30890de SG |
112 | /* RNG */ |
113 | object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); | |
114 | if (err) { | |
115 | error_propagate(errp, err); | |
116 | return; | |
117 | } | |
118 | ||
119 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); | |
120 | memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0); | |
121 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, | |
122 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
123 | BASE_TO_IRQ(NRF51_RNG_BASE))); | |
124 | ||
bb42c4cb SG |
125 | /* GPIO */ |
126 | object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | |
127 | if (err) { | |
128 | error_propagate(errp, err); | |
129 | return; | |
130 | } | |
131 | ||
132 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); | |
133 | memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0); | |
134 | ||
135 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
136 | qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); | |
137 | ||
60facd90 SG |
138 | /* TIMER */ |
139 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { | |
140 | object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); | |
141 | if (err) { | |
142 | error_propagate(errp, err); | |
143 | return; | |
144 | } | |
145 | ||
146 | base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE; | |
147 | ||
148 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr); | |
149 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, | |
150 | qdev_get_gpio_in(DEVICE(&s->cpu), | |
151 | BASE_TO_IRQ(base_addr))); | |
152 | } | |
153 | ||
b39dced6 SG |
154 | /* STUB Peripherals */ |
155 | memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, | |
156 | "nrf51_soc.clock", 0x1000); | |
157 | memory_region_add_subregion_overlap(&s->container, | |
158 | NRF51_IOMEM_BASE, &s->clock, -1); | |
159 | ||
659b85e4 SG |
160 | create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE, |
161 | NRF51_IOMEM_SIZE); | |
162 | create_unimplemented_device("nrf51_soc.ficr", NRF51_FICR_BASE, | |
163 | NRF51_FICR_SIZE); | |
673b2d42 | 164 | create_unimplemented_device("nrf51_soc.private", |
659b85e4 | 165 | NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE); |
673b2d42 JS |
166 | } |
167 | ||
168 | static void nrf51_soc_init(Object *obj) | |
169 | { | |
60facd90 SG |
170 | uint8_t i = 0; |
171 | ||
673b2d42 JS |
172 | NRF51State *s = NRF51_SOC(obj); |
173 | ||
174 | memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); | |
175 | ||
176 | sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu), | |
177 | TYPE_ARMV7M); | |
178 | qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", | |
179 | ARM_CPU_TYPE_NAME("cortex-m0")); | |
180 | qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); | |
b0014913 JS |
181 | |
182 | sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart), | |
183 | TYPE_NRF51_UART); | |
184 | object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev", | |
185 | &error_abort); | |
f30890de SG |
186 | |
187 | sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng), | |
188 | TYPE_NRF51_RNG); | |
bb42c4cb SG |
189 | |
190 | sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), | |
191 | TYPE_NRF51_GPIO); | |
60facd90 SG |
192 | |
193 | for (i = 0; i < NRF51_NUM_TIMERS; i++) { | |
194 | sysbus_init_child_obj(obj, "timer[*]", &s->timer[i], | |
195 | sizeof(s->timer[i]), TYPE_NRF51_TIMER); | |
196 | ||
197 | } | |
673b2d42 JS |
198 | } |
199 | ||
200 | static Property nrf51_soc_properties[] = { | |
201 | DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION, | |
202 | MemoryRegion *), | |
203 | DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), | |
204 | DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, | |
205 | NRF51822_FLASH_SIZE), | |
206 | DEFINE_PROP_END_OF_LIST(), | |
207 | }; | |
208 | ||
209 | static void nrf51_soc_class_init(ObjectClass *klass, void *data) | |
210 | { | |
211 | DeviceClass *dc = DEVICE_CLASS(klass); | |
212 | ||
213 | dc->realize = nrf51_soc_realize; | |
214 | dc->props = nrf51_soc_properties; | |
215 | } | |
216 | ||
217 | static const TypeInfo nrf51_soc_info = { | |
218 | .name = TYPE_NRF51_SOC, | |
219 | .parent = TYPE_SYS_BUS_DEVICE, | |
220 | .instance_size = sizeof(NRF51State), | |
221 | .instance_init = nrf51_soc_init, | |
222 | .class_init = nrf51_soc_class_init, | |
223 | }; | |
224 | ||
225 | static void nrf51_soc_types(void) | |
226 | { | |
227 | type_register_static(&nrf51_soc_info); | |
228 | } | |
229 | type_init(nrf51_soc_types) |