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7e7c5e4c
AZ		 1/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 19 */
20
12b16722 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
33c11879 23#include "cpu.h"
f348b6d1 24#include "qemu/cutils.h"
58369e22 25#include "qemu/bswap.h"
9c17d615 26#include "sysemu/sysemu.h"
0d09e41a 27#include "hw/arm/omap.h"
bd2be150 28#include "hw/arm/arm.h"
83c9f4ca 29#include "hw/irq.h"
28ecbaee 30#include "ui/console.h"
83c9f4ca 31#include "hw/boards.h"
0d09e41a 32#include "hw/i2c/i2c.h"
bd2be150 33#include "hw/devices.h"
0d09e41a 34#include "hw/block/flash.h"
83c9f4ca
PB		 35#include "hw/hw.h"
36#include "hw/bt.h"
37#include "hw/loader.h"
fa1d36df 38#include "sysemu/block-backend.h"
83c9f4ca 39#include "hw/sysbus.h"
03dd024f 40#include "qemu/log.h"
022c62cb 41#include "exec/address-spaces.h"
7e7c5e4c
AZ		 42
43/* Nokia N8x0 support */
44struct n800_s {
518ec134 45 struct omap_mpu_state_s *mpu;
7e7c5e4c
AZ		 46
47 struct rfbi_chip_s blizzard;
e927bb00
AZ		 48 struct {
49 void *opaque;
50 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
bc24a225 51 uWireSlave *chip;
e927bb00 52 } ts;
7e7c5e4c
AZ		 53
54 int keymap[0x80];
c4f05c8c 55 DeviceState *kbd;
7e7c5e4c 56
bdc76462 57 DeviceState *usb;
7e7c5e4c
AZ		 58 void *retu;
59 void *tahvo;
500954e3 60 DeviceState *nand;
7e7c5e4c
AZ		 61};
62
63/* GPIO pins */
e927bb00 64#define N8X0_TUSB_ENABLE_GPIO 0
7e7c5e4c
AZ		 65#define N800_MMC2_WP_GPIO 8
66#define N800_UNKNOWN_GPIO0 9 /* out */
0941041e 67#define N810_MMC2_VIOSD_GPIO 9
99570a40 68#define N810_HEADSET_AMP_GPIO 10
7e7c5e4c 69#define N800_CAM_TURN_GPIO 12
e927bb00 70#define N810_GPS_RESET_GPIO 12
7e7c5e4c
AZ		 71#define N800_BLIZZARD_POWERDOWN_GPIO 15
72#define N800_MMC1_WP_GPIO 23
0941041e 73#define N810_MMC2_VSD_GPIO 23
7e7c5e4c 74#define N8X0_ONENAND_GPIO 26
e927bb00 75#define N810_BLIZZARD_RESET_GPIO 30
7e7c5e4c
AZ		 76#define N800_UNKNOWN_GPIO2 53 /* out */
77#define N8X0_TUSB_INT_GPIO 58
e927bb00
AZ		 78#define N8X0_BT_WKUP_GPIO 61
79#define N8X0_STI_GPIO 62
7e7c5e4c 80#define N8X0_CBUS_SEL_GPIO 64
e927bb00
AZ		 81#define N8X0_CBUS_DAT_GPIO 65
82#define N8X0_CBUS_CLK_GPIO 66
83#define N8X0_WLAN_IRQ_GPIO 87
84#define N8X0_BT_RESET_GPIO 92
85#define N8X0_TEA5761_CS_GPIO 93
7e7c5e4c 86#define N800_UNKNOWN_GPIO 94
e927bb00 87#define N810_TSC_RESET_GPIO 94
7e7c5e4c 88#define N800_CAM_ACT_GPIO 95
e927bb00
AZ		 89#define N810_GPS_WAKEUP_GPIO 95
90#define N8X0_MMC_CS_GPIO 96
91#define N8X0_WLAN_PWR_GPIO 97
7e7c5e4c 92#define N8X0_BT_HOST_WKUP_GPIO 98
99570a40 93#define N810_SPEAKER_AMP_GPIO 101
7e7c5e4c
AZ		 94#define N810_KB_LOCK_GPIO 102
95#define N800_TSC_TS_GPIO 103
e927bb00
AZ		 96#define N810_TSC_TS_GPIO 106
97#define N8X0_HEADPHONE_GPIO 107
7e7c5e4c
AZ		 98#define N8X0_RETU_GPIO 108
99#define N800_TSC_KP_IRQ_GPIO 109
100#define N810_KEYBOARD_GPIO 109
101#define N800_BAT_COVER_GPIO 110
102#define N810_SLIDE_GPIO 110
103#define N8X0_TAHVO_GPIO 111
104#define N800_UNKNOWN_GPIO4 112 /* out */
e927bb00 105#define N810_SLEEPX_LED_GPIO 112
1d4e547b 106#define N800_TSC_RESET_GPIO 118 /* ? */
99570a40 107#define N810_AIC33_RESET_GPIO 118
1d4e547b 108#define N800_TSC_UNKNOWN_GPIO 119 /* out */
7e7c5e4c
AZ		 109#define N8X0_TMP105_GPIO 125
110
111/* Config */
c580d92b 112#define BT_UART 0
7e7c5e4c
AZ		 113#define XLDR_LL_UART 1
114
1d4e547b
AZ		 115/* Addresses on the I2C bus 0 */
116#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
117#define N8X0_TCM825x_ADDR 0x29 /* Camera */
118#define N810_LP5521_ADDR 0x32 /* LEDs */
119#define N810_TSL2563_ADDR 0x3d /* Light sensor */
120#define N810_LM8323_ADDR 0x45 /* Keyboard */
121/* Addresses on the I2C bus 1 */
122#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
123#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
7e7c5e4c
AZ		 124
125/* Chipselects on GPMC NOR interface */
126#define N8X0_ONENAND_CS 0
127#define N8X0_USB_ASYNC_CS 1
128#define N8X0_USB_SYNC_CS 4
129
c580d92b
AZ		 130#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
131
7e7c5e4c
AZ		 132static void n800_mmc_cs_cb(void *opaque, int line, int level)
133{
134 /* TODO: this seems to actually be connected to the menelaus, to
135 * which also both MMC slots connect. */
136 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
7e7c5e4c
AZ		 137}
138
e927bb00 139static void n8x0_gpio_setup(struct n800_s *s)
7e7c5e4c 140{
294972ce
SZ		 141 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO,
142 qemu_allocate_irq(n800_mmc_cs_cb, s->mpu->mmc, 0));
518ec134 143 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
7e7c5e4c
AZ		 144}
145
c580d92b
AZ		 146#define MAEMO_CAL_HEADER(...) \
147 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
148 __VA_ARGS__, \
149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
150
151static const uint8_t n8x0_cal_wlan_mac[] = {
152 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
153 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
154 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
155 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
156 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
157 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
158};
159
160static const uint8_t n8x0_cal_bt_id[] = {
161 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
162 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
163 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
164 N8X0_BD_ADDR,
165};
166
7e7c5e4c
AZ		 167static void n8x0_nand_setup(struct n800_s *s)
168{
c580d92b 169 char *otp_region;
af5a75f4 170 DriveInfo *dinfo;
c580d92b 171
500954e3
JR		 172 s->nand = qdev_create(NULL, "onenand");
173 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
5923ba42 174 /* Either 0x40 or 0x48 are OK for the device ID */
500954e3
JR		 175 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
176 qdev_prop_set_uint16(s->nand, "version_id", 0);
177 qdev_prop_set_int32(s->nand, "shift", 1);
178 dinfo = drive_get(IF_MTD, 0, 0);
fa1d36df 179 if (dinfo) {
6231a6da
MA		 180 qdev_prop_set_drive(s->nand, "drive", blk_by_legacy_dinfo(dinfo),
181 &error_fatal);
500954e3
JR		 182 }
183 qdev_init_nofail(s->nand);
1356b98d 184 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
518ec134
AF		 185 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
186 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
1356b98d 187 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
c580d92b
AZ		 188 otp_region = onenand_raw_otp(s->nand);
189
190 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
191 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
192 /* XXX: in theory should also update the OOB for both pages */
7e7c5e4c
AZ		 193}
194
c72ddb1e
IM		 195static qemu_irq n8x0_system_powerdown;
196
197static void n8x0_powerdown_req(Notifier *n, void *opaque)
198{
199 qemu_irq_raise(n8x0_system_powerdown);
200}
201
202static Notifier n8x0_system_powerdown_notifier = {
203 .notify = n8x0_powerdown_req
204};
205
e927bb00 206static void n8x0_i2c_setup(struct n800_s *s)
7e7c5e4c 207{
697454eb 208 DeviceState *dev;
518ec134 209 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
a5c82852 210 I2CBus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
7e7c5e4c
AZ		 211
212 /* Attach a menelaus PM chip */
54e17933 213 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
0919ac78 214 qdev_connect_gpio_out(dev, 3,
518ec134 215 qdev_get_gpio_in(s->mpu->ih[0],
0919ac78 216 OMAP_INT_24XX_SYS_NIRQ));
7e7c5e4c 217
c72ddb1e
IM		 218 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
219 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
dd4427a6 220
7e7c5e4c 221 /* Attach a TMP105 PM chip (A0 wired to ground) */
54e17933 222 dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
697454eb 223 qdev_connect_gpio_out(dev, 0, tmp_irq);
7e7c5e4c
AZ		 224}
225
226/* Touchscreen and keypad controller */
bc24a225 227static MouseTransformInfo n800_pointercal = {
e927bb00
AZ		 228 .x = 800,
229 .y = 480,
230 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
231};
232
bc24a225 233static MouseTransformInfo n810_pointercal = {
e927bb00
AZ		 234 .x = 800,
235 .y = 480,
236 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
237};
238
7e7c5e4c
AZ		 239#define RETU_KEYCODE 61 /* F3 */
240
241static void n800_key_event(void *opaque, int keycode)
242{
243 struct n800_s *s = (struct n800_s *) opaque;
244 int code = s->keymap[keycode & 0x7f];
245
246 if (code == -1) {
fddbd80c 247 if ((keycode & 0x7f) == RETU_KEYCODE) {
7e7c5e4c 248 retu_key_event(s->retu, !(keycode & 0x80));
fddbd80c 249 }
7e7c5e4c
AZ		 250 return;
251 }
252
e927bb00 253 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
7e7c5e4c
AZ		 254}
255
256static const int n800_keys[16] = {
257 -1,
258 72, /* Up */
259 63, /* Home (F5) */
260 -1,
261 75, /* Left */
262 28, /* Enter */
263 77, /* Right */
264 -1,
1d4e547b 265 1, /* Cycle (ESC) */
7e7c5e4c
AZ		 266 80, /* Down */
267 62, /* Menu (F4) */
268 -1,
269 66, /* Zoom- (F8) */
1d4e547b 270 64, /* FullScreen (F6) */
7e7c5e4c
AZ		 271 65, /* Zoom+ (F7) */
272 -1,
273};
274
e927bb00 275static void n800_tsc_kbd_setup(struct n800_s *s)
7e7c5e4c
AZ		 276{
277 int i;
278
279 /* XXX: are the three pins inverted inside the chip between the
280 * tsc and the cpu (N4111)? */
b9d38e95 281 qemu_irq penirq = NULL; /* NC */
518ec134
AF		 282 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
283 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
7e7c5e4c 284
22d83b14 285 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
e927bb00
AZ		 286 s->ts.opaque = s->ts.chip->opaque;
287 s->ts.txrx = tsc210x_txrx;
7e7c5e4c 288
fddbd80c 289 for (i = 0; i < 0x80; i++) {
7e7c5e4c 290 s->keymap[i] = -1;
fddbd80c
PB		 291 }
292 for (i = 0; i < 0x10; i++) {
293 if (n800_keys[i] >= 0) {
7e7c5e4c 294 s->keymap[n800_keys[i]] = i;
fddbd80c
PB		 295 }
296 }
7e7c5e4c
AZ		 297
298 qemu_add_kbd_event_handler(n800_key_event, s);
299
e927bb00
AZ		 300 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
301}
302
303static void n810_tsc_setup(struct n800_s *s)
304{
518ec134 305 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
e927bb00
AZ		 306
307 s->ts.opaque = tsc2005_init(pintdav);
308 s->ts.txrx = tsc2005_txrx;
309
310 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
7e7c5e4c
AZ		 311}
312
1d4e547b
AZ		 313/* N810 Keyboard controller */
314static void n810_key_event(void *opaque, int keycode)
315{
316 struct n800_s *s = (struct n800_s *) opaque;
317 int code = s->keymap[keycode & 0x7f];
318
319 if (code == -1) {
fddbd80c 320 if ((keycode & 0x7f) == RETU_KEYCODE) {
1d4e547b 321 retu_key_event(s->retu, !(keycode & 0x80));
fddbd80c 322 }
1d4e547b
AZ		 323 return;
324 }
325
326 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
327}
328
329#define M 0
330
331static int n810_keys[0x80] = {
332 [0x01] = 16, /* Q */
333 [0x02] = 37, /* K */
334 [0x03] = 24, /* O */
335 [0x04] = 25, /* P */
336 [0x05] = 14, /* Backspace */
337 [0x06] = 30, /* A */
338 [0x07] = 31, /* S */
339 [0x08] = 32, /* D */
340 [0x09] = 33, /* F */
341 [0x0a] = 34, /* G */
342 [0x0b] = 35, /* H */
343 [0x0c] = 36, /* J */
344
345 [0x11] = 17, /* W */
346 [0x12] = 62, /* Menu (F4) */
347 [0x13] = 38, /* L */
348 [0x14] = 40, /* ' (Apostrophe) */
349 [0x16] = 44, /* Z */
350 [0x17] = 45, /* X */
351 [0x18] = 46, /* C */
352 [0x19] = 47, /* V */
353 [0x1a] = 48, /* B */
354 [0x1b] = 49, /* N */
355 [0x1c] = 42, /* Shift (Left shift) */
356 [0x1f] = 65, /* Zoom+ (F7) */
357
358 [0x21] = 18, /* E */
359 [0x22] = 39, /* ; (Semicolon) */
360 [0x23] = 12, /* - (Minus) */
361 [0x24] = 13, /* = (Equal) */
362 [0x2b] = 56, /* Fn (Left Alt) */
363 [0x2c] = 50, /* M */
364 [0x2f] = 66, /* Zoom- (F8) */
365
366 [0x31] = 19, /* R */
367 [0x32] = 29 | M, /* Right Ctrl */
368 [0x34] = 57, /* Space */
369 [0x35] = 51, /* , (Comma) */
370 [0x37] = 72 | M, /* Up */
371 [0x3c] = 82 | M, /* Compose (Insert) */
372 [0x3f] = 64, /* FullScreen (F6) */
373
374 [0x41] = 20, /* T */
375 [0x44] = 52, /* . (Dot) */
376 [0x46] = 77 | M, /* Right */
377 [0x4f] = 63, /* Home (F5) */
378 [0x51] = 21, /* Y */
379 [0x53] = 80 | M, /* Down */
380 [0x55] = 28, /* Enter */
381 [0x5f] = 1, /* Cycle (ESC) */
382
383 [0x61] = 22, /* U */
384 [0x64] = 75 | M, /* Left */
385
386 [0x71] = 23, /* I */
387#if 0
388 [0x75] = 28 | M, /* KP Enter (KP Enter) */
389#else
390 [0x75] = 15, /* KP Enter (Tab) */
391#endif
392};
393
394#undef M
395
396static void n810_kbd_setup(struct n800_s *s)
397{
518ec134 398 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
1d4e547b
AZ		 399 int i;
400
fddbd80c 401 for (i = 0; i < 0x80; i++) {
1d4e547b 402 s->keymap[i] = -1;
fddbd80c
PB		 403 }
404 for (i = 0; i < 0x80; i++) {
405 if (n810_keys[i] > 0) {
1d4e547b 406 s->keymap[n810_keys[i]] = i;
fddbd80c
PB		 407 }
408 }
1d4e547b
AZ		 409
410 qemu_add_kbd_event_handler(n810_key_event, s);
411
412 /* Attach the LM8322 keyboard to the I2C bus,
413 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
518ec134 414 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
54e17933 415 "lm8323", N810_LM8323_ADDR);
c4f05c8c 416 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
1d4e547b
AZ		 417}
418
7e7c5e4c
AZ		 419/* LCD MIPI DBI-C controller (URAL) */
420struct mipid_s {
421 int resp[4];
422 int param[4];
423 int p;
424 int pm;
425 int cmd;
426
427 int sleep;
428 int booster;
429 int te;
430 int selfcheck;
431 int partial;
432 int normal;
433 int vscr;
434 int invert;
435 int onoff;
436 int gamma;
437 uint32_t id;
438};
439
440static void mipid_reset(struct mipid_s *s)
441{
7e7c5e4c
AZ		 442 s->pm = 0;
443 s->cmd = 0;
444
445 s->sleep = 1;
446 s->booster = 0;
447 s->selfcheck =
448 (1 << 7) | /* Register loading OK. */
449 (1 << 5) | /* The chip is attached. */
450 (1 << 4); /* Display glass still in one piece. */
451 s->te = 0;
452 s->partial = 0;
453 s->normal = 1;
454 s->vscr = 0;
455 s->invert = 0;
456 s->onoff = 1;
457 s->gamma = 0;
458}
459
e927bb00 460static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
7e7c5e4c
AZ		 461{
462 struct mipid_s *s = (struct mipid_s *) opaque;
463 uint8_t ret;
464
fddbd80c 465 if (len > 9) {
2ac71179 466 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
fddbd80c 467 }
e927bb00 468
fddbd80c 469 if (s->p >= ARRAY_SIZE(s->resp)) {
7e7c5e4c 470 ret = 0;
fddbd80c
PB		 471 } else {
472 ret = s->resp[s->p++];
473 }
474 if (s->pm-- > 0) {
7e7c5e4c 475 s->param[s->pm] = cmd;
fddbd80c 476 } else {
7e7c5e4c 477 s->cmd = cmd;
fddbd80c 478 }
7e7c5e4c
AZ		 479
480 switch (s->cmd) {
481 case 0x00: /* NOP */
482 break;
483
484 case 0x01: /* SWRESET */
485 mipid_reset(s);
486 break;
487
488 case 0x02: /* BSTROFF */
489 s->booster = 0;
490 break;
491 case 0x03: /* BSTRON */
492 s->booster = 1;
493 break;
494
495 case 0x04: /* RDDID */
496 s->p = 0;
497 s->resp[0] = (s->id >> 16) & 0xff;
498 s->resp[1] = (s->id >> 8) & 0xff;
499 s->resp[2] = (s->id >> 0) & 0xff;
500 break;
501
502 case 0x06: /* RD_RED */
503 case 0x07: /* RD_GREEN */
504 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
505 * for the bootloader one needs to change this. */
506 case 0x08: /* RD_BLUE */
507 s->p = 0;
508 /* TODO: return first pixel components */
509 s->resp[0] = 0x01;
510 break;
511
512 case 0x09: /* RDDST */
513 s->p = 0;
514 s->resp[0] = s->booster << 7;
515 s->resp[1] = (5 << 4) | (s->partial << 2) |
516 (s->sleep << 1) | s->normal;
517 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
518 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
519 s->resp[3] = s->gamma << 6;
520 break;
521
522 case 0x0a: /* RDDPM */
523 s->p = 0;
524 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
525 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
526 break;
527 case 0x0b: /* RDDMADCTR */
528 s->p = 0;
529 s->resp[0] = 0;
530 break;
531 case 0x0c: /* RDDCOLMOD */
532 s->p = 0;
533 s->resp[0] = 5; /* 65K colours */
534 break;
535 case 0x0d: /* RDDIM */
536 s->p = 0;
537 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
538 break;
539 case 0x0e: /* RDDSM */
540 s->p = 0;
541 s->resp[0] = s->te << 7;
542 break;
543 case 0x0f: /* RDDSDR */
544 s->p = 0;
545 s->resp[0] = s->selfcheck;
546 break;
547
548 case 0x10: /* SLPIN */
549 s->sleep = 1;
550 break;
551 case 0x11: /* SLPOUT */
552 s->sleep = 0;
553 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
554 break;
555
556 case 0x12: /* PTLON */
557 s->partial = 1;
558 s->normal = 0;
559 s->vscr = 0;
560 break;
561 case 0x13: /* NORON */
562 s->partial = 0;
563 s->normal = 1;
564 s->vscr = 0;
565 break;
566
567 case 0x20: /* INVOFF */
568 s->invert = 0;
569 break;
570 case 0x21: /* INVON */
571 s->invert = 1;
572 break;
573
574 case 0x22: /* APOFF */
575 case 0x23: /* APON */
576 goto bad_cmd;
577
578 case 0x25: /* WRCNTR */
fddbd80c 579 if (s->pm < 0) {
7e7c5e4c 580 s->pm = 1;
fddbd80c 581 }
7e7c5e4c
AZ		 582 goto bad_cmd;
583
584 case 0x26: /* GAMSET */
fddbd80c 585 if (!s->pm) {
ad5f5fdc
SH		 586 s->gamma = ctz32(s->param[0] & 0xf);
587 if (s->gamma == 32) {
588 s->gamma = -1; /* XXX: should this be 0? */
589 }
fddbd80c 590 } else if (s->pm < 0) {
7e7c5e4c 591 s->pm = 1;
fddbd80c 592 }
7e7c5e4c
AZ		 593 break;
594
595 case 0x28: /* DISPOFF */
596 s->onoff = 0;
7e7c5e4c
AZ		 597 break;
598 case 0x29: /* DISPON */
599 s->onoff = 1;
7e7c5e4c
AZ		 600 break;
601
602 case 0x2a: /* CASET */
603 case 0x2b: /* RASET */
604 case 0x2c: /* RAMWR */
605 case 0x2d: /* RGBSET */
606 case 0x2e: /* RAMRD */
607 case 0x30: /* PTLAR */
608 case 0x33: /* SCRLAR */
609 goto bad_cmd;
610
611 case 0x34: /* TEOFF */
612 s->te = 0;
613 break;
614 case 0x35: /* TEON */
fddbd80c 615 if (!s->pm) {
7e7c5e4c 616 s->te = 1;
fddbd80c 617 } else if (s->pm < 0) {
7e7c5e4c 618 s->pm = 1;
fddbd80c 619 }
7e7c5e4c
AZ		 620 break;
621
622 case 0x36: /* MADCTR */
623 goto bad_cmd;
624
625 case 0x37: /* VSCSAD */
626 s->partial = 0;
627 s->normal = 0;
628 s->vscr = 1;
629 break;
630
631 case 0x38: /* IDMOFF */
632 case 0x39: /* IDMON */
633 case 0x3a: /* COLMOD */
634 goto bad_cmd;
635
636 case 0xb0: /* CLKINT / DISCTL */
637 case 0xb1: /* CLKEXT */
fddbd80c 638 if (s->pm < 0) {
7e7c5e4c 639 s->pm = 2;
fddbd80c 640 }
7e7c5e4c
AZ		 641 break;
642
643 case 0xb4: /* FRMSEL */
644 break;
645
646 case 0xb5: /* FRM8SEL */
647 case 0xb6: /* TMPRNG / INIESC */
648 case 0xb7: /* TMPHIS / NOP2 */
649 case 0xb8: /* TMPREAD / MADCTL */
650 case 0xba: /* DISTCTR */
651 case 0xbb: /* EPVOL */
652 goto bad_cmd;
653
654 case 0xbd: /* Unknown */
655 s->p = 0;
656 s->resp[0] = 0;
657 s->resp[1] = 1;
658 break;
659
660 case 0xc2: /* IFMOD */
fddbd80c 661 if (s->pm < 0) {
7e7c5e4c 662 s->pm = 2;
fddbd80c 663 }
7e7c5e4c
AZ		 664 break;
665
666 case 0xc6: /* PWRCTL */
667 case 0xc7: /* PPWRCTL */
668 case 0xd0: /* EPWROUT */
669 case 0xd1: /* EPWRIN */
670 case 0xd4: /* RDEV */
671 case 0xd5: /* RDRR */
672 goto bad_cmd;
673
674 case 0xda: /* RDID1 */
675 s->p = 0;
676 s->resp[0] = (s->id >> 16) & 0xff;
677 break;
678 case 0xdb: /* RDID2 */
679 s->p = 0;
680 s->resp[0] = (s->id >> 8) & 0xff;
681 break;
682 case 0xdc: /* RDID3 */
683 s->p = 0;
684 s->resp[0] = (s->id >> 0) & 0xff;
685 break;
686
687 default:
688 bad_cmd:
591f73f6
PM		 689 qemu_log_mask(LOG_GUEST_ERROR,
690 "%s: unknown command %02x\n", __func__, s->cmd);
7e7c5e4c
AZ		 691 break;
692 }
693
694 return ret;
695}
696
697static void *mipid_init(void)
698{
7267c094 699 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
7e7c5e4c
AZ		 700
701 s->id = 0x838f03;
702 mipid_reset(s);
703
704 return s;
705}
706
e927bb00 707static void n8x0_spi_setup(struct n800_s *s)
7e7c5e4c 708{
e927bb00 709 void *tsc = s->ts.opaque;
7e7c5e4c
AZ		 710 void *mipid = mipid_init();
711
518ec134
AF		 712 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
713 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
7e7c5e4c
AZ		 714}
715
716/* This task is normally performed by the bootloader. If we're loading
717 * a kernel directly, we need to enable the Blizzard ourselves. */
718static void n800_dss_init(struct rfbi_chip_s *chip)
719{
720 uint8_t *fb_blank;
721
722 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
723 chip->write(chip->opaque, 1, 0x64);
724 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
725 chip->write(chip->opaque, 1, 0x1e);
726 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
727 chip->write(chip->opaque, 1, 0xe0);
728 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
729 chip->write(chip->opaque, 1, 0x01);
730 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
731 chip->write(chip->opaque, 1, 0x06);
732 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
733 chip->write(chip->opaque, 1, 1); /* Enable bit */
734
735 chip->write(chip->opaque, 0, 0x6c);
736 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
737 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
738 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
739 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
740 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
741 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
742 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
743 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
744 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
745 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
746 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
747 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
748 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
749 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
750 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
751 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
752 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
753 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
754
7267c094 755 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
7e7c5e4c
AZ		 756 /* Display Memory Data Port */
757 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
7267c094 758 g_free(fb_blank);
7e7c5e4c
AZ		 759}
760
3023f332 761static void n8x0_dss_setup(struct n800_s *s)
7e7c5e4c 762{
b9d38e95 763 s->blizzard.opaque = s1d13745_init(NULL);
7e7c5e4c
AZ		 764 s->blizzard.block = s1d13745_write_block;
765 s->blizzard.write = s1d13745_write;
766 s->blizzard.read = s1d13745_read;
767
518ec134 768 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
7e7c5e4c
AZ		 769}
770
e927bb00 771static void n8x0_cbus_setup(struct n800_s *s)
7e7c5e4c 772{
518ec134
AF		 773 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
774 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
775 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
7e7c5e4c 776
bc24a225 777 CBus *cbus = cbus_init(dat_out);
7e7c5e4c 778
518ec134
AF		 779 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
780 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
781 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
7e7c5e4c
AZ		 782
783 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
784 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
785}
786
58a26b47
AZ		 787static void n8x0_uart_setup(struct n800_s *s)
788{
789 CharDriverState *radio = uart_hci_init(
518ec134 790 qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
58a26b47 791
518ec134 792 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
58a26b47 793 csrhci_pins_get(radio)[csrhci_pin_reset]);
518ec134 794 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
58a26b47
AZ		 795 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
796
518ec134 797 omap_uart_attach(s->mpu->uart[BT_UART], radio);
58a26b47
AZ		 798}
799
e927bb00 800static void n8x0_usb_setup(struct n800_s *s)
942ac052 801{
bdc76462
PM		 802 SysBusDevice *dev;
803 s->usb = qdev_create(NULL, "tusb6010");
1356b98d 804 dev = SYS_BUS_DEVICE(s->usb);
bdc76462
PM		 805 qdev_init_nofail(s->usb);
806 sysbus_connect_irq(dev, 0,
518ec134 807 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
942ac052 808 /* Using the NOR interface */
518ec134 809 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
bdc76462 810 sysbus_mmio_get_region(dev, 0));
518ec134 811 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
bdc76462 812 sysbus_mmio_get_region(dev, 1));
518ec134 813 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
bdc76462 814 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
942ac052
AZ		 815}
816
d238db7f
AZ		 817/* Setup done before the main bootloader starts by some early setup code
818 * - used when we want to run the main bootloader in emulation. This
819 * isn't documented. */
820static uint32_t n800_pinout[104] = {
821 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
822 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
823 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
824 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
825 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
826 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
827 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
828 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
829 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
830 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
831 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
832 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
833 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
834 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
835 0x00000000, 0x00000038, 0x00340000, 0x00000000,
836 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
837 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
838 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
839 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
840 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
841 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
842 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
843 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
844 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
845 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
846 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
847};
848
849static void n800_setup_nolo_tags(void *sram_base)
850{
851 int i;
852 uint32_t *p = sram_base + 0x8000;
853 uint32_t *v = sram_base + 0xa000;
854
855 memset(p, 0, 0x3000);
856
857 strcpy((void *) (p + 0), "QEMU N800");
858
859 strcpy((void *) (p + 8), "F5");
860
0983979b 861 stl_p(p + 10, 0x04f70000);
d238db7f
AZ		 862 strcpy((void *) (p + 9), "RX-34");
863
864 /* RAM size in MB? */
0983979b 865 stl_p(p + 12, 0x80);
d238db7f
AZ		 866
867 /* Pointer to the list of tags */
0983979b 868 stl_p(p + 13, OMAP2_SRAM_BASE + 0x9000);
d238db7f
AZ		 869
870 /* The NOLO tags start here */
871 p = sram_base + 0x9000;
872#define ADD_TAG(tag, len) \
0983979b
PB		 873 stw_p((uint16_t *) p + 0, tag); \
874 stw_p((uint16_t *) p + 1, len); p++; \
875 stl_p(p++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
d238db7f
AZ		 876
877 /* OMAP STI console? Pin out settings? */
878 ADD_TAG(0x6e01, 414);
fddbd80c 879 for (i = 0; i < ARRAY_SIZE(n800_pinout); i++) {
0983979b 880 stl_p(v++, n800_pinout[i]);
fddbd80c 881 }
d238db7f
AZ		 882
883 /* Kernel memsize? */
884 ADD_TAG(0x6e05, 1);
0983979b 885 stl_p(v++, 2);
d238db7f
AZ		 886
887 /* NOLO serial console */
888 ADD_TAG(0x6e02, 4);
0983979b 889 stl_p(v++, XLDR_LL_UART); /* UART number (1 - 3) */
d238db7f
AZ		 890
891#if 0
892 /* CBUS settings (Retu/AVilma) */
893 ADD_TAG(0x6e03, 6);
0983979b
PB		 894 stw_p((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
895 stw_p((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
896 stw_p((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
d238db7f
AZ		 897 v += 2;
898#endif
899
900 /* Nokia ASIC BB5 (Retu/Tahvo) */
901 ADD_TAG(0x6e0a, 4);
0983979b
PB		 902 stw_p((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
903 stw_p((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
fddbd80c 904 v++;
d238db7f
AZ		 905
906 /* LCD console? */
907 ADD_TAG(0x6e04, 4);
0983979b
PB		 908 stw_p((uint16_t *) v + 0, 30); /* ??? */
909 stw_p((uint16_t *) v + 1, 24); /* ??? */
fddbd80c 910 v++;
d238db7f
AZ		 911
912#if 0
913 /* LCD settings */
914 ADD_TAG(0x6e06, 2);
0983979b 915 stw_p((uint16_t *) (v++), 15); /* ??? */
d238db7f
AZ		 916#endif
917
918 /* I^2C (Menelaus) */
919 ADD_TAG(0x6e07, 4);
0983979b 920 stl_p(v++, 0x00720000); /* ??? */
d238db7f
AZ		 921
922 /* Unknown */
923 ADD_TAG(0x6e0b, 6);
0983979b
PB		 924 stw_p((uint16_t *) v + 0, 94); /* ??? */
925 stw_p((uint16_t *) v + 1, 23); /* ??? */
926 stw_p((uint16_t *) v + 2, 0); /* ??? */
d238db7f
AZ		 927 v += 2;
928
929 /* OMAP gpio switch info */
930 ADD_TAG(0x6e0c, 80);
931 strcpy((void *) v, "bat_cover"); v += 3;
0983979b
PB		 932 stw_p((uint16_t *) v + 0, 110); /* GPIO num ??? */
933 stw_p((uint16_t *) v + 1, 1); /* GPIO num ??? */
d238db7f
AZ		 934 v += 2;
935 strcpy((void *) v, "cam_act"); v += 3;
0983979b
PB		 936 stw_p((uint16_t *) v + 0, 95); /* GPIO num ??? */
937 stw_p((uint16_t *) v + 1, 32); /* GPIO num ??? */
d238db7f
AZ		 938 v += 2;
939 strcpy((void *) v, "cam_turn"); v += 3;
0983979b
PB		 940 stw_p((uint16_t *) v + 0, 12); /* GPIO num ??? */
941 stw_p((uint16_t *) v + 1, 33); /* GPIO num ??? */
d238db7f
AZ		 942 v += 2;
943 strcpy((void *) v, "headphone"); v += 3;
0983979b
PB		 944 stw_p((uint16_t *) v + 0, 107); /* GPIO num ??? */
945 stw_p((uint16_t *) v + 1, 17); /* GPIO num ??? */
d238db7f
AZ		 946 v += 2;
947
948 /* Bluetooth */
949 ADD_TAG(0x6e0e, 12);
0983979b
PB		 950 stl_p(v++, 0x5c623d01); /* ??? */
951 stl_p(v++, 0x00000201); /* ??? */
952 stl_p(v++, 0x00000000); /* ??? */
d238db7f
AZ		 953
954 /* CX3110x WLAN settings */
955 ADD_TAG(0x6e0f, 8);
0983979b
PB		 956 stl_p(v++, 0x00610025); /* ??? */
957 stl_p(v++, 0xffff0057); /* ??? */
d238db7f
AZ		 958
959 /* MMC host settings */
960 ADD_TAG(0x6e10, 12);
0983979b
PB		 961 stl_p(v++, 0xffff000f); /* ??? */
962 stl_p(v++, 0xffffffff); /* ??? */
963 stl_p(v++, 0x00000060); /* ??? */
d238db7f
AZ		 964
965 /* OneNAND chip select */
966 ADD_TAG(0x6e11, 10);
0983979b
PB		 967 stl_p(v++, 0x00000401); /* ??? */
968 stl_p(v++, 0x0002003a); /* ??? */
969 stl_p(v++, 0x00000002); /* ??? */
d238db7f
AZ		 970
971 /* TEA5761 sensor settings */
972 ADD_TAG(0x6e12, 2);
0983979b 973 stl_p(v++, 93); /* GPIO num ??? */
d238db7f
AZ		 974
975#if 0
976 /* Unknown tag */
977 ADD_TAG(6e09, 0);
978
979 /* Kernel UART / console */
980 ADD_TAG(6e12, 0);
981#endif
982
983 /* End of the list */
0983979b
PB		 984 stl_p(p++, 0x00000000);
985 stl_p(p++, 0x00000000);
d238db7f
AZ		 986}
987
7e7c5e4c
AZ		 988/* This task is normally performed by the bootloader. If we're loading
989 * a kernel directly, we need to set up GPMC mappings ourselves. */
990static void n800_gpmc_init(struct n800_s *s)
991{
992 uint32_t config7 =
993 (0xf << 8) | /* MASKADDRESS */
994 (1 << 6) | /* CSVALID */
995 (4 << 0); /* BASEADDRESS */
996
997 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
e1fe50dc 998 &config7, sizeof(config7));
7e7c5e4c
AZ		 999}
1000
1001/* Setup sequence done by the bootloader */
e927bb00 1002static void n8x0_boot_init(void *opaque)
7e7c5e4c
AZ		 1003{
1004 struct n800_s *s = (struct n800_s *) opaque;
1005 uint32_t buf;
1006
1007 /* PRCM setup */
1008#define omap_writel(addr, val) \
1009 buf = (val); \
e1fe50dc 1010 cpu_physical_memory_write(addr, &buf, sizeof(buf))
7e7c5e4c
AZ		 1011
1012 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
1013 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
1014 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
1015 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
1016 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
1017 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
1018 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1019 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1020 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1021 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1022 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1023 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1024 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1025 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1026 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1027 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1028 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1029 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1030 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1031 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1032 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1033 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1034 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1035 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1036 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1037 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1038 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1039 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1040 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1041 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1042 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1043 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1044 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1045 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1046 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1047 (0x78 << 12) | (6 << 8));
1048 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1049
1050 /* GPMC setup */
1051 n800_gpmc_init(s);
1052
1053 /* Video setup */
1054 n800_dss_init(&s->blizzard);
1055
1056 /* CPU setup */
518ec134 1057 s->mpu->cpu->env.GE = 0x5;
0941041e
AZ		 1058
1059 /* If the machine has a slided keyboard, open it */
fddbd80c 1060 if (s->kbd) {
518ec134 1061 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
fddbd80c 1062 }
7e7c5e4c
AZ		 1063}
1064
1065#define OMAP_TAG_NOKIA_BT 0x4e01
1066#define OMAP_TAG_WLAN_CX3110X 0x4e02
1067#define OMAP_TAG_CBUS 0x4e03
1068#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1069
e927bb00
AZ		 1070static struct omap_gpiosw_info_s {
1071 const char *name;
1072 int line;
1073 int type;
1074} n800_gpiosw_info[] = {
1075 {
1076 "bat_cover", N800_BAT_COVER_GPIO,
1077 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1078 }, {
1079 "cam_act", N800_CAM_ACT_GPIO,
1080 OMAP_GPIOSW_TYPE_ACTIVITY,
1081 }, {
1082 "cam_turn", N800_CAM_TURN_GPIO,
1083 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1084 }, {
1085 "headphone", N8X0_HEADPHONE_GPIO,
1086 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1087 },
b9d38e95 1088 { NULL }
e927bb00
AZ		 1089}, n810_gpiosw_info[] = {
1090 {
1091 "gps_reset", N810_GPS_RESET_GPIO,
1092 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1093 }, {
1094 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1095 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1096 }, {
1097 "headphone", N8X0_HEADPHONE_GPIO,
1098 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1099 }, {
1100 "kb_lock", N810_KB_LOCK_GPIO,
1101 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1102 }, {
1103 "sleepx_led", N810_SLEEPX_LED_GPIO,
1104 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1105 }, {
1106 "slide", N810_SLIDE_GPIO,
1107 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1108 },
b9d38e95 1109 { NULL }
e927bb00
AZ		 1110};
1111
1112static struct omap_partition_info_s {
1113 uint32_t offset;
1114 uint32_t size;
1115 int mask;
1116 const char *name;
1117} n800_part_info[] = {
1118 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1119 { 0x00020000, 0x00060000, 0x0, "config" },
1120 { 0x00080000, 0x00200000, 0x0, "kernel" },
1121 { 0x00280000, 0x00200000, 0x3, "initfs" },
1122 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1123
b9d38e95 1124 { 0, 0, 0, NULL }
e927bb00
AZ		 1125}, n810_part_info[] = {
1126 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1127 { 0x00020000, 0x00060000, 0x0, "config" },
1128 { 0x00080000, 0x00220000, 0x0, "kernel" },
1129 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1130 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1131
b9d38e95 1132 { 0, 0, 0, NULL }
e927bb00
AZ		 1133};
1134
c227f099 1135static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
c580d92b 1136
e927bb00 1137static int n8x0_atag_setup(void *p, int model)
7e7c5e4c
AZ		 1138{
1139 uint8_t *b;
1140 uint16_t *w;
1141 uint32_t *l;
e927bb00
AZ		 1142 struct omap_gpiosw_info_s *gpiosw;
1143 struct omap_partition_info_s *partition;
1144 const char *tag;
7e7c5e4c
AZ		 1145
1146 w = p;
1147
0983979b
PB		 1148 stw_p(w++, OMAP_TAG_UART); /* u16 tag */
1149 stw_p(w++, 4); /* u16 len */
1150 stw_p(w++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
fddbd80c 1151 w++;
7e7c5e4c 1152
e927bb00 1153#if 0
0983979b
PB		 1154 stw_p(w++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1155 stw_p(w++, 4); /* u16 len */
1156 stw_p(w++, XLDR_LL_UART + 1); /* u8 console_uart */
1157 stw_p(w++, 115200); /* u32 console_speed */
e927bb00
AZ		 1158#endif
1159
0983979b
PB		 1160 stw_p(w++, OMAP_TAG_LCD); /* u16 tag */
1161 stw_p(w++, 36); /* u16 len */
e927bb00
AZ		 1162 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1163 w += 8;
1164 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1165 w += 8;
0983979b
PB		 1166 stw_p(w++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1167 stw_p(w++, 24); /* u8 data_lines */
1168
1169 stw_p(w++, OMAP_TAG_CBUS); /* u16 tag */
1170 stw_p(w++, 8); /* u16 len */
1171 stw_p(w++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1172 stw_p(w++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1173 stw_p(w++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
fddbd80c 1174 w++;
7e7c5e4c 1175
0983979b
PB		 1176 stw_p(w++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1177 stw_p(w++, 4); /* u16 len */
1178 stw_p(w++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1179 stw_p(w++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
e927bb00
AZ		 1180
1181 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
fddbd80c 1182 for (; gpiosw->name; gpiosw++) {
0983979b
PB		 1183 stw_p(w++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1184 stw_p(w++, 20); /* u16 len */
e927bb00
AZ		 1185 strcpy((void *) w, gpiosw->name); /* char name[12] */
1186 w += 6;
0983979b
PB		 1187 stw_p(w++, gpiosw->line); /* u16 gpio */
1188 stw_p(w++, gpiosw->type);
1189 stw_p(w++, 0);
1190 stw_p(w++, 0);
e927bb00 1191 }
7e7c5e4c 1192
0983979b
PB		 1193 stw_p(w++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1194 stw_p(w++, 12); /* u16 len */
7e7c5e4c 1195 b = (void *) w;
0983979b
PB		 1196 stb_p(b++, 0x01); /* u8 chip_type (CSR) */
1197 stb_p(b++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1198 stb_p(b++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1199 stb_p(b++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1200 stb_p(b++, BT_UART + 1); /* u8 bt_uart */
c580d92b 1201 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
7e7c5e4c 1202 b += 6;
0983979b 1203 stb_p(b++, 0x02); /* u8 bt_sysclk (38.4) */
7e7c5e4c
AZ		 1204 w = (void *) b;
1205
0983979b
PB		 1206 stw_p(w++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1207 stw_p(w++, 8); /* u16 len */
1208 stw_p(w++, 0x25); /* u8 chip_type */
1209 stw_p(w++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1210 stw_p(w++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1211 stw_p(w++, -1); /* s16 spi_cs_gpio */
7e7c5e4c 1212
0983979b
PB		 1213 stw_p(w++, OMAP_TAG_MMC); /* u16 tag */
1214 stw_p(w++, 16); /* u16 len */
e927bb00 1215 if (model == 810) {
0983979b
PB		 1216 stw_p(w++, 0x23f); /* unsigned flags */
1217 stw_p(w++, -1); /* s16 power_pin */
1218 stw_p(w++, -1); /* s16 switch_pin */
1219 stw_p(w++, -1); /* s16 wp_pin */
1220 stw_p(w++, 0x240); /* unsigned flags */
1221 stw_p(w++, 0xc000); /* s16 power_pin */
1222 stw_p(w++, 0x0248); /* s16 switch_pin */
1223 stw_p(w++, 0xc000); /* s16 wp_pin */
e927bb00 1224 } else {
0983979b
PB		 1225 stw_p(w++, 0xf); /* unsigned flags */
1226 stw_p(w++, -1); /* s16 power_pin */
1227 stw_p(w++, -1); /* s16 switch_pin */
1228 stw_p(w++, -1); /* s16 wp_pin */
1229 stw_p(w++, 0); /* unsigned flags */
1230 stw_p(w++, 0); /* s16 power_pin */
1231 stw_p(w++, 0); /* s16 switch_pin */
1232 stw_p(w++, 0); /* s16 wp_pin */
e927bb00 1233 }
7e7c5e4c 1234
0983979b
PB		 1235 stw_p(w++, OMAP_TAG_TEA5761); /* u16 tag */
1236 stw_p(w++, 4); /* u16 len */
1237 stw_p(w++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
fddbd80c 1238 w++;
7e7c5e4c 1239
e927bb00 1240 partition = (model == 810) ? n810_part_info : n800_part_info;
fddbd80c 1241 for (; partition->name; partition++) {
0983979b
PB		 1242 stw_p(w++, OMAP_TAG_PARTITION); /* u16 tag */
1243 stw_p(w++, 28); /* u16 len */
e927bb00
AZ		 1244 strcpy((void *) w, partition->name); /* char name[16] */
1245 l = (void *) (w + 8);
0983979b
PB		 1246 stl_p(l++, partition->size); /* unsigned int size */
1247 stl_p(l++, partition->offset); /* unsigned int offset */
1248 stl_p(l++, partition->mask); /* unsigned int mask_flags */
e927bb00
AZ		 1249 w = (void *) l;
1250 }
7e7c5e4c 1251
0983979b
PB		 1252 stw_p(w++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1253 stw_p(w++, 12); /* u16 len */
7e7c5e4c
AZ		 1254#if 0
1255 strcpy((void *) w, "por"); /* char reason_str[12] */
1256 strcpy((void *) w, "charger"); /* char reason_str[12] */
1257 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1258 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1259 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1260 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1261 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1262 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1263 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1264 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1265#else
1266 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1267#endif
1268 w += 6;
1269
e927bb00 1270 tag = (model == 810) ? "RX-44" : "RX-34";
0983979b
PB		 1271 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1272 stw_p(w++, 24); /* u16 len */
7e7c5e4c
AZ		 1273 strcpy((void *) w, "product"); /* char component[12] */
1274 w += 6;
e927bb00 1275 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c
AZ		 1276 w += 6;
1277
0983979b
PB		 1278 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1279 stw_p(w++, 24); /* u16 len */
7e7c5e4c
AZ		 1280 strcpy((void *) w, "hw-build"); /* char component[12] */
1281 w += 6;
93bfef4c 1282 strcpy((void *) w, "QEMU ");
35c2c8dc 1283 pstrcat((void *) w, 12, qemu_hw_version()); /* char version[12] */
7e7c5e4c
AZ		 1284 w += 6;
1285
e927bb00 1286 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
0983979b
PB		 1287 stw_p(w++, OMAP_TAG_VERSION_STR); /* u16 tag */
1288 stw_p(w++, 24); /* u16 len */
7e7c5e4c
AZ		 1289 strcpy((void *) w, "nolo"); /* char component[12] */
1290 w += 6;
e927bb00 1291 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c 1292 w += 6;
7e7c5e4c
AZ		 1293
1294 return (void *) w - p;
1295}
1296
462a8bc6 1297static int n800_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1298{
1299 return n8x0_atag_setup(p, 800);
1300}
7e7c5e4c 1301
462a8bc6 1302static int n810_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1303{
1304 return n8x0_atag_setup(p, 810);
1305}
1306
3ef96221 1307static void n8x0_init(MachineState *machine,
462b69bb 1308 struct arm_boot_info *binfo, int model)
7e7c5e4c 1309{
aee39503 1310 MemoryRegion *sysmem = get_system_memory();
7267c094 1311 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
e927bb00 1312 int sdram_size = binfo->ram_size;
7e7c5e4c 1313
3ef96221 1314 s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);
7e7c5e4c 1315
0941041e
AZ		 1316 /* Setup peripherals
1317 *
1318 * Believed external peripherals layout in the N810:
1319 * (spi bus 1)
1320 * tsc2005
1321 * lcd_mipid
1322 * (spi bus 2)
1323 * Conexant cx3110x (WLAN)
1324 * optional: pc2400m (WiMAX)
1325 * (i2c bus 0)
1326 * TLV320AIC33 (audio codec)
1327 * TCM825x (camera by Toshiba)
1328 * lp5521 (clever LEDs)
1329 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1330 * lm8323 (keypad, manf 00, rev 04)
1331 * (i2c bus 1)
1332 * tmp105 (temperature sensor, hwmon)
1333 * menelaus (pm)
d238db7f
AZ		 1334 * (somewhere on i2c - maybe N800-only)
1335 * tea5761 (FM tuner)
1336 * (serial 0)
1337 * GPS
1338 * (some serial port)
1339 * csr41814 (Bluetooth)
0941041e 1340 */
e927bb00 1341 n8x0_gpio_setup(s);
7e7c5e4c 1342 n8x0_nand_setup(s);
e927bb00 1343 n8x0_i2c_setup(s);
fddbd80c 1344 if (model == 800) {
e927bb00 1345 n800_tsc_kbd_setup(s);
fddbd80c 1346 } else if (model == 810) {
e927bb00 1347 n810_tsc_setup(s);
1d4e547b
AZ		 1348 n810_kbd_setup(s);
1349 }
e927bb00 1350 n8x0_spi_setup(s);
3023f332 1351 n8x0_dss_setup(s);
e927bb00 1352 n8x0_cbus_setup(s);
58a26b47 1353 n8x0_uart_setup(s);
4bcbe0b6 1354 if (machine_usb(machine)) {
e927bb00 1355 n8x0_usb_setup(s);
094b287f 1356 }
7e7c5e4c 1357
3ef96221 1358 if (machine->kernel_filename) {
7e7c5e4c 1359 /* Or at the linux loader. */
3ef96221
MA		 1360 binfo->kernel_filename = machine->kernel_filename;
1361 binfo->kernel_cmdline = machine->kernel_cmdline;
1362 binfo->initrd_filename = machine->initrd_filename;
3aaa8dfa 1363 arm_load_kernel(s->mpu->cpu, binfo);
7e7c5e4c 1364
a08d4367 1365 qemu_register_reset(n8x0_boot_init, s);
7e7c5e4c
AZ		 1366 }
1367
462b69bb 1368 if (option_rom[0].name &&
3ef96221 1369 (machine->boot_order[0] == 'n' || !machine->kernel_filename)) {
0b062eb0 1370 uint8_t *nolo_tags = g_new(uint8_t, 0x10000);
d238db7f 1371 /* No, wait, better start at the ROM. */
518ec134 1372 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
d238db7f
AZ		 1373
1374 /* This is intended for loading the `secondary.bin' program from
1375 * Nokia images (the NOLO bootloader). The entry point seems
1376 * to be at OMAP2_Q2_BASE + 0x400000.
1377 *
1378 * The `2nd.bin' files contain some kind of earlier boot code and
1379 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1380 *
1381 * The code above is for loading the `zImage' file from Nokia
1382 * images. */
591f73f6
PM		 1383 load_image_targphys(option_rom[0].name,
1384 OMAP2_Q2_BASE + 0x400000,
1385 sdram_size - 0x400000);
d238db7f 1386
5c130f65
PB		 1387 n800_setup_nolo_tags(nolo_tags);
1388 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
0b062eb0 1389 g_free(nolo_tags);
d238db7f 1390 }
7e7c5e4c
AZ		 1391}
1392
e927bb00
AZ		 1393static struct arm_boot_info n800_binfo = {
1394 .loader_start = OMAP2_Q2_BASE,
1395 /* Actually two chips of 0x4000000 bytes each */
1396 .ram_size = 0x08000000,
1397 .board_id = 0x4f7,
1398 .atag_board = n800_atag_setup,
1399};
1400
1401static struct arm_boot_info n810_binfo = {
1402 .loader_start = OMAP2_Q2_BASE,
1403 /* Actually two chips of 0x4000000 bytes each */
1404 .ram_size = 0x08000000,
1405 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1406 * used by some older versions of the bootloader and 5555 is used
1407 * instead (including versions that shipped with many devices). */
1408 .board_id = 0x60c,
1409 .atag_board = n810_atag_setup,
1410};
1411
3ef96221 1412static void n800_init(MachineState *machine)
e927bb00 1413{
30d76f13 1414 n8x0_init(machine, &n800_binfo, 800);
e927bb00
AZ		 1415}
1416
3ef96221 1417static void n810_init(MachineState *machine)
e927bb00 1418{
30d76f13 1419 n8x0_init(machine, &n810_binfo, 810);
e927bb00
AZ		 1420}
1421
8a661aea 1422static void n800_class_init(ObjectClass *oc, void *data)
e264d29d 1423{
8a661aea
AF		 1424 MachineClass *mc = MACHINE_CLASS(oc);
1425
e264d29d
EH		 1426 mc->desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)";
1427 mc->init = n800_init;
1428 mc->default_boot_order = "";
1429}
e927bb00 1430
8a661aea
AF		 1431static const TypeInfo n800_type = {
1432 .name = MACHINE_TYPE_NAME("n800"),
1433 .parent = TYPE_MACHINE,
1434 .class_init = n800_class_init,
1435};
f80f9ec9 1436
8a661aea 1437static void n810_class_init(ObjectClass *oc, void *data)
f80f9ec9 1438{
8a661aea
AF		 1439 MachineClass *mc = MACHINE_CLASS(oc);
1440
e264d29d
EH		 1441 mc->desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)";
1442 mc->init = n810_init;
1443 mc->default_boot_order = "";
f80f9ec9
AL		 1444}
1445
8a661aea
AF		 1446static const TypeInfo n810_type = {
1447 .name = MACHINE_TYPE_NAME("n810"),
1448 .parent = TYPE_MACHINE,
1449 .class_init = n810_class_init,
1450};
1451
1452static void nseries_machine_init(void)
1453{
1454 type_register_static(&n800_type);
1455 type_register_static(&n810_type);
1456}
1457
0e6aac87 1458type_init(nseries_machine_init)
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