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Commit | Line | Data |
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c3d2689d AZ |
1 | /* |
2 | * TI OMAP processors emulation. | |
3 | * | |
b4e3104b | 4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
c3d2689d AZ |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
827df9f3 AZ |
8 | * published by the Free Software Foundation; either version 2 or |
9 | * (at your option) version 3 of the License. | |
c3d2689d AZ |
10 | * |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
fad6cb1a | 16 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
c3d2689d | 18 | */ |
c8623c02 | 19 | |
12b16722 | 20 | #include "qemu/osdep.h" |
da34e65c | 21 | #include "qapi/error.h" |
4771d756 PB |
22 | #include "qemu-common.h" |
23 | #include "cpu.h" | |
c8623c02 | 24 | #include "hw/boards.h" |
83c9f4ca | 25 | #include "hw/hw.h" |
bd2be150 | 26 | #include "hw/arm/arm.h" |
0d09e41a | 27 | #include "hw/arm/omap.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
0d09e41a | 29 | #include "hw/arm/soc_dma.h" |
fa1d36df | 30 | #include "sysemu/block-backend.h" |
9c17d615 | 31 | #include "sysemu/blockdev.h" |
1de7afc9 | 32 | #include "qemu/range.h" |
83c9f4ca | 33 | #include "hw/sysbus.h" |
c3d2689d | 34 | |
827df9f3 | 35 | /* Should signal the TCMI/GPMC */ |
a8170e5e | 36 | uint32_t omap_badwidth_read8(void *opaque, hwaddr addr) |
66450b15 | 37 | { |
02645926 AZ |
38 | uint8_t ret; |
39 | ||
66450b15 | 40 | OMAP_8B_REG(addr); |
e1fe50dc | 41 | cpu_physical_memory_read(addr, &ret, 1); |
02645926 | 42 | return ret; |
66450b15 AZ |
43 | } |
44 | ||
a8170e5e | 45 | void omap_badwidth_write8(void *opaque, hwaddr addr, |
66450b15 AZ |
46 | uint32_t value) |
47 | { | |
b854bc19 AZ |
48 | uint8_t val8 = value; |
49 | ||
66450b15 | 50 | OMAP_8B_REG(addr); |
e1fe50dc | 51 | cpu_physical_memory_write(addr, &val8, 1); |
66450b15 AZ |
52 | } |
53 | ||
a8170e5e | 54 | uint32_t omap_badwidth_read16(void *opaque, hwaddr addr) |
c3d2689d | 55 | { |
b854bc19 AZ |
56 | uint16_t ret; |
57 | ||
c3d2689d | 58 | OMAP_16B_REG(addr); |
e1fe50dc | 59 | cpu_physical_memory_read(addr, &ret, 2); |
b854bc19 | 60 | return ret; |
c3d2689d AZ |
61 | } |
62 | ||
a8170e5e | 63 | void omap_badwidth_write16(void *opaque, hwaddr addr, |
c3d2689d AZ |
64 | uint32_t value) |
65 | { | |
b854bc19 AZ |
66 | uint16_t val16 = value; |
67 | ||
c3d2689d | 68 | OMAP_16B_REG(addr); |
e1fe50dc | 69 | cpu_physical_memory_write(addr, &val16, 2); |
c3d2689d AZ |
70 | } |
71 | ||
a8170e5e | 72 | uint32_t omap_badwidth_read32(void *opaque, hwaddr addr) |
c3d2689d | 73 | { |
b854bc19 AZ |
74 | uint32_t ret; |
75 | ||
c3d2689d | 76 | OMAP_32B_REG(addr); |
e1fe50dc | 77 | cpu_physical_memory_read(addr, &ret, 4); |
b854bc19 | 78 | return ret; |
c3d2689d AZ |
79 | } |
80 | ||
a8170e5e | 81 | void omap_badwidth_write32(void *opaque, hwaddr addr, |
c3d2689d AZ |
82 | uint32_t value) |
83 | { | |
84 | OMAP_32B_REG(addr); | |
e1fe50dc | 85 | cpu_physical_memory_write(addr, &value, 4); |
c3d2689d AZ |
86 | } |
87 | ||
c3d2689d AZ |
88 | /* MPU OS timers */ |
89 | struct omap_mpu_timer_s { | |
4b3fedf3 | 90 | MemoryRegion iomem; |
c3d2689d AZ |
91 | qemu_irq irq; |
92 | omap_clk clk; | |
c3d2689d AZ |
93 | uint32_t val; |
94 | int64_t time; | |
95 | QEMUTimer *timer; | |
e856f2ad | 96 | QEMUBH *tick; |
c3d2689d AZ |
97 | int64_t rate; |
98 | int it_ena; | |
99 | ||
100 | int enable; | |
101 | int ptv; | |
102 | int ar; | |
103 | int st; | |
104 | uint32_t reset_val; | |
105 | }; | |
106 | ||
107 | static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) | |
108 | { | |
bc72ad67 | 109 | uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; |
c3d2689d AZ |
110 | |
111 | if (timer->st && timer->enable && timer->rate) | |
112 | return timer->val - muldiv64(distance >> (timer->ptv + 1), | |
6ee093c9 | 113 | timer->rate, get_ticks_per_sec()); |
c3d2689d AZ |
114 | else |
115 | return timer->val; | |
116 | } | |
117 | ||
118 | static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) | |
119 | { | |
120 | timer->val = omap_timer_read(timer); | |
bc72ad67 | 121 | timer->time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
c3d2689d AZ |
122 | } |
123 | ||
124 | static inline void omap_timer_update(struct omap_mpu_timer_s *timer) | |
125 | { | |
126 | int64_t expires; | |
127 | ||
128 | if (timer->enable && timer->st && timer->rate) { | |
129 | timer->val = timer->reset_val; /* Should skip this on clk enable */ | |
b8b137d6 | 130 | expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), |
6ee093c9 | 131 | get_ticks_per_sec(), timer->rate); |
b854bc19 AZ |
132 | |
133 | /* If timer expiry would be sooner than in about 1 ms and | |
134 | * auto-reload isn't set, then fire immediately. This is a hack | |
135 | * to make systems like PalmOS run in acceptable time. PalmOS | |
136 | * sets the interval to a very low value and polls the status bit | |
137 | * in a busy loop when it wants to sleep just a couple of CPU | |
138 | * ticks. */ | |
6ee093c9 | 139 | if (expires > (get_ticks_per_sec() >> 10) || timer->ar) |
bc72ad67 | 140 | timer_mod(timer->timer, timer->time + expires); |
e856f2ad AZ |
141 | else |
142 | qemu_bh_schedule(timer->tick); | |
c3d2689d | 143 | } else |
bc72ad67 | 144 | timer_del(timer->timer); |
c3d2689d AZ |
145 | } |
146 | ||
e856f2ad | 147 | static void omap_timer_fire(void *opaque) |
c3d2689d | 148 | { |
e856f2ad | 149 | struct omap_mpu_timer_s *timer = opaque; |
c3d2689d AZ |
150 | |
151 | if (!timer->ar) { | |
152 | timer->val = 0; | |
153 | timer->st = 0; | |
154 | } | |
155 | ||
156 | if (timer->it_ena) | |
106627d0 AZ |
157 | /* Edge-triggered irq */ |
158 | qemu_irq_pulse(timer->irq); | |
e856f2ad AZ |
159 | } |
160 | ||
161 | static void omap_timer_tick(void *opaque) | |
162 | { | |
163 | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | |
164 | ||
165 | omap_timer_sync(timer); | |
166 | omap_timer_fire(timer); | |
c3d2689d AZ |
167 | omap_timer_update(timer); |
168 | } | |
169 | ||
170 | static void omap_timer_clk_update(void *opaque, int line, int on) | |
171 | { | |
172 | struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | |
173 | ||
174 | omap_timer_sync(timer); | |
175 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; | |
176 | omap_timer_update(timer); | |
177 | } | |
178 | ||
179 | static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) | |
180 | { | |
181 | omap_clk_adduser(timer->clk, | |
f3c7d038 | 182 | qemu_allocate_irq(omap_timer_clk_update, timer, 0)); |
c3d2689d AZ |
183 | timer->rate = omap_clk_getrate(timer->clk); |
184 | } | |
185 | ||
a8170e5e | 186 | static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 187 | unsigned size) |
c3d2689d AZ |
188 | { |
189 | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | |
c3d2689d | 190 | |
4b3fedf3 AK |
191 | if (size != 4) { |
192 | return omap_badwidth_read32(opaque, addr); | |
193 | } | |
194 | ||
8da3ff18 | 195 | switch (addr) { |
c3d2689d AZ |
196 | case 0x00: /* CNTL_TIMER */ |
197 | return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; | |
198 | ||
199 | case 0x04: /* LOAD_TIM */ | |
200 | break; | |
201 | ||
202 | case 0x08: /* READ_TIM */ | |
203 | return omap_timer_read(s); | |
204 | } | |
205 | ||
206 | OMAP_BAD_REG(addr); | |
207 | return 0; | |
208 | } | |
209 | ||
a8170e5e | 210 | static void omap_mpu_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 211 | uint64_t value, unsigned size) |
c3d2689d AZ |
212 | { |
213 | struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | |
c3d2689d | 214 | |
4b3fedf3 | 215 | if (size != 4) { |
77a8257e SW |
216 | omap_badwidth_write32(opaque, addr, value); |
217 | return; | |
4b3fedf3 AK |
218 | } |
219 | ||
8da3ff18 | 220 | switch (addr) { |
c3d2689d AZ |
221 | case 0x00: /* CNTL_TIMER */ |
222 | omap_timer_sync(s); | |
223 | s->enable = (value >> 5) & 1; | |
224 | s->ptv = (value >> 2) & 7; | |
225 | s->ar = (value >> 1) & 1; | |
226 | s->st = value & 1; | |
227 | omap_timer_update(s); | |
228 | return; | |
229 | ||
230 | case 0x04: /* LOAD_TIM */ | |
231 | s->reset_val = value; | |
232 | return; | |
233 | ||
234 | case 0x08: /* READ_TIM */ | |
235 | OMAP_RO_REG(addr); | |
236 | break; | |
237 | ||
238 | default: | |
239 | OMAP_BAD_REG(addr); | |
240 | } | |
241 | } | |
242 | ||
4b3fedf3 AK |
243 | static const MemoryRegionOps omap_mpu_timer_ops = { |
244 | .read = omap_mpu_timer_read, | |
245 | .write = omap_mpu_timer_write, | |
246 | .endianness = DEVICE_LITTLE_ENDIAN, | |
c3d2689d AZ |
247 | }; |
248 | ||
249 | static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) | |
250 | { | |
bc72ad67 | 251 | timer_del(s->timer); |
c3d2689d AZ |
252 | s->enable = 0; |
253 | s->reset_val = 31337; | |
254 | s->val = 0; | |
255 | s->ptv = 0; | |
256 | s->ar = 0; | |
257 | s->st = 0; | |
258 | s->it_ena = 1; | |
259 | } | |
260 | ||
4b3fedf3 | 261 | static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory, |
a8170e5e | 262 | hwaddr base, |
c3d2689d AZ |
263 | qemu_irq irq, omap_clk clk) |
264 | { | |
b45c03f5 | 265 | struct omap_mpu_timer_s *s = g_new0(struct omap_mpu_timer_s, 1); |
c3d2689d AZ |
266 | |
267 | s->irq = irq; | |
268 | s->clk = clk; | |
bc72ad67 | 269 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, s); |
e856f2ad | 270 | s->tick = qemu_bh_new(omap_timer_fire, s); |
c3d2689d AZ |
271 | omap_mpu_timer_reset(s); |
272 | omap_timer_clk_setup(s); | |
273 | ||
2c9b15ca | 274 | memory_region_init_io(&s->iomem, NULL, &omap_mpu_timer_ops, s, |
4b3fedf3 AK |
275 | "omap-mpu-timer", 0x100); |
276 | ||
277 | memory_region_add_subregion(system_memory, base, &s->iomem); | |
c3d2689d AZ |
278 | |
279 | return s; | |
280 | } | |
281 | ||
282 | /* Watchdog timer */ | |
283 | struct omap_watchdog_timer_s { | |
284 | struct omap_mpu_timer_s timer; | |
4b3fedf3 | 285 | MemoryRegion iomem; |
c3d2689d AZ |
286 | uint8_t last_wr; |
287 | int mode; | |
288 | int free; | |
289 | int reset; | |
290 | }; | |
291 | ||
a8170e5e | 292 | static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 293 | unsigned size) |
c3d2689d AZ |
294 | { |
295 | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | |
c3d2689d | 296 | |
4b3fedf3 AK |
297 | if (size != 2) { |
298 | return omap_badwidth_read16(opaque, addr); | |
299 | } | |
300 | ||
8da3ff18 | 301 | switch (addr) { |
c3d2689d AZ |
302 | case 0x00: /* CNTL_TIMER */ |
303 | return (s->timer.ptv << 9) | (s->timer.ar << 8) | | |
304 | (s->timer.st << 7) | (s->free << 1); | |
305 | ||
306 | case 0x04: /* READ_TIMER */ | |
307 | return omap_timer_read(&s->timer); | |
308 | ||
309 | case 0x08: /* TIMER_MODE */ | |
310 | return s->mode << 15; | |
311 | } | |
312 | ||
313 | OMAP_BAD_REG(addr); | |
314 | return 0; | |
315 | } | |
316 | ||
a8170e5e | 317 | static void omap_wd_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 318 | uint64_t value, unsigned size) |
c3d2689d AZ |
319 | { |
320 | struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | |
c3d2689d | 321 | |
4b3fedf3 | 322 | if (size != 2) { |
77a8257e SW |
323 | omap_badwidth_write16(opaque, addr, value); |
324 | return; | |
4b3fedf3 AK |
325 | } |
326 | ||
8da3ff18 | 327 | switch (addr) { |
c3d2689d AZ |
328 | case 0x00: /* CNTL_TIMER */ |
329 | omap_timer_sync(&s->timer); | |
330 | s->timer.ptv = (value >> 9) & 7; | |
331 | s->timer.ar = (value >> 8) & 1; | |
332 | s->timer.st = (value >> 7) & 1; | |
333 | s->free = (value >> 1) & 1; | |
334 | omap_timer_update(&s->timer); | |
335 | break; | |
336 | ||
337 | case 0x04: /* LOAD_TIMER */ | |
338 | s->timer.reset_val = value & 0xffff; | |
339 | break; | |
340 | ||
341 | case 0x08: /* TIMER_MODE */ | |
342 | if (!s->mode && ((value >> 15) & 1)) | |
343 | omap_clk_get(s->timer.clk); | |
344 | s->mode |= (value >> 15) & 1; | |
345 | if (s->last_wr == 0xf5) { | |
346 | if ((value & 0xff) == 0xa0) { | |
d8f699cb AZ |
347 | if (s->mode) { |
348 | s->mode = 0; | |
349 | omap_clk_put(s->timer.clk); | |
350 | } | |
c3d2689d AZ |
351 | } else { |
352 | /* XXX: on T|E hardware somehow this has no effect, | |
353 | * on Zire 71 it works as specified. */ | |
354 | s->reset = 1; | |
355 | qemu_system_reset_request(); | |
356 | } | |
357 | } | |
358 | s->last_wr = value & 0xff; | |
359 | break; | |
360 | ||
361 | default: | |
362 | OMAP_BAD_REG(addr); | |
363 | } | |
364 | } | |
365 | ||
4b3fedf3 AK |
366 | static const MemoryRegionOps omap_wd_timer_ops = { |
367 | .read = omap_wd_timer_read, | |
368 | .write = omap_wd_timer_write, | |
369 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
370 | }; |
371 | ||
372 | static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) | |
373 | { | |
bc72ad67 | 374 | timer_del(s->timer.timer); |
c3d2689d AZ |
375 | if (!s->mode) |
376 | omap_clk_get(s->timer.clk); | |
377 | s->mode = 1; | |
378 | s->free = 1; | |
379 | s->reset = 0; | |
380 | s->timer.enable = 1; | |
381 | s->timer.it_ena = 1; | |
382 | s->timer.reset_val = 0xffff; | |
383 | s->timer.val = 0; | |
384 | s->timer.st = 0; | |
385 | s->timer.ptv = 0; | |
386 | s->timer.ar = 0; | |
387 | omap_timer_update(&s->timer); | |
388 | } | |
389 | ||
4b3fedf3 | 390 | static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory, |
a8170e5e | 391 | hwaddr base, |
c3d2689d AZ |
392 | qemu_irq irq, omap_clk clk) |
393 | { | |
b45c03f5 | 394 | struct omap_watchdog_timer_s *s = g_new0(struct omap_watchdog_timer_s, 1); |
c3d2689d AZ |
395 | |
396 | s->timer.irq = irq; | |
397 | s->timer.clk = clk; | |
bc72ad67 | 398 | s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); |
c3d2689d AZ |
399 | omap_wd_timer_reset(s); |
400 | omap_timer_clk_setup(&s->timer); | |
401 | ||
2c9b15ca | 402 | memory_region_init_io(&s->iomem, NULL, &omap_wd_timer_ops, s, |
4b3fedf3 AK |
403 | "omap-wd-timer", 0x100); |
404 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
405 | |
406 | return s; | |
407 | } | |
408 | ||
409 | /* 32-kHz timer */ | |
410 | struct omap_32khz_timer_s { | |
411 | struct omap_mpu_timer_s timer; | |
4b3fedf3 | 412 | MemoryRegion iomem; |
c3d2689d AZ |
413 | }; |
414 | ||
a8170e5e | 415 | static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, |
4b3fedf3 | 416 | unsigned size) |
c3d2689d AZ |
417 | { |
418 | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | |
cf965d24 | 419 | int offset = addr & OMAP_MPUI_REG_MASK; |
c3d2689d | 420 | |
4b3fedf3 AK |
421 | if (size != 4) { |
422 | return omap_badwidth_read32(opaque, addr); | |
423 | } | |
424 | ||
c3d2689d AZ |
425 | switch (offset) { |
426 | case 0x00: /* TVR */ | |
427 | return s->timer.reset_val; | |
428 | ||
429 | case 0x04: /* TCR */ | |
430 | return omap_timer_read(&s->timer); | |
431 | ||
432 | case 0x08: /* CR */ | |
433 | return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; | |
434 | ||
435 | default: | |
436 | break; | |
437 | } | |
438 | OMAP_BAD_REG(addr); | |
439 | return 0; | |
440 | } | |
441 | ||
a8170e5e | 442 | static void omap_os_timer_write(void *opaque, hwaddr addr, |
4b3fedf3 | 443 | uint64_t value, unsigned size) |
c3d2689d AZ |
444 | { |
445 | struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | |
cf965d24 | 446 | int offset = addr & OMAP_MPUI_REG_MASK; |
c3d2689d | 447 | |
4b3fedf3 | 448 | if (size != 4) { |
77a8257e SW |
449 | omap_badwidth_write32(opaque, addr, value); |
450 | return; | |
4b3fedf3 AK |
451 | } |
452 | ||
c3d2689d AZ |
453 | switch (offset) { |
454 | case 0x00: /* TVR */ | |
455 | s->timer.reset_val = value & 0x00ffffff; | |
456 | break; | |
457 | ||
458 | case 0x04: /* TCR */ | |
459 | OMAP_RO_REG(addr); | |
460 | break; | |
461 | ||
462 | case 0x08: /* CR */ | |
463 | s->timer.ar = (value >> 3) & 1; | |
464 | s->timer.it_ena = (value >> 2) & 1; | |
465 | if (s->timer.st != (value & 1) || (value & 2)) { | |
466 | omap_timer_sync(&s->timer); | |
467 | s->timer.enable = value & 1; | |
468 | s->timer.st = value & 1; | |
469 | omap_timer_update(&s->timer); | |
470 | } | |
471 | break; | |
472 | ||
473 | default: | |
474 | OMAP_BAD_REG(addr); | |
475 | } | |
476 | } | |
477 | ||
4b3fedf3 AK |
478 | static const MemoryRegionOps omap_os_timer_ops = { |
479 | .read = omap_os_timer_read, | |
480 | .write = omap_os_timer_write, | |
481 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
482 | }; |
483 | ||
484 | static void omap_os_timer_reset(struct omap_32khz_timer_s *s) | |
485 | { | |
bc72ad67 | 486 | timer_del(s->timer.timer); |
c3d2689d AZ |
487 | s->timer.enable = 0; |
488 | s->timer.it_ena = 0; | |
489 | s->timer.reset_val = 0x00ffffff; | |
490 | s->timer.val = 0; | |
491 | s->timer.st = 0; | |
492 | s->timer.ptv = 0; | |
493 | s->timer.ar = 1; | |
494 | } | |
495 | ||
4b3fedf3 | 496 | static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, |
a8170e5e | 497 | hwaddr base, |
c3d2689d AZ |
498 | qemu_irq irq, omap_clk clk) |
499 | { | |
b45c03f5 | 500 | struct omap_32khz_timer_s *s = g_new0(struct omap_32khz_timer_s, 1); |
c3d2689d AZ |
501 | |
502 | s->timer.irq = irq; | |
503 | s->timer.clk = clk; | |
bc72ad67 | 504 | s->timer.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_timer_tick, &s->timer); |
c3d2689d AZ |
505 | omap_os_timer_reset(s); |
506 | omap_timer_clk_setup(&s->timer); | |
507 | ||
2c9b15ca | 508 | memory_region_init_io(&s->iomem, NULL, &omap_os_timer_ops, s, |
4b3fedf3 AK |
509 | "omap-os-timer", 0x800); |
510 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
511 | |
512 | return s; | |
513 | } | |
514 | ||
515 | /* Ultra Low-Power Device Module */ | |
a8170e5e | 516 | static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, |
4b3fedf3 | 517 | unsigned size) |
c3d2689d AZ |
518 | { |
519 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
520 | uint16_t ret; |
521 | ||
4b3fedf3 AK |
522 | if (size != 2) { |
523 | return omap_badwidth_read16(opaque, addr); | |
524 | } | |
525 | ||
8da3ff18 | 526 | switch (addr) { |
c3d2689d | 527 | case 0x14: /* IT_STATUS */ |
8da3ff18 PB |
528 | ret = s->ulpd_pm_regs[addr >> 2]; |
529 | s->ulpd_pm_regs[addr >> 2] = 0; | |
0919ac78 | 530 | qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); |
c3d2689d AZ |
531 | return ret; |
532 | ||
533 | case 0x18: /* Reserved */ | |
534 | case 0x1c: /* Reserved */ | |
535 | case 0x20: /* Reserved */ | |
536 | case 0x28: /* Reserved */ | |
537 | case 0x2c: /* Reserved */ | |
538 | OMAP_BAD_REG(addr); | |
139bd956 | 539 | /* fall through */ |
c3d2689d AZ |
540 | case 0x00: /* COUNTER_32_LSB */ |
541 | case 0x04: /* COUNTER_32_MSB */ | |
542 | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ | |
543 | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ | |
544 | case 0x10: /* GAUGING_CTRL */ | |
545 | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ | |
546 | case 0x30: /* CLOCK_CTRL */ | |
547 | case 0x34: /* SOFT_REQ */ | |
548 | case 0x38: /* COUNTER_32_FIQ */ | |
549 | case 0x3c: /* DPLL_CTRL */ | |
550 | case 0x40: /* STATUS_REQ */ | |
551 | /* XXX: check clk::usecount state for every clock */ | |
552 | case 0x48: /* LOCL_TIME */ | |
553 | case 0x4c: /* APLL_CTRL */ | |
554 | case 0x50: /* POWER_CTRL */ | |
8da3ff18 | 555 | return s->ulpd_pm_regs[addr >> 2]; |
c3d2689d AZ |
556 | } |
557 | ||
558 | OMAP_BAD_REG(addr); | |
559 | return 0; | |
560 | } | |
561 | ||
562 | static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, | |
563 | uint16_t diff, uint16_t value) | |
564 | { | |
565 | if (diff & (1 << 4)) /* USB_MCLK_EN */ | |
566 | omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); | |
567 | if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ | |
568 | omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); | |
569 | } | |
570 | ||
571 | static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, | |
572 | uint16_t diff, uint16_t value) | |
573 | { | |
574 | if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ | |
575 | omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); | |
576 | if (diff & (1 << 1)) /* SOFT_COM_REQ */ | |
577 | omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); | |
578 | if (diff & (1 << 2)) /* SOFT_SDW_REQ */ | |
579 | omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); | |
580 | if (diff & (1 << 3)) /* SOFT_USB_REQ */ | |
581 | omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); | |
582 | } | |
583 | ||
a8170e5e | 584 | static void omap_ulpd_pm_write(void *opaque, hwaddr addr, |
4b3fedf3 | 585 | uint64_t value, unsigned size) |
c3d2689d AZ |
586 | { |
587 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
588 | int64_t now, ticks; |
589 | int div, mult; | |
590 | static const int bypass_div[4] = { 1, 2, 4, 4 }; | |
591 | uint16_t diff; | |
592 | ||
4b3fedf3 | 593 | if (size != 2) { |
77a8257e SW |
594 | omap_badwidth_write16(opaque, addr, value); |
595 | return; | |
4b3fedf3 AK |
596 | } |
597 | ||
8da3ff18 | 598 | switch (addr) { |
c3d2689d AZ |
599 | case 0x00: /* COUNTER_32_LSB */ |
600 | case 0x04: /* COUNTER_32_MSB */ | |
601 | case 0x08: /* COUNTER_HIGH_FREQ_LSB */ | |
602 | case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ | |
603 | case 0x14: /* IT_STATUS */ | |
604 | case 0x40: /* STATUS_REQ */ | |
605 | OMAP_RO_REG(addr); | |
606 | break; | |
607 | ||
608 | case 0x10: /* GAUGING_CTRL */ | |
609 | /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ | |
8da3ff18 | 610 | if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { |
bc72ad67 | 611 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
c3d2689d AZ |
612 | |
613 | if (value & 1) | |
614 | s->ulpd_gauge_start = now; | |
615 | else { | |
616 | now -= s->ulpd_gauge_start; | |
617 | ||
618 | /* 32-kHz ticks */ | |
6ee093c9 | 619 | ticks = muldiv64(now, 32768, get_ticks_per_sec()); |
c3d2689d AZ |
620 | s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
621 | s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; | |
622 | if (ticks >> 32) /* OVERFLOW_32K */ | |
623 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; | |
624 | ||
625 | /* High frequency ticks */ | |
6ee093c9 | 626 | ticks = muldiv64(now, 12000000, get_ticks_per_sec()); |
c3d2689d AZ |
627 | s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
628 | s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; | |
629 | if (ticks >> 32) /* OVERFLOW_HI_FREQ */ | |
630 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; | |
631 | ||
632 | s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ | |
0919ac78 | 633 | qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K)); |
c3d2689d AZ |
634 | } |
635 | } | |
8da3ff18 | 636 | s->ulpd_pm_regs[addr >> 2] = value; |
c3d2689d AZ |
637 | break; |
638 | ||
639 | case 0x18: /* Reserved */ | |
640 | case 0x1c: /* Reserved */ | |
641 | case 0x20: /* Reserved */ | |
642 | case 0x28: /* Reserved */ | |
643 | case 0x2c: /* Reserved */ | |
644 | OMAP_BAD_REG(addr); | |
139bd956 | 645 | /* fall through */ |
c3d2689d AZ |
646 | case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
647 | case 0x38: /* COUNTER_32_FIQ */ | |
648 | case 0x48: /* LOCL_TIME */ | |
649 | case 0x50: /* POWER_CTRL */ | |
8da3ff18 | 650 | s->ulpd_pm_regs[addr >> 2] = value; |
c3d2689d AZ |
651 | break; |
652 | ||
653 | case 0x30: /* CLOCK_CTRL */ | |
8da3ff18 PB |
654 | diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
655 | s->ulpd_pm_regs[addr >> 2] = value & 0x3f; | |
c3d2689d AZ |
656 | omap_ulpd_clk_update(s, diff, value); |
657 | break; | |
658 | ||
659 | case 0x34: /* SOFT_REQ */ | |
8da3ff18 PB |
660 | diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
661 | s->ulpd_pm_regs[addr >> 2] = value & 0x1f; | |
c3d2689d AZ |
662 | omap_ulpd_req_update(s, diff, value); |
663 | break; | |
664 | ||
665 | case 0x3c: /* DPLL_CTRL */ | |
666 | /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is | |
667 | * omitted altogether, probably a typo. */ | |
668 | /* This register has identical semantics with DPLL(1:3) control | |
669 | * registers, see omap_dpll_write() */ | |
8da3ff18 PB |
670 | diff = s->ulpd_pm_regs[addr >> 2] & value; |
671 | s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; | |
c3d2689d AZ |
672 | if (diff & (0x3ff << 2)) { |
673 | if (value & (1 << 4)) { /* PLL_ENABLE */ | |
674 | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ | |
675 | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ | |
676 | } else { | |
677 | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ | |
678 | mult = 1; | |
679 | } | |
680 | omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); | |
681 | } | |
682 | ||
683 | /* Enter the desired mode. */ | |
8da3ff18 PB |
684 | s->ulpd_pm_regs[addr >> 2] = |
685 | (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | | |
686 | ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); | |
c3d2689d AZ |
687 | |
688 | /* Act as if the lock is restored. */ | |
8da3ff18 | 689 | s->ulpd_pm_regs[addr >> 2] |= 2; |
c3d2689d AZ |
690 | break; |
691 | ||
692 | case 0x4c: /* APLL_CTRL */ | |
8da3ff18 PB |
693 | diff = s->ulpd_pm_regs[addr >> 2] & value; |
694 | s->ulpd_pm_regs[addr >> 2] = value & 0xf; | |
c3d2689d AZ |
695 | if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
696 | omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, | |
697 | (value & (1 << 0)) ? "apll" : "dpll4")); | |
698 | break; | |
699 | ||
700 | default: | |
701 | OMAP_BAD_REG(addr); | |
702 | } | |
703 | } | |
704 | ||
4b3fedf3 AK |
705 | static const MemoryRegionOps omap_ulpd_pm_ops = { |
706 | .read = omap_ulpd_pm_read, | |
707 | .write = omap_ulpd_pm_write, | |
708 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
709 | }; |
710 | ||
711 | static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) | |
712 | { | |
713 | mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; | |
714 | mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; | |
715 | mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; | |
716 | mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; | |
717 | mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; | |
718 | mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; | |
719 | mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; | |
720 | mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; | |
721 | mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; | |
722 | mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; | |
723 | mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; | |
724 | omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); | |
725 | mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; | |
726 | omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); | |
727 | mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; | |
728 | mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; | |
729 | mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; | |
730 | mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ | |
731 | mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; | |
732 | mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; | |
733 | mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; | |
734 | omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); | |
735 | omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); | |
736 | } | |
737 | ||
4b3fedf3 | 738 | static void omap_ulpd_pm_init(MemoryRegion *system_memory, |
a8170e5e | 739 | hwaddr base, |
c3d2689d AZ |
740 | struct omap_mpu_state_s *mpu) |
741 | { | |
2c9b15ca | 742 | memory_region_init_io(&mpu->ulpd_pm_iomem, NULL, &omap_ulpd_pm_ops, mpu, |
4b3fedf3 AK |
743 | "omap-ulpd-pm", 0x800); |
744 | memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem); | |
c3d2689d AZ |
745 | omap_ulpd_pm_reset(mpu); |
746 | } | |
747 | ||
748 | /* OMAP Pin Configuration */ | |
a8170e5e | 749 | static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, |
4b3fedf3 | 750 | unsigned size) |
c3d2689d AZ |
751 | { |
752 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 753 | |
4b3fedf3 AK |
754 | if (size != 4) { |
755 | return omap_badwidth_read32(opaque, addr); | |
756 | } | |
757 | ||
8da3ff18 | 758 | switch (addr) { |
c3d2689d AZ |
759 | case 0x00: /* FUNC_MUX_CTRL_0 */ |
760 | case 0x04: /* FUNC_MUX_CTRL_1 */ | |
761 | case 0x08: /* FUNC_MUX_CTRL_2 */ | |
8da3ff18 | 762 | return s->func_mux_ctrl[addr >> 2]; |
c3d2689d AZ |
763 | |
764 | case 0x0c: /* COMP_MODE_CTRL_0 */ | |
765 | return s->comp_mode_ctrl[0]; | |
766 | ||
767 | case 0x10: /* FUNC_MUX_CTRL_3 */ | |
768 | case 0x14: /* FUNC_MUX_CTRL_4 */ | |
769 | case 0x18: /* FUNC_MUX_CTRL_5 */ | |
770 | case 0x1c: /* FUNC_MUX_CTRL_6 */ | |
771 | case 0x20: /* FUNC_MUX_CTRL_7 */ | |
772 | case 0x24: /* FUNC_MUX_CTRL_8 */ | |
773 | case 0x28: /* FUNC_MUX_CTRL_9 */ | |
774 | case 0x2c: /* FUNC_MUX_CTRL_A */ | |
775 | case 0x30: /* FUNC_MUX_CTRL_B */ | |
776 | case 0x34: /* FUNC_MUX_CTRL_C */ | |
777 | case 0x38: /* FUNC_MUX_CTRL_D */ | |
8da3ff18 | 778 | return s->func_mux_ctrl[(addr >> 2) - 1]; |
c3d2689d AZ |
779 | |
780 | case 0x40: /* PULL_DWN_CTRL_0 */ | |
781 | case 0x44: /* PULL_DWN_CTRL_1 */ | |
782 | case 0x48: /* PULL_DWN_CTRL_2 */ | |
783 | case 0x4c: /* PULL_DWN_CTRL_3 */ | |
8da3ff18 | 784 | return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; |
c3d2689d AZ |
785 | |
786 | case 0x50: /* GATE_INH_CTRL_0 */ | |
787 | return s->gate_inh_ctrl[0]; | |
788 | ||
789 | case 0x60: /* VOLTAGE_CTRL_0 */ | |
790 | return s->voltage_ctrl[0]; | |
791 | ||
792 | case 0x70: /* TEST_DBG_CTRL_0 */ | |
793 | return s->test_dbg_ctrl[0]; | |
794 | ||
795 | case 0x80: /* MOD_CONF_CTRL_0 */ | |
796 | return s->mod_conf_ctrl[0]; | |
797 | } | |
798 | ||
799 | OMAP_BAD_REG(addr); | |
800 | return 0; | |
801 | } | |
802 | ||
803 | static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, | |
804 | uint32_t diff, uint32_t value) | |
805 | { | |
806 | if (s->compat1509) { | |
807 | if (diff & (1 << 9)) /* BLUETOOTH */ | |
808 | omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), | |
809 | (~value >> 9) & 1); | |
810 | if (diff & (1 << 7)) /* USB.CLKO */ | |
811 | omap_clk_onoff(omap_findclk(s, "usb.clko"), | |
812 | (value >> 7) & 1); | |
813 | } | |
814 | } | |
815 | ||
816 | static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, | |
817 | uint32_t diff, uint32_t value) | |
818 | { | |
819 | if (s->compat1509) { | |
d2f41a11 PM |
820 | if (diff & (1U << 31)) { |
821 | /* MCBSP3_CLK_HIZ_DI */ | |
822 | omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1); | |
823 | } | |
824 | if (diff & (1 << 1)) { | |
825 | /* CLK32K */ | |
826 | omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1); | |
827 | } | |
c3d2689d AZ |
828 | } |
829 | } | |
830 | ||
831 | static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, | |
832 | uint32_t diff, uint32_t value) | |
833 | { | |
d2f41a11 PM |
834 | if (diff & (1U << 31)) { |
835 | /* CONF_MOD_UART3_CLK_MODE_R */ | |
836 | omap_clk_reparent(omap_findclk(s, "uart3_ck"), | |
837 | omap_findclk(s, ((value >> 31) & 1) ? | |
838 | "ck_48m" : "armper_ck")); | |
839 | } | |
c3d2689d AZ |
840 | if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
841 | omap_clk_reparent(omap_findclk(s, "uart2_ck"), | |
842 | omap_findclk(s, ((value >> 30) & 1) ? | |
843 | "ck_48m" : "armper_ck")); | |
844 | if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ | |
845 | omap_clk_reparent(omap_findclk(s, "uart1_ck"), | |
846 | omap_findclk(s, ((value >> 29) & 1) ? | |
847 | "ck_48m" : "armper_ck")); | |
848 | if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ | |
849 | omap_clk_reparent(omap_findclk(s, "mmc_ck"), | |
850 | omap_findclk(s, ((value >> 23) & 1) ? | |
851 | "ck_48m" : "armper_ck")); | |
852 | if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ | |
853 | omap_clk_reparent(omap_findclk(s, "com_mclk_out"), | |
854 | omap_findclk(s, ((value >> 12) & 1) ? | |
855 | "ck_48m" : "armper_ck")); | |
856 | if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ | |
857 | omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); | |
858 | } | |
859 | ||
a8170e5e | 860 | static void omap_pin_cfg_write(void *opaque, hwaddr addr, |
4b3fedf3 | 861 | uint64_t value, unsigned size) |
c3d2689d AZ |
862 | { |
863 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
864 | uint32_t diff; |
865 | ||
4b3fedf3 | 866 | if (size != 4) { |
77a8257e SW |
867 | omap_badwidth_write32(opaque, addr, value); |
868 | return; | |
4b3fedf3 AK |
869 | } |
870 | ||
8da3ff18 | 871 | switch (addr) { |
c3d2689d | 872 | case 0x00: /* FUNC_MUX_CTRL_0 */ |
8da3ff18 PB |
873 | diff = s->func_mux_ctrl[addr >> 2] ^ value; |
874 | s->func_mux_ctrl[addr >> 2] = value; | |
c3d2689d AZ |
875 | omap_pin_funcmux0_update(s, diff, value); |
876 | return; | |
877 | ||
878 | case 0x04: /* FUNC_MUX_CTRL_1 */ | |
8da3ff18 PB |
879 | diff = s->func_mux_ctrl[addr >> 2] ^ value; |
880 | s->func_mux_ctrl[addr >> 2] = value; | |
c3d2689d AZ |
881 | omap_pin_funcmux1_update(s, diff, value); |
882 | return; | |
883 | ||
884 | case 0x08: /* FUNC_MUX_CTRL_2 */ | |
8da3ff18 | 885 | s->func_mux_ctrl[addr >> 2] = value; |
c3d2689d AZ |
886 | return; |
887 | ||
888 | case 0x0c: /* COMP_MODE_CTRL_0 */ | |
889 | s->comp_mode_ctrl[0] = value; | |
890 | s->compat1509 = (value != 0x0000eaef); | |
891 | omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); | |
892 | omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); | |
893 | return; | |
894 | ||
895 | case 0x10: /* FUNC_MUX_CTRL_3 */ | |
896 | case 0x14: /* FUNC_MUX_CTRL_4 */ | |
897 | case 0x18: /* FUNC_MUX_CTRL_5 */ | |
898 | case 0x1c: /* FUNC_MUX_CTRL_6 */ | |
899 | case 0x20: /* FUNC_MUX_CTRL_7 */ | |
900 | case 0x24: /* FUNC_MUX_CTRL_8 */ | |
901 | case 0x28: /* FUNC_MUX_CTRL_9 */ | |
902 | case 0x2c: /* FUNC_MUX_CTRL_A */ | |
903 | case 0x30: /* FUNC_MUX_CTRL_B */ | |
904 | case 0x34: /* FUNC_MUX_CTRL_C */ | |
905 | case 0x38: /* FUNC_MUX_CTRL_D */ | |
8da3ff18 | 906 | s->func_mux_ctrl[(addr >> 2) - 1] = value; |
c3d2689d AZ |
907 | return; |
908 | ||
909 | case 0x40: /* PULL_DWN_CTRL_0 */ | |
910 | case 0x44: /* PULL_DWN_CTRL_1 */ | |
911 | case 0x48: /* PULL_DWN_CTRL_2 */ | |
912 | case 0x4c: /* PULL_DWN_CTRL_3 */ | |
8da3ff18 | 913 | s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; |
c3d2689d AZ |
914 | return; |
915 | ||
916 | case 0x50: /* GATE_INH_CTRL_0 */ | |
917 | s->gate_inh_ctrl[0] = value; | |
918 | return; | |
919 | ||
920 | case 0x60: /* VOLTAGE_CTRL_0 */ | |
921 | s->voltage_ctrl[0] = value; | |
922 | return; | |
923 | ||
924 | case 0x70: /* TEST_DBG_CTRL_0 */ | |
925 | s->test_dbg_ctrl[0] = value; | |
926 | return; | |
927 | ||
928 | case 0x80: /* MOD_CONF_CTRL_0 */ | |
929 | diff = s->mod_conf_ctrl[0] ^ value; | |
930 | s->mod_conf_ctrl[0] = value; | |
931 | omap_pin_modconf1_update(s, diff, value); | |
932 | return; | |
933 | ||
934 | default: | |
935 | OMAP_BAD_REG(addr); | |
936 | } | |
937 | } | |
938 | ||
4b3fedf3 AK |
939 | static const MemoryRegionOps omap_pin_cfg_ops = { |
940 | .read = omap_pin_cfg_read, | |
941 | .write = omap_pin_cfg_write, | |
942 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
943 | }; |
944 | ||
945 | static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) | |
946 | { | |
947 | /* Start in Compatibility Mode. */ | |
948 | mpu->compat1509 = 1; | |
949 | omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); | |
950 | omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); | |
951 | omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); | |
952 | memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); | |
953 | memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); | |
954 | memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); | |
955 | memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); | |
956 | memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); | |
957 | memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); | |
958 | memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); | |
959 | } | |
960 | ||
4b3fedf3 | 961 | static void omap_pin_cfg_init(MemoryRegion *system_memory, |
a8170e5e | 962 | hwaddr base, |
c3d2689d AZ |
963 | struct omap_mpu_state_s *mpu) |
964 | { | |
2c9b15ca | 965 | memory_region_init_io(&mpu->pin_cfg_iomem, NULL, &omap_pin_cfg_ops, mpu, |
4b3fedf3 AK |
966 | "omap-pin-cfg", 0x800); |
967 | memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); | |
c3d2689d AZ |
968 | omap_pin_cfg_reset(mpu); |
969 | } | |
970 | ||
971 | /* Device Identification, Die Identification */ | |
a8170e5e | 972 | static uint64_t omap_id_read(void *opaque, hwaddr addr, |
4b3fedf3 | 973 | unsigned size) |
c3d2689d AZ |
974 | { |
975 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
976 | ||
4b3fedf3 AK |
977 | if (size != 4) { |
978 | return omap_badwidth_read32(opaque, addr); | |
979 | } | |
980 | ||
c3d2689d AZ |
981 | switch (addr) { |
982 | case 0xfffe1800: /* DIE_ID_LSB */ | |
983 | return 0xc9581f0e; | |
984 | case 0xfffe1804: /* DIE_ID_MSB */ | |
985 | return 0xa8858bfa; | |
986 | ||
987 | case 0xfffe2000: /* PRODUCT_ID_LSB */ | |
988 | return 0x00aaaafc; | |
989 | case 0xfffe2004: /* PRODUCT_ID_MSB */ | |
990 | return 0xcafeb574; | |
991 | ||
992 | case 0xfffed400: /* JTAG_ID_LSB */ | |
993 | switch (s->mpu_model) { | |
994 | case omap310: | |
995 | return 0x03310315; | |
996 | case omap1510: | |
997 | return 0x03310115; | |
827df9f3 | 998 | default: |
2ac71179 | 999 | hw_error("%s: bad mpu model\n", __FUNCTION__); |
c3d2689d AZ |
1000 | } |
1001 | break; | |
1002 | ||
1003 | case 0xfffed404: /* JTAG_ID_MSB */ | |
1004 | switch (s->mpu_model) { | |
1005 | case omap310: | |
1006 | return 0xfb57402f; | |
1007 | case omap1510: | |
1008 | return 0xfb47002f; | |
827df9f3 | 1009 | default: |
2ac71179 | 1010 | hw_error("%s: bad mpu model\n", __FUNCTION__); |
c3d2689d AZ |
1011 | } |
1012 | break; | |
1013 | } | |
1014 | ||
1015 | OMAP_BAD_REG(addr); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
a8170e5e | 1019 | static void omap_id_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1020 | uint64_t value, unsigned size) |
c3d2689d | 1021 | { |
4b3fedf3 | 1022 | if (size != 4) { |
77a8257e SW |
1023 | omap_badwidth_write32(opaque, addr, value); |
1024 | return; | |
4b3fedf3 AK |
1025 | } |
1026 | ||
c3d2689d AZ |
1027 | OMAP_BAD_REG(addr); |
1028 | } | |
1029 | ||
4b3fedf3 AK |
1030 | static const MemoryRegionOps omap_id_ops = { |
1031 | .read = omap_id_read, | |
1032 | .write = omap_id_write, | |
1033 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1034 | }; |
1035 | ||
4b3fedf3 | 1036 | static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) |
c3d2689d | 1037 | { |
2c9b15ca | 1038 | memory_region_init_io(&mpu->id_iomem, NULL, &omap_id_ops, mpu, |
4b3fedf3 | 1039 | "omap-id", 0x100000000ULL); |
2c9b15ca | 1040 | memory_region_init_alias(&mpu->id_iomem_e18, NULL, "omap-id-e18", &mpu->id_iomem, |
4b3fedf3 AK |
1041 | 0xfffe1800, 0x800); |
1042 | memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18); | |
2c9b15ca | 1043 | memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-ed4", &mpu->id_iomem, |
4b3fedf3 AK |
1044 | 0xfffed400, 0x100); |
1045 | memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4); | |
1046 | if (!cpu_is_omap15xx(mpu)) { | |
2c9b15ca | 1047 | memory_region_init_alias(&mpu->id_iomem_ed4, NULL, "omap-id-e20", |
4b3fedf3 AK |
1048 | &mpu->id_iomem, 0xfffe2000, 0x800); |
1049 | memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20); | |
1050 | } | |
c3d2689d AZ |
1051 | } |
1052 | ||
1053 | /* MPUI Control (Dummy) */ | |
a8170e5e | 1054 | static uint64_t omap_mpui_read(void *opaque, hwaddr addr, |
4b3fedf3 | 1055 | unsigned size) |
c3d2689d AZ |
1056 | { |
1057 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1058 | |
4b3fedf3 AK |
1059 | if (size != 4) { |
1060 | return omap_badwidth_read32(opaque, addr); | |
1061 | } | |
1062 | ||
8da3ff18 | 1063 | switch (addr) { |
c3d2689d AZ |
1064 | case 0x00: /* CTRL */ |
1065 | return s->mpui_ctrl; | |
1066 | case 0x04: /* DEBUG_ADDR */ | |
1067 | return 0x01ffffff; | |
1068 | case 0x08: /* DEBUG_DATA */ | |
1069 | return 0xffffffff; | |
1070 | case 0x0c: /* DEBUG_FLAG */ | |
1071 | return 0x00000800; | |
1072 | case 0x10: /* STATUS */ | |
1073 | return 0x00000000; | |
1074 | ||
1075 | /* Not in OMAP310 */ | |
1076 | case 0x14: /* DSP_STATUS */ | |
1077 | case 0x18: /* DSP_BOOT_CONFIG */ | |
1078 | return 0x00000000; | |
1079 | case 0x1c: /* DSP_MPUI_CONFIG */ | |
1080 | return 0x0000ffff; | |
1081 | } | |
1082 | ||
1083 | OMAP_BAD_REG(addr); | |
1084 | return 0; | |
1085 | } | |
1086 | ||
a8170e5e | 1087 | static void omap_mpui_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1088 | uint64_t value, unsigned size) |
c3d2689d AZ |
1089 | { |
1090 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1091 | |
4b3fedf3 | 1092 | if (size != 4) { |
77a8257e SW |
1093 | omap_badwidth_write32(opaque, addr, value); |
1094 | return; | |
4b3fedf3 AK |
1095 | } |
1096 | ||
8da3ff18 | 1097 | switch (addr) { |
c3d2689d AZ |
1098 | case 0x00: /* CTRL */ |
1099 | s->mpui_ctrl = value & 0x007fffff; | |
1100 | break; | |
1101 | ||
1102 | case 0x04: /* DEBUG_ADDR */ | |
1103 | case 0x08: /* DEBUG_DATA */ | |
1104 | case 0x0c: /* DEBUG_FLAG */ | |
1105 | case 0x10: /* STATUS */ | |
1106 | /* Not in OMAP310 */ | |
1107 | case 0x14: /* DSP_STATUS */ | |
1108 | OMAP_RO_REG(addr); | |
139bd956 | 1109 | break; |
c3d2689d AZ |
1110 | case 0x18: /* DSP_BOOT_CONFIG */ |
1111 | case 0x1c: /* DSP_MPUI_CONFIG */ | |
1112 | break; | |
1113 | ||
1114 | default: | |
1115 | OMAP_BAD_REG(addr); | |
1116 | } | |
1117 | } | |
1118 | ||
4b3fedf3 AK |
1119 | static const MemoryRegionOps omap_mpui_ops = { |
1120 | .read = omap_mpui_read, | |
1121 | .write = omap_mpui_write, | |
1122 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1123 | }; |
1124 | ||
1125 | static void omap_mpui_reset(struct omap_mpu_state_s *s) | |
1126 | { | |
1127 | s->mpui_ctrl = 0x0003ff1b; | |
1128 | } | |
1129 | ||
a8170e5e | 1130 | static void omap_mpui_init(MemoryRegion *memory, hwaddr base, |
c3d2689d AZ |
1131 | struct omap_mpu_state_s *mpu) |
1132 | { | |
2c9b15ca | 1133 | memory_region_init_io(&mpu->mpui_iomem, NULL, &omap_mpui_ops, mpu, |
4b3fedf3 AK |
1134 | "omap-mpui", 0x100); |
1135 | memory_region_add_subregion(memory, base, &mpu->mpui_iomem); | |
c3d2689d AZ |
1136 | |
1137 | omap_mpui_reset(mpu); | |
1138 | } | |
1139 | ||
1140 | /* TIPB Bridges */ | |
1141 | struct omap_tipb_bridge_s { | |
c3d2689d | 1142 | qemu_irq abort; |
4b3fedf3 | 1143 | MemoryRegion iomem; |
c3d2689d AZ |
1144 | |
1145 | int width_intr; | |
1146 | uint16_t control; | |
1147 | uint16_t alloc; | |
1148 | uint16_t buffer; | |
1149 | uint16_t enh_control; | |
1150 | }; | |
1151 | ||
a8170e5e | 1152 | static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, |
4b3fedf3 | 1153 | unsigned size) |
c3d2689d AZ |
1154 | { |
1155 | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | |
c3d2689d | 1156 | |
4b3fedf3 AK |
1157 | if (size < 2) { |
1158 | return omap_badwidth_read16(opaque, addr); | |
1159 | } | |
1160 | ||
8da3ff18 | 1161 | switch (addr) { |
c3d2689d AZ |
1162 | case 0x00: /* TIPB_CNTL */ |
1163 | return s->control; | |
1164 | case 0x04: /* TIPB_BUS_ALLOC */ | |
1165 | return s->alloc; | |
1166 | case 0x08: /* MPU_TIPB_CNTL */ | |
1167 | return s->buffer; | |
1168 | case 0x0c: /* ENHANCED_TIPB_CNTL */ | |
1169 | return s->enh_control; | |
1170 | case 0x10: /* ADDRESS_DBG */ | |
1171 | case 0x14: /* DATA_DEBUG_LOW */ | |
1172 | case 0x18: /* DATA_DEBUG_HIGH */ | |
1173 | return 0xffff; | |
1174 | case 0x1c: /* DEBUG_CNTR_SIG */ | |
1175 | return 0x00f8; | |
1176 | } | |
1177 | ||
1178 | OMAP_BAD_REG(addr); | |
1179 | return 0; | |
1180 | } | |
1181 | ||
a8170e5e | 1182 | static void omap_tipb_bridge_write(void *opaque, hwaddr addr, |
4b3fedf3 | 1183 | uint64_t value, unsigned size) |
c3d2689d AZ |
1184 | { |
1185 | struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | |
c3d2689d | 1186 | |
4b3fedf3 | 1187 | if (size < 2) { |
77a8257e SW |
1188 | omap_badwidth_write16(opaque, addr, value); |
1189 | return; | |
4b3fedf3 AK |
1190 | } |
1191 | ||
8da3ff18 | 1192 | switch (addr) { |
c3d2689d AZ |
1193 | case 0x00: /* TIPB_CNTL */ |
1194 | s->control = value & 0xffff; | |
1195 | break; | |
1196 | ||
1197 | case 0x04: /* TIPB_BUS_ALLOC */ | |
1198 | s->alloc = value & 0x003f; | |
1199 | break; | |
1200 | ||
1201 | case 0x08: /* MPU_TIPB_CNTL */ | |
1202 | s->buffer = value & 0x0003; | |
1203 | break; | |
1204 | ||
1205 | case 0x0c: /* ENHANCED_TIPB_CNTL */ | |
1206 | s->width_intr = !(value & 2); | |
1207 | s->enh_control = value & 0x000f; | |
1208 | break; | |
1209 | ||
1210 | case 0x10: /* ADDRESS_DBG */ | |
1211 | case 0x14: /* DATA_DEBUG_LOW */ | |
1212 | case 0x18: /* DATA_DEBUG_HIGH */ | |
1213 | case 0x1c: /* DEBUG_CNTR_SIG */ | |
1214 | OMAP_RO_REG(addr); | |
1215 | break; | |
1216 | ||
1217 | default: | |
1218 | OMAP_BAD_REG(addr); | |
1219 | } | |
1220 | } | |
1221 | ||
4b3fedf3 AK |
1222 | static const MemoryRegionOps omap_tipb_bridge_ops = { |
1223 | .read = omap_tipb_bridge_read, | |
1224 | .write = omap_tipb_bridge_write, | |
1225 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1226 | }; |
1227 | ||
1228 | static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) | |
1229 | { | |
1230 | s->control = 0xffff; | |
1231 | s->alloc = 0x0009; | |
1232 | s->buffer = 0x0000; | |
1233 | s->enh_control = 0x000f; | |
1234 | } | |
1235 | ||
4b3fedf3 | 1236 | static struct omap_tipb_bridge_s *omap_tipb_bridge_init( |
a8170e5e | 1237 | MemoryRegion *memory, hwaddr base, |
4b3fedf3 | 1238 | qemu_irq abort_irq, omap_clk clk) |
c3d2689d | 1239 | { |
b45c03f5 | 1240 | struct omap_tipb_bridge_s *s = g_new0(struct omap_tipb_bridge_s, 1); |
c3d2689d AZ |
1241 | |
1242 | s->abort = abort_irq; | |
c3d2689d AZ |
1243 | omap_tipb_bridge_reset(s); |
1244 | ||
2c9b15ca | 1245 | memory_region_init_io(&s->iomem, NULL, &omap_tipb_bridge_ops, s, |
4b3fedf3 AK |
1246 | "omap-tipb-bridge", 0x100); |
1247 | memory_region_add_subregion(memory, base, &s->iomem); | |
c3d2689d AZ |
1248 | |
1249 | return s; | |
1250 | } | |
1251 | ||
1252 | /* Dummy Traffic Controller's Memory Interface */ | |
a8170e5e | 1253 | static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1254 | unsigned size) |
c3d2689d AZ |
1255 | { |
1256 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1257 | uint32_t ret; |
1258 | ||
e7aa0ae0 AK |
1259 | if (size != 4) { |
1260 | return omap_badwidth_read32(opaque, addr); | |
1261 | } | |
1262 | ||
8da3ff18 | 1263 | switch (addr) { |
d8f699cb AZ |
1264 | case 0x00: /* IMIF_PRIO */ |
1265 | case 0x04: /* EMIFS_PRIO */ | |
1266 | case 0x08: /* EMIFF_PRIO */ | |
1267 | case 0x0c: /* EMIFS_CONFIG */ | |
1268 | case 0x10: /* EMIFS_CS0_CONFIG */ | |
1269 | case 0x14: /* EMIFS_CS1_CONFIG */ | |
1270 | case 0x18: /* EMIFS_CS2_CONFIG */ | |
1271 | case 0x1c: /* EMIFS_CS3_CONFIG */ | |
1272 | case 0x24: /* EMIFF_MRS */ | |
1273 | case 0x28: /* TIMEOUT1 */ | |
1274 | case 0x2c: /* TIMEOUT2 */ | |
1275 | case 0x30: /* TIMEOUT3 */ | |
1276 | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ | |
1277 | case 0x40: /* EMIFS_CFG_DYN_WAIT */ | |
8da3ff18 | 1278 | return s->tcmi_regs[addr >> 2]; |
c3d2689d | 1279 | |
d8f699cb | 1280 | case 0x20: /* EMIFF_SDRAM_CONFIG */ |
8da3ff18 PB |
1281 | ret = s->tcmi_regs[addr >> 2]; |
1282 | s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ | |
c3d2689d AZ |
1283 | /* XXX: We can try using the VGA_DIRTY flag for this */ |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | OMAP_BAD_REG(addr); | |
1288 | return 0; | |
1289 | } | |
1290 | ||
a8170e5e | 1291 | static void omap_tcmi_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1292 | uint64_t value, unsigned size) |
c3d2689d AZ |
1293 | { |
1294 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1295 | |
e7aa0ae0 | 1296 | if (size != 4) { |
77a8257e SW |
1297 | omap_badwidth_write32(opaque, addr, value); |
1298 | return; | |
e7aa0ae0 AK |
1299 | } |
1300 | ||
8da3ff18 | 1301 | switch (addr) { |
d8f699cb AZ |
1302 | case 0x00: /* IMIF_PRIO */ |
1303 | case 0x04: /* EMIFS_PRIO */ | |
1304 | case 0x08: /* EMIFF_PRIO */ | |
1305 | case 0x10: /* EMIFS_CS0_CONFIG */ | |
1306 | case 0x14: /* EMIFS_CS1_CONFIG */ | |
1307 | case 0x18: /* EMIFS_CS2_CONFIG */ | |
1308 | case 0x1c: /* EMIFS_CS3_CONFIG */ | |
1309 | case 0x20: /* EMIFF_SDRAM_CONFIG */ | |
1310 | case 0x24: /* EMIFF_MRS */ | |
1311 | case 0x28: /* TIMEOUT1 */ | |
1312 | case 0x2c: /* TIMEOUT2 */ | |
1313 | case 0x30: /* TIMEOUT3 */ | |
1314 | case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ | |
1315 | case 0x40: /* EMIFS_CFG_DYN_WAIT */ | |
8da3ff18 | 1316 | s->tcmi_regs[addr >> 2] = value; |
c3d2689d | 1317 | break; |
d8f699cb | 1318 | case 0x0c: /* EMIFS_CONFIG */ |
8da3ff18 | 1319 | s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); |
c3d2689d AZ |
1320 | break; |
1321 | ||
1322 | default: | |
1323 | OMAP_BAD_REG(addr); | |
1324 | } | |
1325 | } | |
1326 | ||
e7aa0ae0 AK |
1327 | static const MemoryRegionOps omap_tcmi_ops = { |
1328 | .read = omap_tcmi_read, | |
1329 | .write = omap_tcmi_write, | |
1330 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1331 | }; |
1332 | ||
1333 | static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) | |
1334 | { | |
1335 | mpu->tcmi_regs[0x00 >> 2] = 0x00000000; | |
1336 | mpu->tcmi_regs[0x04 >> 2] = 0x00000000; | |
1337 | mpu->tcmi_regs[0x08 >> 2] = 0x00000000; | |
1338 | mpu->tcmi_regs[0x0c >> 2] = 0x00000010; | |
1339 | mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; | |
1340 | mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; | |
1341 | mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; | |
1342 | mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; | |
1343 | mpu->tcmi_regs[0x20 >> 2] = 0x00618800; | |
1344 | mpu->tcmi_regs[0x24 >> 2] = 0x00000037; | |
1345 | mpu->tcmi_regs[0x28 >> 2] = 0x00000000; | |
1346 | mpu->tcmi_regs[0x2c >> 2] = 0x00000000; | |
1347 | mpu->tcmi_regs[0x30 >> 2] = 0x00000000; | |
1348 | mpu->tcmi_regs[0x3c >> 2] = 0x00000003; | |
1349 | mpu->tcmi_regs[0x40 >> 2] = 0x00000000; | |
1350 | } | |
1351 | ||
a8170e5e | 1352 | static void omap_tcmi_init(MemoryRegion *memory, hwaddr base, |
c3d2689d AZ |
1353 | struct omap_mpu_state_s *mpu) |
1354 | { | |
2c9b15ca | 1355 | memory_region_init_io(&mpu->tcmi_iomem, NULL, &omap_tcmi_ops, mpu, |
e7aa0ae0 AK |
1356 | "omap-tcmi", 0x100); |
1357 | memory_region_add_subregion(memory, base, &mpu->tcmi_iomem); | |
c3d2689d AZ |
1358 | omap_tcmi_reset(mpu); |
1359 | } | |
1360 | ||
1361 | /* Digital phase-locked loops control */ | |
b9f7bc40 JR |
1362 | struct dpll_ctl_s { |
1363 | MemoryRegion iomem; | |
1364 | uint16_t mode; | |
1365 | omap_clk dpll; | |
1366 | }; | |
1367 | ||
a8170e5e | 1368 | static uint64_t omap_dpll_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1369 | unsigned size) |
c3d2689d AZ |
1370 | { |
1371 | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | |
c3d2689d | 1372 | |
e7aa0ae0 AK |
1373 | if (size != 2) { |
1374 | return omap_badwidth_read16(opaque, addr); | |
1375 | } | |
1376 | ||
8da3ff18 | 1377 | if (addr == 0x00) /* CTL_REG */ |
c3d2689d AZ |
1378 | return s->mode; |
1379 | ||
1380 | OMAP_BAD_REG(addr); | |
1381 | return 0; | |
1382 | } | |
1383 | ||
a8170e5e | 1384 | static void omap_dpll_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1385 | uint64_t value, unsigned size) |
c3d2689d AZ |
1386 | { |
1387 | struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | |
1388 | uint16_t diff; | |
c3d2689d AZ |
1389 | static const int bypass_div[4] = { 1, 2, 4, 4 }; |
1390 | int div, mult; | |
1391 | ||
e7aa0ae0 | 1392 | if (size != 2) { |
77a8257e SW |
1393 | omap_badwidth_write16(opaque, addr, value); |
1394 | return; | |
e7aa0ae0 AK |
1395 | } |
1396 | ||
8da3ff18 | 1397 | if (addr == 0x00) { /* CTL_REG */ |
c3d2689d AZ |
1398 | /* See omap_ulpd_pm_write() too */ |
1399 | diff = s->mode & value; | |
1400 | s->mode = value & 0x2fff; | |
1401 | if (diff & (0x3ff << 2)) { | |
1402 | if (value & (1 << 4)) { /* PLL_ENABLE */ | |
1403 | div = ((value >> 5) & 3) + 1; /* PLL_DIV */ | |
1404 | mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ | |
1405 | } else { | |
1406 | div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ | |
1407 | mult = 1; | |
1408 | } | |
1409 | omap_clk_setrate(s->dpll, div, mult); | |
1410 | } | |
1411 | ||
1412 | /* Enter the desired mode. */ | |
1413 | s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); | |
1414 | ||
1415 | /* Act as if the lock is restored. */ | |
1416 | s->mode |= 2; | |
1417 | } else { | |
1418 | OMAP_BAD_REG(addr); | |
1419 | } | |
1420 | } | |
1421 | ||
e7aa0ae0 AK |
1422 | static const MemoryRegionOps omap_dpll_ops = { |
1423 | .read = omap_dpll_read, | |
1424 | .write = omap_dpll_write, | |
1425 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1426 | }; |
1427 | ||
1428 | static void omap_dpll_reset(struct dpll_ctl_s *s) | |
1429 | { | |
1430 | s->mode = 0x2002; | |
1431 | omap_clk_setrate(s->dpll, 1, 1); | |
1432 | } | |
1433 | ||
b9f7bc40 | 1434 | static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, |
a8170e5e | 1435 | hwaddr base, omap_clk clk) |
c3d2689d | 1436 | { |
b9f7bc40 | 1437 | struct dpll_ctl_s *s = g_malloc0(sizeof(*s)); |
2c9b15ca | 1438 | memory_region_init_io(&s->iomem, NULL, &omap_dpll_ops, s, "omap-dpll", 0x100); |
c3d2689d | 1439 | |
c3d2689d AZ |
1440 | s->dpll = clk; |
1441 | omap_dpll_reset(s); | |
1442 | ||
e7aa0ae0 | 1443 | memory_region_add_subregion(memory, base, &s->iomem); |
b9f7bc40 | 1444 | return s; |
c3d2689d AZ |
1445 | } |
1446 | ||
c3d2689d | 1447 | /* MPU Clock/Reset/Power Mode Control */ |
a8170e5e | 1448 | static uint64_t omap_clkm_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1449 | unsigned size) |
c3d2689d AZ |
1450 | { |
1451 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d | 1452 | |
e7aa0ae0 AK |
1453 | if (size != 2) { |
1454 | return omap_badwidth_read16(opaque, addr); | |
1455 | } | |
1456 | ||
8da3ff18 | 1457 | switch (addr) { |
c3d2689d AZ |
1458 | case 0x00: /* ARM_CKCTL */ |
1459 | return s->clkm.arm_ckctl; | |
1460 | ||
1461 | case 0x04: /* ARM_IDLECT1 */ | |
1462 | return s->clkm.arm_idlect1; | |
1463 | ||
1464 | case 0x08: /* ARM_IDLECT2 */ | |
1465 | return s->clkm.arm_idlect2; | |
1466 | ||
1467 | case 0x0c: /* ARM_EWUPCT */ | |
1468 | return s->clkm.arm_ewupct; | |
1469 | ||
1470 | case 0x10: /* ARM_RSTCT1 */ | |
1471 | return s->clkm.arm_rstct1; | |
1472 | ||
1473 | case 0x14: /* ARM_RSTCT2 */ | |
1474 | return s->clkm.arm_rstct2; | |
1475 | ||
1476 | case 0x18: /* ARM_SYSST */ | |
d8f699cb | 1477 | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
c3d2689d AZ |
1478 | |
1479 | case 0x1c: /* ARM_CKOUT1 */ | |
1480 | return s->clkm.arm_ckout1; | |
1481 | ||
1482 | case 0x20: /* ARM_CKOUT2 */ | |
1483 | break; | |
1484 | } | |
1485 | ||
1486 | OMAP_BAD_REG(addr); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, | |
1491 | uint16_t diff, uint16_t value) | |
1492 | { | |
1493 | omap_clk clk; | |
1494 | ||
1495 | if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ | |
1496 | if (value & (1 << 14)) | |
1497 | /* Reserved */; | |
1498 | else { | |
1499 | clk = omap_findclk(s, "arminth_ck"); | |
1500 | omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); | |
1501 | } | |
1502 | } | |
1503 | if (diff & (1 << 12)) { /* ARM_TIMXO */ | |
1504 | clk = omap_findclk(s, "armtim_ck"); | |
1505 | if (value & (1 << 12)) | |
1506 | omap_clk_reparent(clk, omap_findclk(s, "clkin")); | |
1507 | else | |
1508 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); | |
1509 | } | |
1510 | /* XXX: en_dspck */ | |
1511 | if (diff & (3 << 10)) { /* DSPMMUDIV */ | |
1512 | clk = omap_findclk(s, "dspmmu_ck"); | |
1513 | omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); | |
1514 | } | |
1515 | if (diff & (3 << 8)) { /* TCDIV */ | |
1516 | clk = omap_findclk(s, "tc_ck"); | |
1517 | omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); | |
1518 | } | |
1519 | if (diff & (3 << 6)) { /* DSPDIV */ | |
1520 | clk = omap_findclk(s, "dsp_ck"); | |
1521 | omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); | |
1522 | } | |
1523 | if (diff & (3 << 4)) { /* ARMDIV */ | |
1524 | clk = omap_findclk(s, "arm_ck"); | |
1525 | omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); | |
1526 | } | |
1527 | if (diff & (3 << 2)) { /* LCDDIV */ | |
1528 | clk = omap_findclk(s, "lcd_ck"); | |
1529 | omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); | |
1530 | } | |
1531 | if (diff & (3 << 0)) { /* PERDIV */ | |
1532 | clk = omap_findclk(s, "armper_ck"); | |
1533 | omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, | |
1538 | uint16_t diff, uint16_t value) | |
1539 | { | |
1540 | omap_clk clk; | |
1541 | ||
5f4ef08b | 1542 | if (value & (1 << 11)) { /* SETARM_IDLE */ |
c3affe56 | 1543 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
5f4ef08b | 1544 | } |
c3d2689d AZ |
1545 | if (!(value & (1 << 10))) /* WKUP_MODE */ |
1546 | qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ | |
1547 | ||
1548 | #define SET_CANIDLE(clock, bit) \ | |
1549 | if (diff & (1 << bit)) { \ | |
1550 | clk = omap_findclk(s, clock); \ | |
1551 | omap_clk_canidle(clk, (value >> bit) & 1); \ | |
1552 | } | |
1553 | SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ | |
1554 | SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ | |
1555 | SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ | |
1556 | SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ | |
1557 | SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ | |
1558 | SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ | |
1559 | SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ | |
1560 | SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ | |
1561 | SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ | |
1562 | SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ | |
1563 | SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ | |
1564 | SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ | |
1565 | SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ | |
1566 | SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ | |
1567 | } | |
1568 | ||
1569 | static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, | |
1570 | uint16_t diff, uint16_t value) | |
1571 | { | |
1572 | omap_clk clk; | |
1573 | ||
1574 | #define SET_ONOFF(clock, bit) \ | |
1575 | if (diff & (1 << bit)) { \ | |
1576 | clk = omap_findclk(s, clock); \ | |
1577 | omap_clk_onoff(clk, (value >> bit) & 1); \ | |
1578 | } | |
1579 | SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ | |
1580 | SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ | |
1581 | SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ | |
1582 | SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ | |
1583 | SET_ONOFF("lb_ck", 4) /* EN_LBCK */ | |
1584 | SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ | |
1585 | SET_ONOFF("mpui_ck", 6) /* EN_APICK */ | |
1586 | SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ | |
1587 | SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ | |
1588 | SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ | |
1589 | SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ | |
1590 | } | |
1591 | ||
1592 | static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, | |
1593 | uint16_t diff, uint16_t value) | |
1594 | { | |
1595 | omap_clk clk; | |
1596 | ||
1597 | if (diff & (3 << 4)) { /* TCLKOUT */ | |
1598 | clk = omap_findclk(s, "tclk_out"); | |
1599 | switch ((value >> 4) & 3) { | |
1600 | case 1: | |
1601 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); | |
1602 | omap_clk_onoff(clk, 1); | |
1603 | break; | |
1604 | case 2: | |
1605 | omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); | |
1606 | omap_clk_onoff(clk, 1); | |
1607 | break; | |
1608 | default: | |
1609 | omap_clk_onoff(clk, 0); | |
1610 | } | |
1611 | } | |
1612 | if (diff & (3 << 2)) { /* DCLKOUT */ | |
1613 | clk = omap_findclk(s, "dclk_out"); | |
1614 | switch ((value >> 2) & 3) { | |
1615 | case 0: | |
1616 | omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); | |
1617 | break; | |
1618 | case 1: | |
1619 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); | |
1620 | break; | |
1621 | case 2: | |
1622 | omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); | |
1623 | break; | |
1624 | case 3: | |
1625 | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); | |
1626 | break; | |
1627 | } | |
1628 | } | |
1629 | if (diff & (3 << 0)) { /* ACLKOUT */ | |
1630 | clk = omap_findclk(s, "aclk_out"); | |
1631 | switch ((value >> 0) & 3) { | |
1632 | case 1: | |
1633 | omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); | |
1634 | omap_clk_onoff(clk, 1); | |
1635 | break; | |
1636 | case 2: | |
1637 | omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); | |
1638 | omap_clk_onoff(clk, 1); | |
1639 | break; | |
1640 | case 3: | |
1641 | omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); | |
1642 | omap_clk_onoff(clk, 1); | |
1643 | break; | |
1644 | default: | |
1645 | omap_clk_onoff(clk, 0); | |
1646 | } | |
1647 | } | |
1648 | } | |
1649 | ||
a8170e5e | 1650 | static void omap_clkm_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1651 | uint64_t value, unsigned size) |
c3d2689d AZ |
1652 | { |
1653 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1654 | uint16_t diff; |
1655 | omap_clk clk; | |
1656 | static const char *clkschemename[8] = { | |
1657 | "fully synchronous", "fully asynchronous", "synchronous scalable", | |
1658 | "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", | |
1659 | }; | |
1660 | ||
e7aa0ae0 | 1661 | if (size != 2) { |
77a8257e SW |
1662 | omap_badwidth_write16(opaque, addr, value); |
1663 | return; | |
e7aa0ae0 AK |
1664 | } |
1665 | ||
8da3ff18 | 1666 | switch (addr) { |
c3d2689d AZ |
1667 | case 0x00: /* ARM_CKCTL */ |
1668 | diff = s->clkm.arm_ckctl ^ value; | |
1669 | s->clkm.arm_ckctl = value & 0x7fff; | |
1670 | omap_clkm_ckctl_update(s, diff, value); | |
1671 | return; | |
1672 | ||
1673 | case 0x04: /* ARM_IDLECT1 */ | |
1674 | diff = s->clkm.arm_idlect1 ^ value; | |
1675 | s->clkm.arm_idlect1 = value & 0x0fff; | |
1676 | omap_clkm_idlect1_update(s, diff, value); | |
1677 | return; | |
1678 | ||
1679 | case 0x08: /* ARM_IDLECT2 */ | |
1680 | diff = s->clkm.arm_idlect2 ^ value; | |
1681 | s->clkm.arm_idlect2 = value & 0x07ff; | |
1682 | omap_clkm_idlect2_update(s, diff, value); | |
1683 | return; | |
1684 | ||
1685 | case 0x0c: /* ARM_EWUPCT */ | |
c3d2689d AZ |
1686 | s->clkm.arm_ewupct = value & 0x003f; |
1687 | return; | |
1688 | ||
1689 | case 0x10: /* ARM_RSTCT1 */ | |
1690 | diff = s->clkm.arm_rstct1 ^ value; | |
1691 | s->clkm.arm_rstct1 = value & 0x0007; | |
1692 | if (value & 9) { | |
1693 | qemu_system_reset_request(); | |
1694 | s->clkm.cold_start = 0xa; | |
1695 | } | |
1696 | if (diff & ~value & 4) { /* DSP_RST */ | |
1697 | omap_mpui_reset(s); | |
1698 | omap_tipb_bridge_reset(s->private_tipb); | |
1699 | omap_tipb_bridge_reset(s->public_tipb); | |
1700 | } | |
1701 | if (diff & 2) { /* DSP_EN */ | |
1702 | clk = omap_findclk(s, "dsp_ck"); | |
1703 | omap_clk_canidle(clk, (~value >> 1) & 1); | |
1704 | } | |
1705 | return; | |
1706 | ||
1707 | case 0x14: /* ARM_RSTCT2 */ | |
1708 | s->clkm.arm_rstct2 = value & 0x0001; | |
1709 | return; | |
1710 | ||
1711 | case 0x18: /* ARM_SYSST */ | |
1712 | if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { | |
1713 | s->clkm.clocking_scheme = (value >> 11) & 7; | |
1714 | printf("%s: clocking scheme set to %s\n", __FUNCTION__, | |
1715 | clkschemename[s->clkm.clocking_scheme]); | |
1716 | } | |
1717 | s->clkm.cold_start &= value & 0x3f; | |
1718 | return; | |
1719 | ||
1720 | case 0x1c: /* ARM_CKOUT1 */ | |
1721 | diff = s->clkm.arm_ckout1 ^ value; | |
1722 | s->clkm.arm_ckout1 = value & 0x003f; | |
1723 | omap_clkm_ckout1_update(s, diff, value); | |
1724 | return; | |
1725 | ||
1726 | case 0x20: /* ARM_CKOUT2 */ | |
1727 | default: | |
1728 | OMAP_BAD_REG(addr); | |
1729 | } | |
1730 | } | |
1731 | ||
e7aa0ae0 AK |
1732 | static const MemoryRegionOps omap_clkm_ops = { |
1733 | .read = omap_clkm_read, | |
1734 | .write = omap_clkm_write, | |
1735 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1736 | }; |
1737 | ||
a8170e5e | 1738 | static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1739 | unsigned size) |
c3d2689d AZ |
1740 | { |
1741 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
259186a7 | 1742 | CPUState *cpu = CPU(s->cpu); |
c3d2689d | 1743 | |
e7aa0ae0 AK |
1744 | if (size != 2) { |
1745 | return omap_badwidth_read16(opaque, addr); | |
1746 | } | |
1747 | ||
8da3ff18 | 1748 | switch (addr) { |
c3d2689d AZ |
1749 | case 0x04: /* DSP_IDLECT1 */ |
1750 | return s->clkm.dsp_idlect1; | |
1751 | ||
1752 | case 0x08: /* DSP_IDLECT2 */ | |
1753 | return s->clkm.dsp_idlect2; | |
1754 | ||
1755 | case 0x14: /* DSP_RSTCT2 */ | |
1756 | return s->clkm.dsp_rstct2; | |
1757 | ||
1758 | case 0x18: /* DSP_SYSST */ | |
259186a7 | 1759 | cpu = CPU(s->cpu); |
d8f699cb | 1760 | return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
259186a7 | 1761 | (cpu->halted << 6); /* Quite useless... */ |
c3d2689d AZ |
1762 | } |
1763 | ||
1764 | OMAP_BAD_REG(addr); | |
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, | |
1769 | uint16_t diff, uint16_t value) | |
1770 | { | |
1771 | omap_clk clk; | |
1772 | ||
1773 | SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ | |
1774 | } | |
1775 | ||
1776 | static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, | |
1777 | uint16_t diff, uint16_t value) | |
1778 | { | |
1779 | omap_clk clk; | |
1780 | ||
1781 | SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ | |
1782 | } | |
1783 | ||
a8170e5e | 1784 | static void omap_clkdsp_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1785 | uint64_t value, unsigned size) |
c3d2689d AZ |
1786 | { |
1787 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
c3d2689d AZ |
1788 | uint16_t diff; |
1789 | ||
e7aa0ae0 | 1790 | if (size != 2) { |
77a8257e SW |
1791 | omap_badwidth_write16(opaque, addr, value); |
1792 | return; | |
e7aa0ae0 AK |
1793 | } |
1794 | ||
8da3ff18 | 1795 | switch (addr) { |
c3d2689d AZ |
1796 | case 0x04: /* DSP_IDLECT1 */ |
1797 | diff = s->clkm.dsp_idlect1 ^ value; | |
1798 | s->clkm.dsp_idlect1 = value & 0x01f7; | |
1799 | omap_clkdsp_idlect1_update(s, diff, value); | |
1800 | break; | |
1801 | ||
1802 | case 0x08: /* DSP_IDLECT2 */ | |
1803 | s->clkm.dsp_idlect2 = value & 0x0037; | |
1804 | diff = s->clkm.dsp_idlect1 ^ value; | |
1805 | omap_clkdsp_idlect2_update(s, diff, value); | |
1806 | break; | |
1807 | ||
1808 | case 0x14: /* DSP_RSTCT2 */ | |
1809 | s->clkm.dsp_rstct2 = value & 0x0001; | |
1810 | break; | |
1811 | ||
1812 | case 0x18: /* DSP_SYSST */ | |
1813 | s->clkm.cold_start &= value & 0x3f; | |
1814 | break; | |
1815 | ||
1816 | default: | |
1817 | OMAP_BAD_REG(addr); | |
1818 | } | |
1819 | } | |
1820 | ||
e7aa0ae0 AK |
1821 | static const MemoryRegionOps omap_clkdsp_ops = { |
1822 | .read = omap_clkdsp_read, | |
1823 | .write = omap_clkdsp_write, | |
1824 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c3d2689d AZ |
1825 | }; |
1826 | ||
1827 | static void omap_clkm_reset(struct omap_mpu_state_s *s) | |
1828 | { | |
1829 | if (s->wdt && s->wdt->reset) | |
1830 | s->clkm.cold_start = 0x6; | |
1831 | s->clkm.clocking_scheme = 0; | |
1832 | omap_clkm_ckctl_update(s, ~0, 0x3000); | |
1833 | s->clkm.arm_ckctl = 0x3000; | |
d8f699cb | 1834 | omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
c3d2689d | 1835 | s->clkm.arm_idlect1 = 0x0400; |
d8f699cb | 1836 | omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
c3d2689d AZ |
1837 | s->clkm.arm_idlect2 = 0x0100; |
1838 | s->clkm.arm_ewupct = 0x003f; | |
1839 | s->clkm.arm_rstct1 = 0x0000; | |
1840 | s->clkm.arm_rstct2 = 0x0000; | |
1841 | s->clkm.arm_ckout1 = 0x0015; | |
1842 | s->clkm.dpll1_mode = 0x2002; | |
1843 | omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); | |
1844 | s->clkm.dsp_idlect1 = 0x0040; | |
1845 | omap_clkdsp_idlect2_update(s, ~0, 0x0000); | |
1846 | s->clkm.dsp_idlect2 = 0x0000; | |
1847 | s->clkm.dsp_rstct2 = 0x0000; | |
1848 | } | |
1849 | ||
a8170e5e AK |
1850 | static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base, |
1851 | hwaddr dsp_base, struct omap_mpu_state_s *s) | |
c3d2689d | 1852 | { |
2c9b15ca | 1853 | memory_region_init_io(&s->clkm_iomem, NULL, &omap_clkm_ops, s, |
e7aa0ae0 | 1854 | "omap-clkm", 0x100); |
2c9b15ca | 1855 | memory_region_init_io(&s->clkdsp_iomem, NULL, &omap_clkdsp_ops, s, |
e7aa0ae0 | 1856 | "omap-clkdsp", 0x1000); |
c3d2689d | 1857 | |
d8f699cb AZ |
1858 | s->clkm.arm_idlect1 = 0x03ff; |
1859 | s->clkm.arm_idlect2 = 0x0100; | |
1860 | s->clkm.dsp_idlect1 = 0x0002; | |
c3d2689d | 1861 | omap_clkm_reset(s); |
d8f699cb | 1862 | s->clkm.cold_start = 0x3a; |
c3d2689d | 1863 | |
e7aa0ae0 AK |
1864 | memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem); |
1865 | memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem); | |
c3d2689d AZ |
1866 | } |
1867 | ||
fe71e81a AZ |
1868 | /* MPU I/O */ |
1869 | struct omap_mpuio_s { | |
fe71e81a AZ |
1870 | qemu_irq irq; |
1871 | qemu_irq kbd_irq; | |
1872 | qemu_irq *in; | |
1873 | qemu_irq handler[16]; | |
1874 | qemu_irq wakeup; | |
e7aa0ae0 | 1875 | MemoryRegion iomem; |
fe71e81a AZ |
1876 | |
1877 | uint16_t inputs; | |
1878 | uint16_t outputs; | |
1879 | uint16_t dir; | |
1880 | uint16_t edge; | |
1881 | uint16_t mask; | |
1882 | uint16_t ints; | |
1883 | ||
1884 | uint16_t debounce; | |
1885 | uint16_t latch; | |
1886 | uint8_t event; | |
1887 | ||
1888 | uint8_t buttons[5]; | |
1889 | uint8_t row_latch; | |
1890 | uint8_t cols; | |
1891 | int kbd_mask; | |
1892 | int clk; | |
1893 | }; | |
1894 | ||
1895 | static void omap_mpuio_set(void *opaque, int line, int level) | |
1896 | { | |
1897 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
1898 | uint16_t prev = s->inputs; | |
1899 | ||
1900 | if (level) | |
1901 | s->inputs |= 1 << line; | |
1902 | else | |
1903 | s->inputs &= ~(1 << line); | |
1904 | ||
1905 | if (((1 << line) & s->dir & ~s->mask) && s->clk) { | |
1906 | if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { | |
1907 | s->ints |= 1 << line; | |
1908 | qemu_irq_raise(s->irq); | |
1909 | /* TODO: wakeup */ | |
1910 | } | |
1911 | if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ | |
1912 | (s->event >> 1) == line) /* PIN_SELECT */ | |
1913 | s->latch = s->inputs; | |
1914 | } | |
1915 | } | |
1916 | ||
1917 | static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) | |
1918 | { | |
1919 | int i; | |
1920 | uint8_t *row, rows = 0, cols = ~s->cols; | |
1921 | ||
38a34e1d | 1922 | for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
fe71e81a | 1923 | if (*row & cols) |
38a34e1d | 1924 | rows |= i; |
fe71e81a | 1925 | |
cf6d9118 AZ |
1926 | qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
1927 | s->row_latch = ~rows; | |
fe71e81a AZ |
1928 | } |
1929 | ||
a8170e5e | 1930 | static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, |
e7aa0ae0 | 1931 | unsigned size) |
fe71e81a AZ |
1932 | { |
1933 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
cf965d24 | 1934 | int offset = addr & OMAP_MPUI_REG_MASK; |
fe71e81a AZ |
1935 | uint16_t ret; |
1936 | ||
e7aa0ae0 AK |
1937 | if (size != 2) { |
1938 | return omap_badwidth_read16(opaque, addr); | |
1939 | } | |
1940 | ||
fe71e81a AZ |
1941 | switch (offset) { |
1942 | case 0x00: /* INPUT_LATCH */ | |
1943 | return s->inputs; | |
1944 | ||
1945 | case 0x04: /* OUTPUT_REG */ | |
1946 | return s->outputs; | |
1947 | ||
1948 | case 0x08: /* IO_CNTL */ | |
1949 | return s->dir; | |
1950 | ||
1951 | case 0x10: /* KBR_LATCH */ | |
1952 | return s->row_latch; | |
1953 | ||
1954 | case 0x14: /* KBC_REG */ | |
1955 | return s->cols; | |
1956 | ||
1957 | case 0x18: /* GPIO_EVENT_MODE_REG */ | |
1958 | return s->event; | |
1959 | ||
1960 | case 0x1c: /* GPIO_INT_EDGE_REG */ | |
1961 | return s->edge; | |
1962 | ||
1963 | case 0x20: /* KBD_INT */ | |
cf6d9118 | 1964 | return (~s->row_latch & 0x1f) && !s->kbd_mask; |
fe71e81a AZ |
1965 | |
1966 | case 0x24: /* GPIO_INT */ | |
1967 | ret = s->ints; | |
8e129e07 AZ |
1968 | s->ints &= s->mask; |
1969 | if (ret) | |
1970 | qemu_irq_lower(s->irq); | |
fe71e81a AZ |
1971 | return ret; |
1972 | ||
1973 | case 0x28: /* KBD_MASKIT */ | |
1974 | return s->kbd_mask; | |
1975 | ||
1976 | case 0x2c: /* GPIO_MASKIT */ | |
1977 | return s->mask; | |
1978 | ||
1979 | case 0x30: /* GPIO_DEBOUNCING_REG */ | |
1980 | return s->debounce; | |
1981 | ||
1982 | case 0x34: /* GPIO_LATCH_REG */ | |
1983 | return s->latch; | |
1984 | } | |
1985 | ||
1986 | OMAP_BAD_REG(addr); | |
1987 | return 0; | |
1988 | } | |
1989 | ||
a8170e5e | 1990 | static void omap_mpuio_write(void *opaque, hwaddr addr, |
e7aa0ae0 | 1991 | uint64_t value, unsigned size) |
fe71e81a AZ |
1992 | { |
1993 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
cf965d24 | 1994 | int offset = addr & OMAP_MPUI_REG_MASK; |
fe71e81a AZ |
1995 | uint16_t diff; |
1996 | int ln; | |
1997 | ||
e7aa0ae0 | 1998 | if (size != 2) { |
77a8257e SW |
1999 | omap_badwidth_write16(opaque, addr, value); |
2000 | return; | |
e7aa0ae0 AK |
2001 | } |
2002 | ||
fe71e81a AZ |
2003 | switch (offset) { |
2004 | case 0x04: /* OUTPUT_REG */ | |
d8f699cb | 2005 | diff = (s->outputs ^ value) & ~s->dir; |
fe71e81a | 2006 | s->outputs = value; |
bd2a8884 | 2007 | while ((ln = ctz32(diff)) != 32) { |
fe71e81a AZ |
2008 | if (s->handler[ln]) |
2009 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); | |
2010 | diff &= ~(1 << ln); | |
2011 | } | |
2012 | break; | |
2013 | ||
2014 | case 0x08: /* IO_CNTL */ | |
2015 | diff = s->outputs & (s->dir ^ value); | |
2016 | s->dir = value; | |
2017 | ||
2018 | value = s->outputs & ~s->dir; | |
bd2a8884 | 2019 | while ((ln = ctz32(diff)) != 32) { |
fe71e81a AZ |
2020 | if (s->handler[ln]) |
2021 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); | |
2022 | diff &= ~(1 << ln); | |
2023 | } | |
2024 | break; | |
2025 | ||
2026 | case 0x14: /* KBC_REG */ | |
2027 | s->cols = value; | |
2028 | omap_mpuio_kbd_update(s); | |
2029 | break; | |
2030 | ||
2031 | case 0x18: /* GPIO_EVENT_MODE_REG */ | |
2032 | s->event = value & 0x1f; | |
2033 | break; | |
2034 | ||
2035 | case 0x1c: /* GPIO_INT_EDGE_REG */ | |
2036 | s->edge = value; | |
2037 | break; | |
2038 | ||
2039 | case 0x28: /* KBD_MASKIT */ | |
2040 | s->kbd_mask = value & 1; | |
2041 | omap_mpuio_kbd_update(s); | |
2042 | break; | |
2043 | ||
2044 | case 0x2c: /* GPIO_MASKIT */ | |
2045 | s->mask = value; | |
2046 | break; | |
2047 | ||
2048 | case 0x30: /* GPIO_DEBOUNCING_REG */ | |
2049 | s->debounce = value & 0x1ff; | |
2050 | break; | |
2051 | ||
2052 | case 0x00: /* INPUT_LATCH */ | |
2053 | case 0x10: /* KBR_LATCH */ | |
2054 | case 0x20: /* KBD_INT */ | |
2055 | case 0x24: /* GPIO_INT */ | |
2056 | case 0x34: /* GPIO_LATCH_REG */ | |
2057 | OMAP_RO_REG(addr); | |
2058 | return; | |
2059 | ||
2060 | default: | |
2061 | OMAP_BAD_REG(addr); | |
2062 | return; | |
2063 | } | |
2064 | } | |
2065 | ||
e7aa0ae0 AK |
2066 | static const MemoryRegionOps omap_mpuio_ops = { |
2067 | .read = omap_mpuio_read, | |
2068 | .write = omap_mpuio_write, | |
2069 | .endianness = DEVICE_NATIVE_ENDIAN, | |
fe71e81a AZ |
2070 | }; |
2071 | ||
9596ebb7 | 2072 | static void omap_mpuio_reset(struct omap_mpuio_s *s) |
fe71e81a AZ |
2073 | { |
2074 | s->inputs = 0; | |
2075 | s->outputs = 0; | |
2076 | s->dir = ~0; | |
2077 | s->event = 0; | |
2078 | s->edge = 0; | |
2079 | s->kbd_mask = 0; | |
2080 | s->mask = 0; | |
2081 | s->debounce = 0; | |
2082 | s->latch = 0; | |
2083 | s->ints = 0; | |
2084 | s->row_latch = 0x1f; | |
38a34e1d | 2085 | s->clk = 1; |
fe71e81a AZ |
2086 | } |
2087 | ||
2088 | static void omap_mpuio_onoff(void *opaque, int line, int on) | |
2089 | { | |
2090 | struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | |
2091 | ||
2092 | s->clk = on; | |
2093 | if (on) | |
2094 | omap_mpuio_kbd_update(s); | |
2095 | } | |
2096 | ||
3b204c81 | 2097 | static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory, |
a8170e5e | 2098 | hwaddr base, |
fe71e81a AZ |
2099 | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
2100 | omap_clk clk) | |
2101 | { | |
b45c03f5 | 2102 | struct omap_mpuio_s *s = g_new0(struct omap_mpuio_s, 1); |
fe71e81a | 2103 | |
fe71e81a AZ |
2104 | s->irq = gpio_int; |
2105 | s->kbd_irq = kbd_int; | |
2106 | s->wakeup = wakeup; | |
2107 | s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); | |
2108 | omap_mpuio_reset(s); | |
2109 | ||
2c9b15ca | 2110 | memory_region_init_io(&s->iomem, NULL, &omap_mpuio_ops, s, |
e7aa0ae0 AK |
2111 | "omap-mpuio", 0x800); |
2112 | memory_region_add_subregion(memory, base, &s->iomem); | |
fe71e81a | 2113 | |
f3c7d038 | 2114 | omap_clk_adduser(clk, qemu_allocate_irq(omap_mpuio_onoff, s, 0)); |
fe71e81a AZ |
2115 | |
2116 | return s; | |
2117 | } | |
2118 | ||
2119 | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) | |
2120 | { | |
2121 | return s->in; | |
2122 | } | |
2123 | ||
2124 | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) | |
2125 | { | |
2126 | if (line >= 16 || line < 0) | |
2ac71179 | 2127 | hw_error("%s: No GPIO line %i\n", __FUNCTION__, line); |
fe71e81a AZ |
2128 | s->handler[line] = handler; |
2129 | } | |
2130 | ||
2131 | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) | |
2132 | { | |
2133 | if (row >= 5 || row < 0) | |
2ac71179 | 2134 | hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row); |
fe71e81a AZ |
2135 | |
2136 | if (down) | |
38a34e1d | 2137 | s->buttons[row] |= 1 << col; |
fe71e81a | 2138 | else |
38a34e1d | 2139 | s->buttons[row] &= ~(1 << col); |
fe71e81a AZ |
2140 | |
2141 | omap_mpuio_kbd_update(s); | |
2142 | } | |
2143 | ||
d951f6ff AZ |
2144 | /* MicroWire Interface */ |
2145 | struct omap_uwire_s { | |
a4ebbd18 | 2146 | MemoryRegion iomem; |
d951f6ff AZ |
2147 | qemu_irq txirq; |
2148 | qemu_irq rxirq; | |
2149 | qemu_irq txdrq; | |
2150 | ||
2151 | uint16_t txbuf; | |
2152 | uint16_t rxbuf; | |
2153 | uint16_t control; | |
2154 | uint16_t setup[5]; | |
2155 | ||
bc24a225 | 2156 | uWireSlave *chip[4]; |
d951f6ff AZ |
2157 | }; |
2158 | ||
2159 | static void omap_uwire_transfer_start(struct omap_uwire_s *s) | |
2160 | { | |
2161 | int chipselect = (s->control >> 10) & 3; /* INDEX */ | |
bc24a225 | 2162 | uWireSlave *slave = s->chip[chipselect]; |
d951f6ff AZ |
2163 | |
2164 | if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ | |
2165 | if (s->control & (1 << 12)) /* CS_CMD */ | |
2166 | if (slave && slave->send) | |
2167 | slave->send(slave->opaque, | |
2168 | s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); | |
2169 | s->control &= ~(1 << 14); /* CSRB */ | |
2170 | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or | |
2171 | * a DRQ. When is the level IRQ supposed to be reset? */ | |
2172 | } | |
2173 | ||
2174 | if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ | |
2175 | if (s->control & (1 << 12)) /* CS_CMD */ | |
2176 | if (slave && slave->receive) | |
2177 | s->rxbuf = slave->receive(slave->opaque); | |
2178 | s->control |= 1 << 15; /* RDRB */ | |
2179 | /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or | |
2180 | * a DRQ. When is the level IRQ supposed to be reset? */ | |
2181 | } | |
2182 | } | |
2183 | ||
a8170e5e | 2184 | static uint64_t omap_uwire_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2185 | unsigned size) |
d951f6ff AZ |
2186 | { |
2187 | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | |
cf965d24 | 2188 | int offset = addr & OMAP_MPUI_REG_MASK; |
d951f6ff | 2189 | |
a4ebbd18 AK |
2190 | if (size != 2) { |
2191 | return omap_badwidth_read16(opaque, addr); | |
2192 | } | |
2193 | ||
d951f6ff AZ |
2194 | switch (offset) { |
2195 | case 0x00: /* RDR */ | |
2196 | s->control &= ~(1 << 15); /* RDRB */ | |
2197 | return s->rxbuf; | |
2198 | ||
2199 | case 0x04: /* CSR */ | |
2200 | return s->control; | |
2201 | ||
2202 | case 0x08: /* SR1 */ | |
2203 | return s->setup[0]; | |
2204 | case 0x0c: /* SR2 */ | |
2205 | return s->setup[1]; | |
2206 | case 0x10: /* SR3 */ | |
2207 | return s->setup[2]; | |
2208 | case 0x14: /* SR4 */ | |
2209 | return s->setup[3]; | |
2210 | case 0x18: /* SR5 */ | |
2211 | return s->setup[4]; | |
2212 | } | |
2213 | ||
2214 | OMAP_BAD_REG(addr); | |
2215 | return 0; | |
2216 | } | |
2217 | ||
a8170e5e | 2218 | static void omap_uwire_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2219 | uint64_t value, unsigned size) |
d951f6ff AZ |
2220 | { |
2221 | struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | |
cf965d24 | 2222 | int offset = addr & OMAP_MPUI_REG_MASK; |
d951f6ff | 2223 | |
a4ebbd18 | 2224 | if (size != 2) { |
77a8257e SW |
2225 | omap_badwidth_write16(opaque, addr, value); |
2226 | return; | |
a4ebbd18 AK |
2227 | } |
2228 | ||
d951f6ff AZ |
2229 | switch (offset) { |
2230 | case 0x00: /* TDR */ | |
2231 | s->txbuf = value; /* TD */ | |
d951f6ff AZ |
2232 | if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
2233 | ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ | |
cf965d24 AZ |
2234 | (s->control & (1 << 12)))) { /* CS_CMD */ |
2235 | s->control |= 1 << 14; /* CSRB */ | |
d951f6ff | 2236 | omap_uwire_transfer_start(s); |
cf965d24 | 2237 | } |
d951f6ff AZ |
2238 | break; |
2239 | ||
2240 | case 0x04: /* CSR */ | |
2241 | s->control = value & 0x1fff; | |
2242 | if (value & (1 << 13)) /* START */ | |
2243 | omap_uwire_transfer_start(s); | |
2244 | break; | |
2245 | ||
2246 | case 0x08: /* SR1 */ | |
2247 | s->setup[0] = value & 0x003f; | |
2248 | break; | |
2249 | ||
2250 | case 0x0c: /* SR2 */ | |
2251 | s->setup[1] = value & 0x0fc0; | |
2252 | break; | |
2253 | ||
2254 | case 0x10: /* SR3 */ | |
2255 | s->setup[2] = value & 0x0003; | |
2256 | break; | |
2257 | ||
2258 | case 0x14: /* SR4 */ | |
2259 | s->setup[3] = value & 0x0001; | |
2260 | break; | |
2261 | ||
2262 | case 0x18: /* SR5 */ | |
2263 | s->setup[4] = value & 0x000f; | |
2264 | break; | |
2265 | ||
2266 | default: | |
2267 | OMAP_BAD_REG(addr); | |
2268 | return; | |
2269 | } | |
2270 | } | |
2271 | ||
a4ebbd18 AK |
2272 | static const MemoryRegionOps omap_uwire_ops = { |
2273 | .read = omap_uwire_read, | |
2274 | .write = omap_uwire_write, | |
2275 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d951f6ff AZ |
2276 | }; |
2277 | ||
9596ebb7 | 2278 | static void omap_uwire_reset(struct omap_uwire_s *s) |
d951f6ff | 2279 | { |
66450b15 | 2280 | s->control = 0; |
d951f6ff AZ |
2281 | s->setup[0] = 0; |
2282 | s->setup[1] = 0; | |
2283 | s->setup[2] = 0; | |
2284 | s->setup[3] = 0; | |
2285 | s->setup[4] = 0; | |
2286 | } | |
2287 | ||
0919ac78 | 2288 | static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory, |
a8170e5e | 2289 | hwaddr base, |
0919ac78 PM |
2290 | qemu_irq txirq, qemu_irq rxirq, |
2291 | qemu_irq dma, | |
2292 | omap_clk clk) | |
d951f6ff | 2293 | { |
b45c03f5 | 2294 | struct omap_uwire_s *s = g_new0(struct omap_uwire_s, 1); |
d951f6ff | 2295 | |
0919ac78 PM |
2296 | s->txirq = txirq; |
2297 | s->rxirq = rxirq; | |
d951f6ff AZ |
2298 | s->txdrq = dma; |
2299 | omap_uwire_reset(s); | |
2300 | ||
2c9b15ca | 2301 | memory_region_init_io(&s->iomem, NULL, &omap_uwire_ops, s, "omap-uwire", 0x800); |
a4ebbd18 | 2302 | memory_region_add_subregion(system_memory, base, &s->iomem); |
d951f6ff AZ |
2303 | |
2304 | return s; | |
2305 | } | |
2306 | ||
2307 | void omap_uwire_attach(struct omap_uwire_s *s, | |
bc24a225 | 2308 | uWireSlave *slave, int chipselect) |
d951f6ff | 2309 | { |
827df9f3 AZ |
2310 | if (chipselect < 0 || chipselect > 3) { |
2311 | fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); | |
2312 | exit(-1); | |
2313 | } | |
d951f6ff AZ |
2314 | |
2315 | s->chip[chipselect] = slave; | |
2316 | } | |
2317 | ||
66450b15 | 2318 | /* Pseudonoise Pulse-Width Light Modulator */ |
8717d88a JR |
2319 | struct omap_pwl_s { |
2320 | MemoryRegion iomem; | |
2321 | uint8_t output; | |
2322 | uint8_t level; | |
2323 | uint8_t enable; | |
2324 | int clk; | |
2325 | }; | |
2326 | ||
2327 | static void omap_pwl_update(struct omap_pwl_s *s) | |
66450b15 | 2328 | { |
8717d88a | 2329 | int output = (s->clk && s->enable) ? s->level : 0; |
66450b15 | 2330 | |
8717d88a JR |
2331 | if (output != s->output) { |
2332 | s->output = output; | |
66450b15 AZ |
2333 | printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); |
2334 | } | |
2335 | } | |
2336 | ||
a8170e5e | 2337 | static uint64_t omap_pwl_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2338 | unsigned size) |
66450b15 | 2339 | { |
8717d88a | 2340 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
cf965d24 | 2341 | int offset = addr & OMAP_MPUI_REG_MASK; |
66450b15 | 2342 | |
a4ebbd18 AK |
2343 | if (size != 1) { |
2344 | return omap_badwidth_read8(opaque, addr); | |
2345 | } | |
2346 | ||
66450b15 AZ |
2347 | switch (offset) { |
2348 | case 0x00: /* PWL_LEVEL */ | |
8717d88a | 2349 | return s->level; |
66450b15 | 2350 | case 0x04: /* PWL_CTRL */ |
8717d88a | 2351 | return s->enable; |
66450b15 AZ |
2352 | } |
2353 | OMAP_BAD_REG(addr); | |
2354 | return 0; | |
2355 | } | |
2356 | ||
a8170e5e | 2357 | static void omap_pwl_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2358 | uint64_t value, unsigned size) |
66450b15 | 2359 | { |
8717d88a | 2360 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
cf965d24 | 2361 | int offset = addr & OMAP_MPUI_REG_MASK; |
66450b15 | 2362 | |
a4ebbd18 | 2363 | if (size != 1) { |
77a8257e SW |
2364 | omap_badwidth_write8(opaque, addr, value); |
2365 | return; | |
a4ebbd18 AK |
2366 | } |
2367 | ||
66450b15 AZ |
2368 | switch (offset) { |
2369 | case 0x00: /* PWL_LEVEL */ | |
8717d88a | 2370 | s->level = value; |
66450b15 AZ |
2371 | omap_pwl_update(s); |
2372 | break; | |
2373 | case 0x04: /* PWL_CTRL */ | |
8717d88a | 2374 | s->enable = value & 1; |
66450b15 AZ |
2375 | omap_pwl_update(s); |
2376 | break; | |
2377 | default: | |
2378 | OMAP_BAD_REG(addr); | |
2379 | return; | |
2380 | } | |
2381 | } | |
2382 | ||
a4ebbd18 AK |
2383 | static const MemoryRegionOps omap_pwl_ops = { |
2384 | .read = omap_pwl_read, | |
2385 | .write = omap_pwl_write, | |
2386 | .endianness = DEVICE_NATIVE_ENDIAN, | |
66450b15 AZ |
2387 | }; |
2388 | ||
8717d88a | 2389 | static void omap_pwl_reset(struct omap_pwl_s *s) |
66450b15 | 2390 | { |
8717d88a JR |
2391 | s->output = 0; |
2392 | s->level = 0; | |
2393 | s->enable = 0; | |
2394 | s->clk = 1; | |
66450b15 AZ |
2395 | omap_pwl_update(s); |
2396 | } | |
2397 | ||
2398 | static void omap_pwl_clk_update(void *opaque, int line, int on) | |
2399 | { | |
8717d88a | 2400 | struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; |
66450b15 | 2401 | |
8717d88a | 2402 | s->clk = on; |
66450b15 AZ |
2403 | omap_pwl_update(s); |
2404 | } | |
2405 | ||
8717d88a | 2406 | static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory, |
a8170e5e | 2407 | hwaddr base, |
8717d88a | 2408 | omap_clk clk) |
66450b15 | 2409 | { |
8717d88a JR |
2410 | struct omap_pwl_s *s = g_malloc0(sizeof(*s)); |
2411 | ||
66450b15 AZ |
2412 | omap_pwl_reset(s); |
2413 | ||
2c9b15ca | 2414 | memory_region_init_io(&s->iomem, NULL, &omap_pwl_ops, s, |
a4ebbd18 | 2415 | "omap-pwl", 0x800); |
8717d88a | 2416 | memory_region_add_subregion(system_memory, base, &s->iomem); |
66450b15 | 2417 | |
f3c7d038 | 2418 | omap_clk_adduser(clk, qemu_allocate_irq(omap_pwl_clk_update, s, 0)); |
8717d88a | 2419 | return s; |
66450b15 AZ |
2420 | } |
2421 | ||
f34c417b | 2422 | /* Pulse-Width Tone module */ |
03759534 JR |
2423 | struct omap_pwt_s { |
2424 | MemoryRegion iomem; | |
2425 | uint8_t frc; | |
2426 | uint8_t vrc; | |
2427 | uint8_t gcr; | |
2428 | omap_clk clk; | |
2429 | }; | |
2430 | ||
a8170e5e | 2431 | static uint64_t omap_pwt_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2432 | unsigned size) |
f34c417b | 2433 | { |
03759534 | 2434 | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
cf965d24 | 2435 | int offset = addr & OMAP_MPUI_REG_MASK; |
f34c417b | 2436 | |
a4ebbd18 AK |
2437 | if (size != 1) { |
2438 | return omap_badwidth_read8(opaque, addr); | |
2439 | } | |
2440 | ||
f34c417b AZ |
2441 | switch (offset) { |
2442 | case 0x00: /* FRC */ | |
03759534 | 2443 | return s->frc; |
f34c417b | 2444 | case 0x04: /* VCR */ |
03759534 | 2445 | return s->vrc; |
f34c417b | 2446 | case 0x08: /* GCR */ |
03759534 | 2447 | return s->gcr; |
f34c417b AZ |
2448 | } |
2449 | OMAP_BAD_REG(addr); | |
2450 | return 0; | |
2451 | } | |
2452 | ||
a8170e5e | 2453 | static void omap_pwt_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2454 | uint64_t value, unsigned size) |
f34c417b | 2455 | { |
03759534 | 2456 | struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; |
cf965d24 | 2457 | int offset = addr & OMAP_MPUI_REG_MASK; |
f34c417b | 2458 | |
a4ebbd18 | 2459 | if (size != 1) { |
77a8257e SW |
2460 | omap_badwidth_write8(opaque, addr, value); |
2461 | return; | |
a4ebbd18 AK |
2462 | } |
2463 | ||
f34c417b AZ |
2464 | switch (offset) { |
2465 | case 0x00: /* FRC */ | |
03759534 | 2466 | s->frc = value & 0x3f; |
f34c417b AZ |
2467 | break; |
2468 | case 0x04: /* VRC */ | |
03759534 | 2469 | if ((value ^ s->vrc) & 1) { |
f34c417b AZ |
2470 | if (value & 1) |
2471 | printf("%s: %iHz buzz on\n", __FUNCTION__, (int) | |
2472 | /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ | |
03759534 | 2473 | ((omap_clk_getrate(s->clk) >> 3) / |
f34c417b | 2474 | /* Pre-multiplexer divider */ |
03759534 | 2475 | ((s->gcr & 2) ? 1 : 154) / |
f34c417b AZ |
2476 | /* Octave multiplexer */ |
2477 | (2 << (value & 3)) * | |
2478 | /* 101/107 divider */ | |
2479 | ((value & (1 << 2)) ? 101 : 107) * | |
2480 | /* 49/55 divider */ | |
2481 | ((value & (1 << 3)) ? 49 : 55) * | |
2482 | /* 50/63 divider */ | |
2483 | ((value & (1 << 4)) ? 50 : 63) * | |
2484 | /* 80/127 divider */ | |
2485 | ((value & (1 << 5)) ? 80 : 127) / | |
2486 | (107 * 55 * 63 * 127))); | |
2487 | else | |
2488 | printf("%s: silence!\n", __FUNCTION__); | |
2489 | } | |
03759534 | 2490 | s->vrc = value & 0x7f; |
f34c417b AZ |
2491 | break; |
2492 | case 0x08: /* GCR */ | |
03759534 | 2493 | s->gcr = value & 3; |
f34c417b AZ |
2494 | break; |
2495 | default: | |
2496 | OMAP_BAD_REG(addr); | |
2497 | return; | |
2498 | } | |
2499 | } | |
2500 | ||
a4ebbd18 AK |
2501 | static const MemoryRegionOps omap_pwt_ops = { |
2502 | .read =omap_pwt_read, | |
2503 | .write = omap_pwt_write, | |
2504 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f34c417b AZ |
2505 | }; |
2506 | ||
03759534 | 2507 | static void omap_pwt_reset(struct omap_pwt_s *s) |
f34c417b | 2508 | { |
03759534 JR |
2509 | s->frc = 0; |
2510 | s->vrc = 0; | |
2511 | s->gcr = 0; | |
f34c417b AZ |
2512 | } |
2513 | ||
03759534 | 2514 | static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory, |
a8170e5e | 2515 | hwaddr base, |
03759534 | 2516 | omap_clk clk) |
f34c417b | 2517 | { |
03759534 JR |
2518 | struct omap_pwt_s *s = g_malloc0(sizeof(*s)); |
2519 | s->clk = clk; | |
f34c417b AZ |
2520 | omap_pwt_reset(s); |
2521 | ||
2c9b15ca | 2522 | memory_region_init_io(&s->iomem, NULL, &omap_pwt_ops, s, |
a4ebbd18 | 2523 | "omap-pwt", 0x800); |
03759534 JR |
2524 | memory_region_add_subregion(system_memory, base, &s->iomem); |
2525 | return s; | |
f34c417b AZ |
2526 | } |
2527 | ||
5c1c390f AZ |
2528 | /* Real-time Clock module */ |
2529 | struct omap_rtc_s { | |
a4ebbd18 | 2530 | MemoryRegion iomem; |
5c1c390f AZ |
2531 | qemu_irq irq; |
2532 | qemu_irq alarm; | |
2533 | QEMUTimer *clk; | |
2534 | ||
2535 | uint8_t interrupts; | |
2536 | uint8_t status; | |
2537 | int16_t comp_reg; | |
2538 | int running; | |
2539 | int pm_am; | |
2540 | int auto_comp; | |
2541 | int round; | |
5c1c390f AZ |
2542 | struct tm alarm_tm; |
2543 | time_t alarm_ti; | |
2544 | ||
2545 | struct tm current_tm; | |
2546 | time_t ti; | |
2547 | uint64_t tick; | |
2548 | }; | |
2549 | ||
2550 | static void omap_rtc_interrupts_update(struct omap_rtc_s *s) | |
2551 | { | |
106627d0 | 2552 | /* s->alarm is level-triggered */ |
5c1c390f AZ |
2553 | qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
2554 | } | |
2555 | ||
2556 | static void omap_rtc_alarm_update(struct omap_rtc_s *s) | |
2557 | { | |
0cd2df75 | 2558 | s->alarm_ti = mktimegm(&s->alarm_tm); |
5c1c390f AZ |
2559 | if (s->alarm_ti == -1) |
2560 | printf("%s: conversion failed\n", __FUNCTION__); | |
2561 | } | |
2562 | ||
a8170e5e | 2563 | static uint64_t omap_rtc_read(void *opaque, hwaddr addr, |
a4ebbd18 | 2564 | unsigned size) |
5c1c390f AZ |
2565 | { |
2566 | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | |
cf965d24 | 2567 | int offset = addr & OMAP_MPUI_REG_MASK; |
5c1c390f AZ |
2568 | uint8_t i; |
2569 | ||
a4ebbd18 AK |
2570 | if (size != 1) { |
2571 | return omap_badwidth_read8(opaque, addr); | |
2572 | } | |
2573 | ||
5c1c390f AZ |
2574 | switch (offset) { |
2575 | case 0x00: /* SECONDS_REG */ | |
abd0c6bd | 2576 | return to_bcd(s->current_tm.tm_sec); |
5c1c390f AZ |
2577 | |
2578 | case 0x04: /* MINUTES_REG */ | |
abd0c6bd | 2579 | return to_bcd(s->current_tm.tm_min); |
5c1c390f AZ |
2580 | |
2581 | case 0x08: /* HOURS_REG */ | |
2582 | if (s->pm_am) | |
2583 | return ((s->current_tm.tm_hour > 11) << 7) | | |
abd0c6bd | 2584 | to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
5c1c390f | 2585 | else |
abd0c6bd | 2586 | return to_bcd(s->current_tm.tm_hour); |
5c1c390f AZ |
2587 | |
2588 | case 0x0c: /* DAYS_REG */ | |
abd0c6bd | 2589 | return to_bcd(s->current_tm.tm_mday); |
5c1c390f AZ |
2590 | |
2591 | case 0x10: /* MONTHS_REG */ | |
abd0c6bd | 2592 | return to_bcd(s->current_tm.tm_mon + 1); |
5c1c390f AZ |
2593 | |
2594 | case 0x14: /* YEARS_REG */ | |
abd0c6bd | 2595 | return to_bcd(s->current_tm.tm_year % 100); |
5c1c390f AZ |
2596 | |
2597 | case 0x18: /* WEEK_REG */ | |
2598 | return s->current_tm.tm_wday; | |
2599 | ||
2600 | case 0x20: /* ALARM_SECONDS_REG */ | |
abd0c6bd | 2601 | return to_bcd(s->alarm_tm.tm_sec); |
5c1c390f AZ |
2602 | |
2603 | case 0x24: /* ALARM_MINUTES_REG */ | |
abd0c6bd | 2604 | return to_bcd(s->alarm_tm.tm_min); |
5c1c390f AZ |
2605 | |
2606 | case 0x28: /* ALARM_HOURS_REG */ | |
2607 | if (s->pm_am) | |
2608 | return ((s->alarm_tm.tm_hour > 11) << 7) | | |
abd0c6bd | 2609 | to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
5c1c390f | 2610 | else |
abd0c6bd | 2611 | return to_bcd(s->alarm_tm.tm_hour); |
5c1c390f AZ |
2612 | |
2613 | case 0x2c: /* ALARM_DAYS_REG */ | |
abd0c6bd | 2614 | return to_bcd(s->alarm_tm.tm_mday); |
5c1c390f AZ |
2615 | |
2616 | case 0x30: /* ALARM_MONTHS_REG */ | |
abd0c6bd | 2617 | return to_bcd(s->alarm_tm.tm_mon + 1); |
5c1c390f AZ |
2618 | |
2619 | case 0x34: /* ALARM_YEARS_REG */ | |
abd0c6bd | 2620 | return to_bcd(s->alarm_tm.tm_year % 100); |
5c1c390f AZ |
2621 | |
2622 | case 0x40: /* RTC_CTRL_REG */ | |
2623 | return (s->pm_am << 3) | (s->auto_comp << 2) | | |
2624 | (s->round << 1) | s->running; | |
2625 | ||
2626 | case 0x44: /* RTC_STATUS_REG */ | |
2627 | i = s->status; | |
2628 | s->status &= ~0x3d; | |
2629 | return i; | |
2630 | ||
2631 | case 0x48: /* RTC_INTERRUPTS_REG */ | |
2632 | return s->interrupts; | |
2633 | ||
2634 | case 0x4c: /* RTC_COMP_LSB_REG */ | |
2635 | return ((uint16_t) s->comp_reg) & 0xff; | |
2636 | ||
2637 | case 0x50: /* RTC_COMP_MSB_REG */ | |
2638 | return ((uint16_t) s->comp_reg) >> 8; | |
2639 | } | |
2640 | ||
2641 | OMAP_BAD_REG(addr); | |
2642 | return 0; | |
2643 | } | |
2644 | ||
a8170e5e | 2645 | static void omap_rtc_write(void *opaque, hwaddr addr, |
a4ebbd18 | 2646 | uint64_t value, unsigned size) |
5c1c390f AZ |
2647 | { |
2648 | struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | |
cf965d24 | 2649 | int offset = addr & OMAP_MPUI_REG_MASK; |
5c1c390f AZ |
2650 | struct tm new_tm; |
2651 | time_t ti[2]; | |
2652 | ||
a4ebbd18 | 2653 | if (size != 1) { |
77a8257e SW |
2654 | omap_badwidth_write8(opaque, addr, value); |
2655 | return; | |
a4ebbd18 AK |
2656 | } |
2657 | ||
5c1c390f AZ |
2658 | switch (offset) { |
2659 | case 0x00: /* SECONDS_REG */ | |
eb38c52c | 2660 | #ifdef ALMDEBUG |
5c1c390f AZ |
2661 | printf("RTC SEC_REG <-- %02x\n", value); |
2662 | #endif | |
2663 | s->ti -= s->current_tm.tm_sec; | |
abd0c6bd | 2664 | s->ti += from_bcd(value); |
5c1c390f AZ |
2665 | return; |
2666 | ||
2667 | case 0x04: /* MINUTES_REG */ | |
eb38c52c | 2668 | #ifdef ALMDEBUG |
5c1c390f AZ |
2669 | printf("RTC MIN_REG <-- %02x\n", value); |
2670 | #endif | |
2671 | s->ti -= s->current_tm.tm_min * 60; | |
abd0c6bd | 2672 | s->ti += from_bcd(value) * 60; |
5c1c390f AZ |
2673 | return; |
2674 | ||
2675 | case 0x08: /* HOURS_REG */ | |
eb38c52c | 2676 | #ifdef ALMDEBUG |
5c1c390f AZ |
2677 | printf("RTC HRS_REG <-- %02x\n", value); |
2678 | #endif | |
2679 | s->ti -= s->current_tm.tm_hour * 3600; | |
2680 | if (s->pm_am) { | |
abd0c6bd | 2681 | s->ti += (from_bcd(value & 0x3f) & 12) * 3600; |
5c1c390f AZ |
2682 | s->ti += ((value >> 7) & 1) * 43200; |
2683 | } else | |
abd0c6bd | 2684 | s->ti += from_bcd(value & 0x3f) * 3600; |
5c1c390f AZ |
2685 | return; |
2686 | ||
2687 | case 0x0c: /* DAYS_REG */ | |
eb38c52c | 2688 | #ifdef ALMDEBUG |
5c1c390f AZ |
2689 | printf("RTC DAY_REG <-- %02x\n", value); |
2690 | #endif | |
2691 | s->ti -= s->current_tm.tm_mday * 86400; | |
abd0c6bd | 2692 | s->ti += from_bcd(value) * 86400; |
5c1c390f AZ |
2693 | return; |
2694 | ||
2695 | case 0x10: /* MONTHS_REG */ | |
eb38c52c | 2696 | #ifdef ALMDEBUG |
5c1c390f AZ |
2697 | printf("RTC MTH_REG <-- %02x\n", value); |
2698 | #endif | |
2699 | memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); | |
abd0c6bd | 2700 | new_tm.tm_mon = from_bcd(value); |
0cd2df75 AJ |
2701 | ti[0] = mktimegm(&s->current_tm); |
2702 | ti[1] = mktimegm(&new_tm); | |
5c1c390f AZ |
2703 | |
2704 | if (ti[0] != -1 && ti[1] != -1) { | |
2705 | s->ti -= ti[0]; | |
2706 | s->ti += ti[1]; | |
2707 | } else { | |
2708 | /* A less accurate version */ | |
2709 | s->ti -= s->current_tm.tm_mon * 2592000; | |
abd0c6bd | 2710 | s->ti += from_bcd(value) * 2592000; |
5c1c390f AZ |
2711 | } |
2712 | return; | |
2713 | ||
2714 | case 0x14: /* YEARS_REG */ | |
eb38c52c | 2715 | #ifdef ALMDEBUG |
5c1c390f AZ |
2716 | printf("RTC YRS_REG <-- %02x\n", value); |
2717 | #endif | |
2718 | memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); | |
abd0c6bd | 2719 | new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100); |
0cd2df75 AJ |
2720 | ti[0] = mktimegm(&s->current_tm); |
2721 | ti[1] = mktimegm(&new_tm); | |
5c1c390f AZ |
2722 | |
2723 | if (ti[0] != -1 && ti[1] != -1) { | |
2724 | s->ti -= ti[0]; | |
2725 | s->ti += ti[1]; | |
2726 | } else { | |
2727 | /* A less accurate version */ | |
7e7e5858 PM |
2728 | s->ti -= (time_t)(s->current_tm.tm_year % 100) * 31536000; |
2729 | s->ti += (time_t)from_bcd(value) * 31536000; | |
5c1c390f AZ |
2730 | } |
2731 | return; | |
2732 | ||
2733 | case 0x18: /* WEEK_REG */ | |
2734 | return; /* Ignored */ | |
2735 | ||
2736 | case 0x20: /* ALARM_SECONDS_REG */ | |
eb38c52c | 2737 | #ifdef ALMDEBUG |
5c1c390f AZ |
2738 | printf("ALM SEC_REG <-- %02x\n", value); |
2739 | #endif | |
abd0c6bd | 2740 | s->alarm_tm.tm_sec = from_bcd(value); |
5c1c390f AZ |
2741 | omap_rtc_alarm_update(s); |
2742 | return; | |
2743 | ||
2744 | case 0x24: /* ALARM_MINUTES_REG */ | |
eb38c52c | 2745 | #ifdef ALMDEBUG |
5c1c390f AZ |
2746 | printf("ALM MIN_REG <-- %02x\n", value); |
2747 | #endif | |
abd0c6bd | 2748 | s->alarm_tm.tm_min = from_bcd(value); |
5c1c390f AZ |
2749 | omap_rtc_alarm_update(s); |
2750 | return; | |
2751 | ||
2752 | case 0x28: /* ALARM_HOURS_REG */ | |
eb38c52c | 2753 | #ifdef ALMDEBUG |
5c1c390f AZ |
2754 | printf("ALM HRS_REG <-- %02x\n", value); |
2755 | #endif | |
2756 | if (s->pm_am) | |
2757 | s->alarm_tm.tm_hour = | |
abd0c6bd | 2758 | ((from_bcd(value & 0x3f)) % 12) + |
5c1c390f AZ |
2759 | ((value >> 7) & 1) * 12; |
2760 | else | |
abd0c6bd | 2761 | s->alarm_tm.tm_hour = from_bcd(value); |
5c1c390f AZ |
2762 | omap_rtc_alarm_update(s); |
2763 | return; | |
2764 | ||
2765 | case 0x2c: /* ALARM_DAYS_REG */ | |
eb38c52c | 2766 | #ifdef ALMDEBUG |
5c1c390f AZ |
2767 | printf("ALM DAY_REG <-- %02x\n", value); |
2768 | #endif | |
abd0c6bd | 2769 | s->alarm_tm.tm_mday = from_bcd(value); |
5c1c390f AZ |
2770 | omap_rtc_alarm_update(s); |
2771 | return; | |
2772 | ||
2773 | case 0x30: /* ALARM_MONTHS_REG */ | |
eb38c52c | 2774 | #ifdef ALMDEBUG |
5c1c390f AZ |
2775 | printf("ALM MON_REG <-- %02x\n", value); |
2776 | #endif | |
abd0c6bd | 2777 | s->alarm_tm.tm_mon = from_bcd(value); |
5c1c390f AZ |
2778 | omap_rtc_alarm_update(s); |
2779 | return; | |
2780 | ||
2781 | case 0x34: /* ALARM_YEARS_REG */ | |
eb38c52c | 2782 | #ifdef ALMDEBUG |
5c1c390f AZ |
2783 | printf("ALM YRS_REG <-- %02x\n", value); |
2784 | #endif | |
abd0c6bd | 2785 | s->alarm_tm.tm_year = from_bcd(value); |
5c1c390f AZ |
2786 | omap_rtc_alarm_update(s); |
2787 | return; | |
2788 | ||
2789 | case 0x40: /* RTC_CTRL_REG */ | |
eb38c52c | 2790 | #ifdef ALMDEBUG |
5c1c390f AZ |
2791 | printf("RTC CONTROL <-- %02x\n", value); |
2792 | #endif | |
2793 | s->pm_am = (value >> 3) & 1; | |
2794 | s->auto_comp = (value >> 2) & 1; | |
2795 | s->round = (value >> 1) & 1; | |
2796 | s->running = value & 1; | |
2797 | s->status &= 0xfd; | |
2798 | s->status |= s->running << 1; | |
2799 | return; | |
2800 | ||
2801 | case 0x44: /* RTC_STATUS_REG */ | |
eb38c52c | 2802 | #ifdef ALMDEBUG |
5c1c390f AZ |
2803 | printf("RTC STATUSL <-- %02x\n", value); |
2804 | #endif | |
2805 | s->status &= ~((value & 0xc0) ^ 0x80); | |
2806 | omap_rtc_interrupts_update(s); | |
2807 | return; | |
2808 | ||
2809 | case 0x48: /* RTC_INTERRUPTS_REG */ | |
eb38c52c | 2810 | #ifdef ALMDEBUG |
5c1c390f AZ |
2811 | printf("RTC INTRS <-- %02x\n", value); |
2812 | #endif | |
2813 | s->interrupts = value; | |
2814 | return; | |
2815 | ||
2816 | case 0x4c: /* RTC_COMP_LSB_REG */ | |
eb38c52c | 2817 | #ifdef ALMDEBUG |
5c1c390f AZ |
2818 | printf("RTC COMPLSB <-- %02x\n", value); |
2819 | #endif | |
2820 | s->comp_reg &= 0xff00; | |
2821 | s->comp_reg |= 0x00ff & value; | |
2822 | return; | |
2823 | ||
2824 | case 0x50: /* RTC_COMP_MSB_REG */ | |
eb38c52c | 2825 | #ifdef ALMDEBUG |
5c1c390f AZ |
2826 | printf("RTC COMPMSB <-- %02x\n", value); |
2827 | #endif | |
2828 | s->comp_reg &= 0x00ff; | |
2829 | s->comp_reg |= 0xff00 & (value << 8); | |
2830 | return; | |
2831 | ||
2832 | default: | |
2833 | OMAP_BAD_REG(addr); | |
2834 | return; | |
2835 | } | |
2836 | } | |
2837 | ||
a4ebbd18 AK |
2838 | static const MemoryRegionOps omap_rtc_ops = { |
2839 | .read = omap_rtc_read, | |
2840 | .write = omap_rtc_write, | |
2841 | .endianness = DEVICE_NATIVE_ENDIAN, | |
5c1c390f AZ |
2842 | }; |
2843 | ||
2844 | static void omap_rtc_tick(void *opaque) | |
2845 | { | |
2846 | struct omap_rtc_s *s = opaque; | |
2847 | ||
2848 | if (s->round) { | |
2849 | /* Round to nearest full minute. */ | |
2850 | if (s->current_tm.tm_sec < 30) | |
2851 | s->ti -= s->current_tm.tm_sec; | |
2852 | else | |
2853 | s->ti += 60 - s->current_tm.tm_sec; | |
2854 | ||
2855 | s->round = 0; | |
2856 | } | |
2857 | ||
eb7ff6fb | 2858 | localtime_r(&s->ti, &s->current_tm); |
5c1c390f AZ |
2859 | |
2860 | if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { | |
2861 | s->status |= 0x40; | |
2862 | omap_rtc_interrupts_update(s); | |
2863 | } | |
2864 | ||
2865 | if (s->interrupts & 0x04) | |
2866 | switch (s->interrupts & 3) { | |
2867 | case 0: | |
2868 | s->status |= 0x04; | |
106627d0 | 2869 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2870 | break; |
2871 | case 1: | |
2872 | if (s->current_tm.tm_sec) | |
2873 | break; | |
2874 | s->status |= 0x08; | |
106627d0 | 2875 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2876 | break; |
2877 | case 2: | |
2878 | if (s->current_tm.tm_sec || s->current_tm.tm_min) | |
2879 | break; | |
2880 | s->status |= 0x10; | |
106627d0 | 2881 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2882 | break; |
2883 | case 3: | |
2884 | if (s->current_tm.tm_sec || | |
2885 | s->current_tm.tm_min || s->current_tm.tm_hour) | |
2886 | break; | |
2887 | s->status |= 0x20; | |
106627d0 | 2888 | qemu_irq_pulse(s->irq); |
5c1c390f AZ |
2889 | break; |
2890 | } | |
2891 | ||
2892 | /* Move on */ | |
2893 | if (s->running) | |
2894 | s->ti ++; | |
2895 | s->tick += 1000; | |
2896 | ||
2897 | /* | |
2898 | * Every full hour add a rough approximation of the compensation | |
2899 | * register to the 32kHz Timer (which drives the RTC) value. | |
2900 | */ | |
2901 | if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) | |
2902 | s->tick += s->comp_reg * 1000 / 32768; | |
2903 | ||
bc72ad67 | 2904 | timer_mod(s->clk, s->tick); |
5c1c390f AZ |
2905 | } |
2906 | ||
9596ebb7 | 2907 | static void omap_rtc_reset(struct omap_rtc_s *s) |
5c1c390f | 2908 | { |
f6503059 AZ |
2909 | struct tm tm; |
2910 | ||
5c1c390f AZ |
2911 | s->interrupts = 0; |
2912 | s->comp_reg = 0; | |
2913 | s->running = 0; | |
2914 | s->pm_am = 0; | |
2915 | s->auto_comp = 0; | |
2916 | s->round = 0; | |
884f17c2 | 2917 | s->tick = qemu_clock_get_ms(rtc_clock); |
5c1c390f AZ |
2918 | memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
2919 | s->alarm_tm.tm_mday = 0x01; | |
2920 | s->status = 1 << 7; | |
f6503059 | 2921 | qemu_get_timedate(&tm, 0); |
0cd2df75 | 2922 | s->ti = mktimegm(&tm); |
5c1c390f AZ |
2923 | |
2924 | omap_rtc_alarm_update(s); | |
2925 | omap_rtc_tick(s); | |
2926 | } | |
2927 | ||
a4ebbd18 | 2928 | static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory, |
a8170e5e | 2929 | hwaddr base, |
0919ac78 PM |
2930 | qemu_irq timerirq, qemu_irq alarmirq, |
2931 | omap_clk clk) | |
5c1c390f | 2932 | { |
b45c03f5 | 2933 | struct omap_rtc_s *s = g_new0(struct omap_rtc_s, 1); |
5c1c390f | 2934 | |
0919ac78 PM |
2935 | s->irq = timerirq; |
2936 | s->alarm = alarmirq; | |
884f17c2 | 2937 | s->clk = timer_new_ms(rtc_clock, omap_rtc_tick, s); |
5c1c390f AZ |
2938 | |
2939 | omap_rtc_reset(s); | |
2940 | ||
2c9b15ca | 2941 | memory_region_init_io(&s->iomem, NULL, &omap_rtc_ops, s, |
a4ebbd18 AK |
2942 | "omap-rtc", 0x800); |
2943 | memory_region_add_subregion(system_memory, base, &s->iomem); | |
5c1c390f AZ |
2944 | |
2945 | return s; | |
2946 | } | |
2947 | ||
d8f699cb AZ |
2948 | /* Multi-channel Buffered Serial Port interfaces */ |
2949 | struct omap_mcbsp_s { | |
a4ebbd18 | 2950 | MemoryRegion iomem; |
d8f699cb AZ |
2951 | qemu_irq txirq; |
2952 | qemu_irq rxirq; | |
2953 | qemu_irq txdrq; | |
2954 | qemu_irq rxdrq; | |
2955 | ||
2956 | uint16_t spcr[2]; | |
2957 | uint16_t rcr[2]; | |
2958 | uint16_t xcr[2]; | |
2959 | uint16_t srgr[2]; | |
2960 | uint16_t mcr[2]; | |
2961 | uint16_t pcr; | |
2962 | uint16_t rcer[8]; | |
2963 | uint16_t xcer[8]; | |
2964 | int tx_rate; | |
2965 | int rx_rate; | |
2966 | int tx_req; | |
73560bc8 | 2967 | int rx_req; |
d8f699cb | 2968 | |
bc24a225 | 2969 | I2SCodec *codec; |
73560bc8 AZ |
2970 | QEMUTimer *source_timer; |
2971 | QEMUTimer *sink_timer; | |
d8f699cb AZ |
2972 | }; |
2973 | ||
2974 | static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) | |
2975 | { | |
2976 | int irq; | |
2977 | ||
2978 | switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ | |
2979 | case 0: | |
2980 | irq = (s->spcr[0] >> 1) & 1; /* RRDY */ | |
2981 | break; | |
2982 | case 3: | |
2983 | irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ | |
2984 | break; | |
2985 | default: | |
2986 | irq = 0; | |
2987 | break; | |
2988 | } | |
2989 | ||
106627d0 AZ |
2990 | if (irq) |
2991 | qemu_irq_pulse(s->rxirq); | |
d8f699cb AZ |
2992 | |
2993 | switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ | |
2994 | case 0: | |
2995 | irq = (s->spcr[1] >> 1) & 1; /* XRDY */ | |
2996 | break; | |
2997 | case 3: | |
2998 | irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ | |
2999 | break; | |
3000 | default: | |
3001 | irq = 0; | |
3002 | break; | |
3003 | } | |
3004 | ||
106627d0 AZ |
3005 | if (irq) |
3006 | qemu_irq_pulse(s->txirq); | |
d8f699cb AZ |
3007 | } |
3008 | ||
73560bc8 | 3009 | static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
d8f699cb | 3010 | { |
73560bc8 AZ |
3011 | if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
3012 | s->spcr[0] |= 1 << 2; /* RFULL */ | |
3013 | s->spcr[0] |= 1 << 1; /* RRDY */ | |
3014 | qemu_irq_raise(s->rxdrq); | |
3015 | omap_mcbsp_intr_update(s); | |
d8f699cb AZ |
3016 | } |
3017 | ||
73560bc8 | 3018 | static void omap_mcbsp_source_tick(void *opaque) |
d8f699cb | 3019 | { |
73560bc8 AZ |
3020 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3021 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | |
3022 | ||
3023 | if (!s->rx_rate) | |
d8f699cb | 3024 | return; |
73560bc8 AZ |
3025 | if (s->rx_req) |
3026 | printf("%s: Rx FIFO overrun\n", __FUNCTION__); | |
d8f699cb | 3027 | |
73560bc8 | 3028 | s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
d8f699cb | 3029 | |
73560bc8 | 3030 | omap_mcbsp_rx_newdata(s); |
bc72ad67 | 3031 | timer_mod(s->source_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
6ee093c9 | 3032 | get_ticks_per_sec()); |
d8f699cb AZ |
3033 | } |
3034 | ||
3035 | static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) | |
3036 | { | |
73560bc8 AZ |
3037 | if (!s->codec || !s->codec->rts) |
3038 | omap_mcbsp_source_tick(s); | |
3039 | else if (s->codec->in.len) { | |
3040 | s->rx_req = s->codec->in.len; | |
3041 | omap_mcbsp_rx_newdata(s); | |
d8f699cb | 3042 | } |
d8f699cb AZ |
3043 | } |
3044 | ||
3045 | static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) | |
73560bc8 | 3046 | { |
bc72ad67 | 3047 | timer_del(s->source_timer); |
73560bc8 AZ |
3048 | } |
3049 | ||
3050 | static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) | |
d8f699cb AZ |
3051 | { |
3052 | s->spcr[0] &= ~(1 << 1); /* RRDY */ | |
3053 | qemu_irq_lower(s->rxdrq); | |
3054 | omap_mcbsp_intr_update(s); | |
3055 | } | |
3056 | ||
73560bc8 AZ |
3057 | static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
3058 | { | |
3059 | s->spcr[1] |= 1 << 1; /* XRDY */ | |
3060 | qemu_irq_raise(s->txdrq); | |
3061 | omap_mcbsp_intr_update(s); | |
3062 | } | |
3063 | ||
3064 | static void omap_mcbsp_sink_tick(void *opaque) | |
d8f699cb | 3065 | { |
73560bc8 AZ |
3066 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
3067 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | |
3068 | ||
3069 | if (!s->tx_rate) | |
d8f699cb | 3070 | return; |
73560bc8 AZ |
3071 | if (s->tx_req) |
3072 | printf("%s: Tx FIFO underrun\n", __FUNCTION__); | |
3073 | ||
3074 | s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; | |
3075 | ||
3076 | omap_mcbsp_tx_newdata(s); | |
bc72ad67 | 3077 | timer_mod(s->sink_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
6ee093c9 | 3078 | get_ticks_per_sec()); |
73560bc8 AZ |
3079 | } |
3080 | ||
3081 | static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) | |
3082 | { | |
3083 | if (!s->codec || !s->codec->cts) | |
3084 | omap_mcbsp_sink_tick(s); | |
3085 | else if (s->codec->out.size) { | |
3086 | s->tx_req = s->codec->out.size; | |
3087 | omap_mcbsp_tx_newdata(s); | |
3088 | } | |
3089 | } | |
3090 | ||
3091 | static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) | |
3092 | { | |
3093 | s->spcr[1] &= ~(1 << 1); /* XRDY */ | |
3094 | qemu_irq_lower(s->txdrq); | |
3095 | omap_mcbsp_intr_update(s); | |
3096 | if (s->codec && s->codec->cts) | |
3097 | s->codec->tx_swallow(s->codec->opaque); | |
d8f699cb AZ |
3098 | } |
3099 | ||
3100 | static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) | |
3101 | { | |
73560bc8 AZ |
3102 | s->tx_req = 0; |
3103 | omap_mcbsp_tx_done(s); | |
bc72ad67 | 3104 | timer_del(s->sink_timer); |
73560bc8 AZ |
3105 | } |
3106 | ||
3107 | static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) | |
3108 | { | |
3109 | int prev_rx_rate, prev_tx_rate; | |
3110 | int rx_rate = 0, tx_rate = 0; | |
3111 | int cpu_rate = 1500000; /* XXX */ | |
3112 | ||
3113 | /* TODO: check CLKSTP bit */ | |
3114 | if (s->spcr[1] & (1 << 6)) { /* GRST */ | |
3115 | if (s->spcr[0] & (1 << 0)) { /* RRST */ | |
3116 | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ | |
3117 | (s->pcr & (1 << 8))) { /* CLKRM */ | |
3118 | if (~s->pcr & (1 << 7)) /* SCLKME */ | |
3119 | rx_rate = cpu_rate / | |
3120 | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ | |
3121 | } else | |
3122 | if (s->codec) | |
3123 | rx_rate = s->codec->rx_rate; | |
3124 | } | |
3125 | ||
3126 | if (s->spcr[1] & (1 << 0)) { /* XRST */ | |
3127 | if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ | |
3128 | (s->pcr & (1 << 9))) { /* CLKXM */ | |
3129 | if (~s->pcr & (1 << 7)) /* SCLKME */ | |
3130 | tx_rate = cpu_rate / | |
3131 | ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ | |
3132 | } else | |
3133 | if (s->codec) | |
3134 | tx_rate = s->codec->tx_rate; | |
3135 | } | |
3136 | } | |
3137 | prev_tx_rate = s->tx_rate; | |
3138 | prev_rx_rate = s->rx_rate; | |
3139 | s->tx_rate = tx_rate; | |
3140 | s->rx_rate = rx_rate; | |
3141 | ||
3142 | if (s->codec) | |
3143 | s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); | |
3144 | ||
3145 | if (!prev_tx_rate && tx_rate) | |
3146 | omap_mcbsp_tx_start(s); | |
3147 | else if (s->tx_rate && !tx_rate) | |
3148 | omap_mcbsp_tx_stop(s); | |
3149 | ||
3150 | if (!prev_rx_rate && rx_rate) | |
3151 | omap_mcbsp_rx_start(s); | |
3152 | else if (prev_tx_rate && !tx_rate) | |
3153 | omap_mcbsp_rx_stop(s); | |
d8f699cb AZ |
3154 | } |
3155 | ||
a8170e5e | 3156 | static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, |
a4ebbd18 | 3157 | unsigned size) |
d8f699cb AZ |
3158 | { |
3159 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3160 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3161 | uint16_t ret; | |
3162 | ||
a4ebbd18 AK |
3163 | if (size != 2) { |
3164 | return omap_badwidth_read16(opaque, addr); | |
3165 | } | |
3166 | ||
d8f699cb AZ |
3167 | switch (offset) { |
3168 | case 0x00: /* DRR2 */ | |
3169 | if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ | |
3170 | return 0x0000; | |
3171 | /* Fall through. */ | |
3172 | case 0x02: /* DRR1 */ | |
73560bc8 | 3173 | if (s->rx_req < 2) { |
d8f699cb | 3174 | printf("%s: Rx FIFO underrun\n", __FUNCTION__); |
73560bc8 | 3175 | omap_mcbsp_rx_done(s); |
d8f699cb | 3176 | } else { |
73560bc8 AZ |
3177 | s->tx_req -= 2; |
3178 | if (s->codec && s->codec->in.len >= 2) { | |
3179 | ret = s->codec->in.fifo[s->codec->in.start ++] << 8; | |
3180 | ret |= s->codec->in.fifo[s->codec->in.start ++]; | |
3181 | s->codec->in.len -= 2; | |
3182 | } else | |
3183 | ret = 0x0000; | |
3184 | if (!s->tx_req) | |
3185 | omap_mcbsp_rx_done(s); | |
d8f699cb AZ |
3186 | return ret; |
3187 | } | |
3188 | return 0x0000; | |
3189 | ||
3190 | case 0x04: /* DXR2 */ | |
3191 | case 0x06: /* DXR1 */ | |
3192 | return 0x0000; | |
3193 | ||
3194 | case 0x08: /* SPCR2 */ | |
3195 | return s->spcr[1]; | |
3196 | case 0x0a: /* SPCR1 */ | |
3197 | return s->spcr[0]; | |
3198 | case 0x0c: /* RCR2 */ | |
3199 | return s->rcr[1]; | |
3200 | case 0x0e: /* RCR1 */ | |
3201 | return s->rcr[0]; | |
3202 | case 0x10: /* XCR2 */ | |
3203 | return s->xcr[1]; | |
3204 | case 0x12: /* XCR1 */ | |
3205 | return s->xcr[0]; | |
3206 | case 0x14: /* SRGR2 */ | |
3207 | return s->srgr[1]; | |
3208 | case 0x16: /* SRGR1 */ | |
3209 | return s->srgr[0]; | |
3210 | case 0x18: /* MCR2 */ | |
3211 | return s->mcr[1]; | |
3212 | case 0x1a: /* MCR1 */ | |
3213 | return s->mcr[0]; | |
3214 | case 0x1c: /* RCERA */ | |
3215 | return s->rcer[0]; | |
3216 | case 0x1e: /* RCERB */ | |
3217 | return s->rcer[1]; | |
3218 | case 0x20: /* XCERA */ | |
3219 | return s->xcer[0]; | |
3220 | case 0x22: /* XCERB */ | |
3221 | return s->xcer[1]; | |
3222 | case 0x24: /* PCR0 */ | |
3223 | return s->pcr; | |
3224 | case 0x26: /* RCERC */ | |
3225 | return s->rcer[2]; | |
3226 | case 0x28: /* RCERD */ | |
3227 | return s->rcer[3]; | |
3228 | case 0x2a: /* XCERC */ | |
3229 | return s->xcer[2]; | |
3230 | case 0x2c: /* XCERD */ | |
3231 | return s->xcer[3]; | |
3232 | case 0x2e: /* RCERE */ | |
3233 | return s->rcer[4]; | |
3234 | case 0x30: /* RCERF */ | |
3235 | return s->rcer[5]; | |
3236 | case 0x32: /* XCERE */ | |
3237 | return s->xcer[4]; | |
3238 | case 0x34: /* XCERF */ | |
3239 | return s->xcer[5]; | |
3240 | case 0x36: /* RCERG */ | |
3241 | return s->rcer[6]; | |
3242 | case 0x38: /* RCERH */ | |
3243 | return s->rcer[7]; | |
3244 | case 0x3a: /* XCERG */ | |
3245 | return s->xcer[6]; | |
3246 | case 0x3c: /* XCERH */ | |
3247 | return s->xcer[7]; | |
3248 | } | |
3249 | ||
3250 | OMAP_BAD_REG(addr); | |
3251 | return 0; | |
3252 | } | |
3253 | ||
a8170e5e | 3254 | static void omap_mcbsp_writeh(void *opaque, hwaddr addr, |
d8f699cb AZ |
3255 | uint32_t value) |
3256 | { | |
3257 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3258 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3259 | ||
3260 | switch (offset) { | |
3261 | case 0x00: /* DRR2 */ | |
3262 | case 0x02: /* DRR1 */ | |
3263 | OMAP_RO_REG(addr); | |
3264 | return; | |
3265 | ||
3266 | case 0x04: /* DXR2 */ | |
3267 | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ | |
3268 | return; | |
3269 | /* Fall through. */ | |
3270 | case 0x06: /* DXR1 */ | |
73560bc8 AZ |
3271 | if (s->tx_req > 1) { |
3272 | s->tx_req -= 2; | |
3273 | if (s->codec && s->codec->cts) { | |
d8f699cb AZ |
3274 | s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
3275 | s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; | |
d8f699cb | 3276 | } |
73560bc8 AZ |
3277 | if (s->tx_req < 2) |
3278 | omap_mcbsp_tx_done(s); | |
d8f699cb AZ |
3279 | } else |
3280 | printf("%s: Tx FIFO overrun\n", __FUNCTION__); | |
3281 | return; | |
3282 | ||
3283 | case 0x08: /* SPCR2 */ | |
3284 | s->spcr[1] &= 0x0002; | |
3285 | s->spcr[1] |= 0x03f9 & value; | |
3286 | s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ | |
73560bc8 | 3287 | if (~value & 1) /* XRST */ |
d8f699cb | 3288 | s->spcr[1] &= ~6; |
d8f699cb AZ |
3289 | omap_mcbsp_req_update(s); |
3290 | return; | |
3291 | case 0x0a: /* SPCR1 */ | |
3292 | s->spcr[0] &= 0x0006; | |
3293 | s->spcr[0] |= 0xf8f9 & value; | |
3294 | if (value & (1 << 15)) /* DLB */ | |
3295 | printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); | |
3296 | if (~value & 1) { /* RRST */ | |
3297 | s->spcr[0] &= ~6; | |
73560bc8 AZ |
3298 | s->rx_req = 0; |
3299 | omap_mcbsp_rx_done(s); | |
d8f699cb | 3300 | } |
d8f699cb AZ |
3301 | omap_mcbsp_req_update(s); |
3302 | return; | |
3303 | ||
3304 | case 0x0c: /* RCR2 */ | |
3305 | s->rcr[1] = value & 0xffff; | |
3306 | return; | |
3307 | case 0x0e: /* RCR1 */ | |
3308 | s->rcr[0] = value & 0x7fe0; | |
3309 | return; | |
3310 | case 0x10: /* XCR2 */ | |
3311 | s->xcr[1] = value & 0xffff; | |
3312 | return; | |
3313 | case 0x12: /* XCR1 */ | |
3314 | s->xcr[0] = value & 0x7fe0; | |
3315 | return; | |
3316 | case 0x14: /* SRGR2 */ | |
3317 | s->srgr[1] = value & 0xffff; | |
73560bc8 | 3318 | omap_mcbsp_req_update(s); |
d8f699cb AZ |
3319 | return; |
3320 | case 0x16: /* SRGR1 */ | |
3321 | s->srgr[0] = value & 0xffff; | |
73560bc8 | 3322 | omap_mcbsp_req_update(s); |
d8f699cb AZ |
3323 | return; |
3324 | case 0x18: /* MCR2 */ | |
3325 | s->mcr[1] = value & 0x03e3; | |
3326 | if (value & 3) /* XMCM */ | |
3327 | printf("%s: Tx channel selection mode enable attempt\n", | |
3328 | __FUNCTION__); | |
3329 | return; | |
3330 | case 0x1a: /* MCR1 */ | |
3331 | s->mcr[0] = value & 0x03e1; | |
3332 | if (value & 1) /* RMCM */ | |
3333 | printf("%s: Rx channel selection mode enable attempt\n", | |
3334 | __FUNCTION__); | |
3335 | return; | |
3336 | case 0x1c: /* RCERA */ | |
3337 | s->rcer[0] = value & 0xffff; | |
3338 | return; | |
3339 | case 0x1e: /* RCERB */ | |
3340 | s->rcer[1] = value & 0xffff; | |
3341 | return; | |
3342 | case 0x20: /* XCERA */ | |
3343 | s->xcer[0] = value & 0xffff; | |
3344 | return; | |
3345 | case 0x22: /* XCERB */ | |
3346 | s->xcer[1] = value & 0xffff; | |
3347 | return; | |
3348 | case 0x24: /* PCR0 */ | |
3349 | s->pcr = value & 0x7faf; | |
3350 | return; | |
3351 | case 0x26: /* RCERC */ | |
3352 | s->rcer[2] = value & 0xffff; | |
3353 | return; | |
3354 | case 0x28: /* RCERD */ | |
3355 | s->rcer[3] = value & 0xffff; | |
3356 | return; | |
3357 | case 0x2a: /* XCERC */ | |
3358 | s->xcer[2] = value & 0xffff; | |
3359 | return; | |
3360 | case 0x2c: /* XCERD */ | |
3361 | s->xcer[3] = value & 0xffff; | |
3362 | return; | |
3363 | case 0x2e: /* RCERE */ | |
3364 | s->rcer[4] = value & 0xffff; | |
3365 | return; | |
3366 | case 0x30: /* RCERF */ | |
3367 | s->rcer[5] = value & 0xffff; | |
3368 | return; | |
3369 | case 0x32: /* XCERE */ | |
3370 | s->xcer[4] = value & 0xffff; | |
3371 | return; | |
3372 | case 0x34: /* XCERF */ | |
3373 | s->xcer[5] = value & 0xffff; | |
3374 | return; | |
3375 | case 0x36: /* RCERG */ | |
3376 | s->rcer[6] = value & 0xffff; | |
3377 | return; | |
3378 | case 0x38: /* RCERH */ | |
3379 | s->rcer[7] = value & 0xffff; | |
3380 | return; | |
3381 | case 0x3a: /* XCERG */ | |
3382 | s->xcer[6] = value & 0xffff; | |
3383 | return; | |
3384 | case 0x3c: /* XCERH */ | |
3385 | s->xcer[7] = value & 0xffff; | |
3386 | return; | |
3387 | } | |
3388 | ||
3389 | OMAP_BAD_REG(addr); | |
3390 | } | |
3391 | ||
a8170e5e | 3392 | static void omap_mcbsp_writew(void *opaque, hwaddr addr, |
73560bc8 AZ |
3393 | uint32_t value) |
3394 | { | |
3395 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3396 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3397 | ||
3398 | if (offset == 0x04) { /* DXR */ | |
3399 | if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ | |
3400 | return; | |
3401 | if (s->tx_req > 3) { | |
3402 | s->tx_req -= 4; | |
3403 | if (s->codec && s->codec->cts) { | |
3404 | s->codec->out.fifo[s->codec->out.len ++] = | |
3405 | (value >> 24) & 0xff; | |
3406 | s->codec->out.fifo[s->codec->out.len ++] = | |
3407 | (value >> 16) & 0xff; | |
3408 | s->codec->out.fifo[s->codec->out.len ++] = | |
3409 | (value >> 8) & 0xff; | |
3410 | s->codec->out.fifo[s->codec->out.len ++] = | |
3411 | (value >> 0) & 0xff; | |
3412 | } | |
3413 | if (s->tx_req < 4) | |
3414 | omap_mcbsp_tx_done(s); | |
3415 | } else | |
3416 | printf("%s: Tx FIFO overrun\n", __FUNCTION__); | |
3417 | return; | |
3418 | } | |
3419 | ||
3420 | omap_badwidth_write16(opaque, addr, value); | |
3421 | } | |
3422 | ||
a8170e5e | 3423 | static void omap_mcbsp_write(void *opaque, hwaddr addr, |
a4ebbd18 AK |
3424 | uint64_t value, unsigned size) |
3425 | { | |
3426 | switch (size) { | |
77a8257e SW |
3427 | case 2: |
3428 | omap_mcbsp_writeh(opaque, addr, value); | |
3429 | break; | |
3430 | case 4: | |
3431 | omap_mcbsp_writew(opaque, addr, value); | |
3432 | break; | |
3433 | default: | |
3434 | omap_badwidth_write16(opaque, addr, value); | |
a4ebbd18 AK |
3435 | } |
3436 | } | |
d8f699cb | 3437 | |
a4ebbd18 AK |
3438 | static const MemoryRegionOps omap_mcbsp_ops = { |
3439 | .read = omap_mcbsp_read, | |
3440 | .write = omap_mcbsp_write, | |
3441 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d8f699cb AZ |
3442 | }; |
3443 | ||
3444 | static void omap_mcbsp_reset(struct omap_mcbsp_s *s) | |
3445 | { | |
3446 | memset(&s->spcr, 0, sizeof(s->spcr)); | |
3447 | memset(&s->rcr, 0, sizeof(s->rcr)); | |
3448 | memset(&s->xcr, 0, sizeof(s->xcr)); | |
3449 | s->srgr[0] = 0x0001; | |
3450 | s->srgr[1] = 0x2000; | |
3451 | memset(&s->mcr, 0, sizeof(s->mcr)); | |
3452 | memset(&s->pcr, 0, sizeof(s->pcr)); | |
3453 | memset(&s->rcer, 0, sizeof(s->rcer)); | |
3454 | memset(&s->xcer, 0, sizeof(s->xcer)); | |
3455 | s->tx_req = 0; | |
73560bc8 | 3456 | s->rx_req = 0; |
d8f699cb AZ |
3457 | s->tx_rate = 0; |
3458 | s->rx_rate = 0; | |
bc72ad67 AB |
3459 | timer_del(s->source_timer); |
3460 | timer_del(s->sink_timer); | |
d8f699cb AZ |
3461 | } |
3462 | ||
0919ac78 | 3463 | static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, |
a8170e5e | 3464 | hwaddr base, |
0919ac78 PM |
3465 | qemu_irq txirq, qemu_irq rxirq, |
3466 | qemu_irq *dma, omap_clk clk) | |
d8f699cb | 3467 | { |
b45c03f5 | 3468 | struct omap_mcbsp_s *s = g_new0(struct omap_mcbsp_s, 1); |
d8f699cb | 3469 | |
0919ac78 PM |
3470 | s->txirq = txirq; |
3471 | s->rxirq = rxirq; | |
d8f699cb AZ |
3472 | s->txdrq = dma[0]; |
3473 | s->rxdrq = dma[1]; | |
bc72ad67 AB |
3474 | s->sink_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_sink_tick, s); |
3475 | s->source_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, omap_mcbsp_source_tick, s); | |
d8f699cb AZ |
3476 | omap_mcbsp_reset(s); |
3477 | ||
2c9b15ca | 3478 | memory_region_init_io(&s->iomem, NULL, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800); |
a4ebbd18 | 3479 | memory_region_add_subregion(system_memory, base, &s->iomem); |
d8f699cb AZ |
3480 | |
3481 | return s; | |
3482 | } | |
3483 | ||
9596ebb7 | 3484 | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
d8f699cb AZ |
3485 | { |
3486 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3487 | ||
73560bc8 AZ |
3488 | if (s->rx_rate) { |
3489 | s->rx_req = s->codec->in.len; | |
3490 | omap_mcbsp_rx_newdata(s); | |
3491 | } | |
d8f699cb AZ |
3492 | } |
3493 | ||
9596ebb7 | 3494 | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
d8f699cb AZ |
3495 | { |
3496 | struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | |
3497 | ||
73560bc8 AZ |
3498 | if (s->tx_rate) { |
3499 | s->tx_req = s->codec->out.size; | |
3500 | omap_mcbsp_tx_newdata(s); | |
3501 | } | |
d8f699cb AZ |
3502 | } |
3503 | ||
bc24a225 | 3504 | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave) |
d8f699cb AZ |
3505 | { |
3506 | s->codec = slave; | |
f3c7d038 AF |
3507 | slave->rx_swallow = qemu_allocate_irq(omap_mcbsp_i2s_swallow, s, 0); |
3508 | slave->tx_start = qemu_allocate_irq(omap_mcbsp_i2s_start, s, 0); | |
d8f699cb AZ |
3509 | } |
3510 | ||
f9d43072 AZ |
3511 | /* LED Pulse Generators */ |
3512 | struct omap_lpg_s { | |
60fe76e3 | 3513 | MemoryRegion iomem; |
f9d43072 AZ |
3514 | QEMUTimer *tm; |
3515 | ||
3516 | uint8_t control; | |
3517 | uint8_t power; | |
3518 | int64_t on; | |
3519 | int64_t period; | |
3520 | int clk; | |
3521 | int cycle; | |
3522 | }; | |
3523 | ||
3524 | static void omap_lpg_tick(void *opaque) | |
3525 | { | |
3526 | struct omap_lpg_s *s = opaque; | |
3527 | ||
3528 | if (s->cycle) | |
bc72ad67 | 3529 | timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->period - s->on); |
f9d43072 | 3530 | else |
bc72ad67 | 3531 | timer_mod(s->tm, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->on); |
f9d43072 AZ |
3532 | |
3533 | s->cycle = !s->cycle; | |
3534 | printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); | |
3535 | } | |
3536 | ||
3537 | static void omap_lpg_update(struct omap_lpg_s *s) | |
3538 | { | |
3539 | int64_t on, period = 1, ticks = 1000; | |
3540 | static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; | |
3541 | ||
3542 | if (~s->control & (1 << 6)) /* LPGRES */ | |
3543 | on = 0; | |
3544 | else if (s->control & (1 << 7)) /* PERM_ON */ | |
3545 | on = period; | |
3546 | else { | |
3547 | period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ | |
3548 | 256 / 32); | |
3549 | on = (s->clk && s->power) ? muldiv64(ticks, | |
3550 | per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ | |
3551 | } | |
3552 | ||
bc72ad67 | 3553 | timer_del(s->tm); |
f9d43072 AZ |
3554 | if (on == period && s->on < s->period) |
3555 | printf("%s: LED is on\n", __FUNCTION__); | |
3556 | else if (on == 0 && s->on) | |
3557 | printf("%s: LED is off\n", __FUNCTION__); | |
3558 | else if (on && (on != s->on || period != s->period)) { | |
3559 | s->cycle = 0; | |
3560 | s->on = on; | |
3561 | s->period = period; | |
3562 | omap_lpg_tick(s); | |
3563 | return; | |
3564 | } | |
3565 | ||
3566 | s->on = on; | |
3567 | s->period = period; | |
3568 | } | |
3569 | ||
3570 | static void omap_lpg_reset(struct omap_lpg_s *s) | |
3571 | { | |
3572 | s->control = 0x00; | |
3573 | s->power = 0x00; | |
3574 | s->clk = 1; | |
3575 | omap_lpg_update(s); | |
3576 | } | |
3577 | ||
a8170e5e | 3578 | static uint64_t omap_lpg_read(void *opaque, hwaddr addr, |
60fe76e3 | 3579 | unsigned size) |
f9d43072 AZ |
3580 | { |
3581 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3582 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3583 | ||
60fe76e3 AK |
3584 | if (size != 1) { |
3585 | return omap_badwidth_read8(opaque, addr); | |
3586 | } | |
3587 | ||
f9d43072 AZ |
3588 | switch (offset) { |
3589 | case 0x00: /* LCR */ | |
3590 | return s->control; | |
3591 | ||
3592 | case 0x04: /* PMR */ | |
3593 | return s->power; | |
3594 | } | |
3595 | ||
3596 | OMAP_BAD_REG(addr); | |
3597 | return 0; | |
3598 | } | |
3599 | ||
a8170e5e | 3600 | static void omap_lpg_write(void *opaque, hwaddr addr, |
60fe76e3 | 3601 | uint64_t value, unsigned size) |
f9d43072 AZ |
3602 | { |
3603 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3604 | int offset = addr & OMAP_MPUI_REG_MASK; | |
3605 | ||
60fe76e3 | 3606 | if (size != 1) { |
77a8257e SW |
3607 | omap_badwidth_write8(opaque, addr, value); |
3608 | return; | |
60fe76e3 AK |
3609 | } |
3610 | ||
f9d43072 AZ |
3611 | switch (offset) { |
3612 | case 0x00: /* LCR */ | |
3613 | if (~value & (1 << 6)) /* LPGRES */ | |
3614 | omap_lpg_reset(s); | |
3615 | s->control = value & 0xff; | |
3616 | omap_lpg_update(s); | |
3617 | return; | |
3618 | ||
3619 | case 0x04: /* PMR */ | |
3620 | s->power = value & 0x01; | |
3621 | omap_lpg_update(s); | |
3622 | return; | |
3623 | ||
3624 | default: | |
3625 | OMAP_BAD_REG(addr); | |
3626 | return; | |
3627 | } | |
3628 | } | |
3629 | ||
60fe76e3 AK |
3630 | static const MemoryRegionOps omap_lpg_ops = { |
3631 | .read = omap_lpg_read, | |
3632 | .write = omap_lpg_write, | |
3633 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f9d43072 AZ |
3634 | }; |
3635 | ||
3636 | static void omap_lpg_clk_update(void *opaque, int line, int on) | |
3637 | { | |
3638 | struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | |
3639 | ||
3640 | s->clk = on; | |
3641 | omap_lpg_update(s); | |
3642 | } | |
3643 | ||
60fe76e3 | 3644 | static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory, |
a8170e5e | 3645 | hwaddr base, omap_clk clk) |
f9d43072 | 3646 | { |
b45c03f5 | 3647 | struct omap_lpg_s *s = g_new0(struct omap_lpg_s, 1); |
f9d43072 | 3648 | |
bc72ad67 | 3649 | s->tm = timer_new_ms(QEMU_CLOCK_VIRTUAL, omap_lpg_tick, s); |
f9d43072 AZ |
3650 | |
3651 | omap_lpg_reset(s); | |
3652 | ||
2c9b15ca | 3653 | memory_region_init_io(&s->iomem, NULL, &omap_lpg_ops, s, "omap-lpg", 0x800); |
60fe76e3 | 3654 | memory_region_add_subregion(system_memory, base, &s->iomem); |
f9d43072 | 3655 | |
f3c7d038 | 3656 | omap_clk_adduser(clk, qemu_allocate_irq(omap_lpg_clk_update, s, 0)); |
f9d43072 AZ |
3657 | |
3658 | return s; | |
3659 | } | |
3660 | ||
3661 | /* MPUI Peripheral Bridge configuration */ | |
a8170e5e | 3662 | static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr, |
60fe76e3 | 3663 | unsigned size) |
f9d43072 | 3664 | { |
60fe76e3 AK |
3665 | if (size != 2) { |
3666 | return omap_badwidth_read16(opaque, addr); | |
3667 | } | |
3668 | ||
f9d43072 AZ |
3669 | if (addr == OMAP_MPUI_BASE) /* CMR */ |
3670 | return 0xfe4d; | |
3671 | ||
3672 | OMAP_BAD_REG(addr); | |
3673 | return 0; | |
3674 | } | |
3675 | ||
a8170e5e | 3676 | static void omap_mpui_io_write(void *opaque, hwaddr addr, |
60fe76e3 AK |
3677 | uint64_t value, unsigned size) |
3678 | { | |
3679 | /* FIXME: infinite loop */ | |
3680 | omap_badwidth_write16(opaque, addr, value); | |
3681 | } | |
f9d43072 | 3682 | |
60fe76e3 AK |
3683 | static const MemoryRegionOps omap_mpui_io_ops = { |
3684 | .read = omap_mpui_io_read, | |
3685 | .write = omap_mpui_io_write, | |
3686 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f9d43072 AZ |
3687 | }; |
3688 | ||
60fe76e3 AK |
3689 | static void omap_setup_mpui_io(MemoryRegion *system_memory, |
3690 | struct omap_mpu_state_s *mpu) | |
f9d43072 | 3691 | { |
2c9b15ca | 3692 | memory_region_init_io(&mpu->mpui_io_iomem, NULL, &omap_mpui_io_ops, mpu, |
60fe76e3 AK |
3693 | "omap-mpui-io", 0x7fff); |
3694 | memory_region_add_subregion(system_memory, OMAP_MPUI_BASE, | |
3695 | &mpu->mpui_io_iomem); | |
f9d43072 AZ |
3696 | } |
3697 | ||
c3d2689d | 3698 | /* General chip reset */ |
827df9f3 | 3699 | static void omap1_mpu_reset(void *opaque) |
c3d2689d AZ |
3700 | { |
3701 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | |
3702 | ||
c3d2689d AZ |
3703 | omap_dma_reset(mpu->dma); |
3704 | omap_mpu_timer_reset(mpu->timer[0]); | |
3705 | omap_mpu_timer_reset(mpu->timer[1]); | |
3706 | omap_mpu_timer_reset(mpu->timer[2]); | |
3707 | omap_wd_timer_reset(mpu->wdt); | |
3708 | omap_os_timer_reset(mpu->os_timer); | |
3709 | omap_lcdc_reset(mpu->lcd); | |
3710 | omap_ulpd_pm_reset(mpu); | |
3711 | omap_pin_cfg_reset(mpu); | |
3712 | omap_mpui_reset(mpu); | |
3713 | omap_tipb_bridge_reset(mpu->private_tipb); | |
3714 | omap_tipb_bridge_reset(mpu->public_tipb); | |
b9f7bc40 JR |
3715 | omap_dpll_reset(mpu->dpll[0]); |
3716 | omap_dpll_reset(mpu->dpll[1]); | |
3717 | omap_dpll_reset(mpu->dpll[2]); | |
d951f6ff AZ |
3718 | omap_uart_reset(mpu->uart[0]); |
3719 | omap_uart_reset(mpu->uart[1]); | |
3720 | omap_uart_reset(mpu->uart[2]); | |
b30bb3a2 | 3721 | omap_mmc_reset(mpu->mmc); |
fe71e81a | 3722 | omap_mpuio_reset(mpu->mpuio); |
d951f6ff | 3723 | omap_uwire_reset(mpu->microwire); |
8717d88a | 3724 | omap_pwl_reset(mpu->pwl); |
03759534 | 3725 | omap_pwt_reset(mpu->pwt); |
5c1c390f | 3726 | omap_rtc_reset(mpu->rtc); |
d8f699cb AZ |
3727 | omap_mcbsp_reset(mpu->mcbsp1); |
3728 | omap_mcbsp_reset(mpu->mcbsp2); | |
3729 | omap_mcbsp_reset(mpu->mcbsp3); | |
f9d43072 AZ |
3730 | omap_lpg_reset(mpu->led[0]); |
3731 | omap_lpg_reset(mpu->led[1]); | |
8ef6367e | 3732 | omap_clkm_reset(mpu); |
5f4ef08b | 3733 | cpu_reset(CPU(mpu->cpu)); |
c3d2689d AZ |
3734 | } |
3735 | ||
cf965d24 | 3736 | static const struct omap_map_s { |
a8170e5e AK |
3737 | hwaddr phys_dsp; |
3738 | hwaddr phys_mpu; | |
cf965d24 AZ |
3739 | uint32_t size; |
3740 | const char *name; | |
3741 | } omap15xx_dsp_mm[] = { | |
3742 | /* Strobe 0 */ | |
3743 | { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ | |
3744 | { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ | |
3745 | { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ | |
3746 | { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ | |
3747 | { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ | |
3748 | { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ | |
3749 | { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ | |
3750 | { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ | |
3751 | { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ | |
3752 | { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ | |
3753 | { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ | |
3754 | { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ | |
3755 | { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ | |
3756 | { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ | |
3757 | { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ | |
3758 | { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ | |
3759 | { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ | |
3760 | /* Strobe 1 */ | |
3761 | { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ | |
3762 | ||
3763 | { 0 } | |
3764 | }; | |
3765 | ||
763b946c AK |
3766 | static void omap_setup_dsp_mapping(MemoryRegion *system_memory, |
3767 | const struct omap_map_s *map) | |
cf965d24 | 3768 | { |
763b946c | 3769 | MemoryRegion *io; |
cf965d24 AZ |
3770 | |
3771 | for (; map->phys_dsp; map ++) { | |
763b946c | 3772 | io = g_new(MemoryRegion, 1); |
2c9b15ca | 3773 | memory_region_init_alias(io, NULL, map->name, |
763b946c AK |
3774 | system_memory, map->phys_mpu, map->size); |
3775 | memory_region_add_subregion(system_memory, map->phys_dsp, io); | |
cf965d24 AZ |
3776 | } |
3777 | } | |
3778 | ||
827df9f3 | 3779 | void omap_mpu_wakeup(void *opaque, int irq, int req) |
c3d2689d AZ |
3780 | { |
3781 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | |
259186a7 | 3782 | CPUState *cpu = CPU(mpu->cpu); |
c3d2689d | 3783 | |
259186a7 | 3784 | if (cpu->halted) { |
c3affe56 | 3785 | cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
5f4ef08b | 3786 | } |
c3d2689d AZ |
3787 | } |
3788 | ||
827df9f3 | 3789 | static const struct dma_irq_map omap1_dma_irq_map[] = { |
089b7c0a AZ |
3790 | { 0, OMAP_INT_DMA_CH0_6 }, |
3791 | { 0, OMAP_INT_DMA_CH1_7 }, | |
3792 | { 0, OMAP_INT_DMA_CH2_8 }, | |
3793 | { 0, OMAP_INT_DMA_CH3 }, | |
3794 | { 0, OMAP_INT_DMA_CH4 }, | |
3795 | { 0, OMAP_INT_DMA_CH5 }, | |
3796 | { 1, OMAP_INT_1610_DMA_CH6 }, | |
3797 | { 1, OMAP_INT_1610_DMA_CH7 }, | |
3798 | { 1, OMAP_INT_1610_DMA_CH8 }, | |
3799 | { 1, OMAP_INT_1610_DMA_CH9 }, | |
3800 | { 1, OMAP_INT_1610_DMA_CH10 }, | |
3801 | { 1, OMAP_INT_1610_DMA_CH11 }, | |
3802 | { 1, OMAP_INT_1610_DMA_CH12 }, | |
3803 | { 1, OMAP_INT_1610_DMA_CH13 }, | |
3804 | { 1, OMAP_INT_1610_DMA_CH14 }, | |
3805 | { 1, OMAP_INT_1610_DMA_CH15 } | |
3806 | }; | |
3807 | ||
b4e3104b AZ |
3808 | /* DMA ports for OMAP1 */ |
3809 | static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3810 | hwaddr addr) |
b4e3104b | 3811 | { |
45416789 | 3812 | return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr); |
b4e3104b AZ |
3813 | } |
3814 | ||
3815 | static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3816 | hwaddr addr) |
b4e3104b | 3817 | { |
45416789 BS |
3818 | return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE, |
3819 | addr); | |
b4e3104b AZ |
3820 | } |
3821 | ||
3822 | static int omap_validate_imif_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3823 | hwaddr addr) |
b4e3104b | 3824 | { |
45416789 | 3825 | return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr); |
b4e3104b AZ |
3826 | } |
3827 | ||
3828 | static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3829 | hwaddr addr) |
b4e3104b | 3830 | { |
45416789 | 3831 | return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr); |
b4e3104b AZ |
3832 | } |
3833 | ||
3834 | static int omap_validate_local_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3835 | hwaddr addr) |
b4e3104b | 3836 | { |
45416789 | 3837 | return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr); |
b4e3104b AZ |
3838 | } |
3839 | ||
3840 | static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, | |
a8170e5e | 3841 | hwaddr addr) |
b4e3104b | 3842 | { |
45416789 | 3843 | return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr); |
b4e3104b AZ |
3844 | } |
3845 | ||
4b3fedf3 AK |
3846 | struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, |
3847 | unsigned long sdram_size, | |
3023f332 | 3848 | const char *core) |
c3d2689d | 3849 | { |
089b7c0a | 3850 | int i; |
b45c03f5 | 3851 | struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1); |
089b7c0a | 3852 | qemu_irq dma_irqs[6]; |
751c6a17 | 3853 | DriveInfo *dinfo; |
0919ac78 | 3854 | SysBusDevice *busdev; |
106627d0 | 3855 | |
aaed909a FB |
3856 | if (!core) |
3857 | core = "ti925t"; | |
c3d2689d AZ |
3858 | |
3859 | /* Core */ | |
3860 | s->mpu_model = omap310; | |
5f4ef08b AF |
3861 | s->cpu = cpu_arm_init(core); |
3862 | if (s->cpu == NULL) { | |
aaed909a FB |
3863 | fprintf(stderr, "Unable to find CPU definition\n"); |
3864 | exit(1); | |
3865 | } | |
c3d2689d AZ |
3866 | s->sdram_size = sdram_size; |
3867 | s->sram_size = OMAP15XX_SRAM_SIZE; | |
3868 | ||
f3c7d038 | 3869 | s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0); |
fe71e81a | 3870 | |
c3d2689d AZ |
3871 | /* Clocks */ |
3872 | omap_clk_init(s); | |
3873 | ||
3874 | /* Memory-mapped stuff */ | |
c8623c02 DM |
3875 | memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram", |
3876 | s->sdram_size); | |
2654c962 | 3877 | memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); |
49946538 | 3878 | memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, |
f8ed85ac | 3879 | &error_fatal); |
c5705a77 | 3880 | vmstate_register_ram_global(&s->imif_ram); |
2654c962 | 3881 | memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); |
c3d2689d | 3882 | |
e7aa0ae0 | 3883 | omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); |
c3d2689d | 3884 | |
0919ac78 PM |
3885 | s->ih[0] = qdev_create(NULL, "omap-intc"); |
3886 | qdev_prop_set_uint32(s->ih[0], "size", 0x100); | |
3887 | qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); | |
3888 | qdev_init_nofail(s->ih[0]); | |
1356b98d | 3889 | busdev = SYS_BUS_DEVICE(s->ih[0]); |
437f0f10 PM |
3890 | sysbus_connect_irq(busdev, 0, |
3891 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | |
3892 | sysbus_connect_irq(busdev, 1, | |
3893 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ)); | |
0919ac78 PM |
3894 | sysbus_mmio_map(busdev, 0, 0xfffecb00); |
3895 | s->ih[1] = qdev_create(NULL, "omap-intc"); | |
3896 | qdev_prop_set_uint32(s->ih[1], "size", 0x800); | |
3897 | qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck")); | |
3898 | qdev_init_nofail(s->ih[1]); | |
1356b98d | 3899 | busdev = SYS_BUS_DEVICE(s->ih[1]); |
0919ac78 PM |
3900 | sysbus_connect_irq(busdev, 0, |
3901 | qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ)); | |
3902 | /* The second interrupt controller's FIQ output is not wired up */ | |
3903 | sysbus_mmio_map(busdev, 0, 0xfffe0000); | |
3904 | ||
3905 | for (i = 0; i < 6; i++) { | |
3906 | dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih], | |
3907 | omap1_dma_irq_map[i].intr); | |
3908 | } | |
7405165e | 3909 | s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory, |
0919ac78 | 3910 | qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD), |
089b7c0a AZ |
3911 | s, omap_findclk(s, "dma_ck"), omap_dma_3_1); |
3912 | ||
c3d2689d AZ |
3913 | s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
3914 | s->port[emifs ].addr_valid = omap_validate_emifs_addr; | |
3915 | s->port[imif ].addr_valid = omap_validate_imif_addr; | |
3916 | s->port[tipb ].addr_valid = omap_validate_tipb_addr; | |
3917 | s->port[local ].addr_valid = omap_validate_local_addr; | |
3918 | s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; | |
3919 | ||
afbb5194 | 3920 | /* Register SDRAM and SRAM DMA ports for fast transfers. */ |
2654c962 AK |
3921 | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram), |
3922 | OMAP_EMIFF_BASE, s->sdram_size); | |
3923 | soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram), | |
90aeba9d | 3924 | OMAP_IMIF_BASE, s->sram_size); |
afbb5194 | 3925 | |
4b3fedf3 | 3926 | s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500, |
0919ac78 | 3927 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1), |
c3d2689d | 3928 | omap_findclk(s, "mputim_ck")); |
4b3fedf3 | 3929 | s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600, |
0919ac78 | 3930 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2), |
c3d2689d | 3931 | omap_findclk(s, "mputim_ck")); |
4b3fedf3 | 3932 | s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700, |
0919ac78 | 3933 | qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3), |
c3d2689d AZ |
3934 | omap_findclk(s, "mputim_ck")); |
3935 | ||
4b3fedf3 | 3936 | s->wdt = omap_wd_timer_init(system_memory, 0xfffec800, |
0919ac78 | 3937 | qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER), |
c3d2689d AZ |
3938 | omap_findclk(s, "armwdt_ck")); |
3939 | ||
4b3fedf3 | 3940 | s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000, |
0919ac78 | 3941 | qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER), |
c3d2689d AZ |
3942 | omap_findclk(s, "clk32-kHz")); |
3943 | ||
30af1ec7 | 3944 | s->lcd = omap_lcdc_init(system_memory, 0xfffec000, |
0919ac78 PM |
3945 | qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL), |
3946 | omap_dma_get_lcdch(s->dma), | |
3947 | omap_findclk(s, "lcd_ck")); | |
c3d2689d | 3948 | |
4b3fedf3 AK |
3949 | omap_ulpd_pm_init(system_memory, 0xfffe0800, s); |
3950 | omap_pin_cfg_init(system_memory, 0xfffe1000, s); | |
3951 | omap_id_init(system_memory, s); | |
c3d2689d | 3952 | |
4b3fedf3 | 3953 | omap_mpui_init(system_memory, 0xfffec900, s); |
c3d2689d | 3954 | |
4b3fedf3 | 3955 | s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00, |
0919ac78 | 3956 | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV), |
c3d2689d | 3957 | omap_findclk(s, "tipb_ck")); |
4b3fedf3 | 3958 | s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300, |
0919ac78 | 3959 | qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB), |
c3d2689d AZ |
3960 | omap_findclk(s, "tipb_ck")); |
3961 | ||
e7aa0ae0 | 3962 | omap_tcmi_init(system_memory, 0xfffecc00, s); |
c3d2689d | 3963 | |
0919ac78 PM |
3964 | s->uart[0] = omap_uart_init(0xfffb0000, |
3965 | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1), | |
c3d2689d | 3966 | omap_findclk(s, "uart1_ck"), |
827df9f3 AZ |
3967 | omap_findclk(s, "uart1_ck"), |
3968 | s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], | |
6a8aabd3 | 3969 | "uart1", |
c3d2689d | 3970 | serial_hds[0]); |
0919ac78 PM |
3971 | s->uart[1] = omap_uart_init(0xfffb0800, |
3972 | qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), | |
c3d2689d | 3973 | omap_findclk(s, "uart2_ck"), |
827df9f3 AZ |
3974 | omap_findclk(s, "uart2_ck"), |
3975 | s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], | |
6a8aabd3 | 3976 | "uart2", |
b9d38e95 | 3977 | serial_hds[0] ? serial_hds[1] : NULL); |
0919ac78 PM |
3978 | s->uart[2] = omap_uart_init(0xfffb9800, |
3979 | qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), | |
c3d2689d | 3980 | omap_findclk(s, "uart3_ck"), |
827df9f3 AZ |
3981 | omap_findclk(s, "uart3_ck"), |
3982 | s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], | |
6a8aabd3 | 3983 | "uart3", |
b9d38e95 | 3984 | serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); |
c3d2689d | 3985 | |
b9f7bc40 JR |
3986 | s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, |
3987 | omap_findclk(s, "dpll1")); | |
3988 | s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000, | |
3989 | omap_findclk(s, "dpll2")); | |
3990 | s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100, | |
3991 | omap_findclk(s, "dpll3")); | |
c3d2689d | 3992 | |
751c6a17 GH |
3993 | dinfo = drive_get(IF_SD, 0, 0); |
3994 | if (!dinfo) { | |
e4bcb14c TS |
3995 | fprintf(stderr, "qemu: missing SecureDigital device\n"); |
3996 | exit(1); | |
3997 | } | |
fa1d36df | 3998 | s->mmc = omap_mmc_init(0xfffb7800, system_memory, |
4be74634 | 3999 | blk_by_legacy_dinfo(dinfo), |
0919ac78 PM |
4000 | qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN), |
4001 | &s->drq[OMAP_DMA_MMC_TX], | |
9d413d1d | 4002 | omap_findclk(s, "mmc_ck")); |
b30bb3a2 | 4003 | |
e7aa0ae0 | 4004 | s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000, |
0919ac78 PM |
4005 | qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD), |
4006 | qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO), | |
4007 | s->wakeup, omap_findclk(s, "clk32-kHz")); | |
fe71e81a | 4008 | |
77831c20 JR |
4009 | s->gpio = qdev_create(NULL, "omap-gpio"); |
4010 | qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); | |
bdbc1b3c | 4011 | qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); |
77831c20 | 4012 | qdev_init_nofail(s->gpio); |
1356b98d | 4013 | sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, |
0919ac78 | 4014 | qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); |
1356b98d | 4015 | sysbus_mmio_map(SYS_BUS_DEVICE(s->gpio), 0, 0xfffce000); |
64330148 | 4016 | |
0919ac78 PM |
4017 | s->microwire = omap_uwire_init(system_memory, 0xfffb3000, |
4018 | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX), | |
4019 | qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX), | |
d951f6ff AZ |
4020 | s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); |
4021 | ||
8717d88a JR |
4022 | s->pwl = omap_pwl_init(system_memory, 0xfffb5800, |
4023 | omap_findclk(s, "armxor_ck")); | |
03759534 JR |
4024 | s->pwt = omap_pwt_init(system_memory, 0xfffb6000, |
4025 | omap_findclk(s, "armxor_ck")); | |
66450b15 | 4026 | |
54e17933 JR |
4027 | s->i2c[0] = qdev_create(NULL, "omap_i2c"); |
4028 | qdev_prop_set_uint8(s->i2c[0], "revision", 0x11); | |
4029 | qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck")); | |
4030 | qdev_init_nofail(s->i2c[0]); | |
1356b98d | 4031 | busdev = SYS_BUS_DEVICE(s->i2c[0]); |
54e17933 JR |
4032 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C)); |
4033 | sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]); | |
4034 | sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]); | |
4035 | sysbus_mmio_map(busdev, 0, 0xfffb3800); | |
4a2c8ac2 | 4036 | |
a4ebbd18 | 4037 | s->rtc = omap_rtc_init(system_memory, 0xfffb4800, |
0919ac78 PM |
4038 | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER), |
4039 | qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM), | |
5c1c390f | 4040 | omap_findclk(s, "clk32-kHz")); |
02645926 | 4041 | |
0919ac78 PM |
4042 | s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800, |
4043 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX), | |
4044 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX), | |
d8f699cb | 4045 | &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); |
0919ac78 PM |
4046 | s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000, |
4047 | qdev_get_gpio_in(s->ih[0], | |
4048 | OMAP_INT_310_McBSP2_TX), | |
4049 | qdev_get_gpio_in(s->ih[0], | |
4050 | OMAP_INT_310_McBSP2_RX), | |
d8f699cb | 4051 | &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); |
0919ac78 PM |
4052 | s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000, |
4053 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX), | |
4054 | qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX), | |
d8f699cb AZ |
4055 | &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); |
4056 | ||
60fe76e3 AK |
4057 | s->led[0] = omap_lpg_init(system_memory, |
4058 | 0xfffbd000, omap_findclk(s, "clk32-kHz")); | |
4059 | s->led[1] = omap_lpg_init(system_memory, | |
4060 | 0xfffbd800, omap_findclk(s, "clk32-kHz")); | |
f9d43072 | 4061 | |
02645926 | 4062 | /* Register mappings not currenlty implemented: |
02645926 AZ |
4063 | * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) |
4064 | * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) | |
4065 | * USB W2FC fffb4000 - fffb47ff | |
4066 | * Camera Interface fffb6800 - fffb6fff | |
02645926 AZ |
4067 | * USB Host fffba000 - fffba7ff |
4068 | * FAC fffba800 - fffbafff | |
4069 | * HDQ/1-Wire fffbc000 - fffbc7ff | |
b854bc19 | 4070 | * TIPB switches fffbc800 - fffbcfff |
02645926 AZ |
4071 | * Mailbox fffcf000 - fffcf7ff |
4072 | * Local bus IF fffec100 - fffec1ff | |
4073 | * Local bus MMU fffec200 - fffec2ff | |
4074 | * DSP MMU fffed200 - fffed2ff | |
4075 | */ | |
4076 | ||
763b946c | 4077 | omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm); |
60fe76e3 | 4078 | omap_setup_mpui_io(system_memory, s); |
cf965d24 | 4079 | |
a08d4367 | 4080 | qemu_register_reset(omap1_mpu_reset, s); |
c3d2689d AZ |
4081 | |
4082 | return s; | |
4083 | } |