]>
Commit | Line | Data |
---|---|---|
c1713132 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 processor support. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
c1713132 AZ |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
a8d25326 | 11 | #include "qemu-common.h" |
c0dbca36 | 12 | #include "qemu/error-report.h" |
0b8fa32f | 13 | #include "qemu/module.h" |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
83c9f4ca | 16 | #include "hw/sysbus.h" |
d6454270 | 17 | #include "migration/vmstate.h" |
0d09e41a | 18 | #include "hw/arm/pxa.h" |
9c17d615 | 19 | #include "sysemu/sysemu.h" |
0d09e41a PB |
20 | #include "hw/char/serial.h" |
21 | #include "hw/i2c/i2c.h" | |
64552b6b | 22 | #include "hw/irq.h" |
a27bd6c7 | 23 | #include "hw/qdev-properties.h" |
8fd06719 | 24 | #include "hw/ssi/ssi.h" |
4d43a603 | 25 | #include "chardev/char-fe.h" |
9c17d615 | 26 | #include "sysemu/blockdev.h" |
a82929a2 | 27 | #include "sysemu/qtest.h" |
f348b6d1 | 28 | #include "qemu/cutils.h" |
fc417e5b | 29 | #include "qemu/log.h" |
c1713132 AZ |
30 | |
31 | static struct { | |
a8170e5e | 32 | hwaddr io_base; |
c1713132 AZ |
33 | int irqn; |
34 | } pxa255_serial[] = { | |
35 | { 0x40100000, PXA2XX_PIC_FFUART }, | |
36 | { 0x40200000, PXA2XX_PIC_BTUART }, | |
37 | { 0x40700000, PXA2XX_PIC_STUART }, | |
38 | { 0x41600000, PXA25X_PIC_HWUART }, | |
39 | { 0, 0 } | |
40 | }, pxa270_serial[] = { | |
41 | { 0x40100000, PXA2XX_PIC_FFUART }, | |
42 | { 0x40200000, PXA2XX_PIC_BTUART }, | |
43 | { 0x40700000, PXA2XX_PIC_STUART }, | |
44 | { 0, 0 } | |
45 | }; | |
46 | ||
fa58c156 | 47 | typedef struct PXASSPDef { |
a8170e5e | 48 | hwaddr io_base; |
c1713132 | 49 | int irqn; |
fa58c156 FB |
50 | } PXASSPDef; |
51 | ||
52 | #if 0 | |
53 | static PXASSPDef pxa250_ssp[] = { | |
c1713132 AZ |
54 | { 0x41000000, PXA2XX_PIC_SSP }, |
55 | { 0, 0 } | |
fa58c156 FB |
56 | }; |
57 | #endif | |
58 | ||
59 | static PXASSPDef pxa255_ssp[] = { | |
c1713132 AZ |
60 | { 0x41000000, PXA2XX_PIC_SSP }, |
61 | { 0x41400000, PXA25X_PIC_NSSP }, | |
62 | { 0, 0 } | |
fa58c156 FB |
63 | }; |
64 | ||
65 | #if 0 | |
66 | static PXASSPDef pxa26x_ssp[] = { | |
c1713132 AZ |
67 | { 0x41000000, PXA2XX_PIC_SSP }, |
68 | { 0x41400000, PXA25X_PIC_NSSP }, | |
69 | { 0x41500000, PXA26X_PIC_ASSP }, | |
70 | { 0, 0 } | |
fa58c156 FB |
71 | }; |
72 | #endif | |
73 | ||
74 | static PXASSPDef pxa27x_ssp[] = { | |
c1713132 AZ |
75 | { 0x41000000, PXA2XX_PIC_SSP }, |
76 | { 0x41700000, PXA27X_PIC_SSP2 }, | |
77 | { 0x41900000, PXA2XX_PIC_SSP3 }, | |
78 | { 0, 0 } | |
79 | }; | |
80 | ||
81 | #define PMCR 0x00 /* Power Manager Control register */ | |
82 | #define PSSR 0x04 /* Power Manager Sleep Status register */ | |
83 | #define PSPR 0x08 /* Power Manager Scratch-Pad register */ | |
84 | #define PWER 0x0c /* Power Manager Wake-Up Enable register */ | |
85 | #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ | |
86 | #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ | |
87 | #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ | |
88 | #define PCFR 0x1c /* Power Manager General Configuration register */ | |
89 | #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ | |
90 | #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ | |
91 | #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ | |
92 | #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ | |
93 | #define RCSR 0x30 /* Reset Controller Status register */ | |
94 | #define PSLR 0x34 /* Power Manager Sleep Configuration register */ | |
95 | #define PTSR 0x38 /* Power Manager Standby Configuration register */ | |
96 | #define PVCR 0x40 /* Power Manager Voltage Change Control register */ | |
97 | #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ | |
98 | #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ | |
99 | #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ | |
100 | #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ | |
101 | #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ | |
102 | ||
a8170e5e | 103 | static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, |
adfc39ea | 104 | unsigned size) |
c1713132 | 105 | { |
bc24a225 | 106 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
107 | |
108 | switch (addr) { | |
109 | case PMCR ... PCMD31: | |
110 | if (addr & 3) | |
111 | goto fail; | |
112 | ||
113 | return s->pm_regs[addr >> 2]; | |
114 | default: | |
115 | fail: | |
fc417e5b PMD |
116 | qemu_log_mask(LOG_GUEST_ERROR, |
117 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
118 | __func__, addr); | |
c1713132 AZ |
119 | break; |
120 | } | |
121 | return 0; | |
122 | } | |
123 | ||
a8170e5e | 124 | static void pxa2xx_pm_write(void *opaque, hwaddr addr, |
adfc39ea | 125 | uint64_t value, unsigned size) |
c1713132 | 126 | { |
bc24a225 | 127 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
128 | |
129 | switch (addr) { | |
130 | case PMCR: | |
afd4a652 PM |
131 | /* Clear the write-one-to-clear bits... */ |
132 | s->pm_regs[addr >> 2] &= ~(value & 0x2a); | |
133 | /* ...and set the plain r/w bits */ | |
7c64d297 | 134 | s->pm_regs[addr >> 2] &= ~0x15; |
c1713132 AZ |
135 | s->pm_regs[addr >> 2] |= value & 0x15; |
136 | break; | |
137 | ||
138 | case PSSR: /* Read-clean registers */ | |
139 | case RCSR: | |
140 | case PKSR: | |
141 | s->pm_regs[addr >> 2] &= ~value; | |
142 | break; | |
143 | ||
144 | default: /* Read-write registers */ | |
603ff776 | 145 | if (!(addr & 3)) { |
c1713132 AZ |
146 | s->pm_regs[addr >> 2] = value; |
147 | break; | |
148 | } | |
fc417e5b PMD |
149 | qemu_log_mask(LOG_GUEST_ERROR, |
150 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
151 | __func__, addr); | |
c1713132 AZ |
152 | break; |
153 | } | |
154 | } | |
155 | ||
adfc39ea AK |
156 | static const MemoryRegionOps pxa2xx_pm_ops = { |
157 | .read = pxa2xx_pm_read, | |
158 | .write = pxa2xx_pm_write, | |
159 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
160 | }; |
161 | ||
f0ab24ce JQ |
162 | static const VMStateDescription vmstate_pxa2xx_pm = { |
163 | .name = "pxa2xx_pm", | |
164 | .version_id = 0, | |
165 | .minimum_version_id = 0, | |
8f1e884b | 166 | .fields = (VMStateField[]) { |
f0ab24ce JQ |
167 | VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), |
168 | VMSTATE_END_OF_LIST() | |
169 | } | |
170 | }; | |
aa941b94 | 171 | |
c1713132 AZ |
172 | #define CCCR 0x00 /* Core Clock Configuration register */ |
173 | #define CKEN 0x04 /* Clock Enable register */ | |
174 | #define OSCC 0x08 /* Oscillator Configuration register */ | |
175 | #define CCSR 0x0c /* Core Clock Status register */ | |
176 | ||
a8170e5e | 177 | static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, |
adfc39ea | 178 | unsigned size) |
c1713132 | 179 | { |
bc24a225 | 180 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
181 | |
182 | switch (addr) { | |
183 | case CCCR: | |
184 | case CKEN: | |
185 | case OSCC: | |
186 | return s->cm_regs[addr >> 2]; | |
187 | ||
188 | case CCSR: | |
189 | return s->cm_regs[CCCR >> 2] | (3 << 28); | |
190 | ||
191 | default: | |
fc417e5b PMD |
192 | qemu_log_mask(LOG_GUEST_ERROR, |
193 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
194 | __func__, addr); | |
c1713132 AZ |
195 | break; |
196 | } | |
197 | return 0; | |
198 | } | |
199 | ||
a8170e5e | 200 | static void pxa2xx_cm_write(void *opaque, hwaddr addr, |
adfc39ea | 201 | uint64_t value, unsigned size) |
c1713132 | 202 | { |
bc24a225 | 203 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
204 | |
205 | switch (addr) { | |
206 | case CCCR: | |
207 | case CKEN: | |
208 | s->cm_regs[addr >> 2] = value; | |
209 | break; | |
210 | ||
211 | case OSCC: | |
565d2895 | 212 | s->cm_regs[addr >> 2] &= ~0x6c; |
c1713132 | 213 | s->cm_regs[addr >> 2] |= value & 0x6e; |
565d2895 AZ |
214 | if ((value >> 1) & 1) /* OON */ |
215 | s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ | |
c1713132 AZ |
216 | break; |
217 | ||
218 | default: | |
fc417e5b PMD |
219 | qemu_log_mask(LOG_GUEST_ERROR, |
220 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
221 | __func__, addr); | |
c1713132 AZ |
222 | break; |
223 | } | |
224 | } | |
225 | ||
adfc39ea AK |
226 | static const MemoryRegionOps pxa2xx_cm_ops = { |
227 | .read = pxa2xx_cm_read, | |
228 | .write = pxa2xx_cm_write, | |
229 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
230 | }; |
231 | ||
ae1f90de JQ |
232 | static const VMStateDescription vmstate_pxa2xx_cm = { |
233 | .name = "pxa2xx_cm", | |
234 | .version_id = 0, | |
235 | .minimum_version_id = 0, | |
8f1e884b | 236 | .fields = (VMStateField[]) { |
ae1f90de JQ |
237 | VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), |
238 | VMSTATE_UINT32(clkcfg, PXA2xxState), | |
239 | VMSTATE_UINT32(pmnc, PXA2xxState), | |
240 | VMSTATE_END_OF_LIST() | |
241 | } | |
242 | }; | |
aa941b94 | 243 | |
c4241c7d | 244 | static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) |
c1713132 | 245 | { |
e2f8a44d | 246 | PXA2xxState *s = (PXA2xxState *)ri->opaque; |
c4241c7d | 247 | return s->clkcfg; |
e2f8a44d | 248 | } |
c1713132 | 249 | |
c4241c7d PM |
250 | static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, |
251 | uint64_t value) | |
e2f8a44d PM |
252 | { |
253 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
254 | s->clkcfg = value & 0xf; | |
255 | if (value & 2) { | |
256 | printf("%s: CPU frequency change attempt\n", __func__); | |
c1713132 | 257 | } |
c1713132 AZ |
258 | } |
259 | ||
c4241c7d PM |
260 | static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, |
261 | uint64_t value) | |
c1713132 | 262 | { |
e2f8a44d | 263 | PXA2xxState *s = (PXA2xxState *)ri->opaque; |
c1713132 AZ |
264 | static const char *pwrmode[8] = { |
265 | "Normal", "Idle", "Deep-idle", "Standby", | |
266 | "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", | |
267 | }; | |
268 | ||
e2f8a44d PM |
269 | if (value & 8) { |
270 | printf("%s: CPU voltage change attempt\n", __func__); | |
271 | } | |
272 | switch (value & 7) { | |
273 | case 0: | |
274 | /* Do nothing */ | |
c1713132 AZ |
275 | break; |
276 | ||
e2f8a44d PM |
277 | case 1: |
278 | /* Idle */ | |
43a32ed6 | 279 | if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ |
c3affe56 | 280 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
e2f8a44d PM |
281 | break; |
282 | } | |
283 | /* Fall through. */ | |
284 | ||
285 | case 2: | |
286 | /* Deep-Idle */ | |
c3affe56 | 287 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
e2f8a44d PM |
288 | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
289 | goto message; | |
290 | ||
291 | case 3: | |
4cc35614 PM |
292 | s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; |
293 | s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; | |
137feaa9 | 294 | s->cpu->env.cp15.sctlr_ns = 0; |
7ebd5f2e | 295 | s->cpu->env.cp15.cpacr_el1 = 0; |
7dd8c9af | 296 | s->cpu->env.cp15.ttbr0_el[1] = 0; |
0c17d68c | 297 | s->cpu->env.cp15.dacr_ns = 0; |
e2f8a44d PM |
298 | s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
299 | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ | |
300 | ||
301 | /* | |
302 | * The scratch-pad register is almost universally used | |
303 | * for storing the return address on suspend. For the | |
304 | * lack of a resuming bootloader, perform a jump | |
305 | * directly to that address. | |
306 | */ | |
307 | memset(s->cpu->env.regs, 0, 4 * 15); | |
308 | s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; | |
c1713132 AZ |
309 | |
310 | #if 0 | |
e2f8a44d PM |
311 | buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ |
312 | cpu_physical_memory_write(0, &buffer, 4); | |
313 | buffer = s->pm_regs[PSPR >> 2]; | |
314 | cpu_physical_memory_write(8, &buffer, 4); | |
c1713132 AZ |
315 | #endif |
316 | ||
e2f8a44d | 317 | /* Suspend */ |
4917cf44 | 318 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); |
c1713132 | 319 | |
e2f8a44d | 320 | goto message; |
c1713132 AZ |
321 | |
322 | default: | |
e2f8a44d PM |
323 | message: |
324 | printf("%s: machine entered %s mode\n", __func__, | |
325 | pwrmode[value & 7]); | |
c1713132 | 326 | } |
c1713132 AZ |
327 | } |
328 | ||
c4241c7d | 329 | static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) |
dc2a9045 PM |
330 | { |
331 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
c4241c7d | 332 | return s->pmnc; |
dc2a9045 PM |
333 | } |
334 | ||
c4241c7d PM |
335 | static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
336 | uint64_t value) | |
dc2a9045 PM |
337 | { |
338 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
339 | s->pmnc = value; | |
dc2a9045 PM |
340 | } |
341 | ||
c4241c7d | 342 | static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
dc2a9045 PM |
343 | { |
344 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
345 | if (s->pmnc & 1) { | |
c4241c7d | 346 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
dc2a9045 | 347 | } else { |
c4241c7d | 348 | return 0; |
dc2a9045 | 349 | } |
dc2a9045 PM |
350 | } |
351 | ||
352 | static const ARMCPRegInfo pxa_cp_reginfo[] = { | |
f565235b PM |
353 | /* cp14 crm==1: perf registers */ |
354 | { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, | |
14c3032a | 355 | .access = PL1_RW, .type = ARM_CP_IO, |
dc2a9045 PM |
356 | .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, |
357 | { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, | |
14c3032a | 358 | .access = PL1_RW, .type = ARM_CP_IO, |
dc2a9045 | 359 | .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, |
f565235b | 360 | { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 361 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 362 | { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 363 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 364 | { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 365 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b PM |
366 | /* cp14 crm==2: performance count registers */ |
367 | { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, | |
dc2a9045 | 368 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 369 | { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, |
dc2a9045 PM |
370 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
371 | { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, | |
372 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
373 | { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, | |
374 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
e2f8a44d PM |
375 | /* cp14 crn==6: CLKCFG */ |
376 | { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
14c3032a | 377 | .access = PL1_RW, .type = ARM_CP_IO, |
e2f8a44d PM |
378 | .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, |
379 | /* cp14 crn==7: PWRMODE */ | |
380 | { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, | |
14c3032a | 381 | .access = PL1_RW, .type = ARM_CP_IO, |
e2f8a44d | 382 | .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, |
dc2a9045 PM |
383 | REGINFO_SENTINEL |
384 | }; | |
385 | ||
386 | static void pxa2xx_setup_cp14(PXA2xxState *s) | |
387 | { | |
388 | define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); | |
389 | } | |
390 | ||
c1713132 AZ |
391 | #define MDCNFG 0x00 /* SDRAM Configuration register */ |
392 | #define MDREFR 0x04 /* SDRAM Refresh Control register */ | |
393 | #define MSC0 0x08 /* Static Memory Control register 0 */ | |
394 | #define MSC1 0x0c /* Static Memory Control register 1 */ | |
395 | #define MSC2 0x10 /* Static Memory Control register 2 */ | |
396 | #define MECR 0x14 /* Expansion Memory Bus Config register */ | |
397 | #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ | |
398 | #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ | |
399 | #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ | |
400 | #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ | |
401 | #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ | |
402 | #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ | |
403 | #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ | |
404 | #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ | |
405 | #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ | |
406 | #define ARB_CNTL 0x48 /* Arbiter Control register */ | |
407 | #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ | |
408 | #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ | |
409 | #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ | |
410 | #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ | |
411 | #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ | |
412 | #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ | |
413 | #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ | |
414 | ||
a8170e5e | 415 | static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, |
adfc39ea | 416 | unsigned size) |
c1713132 | 417 | { |
bc24a225 | 418 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
419 | |
420 | switch (addr) { | |
421 | case MDCNFG ... SA1110: | |
422 | if ((addr & 3) == 0) | |
423 | return s->mm_regs[addr >> 2]; | |
edd7541b | 424 | /* fall through */ |
c1713132 | 425 | default: |
fc417e5b PMD |
426 | qemu_log_mask(LOG_GUEST_ERROR, |
427 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
428 | __func__, addr); | |
c1713132 AZ |
429 | break; |
430 | } | |
431 | return 0; | |
432 | } | |
433 | ||
a8170e5e | 434 | static void pxa2xx_mm_write(void *opaque, hwaddr addr, |
adfc39ea | 435 | uint64_t value, unsigned size) |
c1713132 | 436 | { |
bc24a225 | 437 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
438 | |
439 | switch (addr) { | |
440 | case MDCNFG ... SA1110: | |
441 | if ((addr & 3) == 0) { | |
442 | s->mm_regs[addr >> 2] = value; | |
443 | break; | |
444 | } | |
445 | ||
446 | default: | |
fc417e5b PMD |
447 | qemu_log_mask(LOG_GUEST_ERROR, |
448 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
449 | __func__, addr); | |
c1713132 AZ |
450 | break; |
451 | } | |
452 | } | |
453 | ||
adfc39ea AK |
454 | static const MemoryRegionOps pxa2xx_mm_ops = { |
455 | .read = pxa2xx_mm_read, | |
456 | .write = pxa2xx_mm_write, | |
457 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
458 | }; |
459 | ||
d102d495 JQ |
460 | static const VMStateDescription vmstate_pxa2xx_mm = { |
461 | .name = "pxa2xx_mm", | |
462 | .version_id = 0, | |
463 | .minimum_version_id = 0, | |
8f1e884b | 464 | .fields = (VMStateField[]) { |
d102d495 JQ |
465 | VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), |
466 | VMSTATE_END_OF_LIST() | |
467 | } | |
468 | }; | |
aa941b94 | 469 | |
12a82804 AF |
470 | #define TYPE_PXA2XX_SSP "pxa2xx-ssp" |
471 | #define PXA2XX_SSP(obj) \ | |
472 | OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) | |
473 | ||
c1713132 | 474 | /* Synchronous Serial Ports */ |
a984a69e | 475 | typedef struct { |
12a82804 AF |
476 | /*< private >*/ |
477 | SysBusDevice parent_obj; | |
478 | /*< public >*/ | |
479 | ||
9c843933 | 480 | MemoryRegion iomem; |
c1713132 | 481 | qemu_irq irq; |
8e079caf | 482 | uint32_t enable; |
a984a69e | 483 | SSIBus *bus; |
c1713132 AZ |
484 | |
485 | uint32_t sscr[2]; | |
486 | uint32_t sspsp; | |
487 | uint32_t ssto; | |
488 | uint32_t ssitr; | |
489 | uint32_t sssr; | |
490 | uint8_t sstsa; | |
491 | uint8_t ssrsa; | |
492 | uint8_t ssacd; | |
493 | ||
494 | uint32_t rx_fifo[16]; | |
8e079caf PM |
495 | uint32_t rx_level; |
496 | uint32_t rx_start; | |
a984a69e | 497 | } PXA2xxSSPState; |
c1713132 | 498 | |
8e079caf PM |
499 | static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) |
500 | { | |
501 | PXA2xxSSPState *s = opaque; | |
502 | ||
503 | return s->rx_start < sizeof(s->rx_fifo); | |
504 | } | |
505 | ||
506 | static const VMStateDescription vmstate_pxa2xx_ssp = { | |
507 | .name = "pxa2xx-ssp", | |
508 | .version_id = 1, | |
509 | .minimum_version_id = 1, | |
510 | .fields = (VMStateField[]) { | |
511 | VMSTATE_UINT32(enable, PXA2xxSSPState), | |
512 | VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), | |
513 | VMSTATE_UINT32(sspsp, PXA2xxSSPState), | |
514 | VMSTATE_UINT32(ssto, PXA2xxSSPState), | |
515 | VMSTATE_UINT32(ssitr, PXA2xxSSPState), | |
516 | VMSTATE_UINT32(sssr, PXA2xxSSPState), | |
517 | VMSTATE_UINT8(sstsa, PXA2xxSSPState), | |
518 | VMSTATE_UINT8(ssrsa, PXA2xxSSPState), | |
519 | VMSTATE_UINT8(ssacd, PXA2xxSSPState), | |
520 | VMSTATE_UINT32(rx_level, PXA2xxSSPState), | |
521 | VMSTATE_UINT32(rx_start, PXA2xxSSPState), | |
522 | VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), | |
523 | VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), | |
524 | VMSTATE_END_OF_LIST() | |
525 | } | |
526 | }; | |
527 | ||
c1713132 AZ |
528 | #define SSCR0 0x00 /* SSP Control register 0 */ |
529 | #define SSCR1 0x04 /* SSP Control register 1 */ | |
530 | #define SSSR 0x08 /* SSP Status register */ | |
531 | #define SSITR 0x0c /* SSP Interrupt Test register */ | |
532 | #define SSDR 0x10 /* SSP Data register */ | |
533 | #define SSTO 0x28 /* SSP Time-Out register */ | |
534 | #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ | |
535 | #define SSTSA 0x30 /* SSP TX Time Slot Active register */ | |
536 | #define SSRSA 0x34 /* SSP RX Time Slot Active register */ | |
537 | #define SSTSS 0x38 /* SSP Time Slot Status register */ | |
538 | #define SSACD 0x3c /* SSP Audio Clock Divider register */ | |
539 | ||
540 | /* Bitfields for above registers */ | |
541 | #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) | |
542 | #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) | |
543 | #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) | |
544 | #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) | |
545 | #define SSCR0_SSE (1 << 7) | |
546 | #define SSCR0_RIM (1 << 22) | |
547 | #define SSCR0_TIM (1 << 23) | |
43a32ed6 | 548 | #define SSCR0_MOD (1U << 31) |
c1713132 AZ |
549 | #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
550 | #define SSCR1_RIE (1 << 0) | |
551 | #define SSCR1_TIE (1 << 1) | |
552 | #define SSCR1_LBM (1 << 2) | |
553 | #define SSCR1_MWDS (1 << 5) | |
554 | #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) | |
555 | #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) | |
556 | #define SSCR1_EFWR (1 << 14) | |
557 | #define SSCR1_PINTE (1 << 18) | |
558 | #define SSCR1_TINTE (1 << 19) | |
559 | #define SSCR1_RSRE (1 << 20) | |
560 | #define SSCR1_TSRE (1 << 21) | |
561 | #define SSCR1_EBCEI (1 << 29) | |
562 | #define SSITR_INT (7 << 5) | |
563 | #define SSSR_TNF (1 << 2) | |
564 | #define SSSR_RNE (1 << 3) | |
565 | #define SSSR_TFS (1 << 5) | |
566 | #define SSSR_RFS (1 << 6) | |
567 | #define SSSR_ROR (1 << 7) | |
568 | #define SSSR_PINT (1 << 18) | |
569 | #define SSSR_TINT (1 << 19) | |
570 | #define SSSR_EOC (1 << 20) | |
571 | #define SSSR_TUR (1 << 21) | |
572 | #define SSSR_BCE (1 << 23) | |
573 | #define SSSR_RW 0x00bc0080 | |
574 | ||
bc24a225 | 575 | static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) |
c1713132 AZ |
576 | { |
577 | int level = 0; | |
578 | ||
579 | level |= s->ssitr & SSITR_INT; | |
580 | level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); | |
581 | level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); | |
582 | level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); | |
583 | level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); | |
584 | level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); | |
585 | level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); | |
586 | level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); | |
587 | level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); | |
588 | qemu_set_irq(s->irq, !!level); | |
589 | } | |
590 | ||
bc24a225 | 591 | static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) |
c1713132 AZ |
592 | { |
593 | s->sssr &= ~(0xf << 12); /* Clear RFL */ | |
594 | s->sssr &= ~(0xf << 8); /* Clear TFL */ | |
7d147689 | 595 | s->sssr &= ~SSSR_TFS; |
c1713132 AZ |
596 | s->sssr &= ~SSSR_TNF; |
597 | if (s->enable) { | |
598 | s->sssr |= ((s->rx_level - 1) & 0xf) << 12; | |
599 | if (s->rx_level >= SSCR1_RFT(s->sscr[1])) | |
600 | s->sssr |= SSSR_RFS; | |
601 | else | |
602 | s->sssr &= ~SSSR_RFS; | |
c1713132 AZ |
603 | if (s->rx_level) |
604 | s->sssr |= SSSR_RNE; | |
605 | else | |
606 | s->sssr &= ~SSSR_RNE; | |
7d147689 BS |
607 | /* TX FIFO is never filled, so it is always in underrun |
608 | condition if SSP is enabled */ | |
609 | s->sssr |= SSSR_TFS; | |
c1713132 AZ |
610 | s->sssr |= SSSR_TNF; |
611 | } | |
612 | ||
613 | pxa2xx_ssp_int_update(s); | |
614 | } | |
615 | ||
a8170e5e | 616 | static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, |
9c843933 | 617 | unsigned size) |
c1713132 | 618 | { |
bc24a225 | 619 | PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
c1713132 | 620 | uint32_t retval; |
c1713132 AZ |
621 | |
622 | switch (addr) { | |
623 | case SSCR0: | |
624 | return s->sscr[0]; | |
625 | case SSCR1: | |
626 | return s->sscr[1]; | |
627 | case SSPSP: | |
628 | return s->sspsp; | |
629 | case SSTO: | |
630 | return s->ssto; | |
631 | case SSITR: | |
632 | return s->ssitr; | |
633 | case SSSR: | |
634 | return s->sssr | s->ssitr; | |
635 | case SSDR: | |
636 | if (!s->enable) | |
637 | return 0xffffffff; | |
638 | if (s->rx_level < 1) { | |
a89f364a | 639 | printf("%s: SSP Rx Underrun\n", __func__); |
c1713132 AZ |
640 | return 0xffffffff; |
641 | } | |
642 | s->rx_level --; | |
643 | retval = s->rx_fifo[s->rx_start ++]; | |
644 | s->rx_start &= 0xf; | |
645 | pxa2xx_ssp_fifo_update(s); | |
646 | return retval; | |
647 | case SSTSA: | |
648 | return s->sstsa; | |
649 | case SSRSA: | |
650 | return s->ssrsa; | |
651 | case SSTSS: | |
652 | return 0; | |
653 | case SSACD: | |
654 | return s->ssacd; | |
655 | default: | |
fc417e5b PMD |
656 | qemu_log_mask(LOG_GUEST_ERROR, |
657 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
658 | __func__, addr); | |
c1713132 AZ |
659 | break; |
660 | } | |
661 | return 0; | |
662 | } | |
663 | ||
a8170e5e | 664 | static void pxa2xx_ssp_write(void *opaque, hwaddr addr, |
9c843933 | 665 | uint64_t value64, unsigned size) |
c1713132 | 666 | { |
bc24a225 | 667 | PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
9c843933 | 668 | uint32_t value = value64; |
c1713132 AZ |
669 | |
670 | switch (addr) { | |
671 | case SSCR0: | |
672 | s->sscr[0] = value & 0xc7ffffff; | |
673 | s->enable = value & SSCR0_SSE; | |
674 | if (value & SSCR0_MOD) | |
a89f364a | 675 | printf("%s: Attempt to use network mode\n", __func__); |
c1713132 | 676 | if (s->enable && SSCR0_DSS(value) < 4) |
a89f364a | 677 | printf("%s: Wrong data size: %i bits\n", __func__, |
c1713132 AZ |
678 | SSCR0_DSS(value)); |
679 | if (!(value & SSCR0_SSE)) { | |
680 | s->sssr = 0; | |
681 | s->ssitr = 0; | |
682 | s->rx_level = 0; | |
683 | } | |
684 | pxa2xx_ssp_fifo_update(s); | |
685 | break; | |
686 | ||
687 | case SSCR1: | |
688 | s->sscr[1] = value; | |
689 | if (value & (SSCR1_LBM | SSCR1_EFWR)) | |
a89f364a | 690 | printf("%s: Attempt to use SSP test mode\n", __func__); |
c1713132 AZ |
691 | pxa2xx_ssp_fifo_update(s); |
692 | break; | |
693 | ||
694 | case SSPSP: | |
695 | s->sspsp = value; | |
696 | break; | |
697 | ||
698 | case SSTO: | |
699 | s->ssto = value; | |
700 | break; | |
701 | ||
702 | case SSITR: | |
703 | s->ssitr = value & SSITR_INT; | |
704 | pxa2xx_ssp_int_update(s); | |
705 | break; | |
706 | ||
707 | case SSSR: | |
708 | s->sssr &= ~(value & SSSR_RW); | |
709 | pxa2xx_ssp_int_update(s); | |
710 | break; | |
711 | ||
712 | case SSDR: | |
713 | if (SSCR0_UWIRE(s->sscr[0])) { | |
714 | if (s->sscr[1] & SSCR1_MWDS) | |
715 | value &= 0xffff; | |
716 | else | |
717 | value &= 0xff; | |
718 | } else | |
719 | /* Note how 32bits overflow does no harm here */ | |
720 | value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; | |
721 | ||
722 | /* Data goes from here to the Tx FIFO and is shifted out from | |
723 | * there directly to the slave, no need to buffer it. | |
724 | */ | |
725 | if (s->enable) { | |
a984a69e PB |
726 | uint32_t readval; |
727 | readval = ssi_transfer(s->bus, value); | |
c1713132 | 728 | if (s->rx_level < 0x10) { |
a984a69e PB |
729 | s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; |
730 | } else { | |
c1713132 | 731 | s->sssr |= SSSR_ROR; |
a984a69e | 732 | } |
c1713132 AZ |
733 | } |
734 | pxa2xx_ssp_fifo_update(s); | |
735 | break; | |
736 | ||
737 | case SSTSA: | |
738 | s->sstsa = value; | |
739 | break; | |
740 | ||
741 | case SSRSA: | |
742 | s->ssrsa = value; | |
743 | break; | |
744 | ||
745 | case SSACD: | |
746 | s->ssacd = value; | |
747 | break; | |
748 | ||
749 | default: | |
fc417e5b PMD |
750 | qemu_log_mask(LOG_GUEST_ERROR, |
751 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
752 | __func__, addr); | |
c1713132 AZ |
753 | break; |
754 | } | |
755 | } | |
756 | ||
9c843933 AK |
757 | static const MemoryRegionOps pxa2xx_ssp_ops = { |
758 | .read = pxa2xx_ssp_read, | |
759 | .write = pxa2xx_ssp_write, | |
760 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
761 | }; |
762 | ||
ce320346 PM |
763 | static void pxa2xx_ssp_reset(DeviceState *d) |
764 | { | |
765 | PXA2xxSSPState *s = PXA2XX_SSP(d); | |
766 | ||
767 | s->enable = 0; | |
768 | s->sscr[0] = s->sscr[1] = 0; | |
769 | s->sspsp = 0; | |
770 | s->ssto = 0; | |
771 | s->ssitr = 0; | |
772 | s->sssr = 0; | |
773 | s->sstsa = 0; | |
774 | s->ssrsa = 0; | |
775 | s->ssacd = 0; | |
776 | s->rx_start = s->rx_level = 0; | |
777 | } | |
778 | ||
0493a139 | 779 | static void pxa2xx_ssp_init(Object *obj) |
a984a69e | 780 | { |
0493a139 SS |
781 | DeviceState *dev = DEVICE(obj); |
782 | PXA2xxSSPState *s = PXA2XX_SSP(obj); | |
783 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
12a82804 | 784 | sysbus_init_irq(sbd, &s->irq); |
a984a69e | 785 | |
0493a139 | 786 | memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, |
64bde0f3 | 787 | "pxa2xx-ssp", 0x1000); |
12a82804 | 788 | sysbus_init_mmio(sbd, &s->iomem); |
a984a69e | 789 | |
12a82804 | 790 | s->bus = ssi_create_bus(dev, "ssi"); |
a984a69e PB |
791 | } |
792 | ||
c1713132 AZ |
793 | /* Real-Time Clock */ |
794 | #define RCNR 0x00 /* RTC Counter register */ | |
795 | #define RTAR 0x04 /* RTC Alarm register */ | |
796 | #define RTSR 0x08 /* RTC Status register */ | |
797 | #define RTTR 0x0c /* RTC Timer Trim register */ | |
798 | #define RDCR 0x10 /* RTC Day Counter register */ | |
799 | #define RYCR 0x14 /* RTC Year Counter register */ | |
800 | #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ | |
801 | #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ | |
802 | #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ | |
803 | #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ | |
804 | #define SWCR 0x28 /* RTC Stopwatch Counter register */ | |
805 | #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ | |
806 | #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ | |
807 | #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ | |
808 | #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ | |
809 | ||
548c6f18 AF |
810 | #define TYPE_PXA2XX_RTC "pxa2xx_rtc" |
811 | #define PXA2XX_RTC(obj) \ | |
812 | OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) | |
813 | ||
8a231487 | 814 | typedef struct { |
548c6f18 AF |
815 | /*< private >*/ |
816 | SysBusDevice parent_obj; | |
817 | /*< public >*/ | |
818 | ||
9c843933 | 819 | MemoryRegion iomem; |
8a231487 AZ |
820 | uint32_t rttr; |
821 | uint32_t rtsr; | |
822 | uint32_t rtar; | |
823 | uint32_t rdar1; | |
824 | uint32_t rdar2; | |
825 | uint32_t ryar1; | |
826 | uint32_t ryar2; | |
827 | uint32_t swar1; | |
828 | uint32_t swar2; | |
829 | uint32_t piar; | |
830 | uint32_t last_rcnr; | |
831 | uint32_t last_rdcr; | |
832 | uint32_t last_rycr; | |
833 | uint32_t last_swcr; | |
834 | uint32_t last_rtcpicr; | |
835 | int64_t last_hz; | |
836 | int64_t last_sw; | |
837 | int64_t last_pi; | |
838 | QEMUTimer *rtc_hz; | |
839 | QEMUTimer *rtc_rdal1; | |
840 | QEMUTimer *rtc_rdal2; | |
841 | QEMUTimer *rtc_swal1; | |
842 | QEMUTimer *rtc_swal2; | |
843 | QEMUTimer *rtc_pi; | |
844 | qemu_irq rtc_irq; | |
845 | } PXA2xxRTCState; | |
846 | ||
847 | static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) | |
c1713132 | 848 | { |
e1f8c729 | 849 | qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); |
c1713132 AZ |
850 | } |
851 | ||
8a231487 | 852 | static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) |
c1713132 | 853 | { |
884f17c2 | 854 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
855 | s->last_rcnr += ((rt - s->last_hz) << 15) / |
856 | (1000 * ((s->rttr & 0xffff) + 1)); | |
857 | s->last_rdcr += ((rt - s->last_hz) << 15) / | |
858 | (1000 * ((s->rttr & 0xffff) + 1)); | |
859 | s->last_hz = rt; | |
860 | } | |
861 | ||
8a231487 | 862 | static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) |
c1713132 | 863 | { |
884f17c2 | 864 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
865 | if (s->rtsr & (1 << 12)) |
866 | s->last_swcr += (rt - s->last_sw) / 10; | |
867 | s->last_sw = rt; | |
868 | } | |
869 | ||
8a231487 | 870 | static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) |
c1713132 | 871 | { |
884f17c2 | 872 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
873 | if (s->rtsr & (1 << 15)) |
874 | s->last_swcr += rt - s->last_pi; | |
875 | s->last_pi = rt; | |
876 | } | |
877 | ||
8a231487 | 878 | static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, |
c1713132 AZ |
879 | uint32_t rtsr) |
880 | { | |
881 | if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) | |
bc72ad67 | 882 | timer_mod(s->rtc_hz, s->last_hz + |
c1713132 AZ |
883 | (((s->rtar - s->last_rcnr) * 1000 * |
884 | ((s->rttr & 0xffff) + 1)) >> 15)); | |
885 | else | |
bc72ad67 | 886 | timer_del(s->rtc_hz); |
c1713132 AZ |
887 | |
888 | if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) | |
bc72ad67 | 889 | timer_mod(s->rtc_rdal1, s->last_hz + |
c1713132 AZ |
890 | (((s->rdar1 - s->last_rdcr) * 1000 * |
891 | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ | |
892 | else | |
bc72ad67 | 893 | timer_del(s->rtc_rdal1); |
c1713132 AZ |
894 | |
895 | if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) | |
bc72ad67 | 896 | timer_mod(s->rtc_rdal2, s->last_hz + |
c1713132 AZ |
897 | (((s->rdar2 - s->last_rdcr) * 1000 * |
898 | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ | |
899 | else | |
bc72ad67 | 900 | timer_del(s->rtc_rdal2); |
c1713132 AZ |
901 | |
902 | if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) | |
bc72ad67 | 903 | timer_mod(s->rtc_swal1, s->last_sw + |
c1713132 AZ |
904 | (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
905 | else | |
bc72ad67 | 906 | timer_del(s->rtc_swal1); |
c1713132 AZ |
907 | |
908 | if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) | |
bc72ad67 | 909 | timer_mod(s->rtc_swal2, s->last_sw + |
c1713132 AZ |
910 | (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
911 | else | |
bc72ad67 | 912 | timer_del(s->rtc_swal2); |
c1713132 AZ |
913 | |
914 | if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) | |
bc72ad67 | 915 | timer_mod(s->rtc_pi, s->last_pi + |
c1713132 AZ |
916 | (s->piar & 0xffff) - s->last_rtcpicr); |
917 | else | |
bc72ad67 | 918 | timer_del(s->rtc_pi); |
c1713132 AZ |
919 | } |
920 | ||
921 | static inline void pxa2xx_rtc_hz_tick(void *opaque) | |
922 | { | |
8a231487 | 923 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
924 | s->rtsr |= (1 << 0); |
925 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
926 | pxa2xx_rtc_int_update(s); | |
927 | } | |
928 | ||
929 | static inline void pxa2xx_rtc_rdal1_tick(void *opaque) | |
930 | { | |
8a231487 | 931 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
932 | s->rtsr |= (1 << 4); |
933 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
934 | pxa2xx_rtc_int_update(s); | |
935 | } | |
936 | ||
937 | static inline void pxa2xx_rtc_rdal2_tick(void *opaque) | |
938 | { | |
8a231487 | 939 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
940 | s->rtsr |= (1 << 6); |
941 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
942 | pxa2xx_rtc_int_update(s); | |
943 | } | |
944 | ||
945 | static inline void pxa2xx_rtc_swal1_tick(void *opaque) | |
946 | { | |
8a231487 | 947 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
948 | s->rtsr |= (1 << 8); |
949 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
950 | pxa2xx_rtc_int_update(s); | |
951 | } | |
952 | ||
953 | static inline void pxa2xx_rtc_swal2_tick(void *opaque) | |
954 | { | |
8a231487 | 955 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
956 | s->rtsr |= (1 << 10); |
957 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
958 | pxa2xx_rtc_int_update(s); | |
959 | } | |
960 | ||
961 | static inline void pxa2xx_rtc_pi_tick(void *opaque) | |
962 | { | |
8a231487 | 963 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
964 | s->rtsr |= (1 << 13); |
965 | pxa2xx_rtc_piupdate(s); | |
966 | s->last_rtcpicr = 0; | |
967 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
968 | pxa2xx_rtc_int_update(s); | |
969 | } | |
970 | ||
a8170e5e | 971 | static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, |
9c843933 | 972 | unsigned size) |
c1713132 | 973 | { |
8a231487 | 974 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
975 | |
976 | switch (addr) { | |
977 | case RTTR: | |
978 | return s->rttr; | |
979 | case RTSR: | |
980 | return s->rtsr; | |
981 | case RTAR: | |
982 | return s->rtar; | |
983 | case RDAR1: | |
984 | return s->rdar1; | |
985 | case RDAR2: | |
986 | return s->rdar2; | |
987 | case RYAR1: | |
988 | return s->ryar1; | |
989 | case RYAR2: | |
990 | return s->ryar2; | |
991 | case SWAR1: | |
992 | return s->swar1; | |
993 | case SWAR2: | |
994 | return s->swar2; | |
995 | case PIAR: | |
996 | return s->piar; | |
997 | case RCNR: | |
884f17c2 AB |
998 | return s->last_rcnr + |
999 | ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / | |
1000 | (1000 * ((s->rttr & 0xffff) + 1)); | |
c1713132 | 1001 | case RDCR: |
884f17c2 AB |
1002 | return s->last_rdcr + |
1003 | ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / | |
1004 | (1000 * ((s->rttr & 0xffff) + 1)); | |
c1713132 AZ |
1005 | case RYCR: |
1006 | return s->last_rycr; | |
1007 | case SWCR: | |
1008 | if (s->rtsr & (1 << 12)) | |
884f17c2 AB |
1009 | return s->last_swcr + |
1010 | (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; | |
c1713132 AZ |
1011 | else |
1012 | return s->last_swcr; | |
1013 | default: | |
fc417e5b PMD |
1014 | qemu_log_mask(LOG_GUEST_ERROR, |
1015 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
1016 | __func__, addr); | |
c1713132 AZ |
1017 | break; |
1018 | } | |
1019 | return 0; | |
1020 | } | |
1021 | ||
a8170e5e | 1022 | static void pxa2xx_rtc_write(void *opaque, hwaddr addr, |
9c843933 | 1023 | uint64_t value64, unsigned size) |
c1713132 | 1024 | { |
8a231487 | 1025 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
9c843933 | 1026 | uint32_t value = value64; |
c1713132 AZ |
1027 | |
1028 | switch (addr) { | |
1029 | case RTTR: | |
43a32ed6 | 1030 | if (!(s->rttr & (1U << 31))) { |
c1713132 AZ |
1031 | pxa2xx_rtc_hzupdate(s); |
1032 | s->rttr = value; | |
1033 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1034 | } | |
1035 | break; | |
1036 | ||
1037 | case RTSR: | |
1038 | if ((s->rtsr ^ value) & (1 << 15)) | |
1039 | pxa2xx_rtc_piupdate(s); | |
1040 | ||
1041 | if ((s->rtsr ^ value) & (1 << 12)) | |
1042 | pxa2xx_rtc_swupdate(s); | |
1043 | ||
1044 | if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) | |
1045 | pxa2xx_rtc_alarm_update(s, value); | |
1046 | ||
1047 | s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); | |
1048 | pxa2xx_rtc_int_update(s); | |
1049 | break; | |
1050 | ||
1051 | case RTAR: | |
1052 | s->rtar = value; | |
1053 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1054 | break; | |
1055 | ||
1056 | case RDAR1: | |
1057 | s->rdar1 = value; | |
1058 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1059 | break; | |
1060 | ||
1061 | case RDAR2: | |
1062 | s->rdar2 = value; | |
1063 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1064 | break; | |
1065 | ||
1066 | case RYAR1: | |
1067 | s->ryar1 = value; | |
1068 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1069 | break; | |
1070 | ||
1071 | case RYAR2: | |
1072 | s->ryar2 = value; | |
1073 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1074 | break; | |
1075 | ||
1076 | case SWAR1: | |
1077 | pxa2xx_rtc_swupdate(s); | |
1078 | s->swar1 = value; | |
1079 | s->last_swcr = 0; | |
1080 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1081 | break; | |
1082 | ||
1083 | case SWAR2: | |
1084 | s->swar2 = value; | |
1085 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1086 | break; | |
1087 | ||
1088 | case PIAR: | |
1089 | s->piar = value; | |
1090 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1091 | break; | |
1092 | ||
1093 | case RCNR: | |
1094 | pxa2xx_rtc_hzupdate(s); | |
1095 | s->last_rcnr = value; | |
1096 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1097 | break; | |
1098 | ||
1099 | case RDCR: | |
1100 | pxa2xx_rtc_hzupdate(s); | |
1101 | s->last_rdcr = value; | |
1102 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1103 | break; | |
1104 | ||
1105 | case RYCR: | |
1106 | s->last_rycr = value; | |
1107 | break; | |
1108 | ||
1109 | case SWCR: | |
1110 | pxa2xx_rtc_swupdate(s); | |
1111 | s->last_swcr = value; | |
1112 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1113 | break; | |
1114 | ||
1115 | case RTCPICR: | |
1116 | pxa2xx_rtc_piupdate(s); | |
1117 | s->last_rtcpicr = value & 0xffff; | |
1118 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1119 | break; | |
1120 | ||
1121 | default: | |
fc417e5b PMD |
1122 | qemu_log_mask(LOG_GUEST_ERROR, |
1123 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
1124 | __func__, addr); | |
c1713132 AZ |
1125 | } |
1126 | } | |
1127 | ||
9c843933 AK |
1128 | static const MemoryRegionOps pxa2xx_rtc_ops = { |
1129 | .read = pxa2xx_rtc_read, | |
1130 | .write = pxa2xx_rtc_write, | |
1131 | .endianness = DEVICE_NATIVE_ENDIAN, | |
aa941b94 AZ |
1132 | }; |
1133 | ||
16fb31a3 | 1134 | static void pxa2xx_rtc_init(Object *obj) |
c1713132 | 1135 | { |
16fb31a3 XZ |
1136 | PXA2xxRTCState *s = PXA2XX_RTC(obj); |
1137 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
f6503059 | 1138 | struct tm tm; |
c1713132 AZ |
1139 | int wom; |
1140 | ||
1141 | s->rttr = 0x7fff; | |
1142 | s->rtsr = 0; | |
1143 | ||
f6503059 AZ |
1144 | qemu_get_timedate(&tm, 0); |
1145 | wom = ((tm.tm_mday - 1) / 7) + 1; | |
1146 | ||
0cd2df75 | 1147 | s->last_rcnr = (uint32_t) mktimegm(&tm); |
f6503059 AZ |
1148 | s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | |
1149 | (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; | |
1150 | s->last_rycr = ((tm.tm_year + 1900) << 9) | | |
1151 | ((tm.tm_mon + 1) << 5) | tm.tm_mday; | |
1152 | s->last_swcr = (tm.tm_hour << 19) | | |
1153 | (tm.tm_min << 13) | (tm.tm_sec << 7); | |
c1713132 | 1154 | s->last_rtcpicr = 0; |
884f17c2 AB |
1155 | s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); |
1156 | ||
1afaadb5 PN |
1157 | sysbus_init_irq(dev, &s->rtc_irq); |
1158 | ||
1159 | memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, | |
1160 | "pxa2xx-rtc", 0x10000); | |
1161 | sysbus_init_mmio(dev, &s->iomem); | |
1162 | } | |
1163 | ||
1164 | static void pxa2xx_rtc_realize(DeviceState *dev, Error **errp) | |
1165 | { | |
1166 | PXA2xxRTCState *s = PXA2XX_RTC(dev); | |
884f17c2 AB |
1167 | s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); |
1168 | s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); | |
1169 | s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); | |
1170 | s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); | |
1171 | s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); | |
1172 | s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); | |
c1713132 AZ |
1173 | } |
1174 | ||
44b1ff31 | 1175 | static int pxa2xx_rtc_pre_save(void *opaque) |
aa941b94 | 1176 | { |
8a231487 | 1177 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 | 1178 | |
aa941b94 AZ |
1179 | pxa2xx_rtc_hzupdate(s); |
1180 | pxa2xx_rtc_piupdate(s); | |
1181 | pxa2xx_rtc_swupdate(s); | |
44b1ff31 DDAG |
1182 | |
1183 | return 0; | |
8a231487 | 1184 | } |
aa941b94 | 1185 | |
8a231487 | 1186 | static int pxa2xx_rtc_post_load(void *opaque, int version_id) |
aa941b94 | 1187 | { |
8a231487 | 1188 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
aa941b94 AZ |
1189 | |
1190 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
c1713132 | 1194 | |
8a231487 AZ |
1195 | static const VMStateDescription vmstate_pxa2xx_rtc_regs = { |
1196 | .name = "pxa2xx_rtc", | |
1197 | .version_id = 0, | |
1198 | .minimum_version_id = 0, | |
8a231487 AZ |
1199 | .pre_save = pxa2xx_rtc_pre_save, |
1200 | .post_load = pxa2xx_rtc_post_load, | |
1201 | .fields = (VMStateField[]) { | |
1202 | VMSTATE_UINT32(rttr, PXA2xxRTCState), | |
1203 | VMSTATE_UINT32(rtsr, PXA2xxRTCState), | |
1204 | VMSTATE_UINT32(rtar, PXA2xxRTCState), | |
1205 | VMSTATE_UINT32(rdar1, PXA2xxRTCState), | |
1206 | VMSTATE_UINT32(rdar2, PXA2xxRTCState), | |
1207 | VMSTATE_UINT32(ryar1, PXA2xxRTCState), | |
1208 | VMSTATE_UINT32(ryar2, PXA2xxRTCState), | |
1209 | VMSTATE_UINT32(swar1, PXA2xxRTCState), | |
1210 | VMSTATE_UINT32(swar2, PXA2xxRTCState), | |
1211 | VMSTATE_UINT32(piar, PXA2xxRTCState), | |
1212 | VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), | |
1213 | VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), | |
1214 | VMSTATE_UINT32(last_rycr, PXA2xxRTCState), | |
1215 | VMSTATE_UINT32(last_swcr, PXA2xxRTCState), | |
1216 | VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), | |
1217 | VMSTATE_INT64(last_hz, PXA2xxRTCState), | |
1218 | VMSTATE_INT64(last_sw, PXA2xxRTCState), | |
1219 | VMSTATE_INT64(last_pi, PXA2xxRTCState), | |
1220 | VMSTATE_END_OF_LIST(), | |
1221 | }, | |
1222 | }; | |
1223 | ||
999e12bb AL |
1224 | static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) |
1225 | { | |
39bffca2 | 1226 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1227 | |
39bffca2 AL |
1228 | dc->desc = "PXA2xx RTC Controller"; |
1229 | dc->vmsd = &vmstate_pxa2xx_rtc_regs; | |
1afaadb5 | 1230 | dc->realize = pxa2xx_rtc_realize; |
999e12bb AL |
1231 | } |
1232 | ||
8c43a6f0 | 1233 | static const TypeInfo pxa2xx_rtc_sysbus_info = { |
548c6f18 | 1234 | .name = TYPE_PXA2XX_RTC, |
39bffca2 AL |
1235 | .parent = TYPE_SYS_BUS_DEVICE, |
1236 | .instance_size = sizeof(PXA2xxRTCState), | |
16fb31a3 | 1237 | .instance_init = pxa2xx_rtc_init, |
39bffca2 | 1238 | .class_init = pxa2xx_rtc_sysbus_class_init, |
8a231487 AZ |
1239 | }; |
1240 | ||
3f582262 | 1241 | /* I2C Interface */ |
96dca6b9 AF |
1242 | |
1243 | #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" | |
1244 | #define PXA2XX_I2C_SLAVE(obj) \ | |
1245 | OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) | |
1246 | ||
1247 | typedef struct PXA2xxI2CSlaveState { | |
1248 | I2CSlave parent_obj; | |
1249 | ||
e3b42536 PB |
1250 | PXA2xxI2CState *host; |
1251 | } PXA2xxI2CSlaveState; | |
1252 | ||
5354c21e AF |
1253 | #define TYPE_PXA2XX_I2C "pxa2xx_i2c" |
1254 | #define PXA2XX_I2C(obj) \ | |
1255 | OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) | |
1256 | ||
bc24a225 | 1257 | struct PXA2xxI2CState { |
5354c21e AF |
1258 | /*< private >*/ |
1259 | SysBusDevice parent_obj; | |
1260 | /*< public >*/ | |
1261 | ||
9c843933 | 1262 | MemoryRegion iomem; |
e3b42536 | 1263 | PXA2xxI2CSlaveState *slave; |
a5c82852 | 1264 | I2CBus *bus; |
3f582262 | 1265 | qemu_irq irq; |
c8ba63f8 DES |
1266 | uint32_t offset; |
1267 | uint32_t region_size; | |
3f582262 AZ |
1268 | |
1269 | uint16_t control; | |
1270 | uint16_t status; | |
1271 | uint8_t ibmr; | |
1272 | uint8_t data; | |
1273 | }; | |
1274 | ||
1275 | #define IBMR 0x80 /* I2C Bus Monitor register */ | |
1276 | #define IDBR 0x88 /* I2C Data Buffer register */ | |
1277 | #define ICR 0x90 /* I2C Control register */ | |
1278 | #define ISR 0x98 /* I2C Status register */ | |
1279 | #define ISAR 0xa0 /* I2C Slave Address register */ | |
1280 | ||
bc24a225 | 1281 | static void pxa2xx_i2c_update(PXA2xxI2CState *s) |
3f582262 AZ |
1282 | { |
1283 | uint16_t level = 0; | |
1284 | level |= s->status & s->control & (1 << 10); /* BED */ | |
1285 | level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ | |
1286 | level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ | |
1287 | level |= s->status & (1 << 9); /* SAD */ | |
1288 | qemu_set_irq(s->irq, !!level); | |
1289 | } | |
1290 | ||
1291 | /* These are only stubs now. */ | |
d307c28c | 1292 | static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) |
3f582262 | 1293 | { |
96dca6b9 | 1294 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1295 | PXA2xxI2CState *s = slave->host; |
3f582262 AZ |
1296 | |
1297 | switch (event) { | |
1298 | case I2C_START_SEND: | |
1299 | s->status |= (1 << 9); /* set SAD */ | |
1300 | s->status &= ~(1 << 0); /* clear RWM */ | |
1301 | break; | |
1302 | case I2C_START_RECV: | |
1303 | s->status |= (1 << 9); /* set SAD */ | |
1304 | s->status |= 1 << 0; /* set RWM */ | |
1305 | break; | |
1306 | case I2C_FINISH: | |
1307 | s->status |= (1 << 4); /* set SSD */ | |
1308 | break; | |
1309 | case I2C_NACK: | |
1310 | s->status |= 1 << 1; /* set ACKNAK */ | |
1311 | break; | |
1312 | } | |
1313 | pxa2xx_i2c_update(s); | |
d307c28c CM |
1314 | |
1315 | return 0; | |
3f582262 AZ |
1316 | } |
1317 | ||
2ac4c5f4 | 1318 | static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) |
3f582262 | 1319 | { |
96dca6b9 | 1320 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1321 | PXA2xxI2CState *s = slave->host; |
96dca6b9 AF |
1322 | |
1323 | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { | |
3f582262 | 1324 | return 0; |
96dca6b9 | 1325 | } |
3f582262 AZ |
1326 | |
1327 | if (s->status & (1 << 0)) { /* RWM */ | |
1328 | s->status |= 1 << 6; /* set ITE */ | |
1329 | } | |
1330 | pxa2xx_i2c_update(s); | |
1331 | ||
1332 | return s->data; | |
1333 | } | |
1334 | ||
9e07bdf8 | 1335 | static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) |
3f582262 | 1336 | { |
96dca6b9 | 1337 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1338 | PXA2xxI2CState *s = slave->host; |
96dca6b9 AF |
1339 | |
1340 | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { | |
3f582262 | 1341 | return 1; |
96dca6b9 | 1342 | } |
3f582262 AZ |
1343 | |
1344 | if (!(s->status & (1 << 0))) { /* RWM */ | |
1345 | s->status |= 1 << 7; /* set IRF */ | |
1346 | s->data = data; | |
1347 | } | |
1348 | pxa2xx_i2c_update(s); | |
1349 | ||
1350 | return 1; | |
1351 | } | |
1352 | ||
a8170e5e | 1353 | static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, |
9c843933 | 1354 | unsigned size) |
3f582262 | 1355 | { |
bc24a225 | 1356 | PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
96dca6b9 | 1357 | I2CSlave *slave; |
3f582262 | 1358 | |
ed005253 | 1359 | addr -= s->offset; |
3f582262 AZ |
1360 | switch (addr) { |
1361 | case ICR: | |
1362 | return s->control; | |
1363 | case ISR: | |
1364 | return s->status | (i2c_bus_busy(s->bus) << 2); | |
1365 | case ISAR: | |
96dca6b9 AF |
1366 | slave = I2C_SLAVE(s->slave); |
1367 | return slave->address; | |
3f582262 AZ |
1368 | case IDBR: |
1369 | return s->data; | |
1370 | case IBMR: | |
1371 | if (s->status & (1 << 2)) | |
1372 | s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ | |
1373 | else | |
1374 | s->ibmr = 0; | |
1375 | return s->ibmr; | |
1376 | default: | |
fc417e5b PMD |
1377 | qemu_log_mask(LOG_GUEST_ERROR, |
1378 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
1379 | __func__, addr); | |
3f582262 AZ |
1380 | break; |
1381 | } | |
1382 | return 0; | |
1383 | } | |
1384 | ||
a8170e5e | 1385 | static void pxa2xx_i2c_write(void *opaque, hwaddr addr, |
9c843933 | 1386 | uint64_t value64, unsigned size) |
3f582262 | 1387 | { |
bc24a225 | 1388 | PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
9c843933 | 1389 | uint32_t value = value64; |
3f582262 | 1390 | int ack; |
3f582262 | 1391 | |
ed005253 | 1392 | addr -= s->offset; |
3f582262 AZ |
1393 | switch (addr) { |
1394 | case ICR: | |
1395 | s->control = value & 0xfff7; | |
1396 | if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ | |
1397 | /* TODO: slave mode */ | |
1398 | if (value & (1 << 0)) { /* START condition */ | |
1399 | if (s->data & 1) | |
1400 | s->status |= 1 << 0; /* set RWM */ | |
1401 | else | |
1402 | s->status &= ~(1 << 0); /* clear RWM */ | |
1403 | ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); | |
1404 | } else { | |
1405 | if (s->status & (1 << 0)) { /* RWM */ | |
1406 | s->data = i2c_recv(s->bus); | |
1407 | if (value & (1 << 2)) /* ACKNAK */ | |
1408 | i2c_nack(s->bus); | |
1409 | ack = 1; | |
1410 | } else | |
1411 | ack = !i2c_send(s->bus, s->data); | |
1412 | } | |
1413 | ||
1414 | if (value & (1 << 1)) /* STOP condition */ | |
1415 | i2c_end_transfer(s->bus); | |
1416 | ||
1417 | if (ack) { | |
1418 | if (value & (1 << 0)) /* START condition */ | |
1419 | s->status |= 1 << 6; /* set ITE */ | |
1420 | else | |
1421 | if (s->status & (1 << 0)) /* RWM */ | |
1422 | s->status |= 1 << 7; /* set IRF */ | |
1423 | else | |
1424 | s->status |= 1 << 6; /* set ITE */ | |
1425 | s->status &= ~(1 << 1); /* clear ACKNAK */ | |
1426 | } else { | |
1427 | s->status |= 1 << 6; /* set ITE */ | |
1428 | s->status |= 1 << 10; /* set BED */ | |
1429 | s->status |= 1 << 1; /* set ACKNAK */ | |
1430 | } | |
1431 | } | |
1432 | if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ | |
1433 | if (value & (1 << 4)) /* MA */ | |
1434 | i2c_end_transfer(s->bus); | |
1435 | pxa2xx_i2c_update(s); | |
1436 | break; | |
1437 | ||
1438 | case ISR: | |
1439 | s->status &= ~(value & 0x07f0); | |
1440 | pxa2xx_i2c_update(s); | |
1441 | break; | |
1442 | ||
1443 | case ISAR: | |
96dca6b9 | 1444 | i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); |
3f582262 AZ |
1445 | break; |
1446 | ||
1447 | case IDBR: | |
1448 | s->data = value & 0xff; | |
1449 | break; | |
1450 | ||
1451 | default: | |
fc417e5b PMD |
1452 | qemu_log_mask(LOG_GUEST_ERROR, |
1453 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
1454 | __func__, addr); | |
3f582262 AZ |
1455 | } |
1456 | } | |
1457 | ||
9c843933 AK |
1458 | static const MemoryRegionOps pxa2xx_i2c_ops = { |
1459 | .read = pxa2xx_i2c_read, | |
1460 | .write = pxa2xx_i2c_write, | |
1461 | .endianness = DEVICE_NATIVE_ENDIAN, | |
3f582262 AZ |
1462 | }; |
1463 | ||
0211364d JQ |
1464 | static const VMStateDescription vmstate_pxa2xx_i2c_slave = { |
1465 | .name = "pxa2xx_i2c_slave", | |
1466 | .version_id = 1, | |
1467 | .minimum_version_id = 1, | |
8f1e884b | 1468 | .fields = (VMStateField[]) { |
96dca6b9 | 1469 | VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), |
0211364d JQ |
1470 | VMSTATE_END_OF_LIST() |
1471 | } | |
1472 | }; | |
aa941b94 | 1473 | |
0211364d JQ |
1474 | static const VMStateDescription vmstate_pxa2xx_i2c = { |
1475 | .name = "pxa2xx_i2c", | |
1476 | .version_id = 1, | |
1477 | .minimum_version_id = 1, | |
8f1e884b | 1478 | .fields = (VMStateField[]) { |
0211364d JQ |
1479 | VMSTATE_UINT16(control, PXA2xxI2CState), |
1480 | VMSTATE_UINT16(status, PXA2xxI2CState), | |
1481 | VMSTATE_UINT8(ibmr, PXA2xxI2CState), | |
1482 | VMSTATE_UINT8(data, PXA2xxI2CState), | |
1483 | VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, | |
20bcf73f | 1484 | vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), |
0211364d JQ |
1485 | VMSTATE_END_OF_LIST() |
1486 | } | |
1487 | }; | |
aa941b94 | 1488 | |
999e12bb | 1489 | static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) |
b5ea9327 AL |
1490 | { |
1491 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | |
1492 | ||
b5ea9327 AL |
1493 | k->event = pxa2xx_i2c_event; |
1494 | k->recv = pxa2xx_i2c_rx; | |
1495 | k->send = pxa2xx_i2c_tx; | |
1496 | } | |
1497 | ||
8c43a6f0 | 1498 | static const TypeInfo pxa2xx_i2c_slave_info = { |
96dca6b9 | 1499 | .name = TYPE_PXA2XX_I2C_SLAVE, |
39bffca2 AL |
1500 | .parent = TYPE_I2C_SLAVE, |
1501 | .instance_size = sizeof(PXA2xxI2CSlaveState), | |
1502 | .class_init = pxa2xx_i2c_slave_class_init, | |
e3b42536 PB |
1503 | }; |
1504 | ||
a8170e5e | 1505 | PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, |
ed005253 | 1506 | qemu_irq irq, uint32_t region_size) |
3f582262 | 1507 | { |
e3b42536 | 1508 | DeviceState *dev; |
c8ba63f8 DES |
1509 | SysBusDevice *i2c_dev; |
1510 | PXA2xxI2CState *s; | |
a5c82852 | 1511 | I2CBus *i2cbus; |
c8ba63f8 | 1512 | |
3e80f690 | 1513 | dev = qdev_new(TYPE_PXA2XX_I2C); |
5354c21e AF |
1514 | qdev_prop_set_uint32(dev, "size", region_size + 1); |
1515 | qdev_prop_set_uint32(dev, "offset", base & region_size); | |
c8ba63f8 | 1516 | |
5354c21e | 1517 | i2c_dev = SYS_BUS_DEVICE(dev); |
3c6ef471 | 1518 | sysbus_realize_and_unref(i2c_dev, &error_fatal); |
c8ba63f8 DES |
1519 | sysbus_mmio_map(i2c_dev, 0, base & ~region_size); |
1520 | sysbus_connect_irq(i2c_dev, 0, irq); | |
e3b42536 | 1521 | |
5354c21e | 1522 | s = PXA2XX_I2C(i2c_dev); |
c701b35b | 1523 | /* FIXME: Should the slave device really be on a separate bus? */ |
be2f78b6 | 1524 | i2cbus = i2c_init_bus(dev, "dummy"); |
96dca6b9 AF |
1525 | dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); |
1526 | s->slave = PXA2XX_I2C_SLAVE(dev); | |
e3b42536 | 1527 | s->slave->host = s; |
3f582262 | 1528 | |
c8ba63f8 DES |
1529 | return s; |
1530 | } | |
1531 | ||
16fb31a3 | 1532 | static void pxa2xx_i2c_initfn(Object *obj) |
c8ba63f8 | 1533 | { |
16fb31a3 XZ |
1534 | DeviceState *dev = DEVICE(obj); |
1535 | PXA2xxI2CState *s = PXA2XX_I2C(obj); | |
1536 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
c8ba63f8 | 1537 | |
08426da7 | 1538 | s->bus = i2c_init_bus(dev, NULL); |
3f582262 | 1539 | |
16fb31a3 | 1540 | memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, |
64bde0f3 | 1541 | "pxa2xx-i2c", s->region_size); |
5354c21e AF |
1542 | sysbus_init_mmio(sbd, &s->iomem); |
1543 | sysbus_init_irq(sbd, &s->irq); | |
3f582262 AZ |
1544 | } |
1545 | ||
a5c82852 | 1546 | I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) |
3f582262 AZ |
1547 | { |
1548 | return s->bus; | |
1549 | } | |
1550 | ||
999e12bb AL |
1551 | static Property pxa2xx_i2c_properties[] = { |
1552 | DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), | |
1553 | DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), | |
1554 | DEFINE_PROP_END_OF_LIST(), | |
1555 | }; | |
1556 | ||
1557 | static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) | |
1558 | { | |
39bffca2 | 1559 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1560 | |
39bffca2 AL |
1561 | dc->desc = "PXA2xx I2C Bus Controller"; |
1562 | dc->vmsd = &vmstate_pxa2xx_i2c; | |
4f67d30b | 1563 | device_class_set_props(dc, pxa2xx_i2c_properties); |
999e12bb AL |
1564 | } |
1565 | ||
8c43a6f0 | 1566 | static const TypeInfo pxa2xx_i2c_info = { |
5354c21e | 1567 | .name = TYPE_PXA2XX_I2C, |
39bffca2 AL |
1568 | .parent = TYPE_SYS_BUS_DEVICE, |
1569 | .instance_size = sizeof(PXA2xxI2CState), | |
16fb31a3 | 1570 | .instance_init = pxa2xx_i2c_initfn, |
39bffca2 | 1571 | .class_init = pxa2xx_i2c_class_init, |
c8ba63f8 DES |
1572 | }; |
1573 | ||
c1713132 | 1574 | /* PXA Inter-IC Sound Controller */ |
bc24a225 | 1575 | static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) |
c1713132 AZ |
1576 | { |
1577 | i2s->rx_len = 0; | |
1578 | i2s->tx_len = 0; | |
1579 | i2s->fifo_len = 0; | |
1580 | i2s->clk = 0x1a; | |
1581 | i2s->control[0] = 0x00; | |
1582 | i2s->control[1] = 0x00; | |
1583 | i2s->status = 0x00; | |
1584 | i2s->mask = 0x00; | |
1585 | } | |
1586 | ||
1587 | #define SACR_TFTH(val) ((val >> 8) & 0xf) | |
1588 | #define SACR_RFTH(val) ((val >> 12) & 0xf) | |
1589 | #define SACR_DREC(val) (val & (1 << 3)) | |
1590 | #define SACR_DPRL(val) (val & (1 << 4)) | |
1591 | ||
bc24a225 | 1592 | static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) |
c1713132 AZ |
1593 | { |
1594 | int rfs, tfs; | |
1595 | rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && | |
1596 | !SACR_DREC(i2s->control[1]); | |
1597 | tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && | |
1598 | i2s->enable && !SACR_DPRL(i2s->control[1]); | |
1599 | ||
2115c019 AZ |
1600 | qemu_set_irq(i2s->rx_dma, rfs); |
1601 | qemu_set_irq(i2s->tx_dma, tfs); | |
c1713132 AZ |
1602 | |
1603 | i2s->status &= 0xe0; | |
59c0149b AZ |
1604 | if (i2s->fifo_len < 16 || !i2s->enable) |
1605 | i2s->status |= 1 << 0; /* TNF */ | |
c1713132 AZ |
1606 | if (i2s->rx_len) |
1607 | i2s->status |= 1 << 1; /* RNE */ | |
1608 | if (i2s->enable) | |
1609 | i2s->status |= 1 << 2; /* BSY */ | |
1610 | if (tfs) | |
1611 | i2s->status |= 1 << 3; /* TFS */ | |
1612 | if (rfs) | |
1613 | i2s->status |= 1 << 4; /* RFS */ | |
1614 | if (!(i2s->tx_len && i2s->enable)) | |
1615 | i2s->status |= i2s->fifo_len << 8; /* TFL */ | |
1616 | i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ | |
1617 | ||
1618 | qemu_set_irq(i2s->irq, i2s->status & i2s->mask); | |
1619 | } | |
1620 | ||
1621 | #define SACR0 0x00 /* Serial Audio Global Control register */ | |
1622 | #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ | |
1623 | #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ | |
1624 | #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ | |
1625 | #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ | |
1626 | #define SADIV 0x60 /* Serial Audio Clock Divider register */ | |
1627 | #define SADR 0x80 /* Serial Audio Data register */ | |
1628 | ||
a8170e5e | 1629 | static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, |
9c843933 | 1630 | unsigned size) |
c1713132 | 1631 | { |
bc24a225 | 1632 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 AZ |
1633 | |
1634 | switch (addr) { | |
1635 | case SACR0: | |
1636 | return s->control[0]; | |
1637 | case SACR1: | |
1638 | return s->control[1]; | |
1639 | case SASR0: | |
1640 | return s->status; | |
1641 | case SAIMR: | |
1642 | return s->mask; | |
1643 | case SAICR: | |
1644 | return 0; | |
1645 | case SADIV: | |
1646 | return s->clk; | |
1647 | case SADR: | |
1648 | if (s->rx_len > 0) { | |
1649 | s->rx_len --; | |
1650 | pxa2xx_i2s_update(s); | |
1651 | return s->codec_in(s->opaque); | |
1652 | } | |
1653 | return 0; | |
1654 | default: | |
fc417e5b PMD |
1655 | qemu_log_mask(LOG_GUEST_ERROR, |
1656 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
1657 | __func__, addr); | |
c1713132 AZ |
1658 | break; |
1659 | } | |
1660 | return 0; | |
1661 | } | |
1662 | ||
a8170e5e | 1663 | static void pxa2xx_i2s_write(void *opaque, hwaddr addr, |
9c843933 | 1664 | uint64_t value, unsigned size) |
c1713132 | 1665 | { |
bc24a225 | 1666 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 | 1667 | uint32_t *sample; |
c1713132 AZ |
1668 | |
1669 | switch (addr) { | |
1670 | case SACR0: | |
1671 | if (value & (1 << 3)) /* RST */ | |
1672 | pxa2xx_i2s_reset(s); | |
1673 | s->control[0] = value & 0xff3d; | |
1674 | if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ | |
1675 | for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) | |
1676 | s->codec_out(s->opaque, *sample); | |
1677 | s->status &= ~(1 << 7); /* I2SOFF */ | |
1678 | } | |
1679 | if (value & (1 << 4)) /* EFWR */ | |
a89f364a | 1680 | printf("%s: Attempt to use special function\n", __func__); |
9dda2465 | 1681 | s->enable = (value & 9) == 1; /* ENB && !RST*/ |
c1713132 AZ |
1682 | pxa2xx_i2s_update(s); |
1683 | break; | |
1684 | case SACR1: | |
1685 | s->control[1] = value & 0x0039; | |
1686 | if (value & (1 << 5)) /* ENLBF */ | |
a89f364a | 1687 | printf("%s: Attempt to use loopback function\n", __func__); |
c1713132 AZ |
1688 | if (value & (1 << 4)) /* DPRL */ |
1689 | s->fifo_len = 0; | |
1690 | pxa2xx_i2s_update(s); | |
1691 | break; | |
1692 | case SAIMR: | |
1693 | s->mask = value & 0x0078; | |
1694 | pxa2xx_i2s_update(s); | |
1695 | break; | |
1696 | case SAICR: | |
1697 | s->status &= ~(value & (3 << 5)); | |
1698 | pxa2xx_i2s_update(s); | |
1699 | break; | |
1700 | case SADIV: | |
1701 | s->clk = value & 0x007f; | |
1702 | break; | |
1703 | case SADR: | |
1704 | if (s->tx_len && s->enable) { | |
1705 | s->tx_len --; | |
1706 | pxa2xx_i2s_update(s); | |
1707 | s->codec_out(s->opaque, value); | |
1708 | } else if (s->fifo_len < 16) { | |
1709 | s->fifo[s->fifo_len ++] = value; | |
1710 | pxa2xx_i2s_update(s); | |
1711 | } | |
1712 | break; | |
1713 | default: | |
fc417e5b PMD |
1714 | qemu_log_mask(LOG_GUEST_ERROR, |
1715 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
1716 | __func__, addr); | |
c1713132 AZ |
1717 | } |
1718 | } | |
1719 | ||
9c843933 AK |
1720 | static const MemoryRegionOps pxa2xx_i2s_ops = { |
1721 | .read = pxa2xx_i2s_read, | |
1722 | .write = pxa2xx_i2s_write, | |
1723 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
1724 | }; |
1725 | ||
9f5dfe29 JQ |
1726 | static const VMStateDescription vmstate_pxa2xx_i2s = { |
1727 | .name = "pxa2xx_i2s", | |
1728 | .version_id = 0, | |
1729 | .minimum_version_id = 0, | |
8f1e884b | 1730 | .fields = (VMStateField[]) { |
9f5dfe29 JQ |
1731 | VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), |
1732 | VMSTATE_UINT32(status, PXA2xxI2SState), | |
1733 | VMSTATE_UINT32(mask, PXA2xxI2SState), | |
1734 | VMSTATE_UINT32(clk, PXA2xxI2SState), | |
1735 | VMSTATE_INT32(enable, PXA2xxI2SState), | |
1736 | VMSTATE_INT32(rx_len, PXA2xxI2SState), | |
1737 | VMSTATE_INT32(tx_len, PXA2xxI2SState), | |
1738 | VMSTATE_INT32(fifo_len, PXA2xxI2SState), | |
1739 | VMSTATE_END_OF_LIST() | |
1740 | } | |
1741 | }; | |
aa941b94 | 1742 | |
c1713132 AZ |
1743 | static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1744 | { | |
bc24a225 | 1745 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 AZ |
1746 | uint32_t *sample; |
1747 | ||
1748 | /* Signal FIFO errors */ | |
1749 | if (s->enable && s->tx_len) | |
1750 | s->status |= 1 << 5; /* TUR */ | |
1751 | if (s->enable && s->rx_len) | |
1752 | s->status |= 1 << 6; /* ROR */ | |
1753 | ||
1754 | /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to | |
1755 | * handle the cases where it makes a difference. */ | |
1756 | s->tx_len = tx - s->fifo_len; | |
1757 | s->rx_len = rx; | |
1758 | /* Note that is s->codec_out wasn't set, we wouldn't get called. */ | |
1759 | if (s->enable) | |
1760 | for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) | |
1761 | s->codec_out(s->opaque, *sample); | |
1762 | pxa2xx_i2s_update(s); | |
1763 | } | |
1764 | ||
9c843933 | 1765 | static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, |
a8170e5e | 1766 | hwaddr base, |
2115c019 | 1767 | qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) |
c1713132 | 1768 | { |
b45c03f5 | 1769 | PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); |
c1713132 | 1770 | |
c1713132 | 1771 | s->irq = irq; |
2115c019 AZ |
1772 | s->rx_dma = rx_dma; |
1773 | s->tx_dma = tx_dma; | |
c1713132 AZ |
1774 | s->data_req = pxa2xx_i2s_data_req; |
1775 | ||
1776 | pxa2xx_i2s_reset(s); | |
1777 | ||
2c9b15ca | 1778 | memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, |
9c843933 AK |
1779 | "pxa2xx-i2s", 0x100000); |
1780 | memory_region_add_subregion(sysmem, base, &s->iomem); | |
c1713132 | 1781 | |
9f5dfe29 | 1782 | vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); |
aa941b94 | 1783 | |
c1713132 AZ |
1784 | return s; |
1785 | } | |
1786 | ||
1787 | /* PXA Fast Infra-red Communications Port */ | |
1fd9f2df PM |
1788 | #define TYPE_PXA2XX_FIR "pxa2xx-fir" |
1789 | #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR) | |
1790 | ||
bc24a225 | 1791 | struct PXA2xxFIrState { |
1fd9f2df PM |
1792 | /*< private >*/ |
1793 | SysBusDevice parent_obj; | |
1794 | /*< public >*/ | |
1795 | ||
adfc39ea | 1796 | MemoryRegion iomem; |
c1713132 | 1797 | qemu_irq irq; |
2115c019 AZ |
1798 | qemu_irq rx_dma; |
1799 | qemu_irq tx_dma; | |
1fd9f2df | 1800 | uint32_t enable; |
becdfa00 | 1801 | CharBackend chr; |
c1713132 AZ |
1802 | |
1803 | uint8_t control[3]; | |
1804 | uint8_t status[2]; | |
1805 | ||
1fd9f2df PM |
1806 | uint32_t rx_len; |
1807 | uint32_t rx_start; | |
c1713132 AZ |
1808 | uint8_t rx_fifo[64]; |
1809 | }; | |
1810 | ||
1fd9f2df | 1811 | static void pxa2xx_fir_reset(DeviceState *d) |
c1713132 | 1812 | { |
1fd9f2df PM |
1813 | PXA2xxFIrState *s = PXA2XX_FIR(d); |
1814 | ||
c1713132 AZ |
1815 | s->control[0] = 0x00; |
1816 | s->control[1] = 0x00; | |
1817 | s->control[2] = 0x00; | |
1818 | s->status[0] = 0x00; | |
1819 | s->status[1] = 0x00; | |
1820 | s->enable = 0; | |
1821 | } | |
1822 | ||
bc24a225 | 1823 | static inline void pxa2xx_fir_update(PXA2xxFIrState *s) |
c1713132 AZ |
1824 | { |
1825 | static const int tresh[4] = { 8, 16, 32, 0 }; | |
1826 | int intr = 0; | |
1827 | if ((s->control[0] & (1 << 4)) && /* RXE */ | |
1828 | s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ | |
1829 | s->status[0] |= 1 << 4; /* RFS */ | |
1830 | else | |
1831 | s->status[0] &= ~(1 << 4); /* RFS */ | |
1832 | if (s->control[0] & (1 << 3)) /* TXE */ | |
1833 | s->status[0] |= 1 << 3; /* TFS */ | |
1834 | else | |
1835 | s->status[0] &= ~(1 << 3); /* TFS */ | |
1836 | if (s->rx_len) | |
1837 | s->status[1] |= 1 << 2; /* RNE */ | |
1838 | else | |
1839 | s->status[1] &= ~(1 << 2); /* RNE */ | |
1840 | if (s->control[0] & (1 << 4)) /* RXE */ | |
1841 | s->status[1] |= 1 << 0; /* RSY */ | |
1842 | else | |
1843 | s->status[1] &= ~(1 << 0); /* RSY */ | |
1844 | ||
1845 | intr |= (s->control[0] & (1 << 5)) && /* RIE */ | |
1846 | (s->status[0] & (1 << 4)); /* RFS */ | |
1847 | intr |= (s->control[0] & (1 << 6)) && /* TIE */ | |
1848 | (s->status[0] & (1 << 3)); /* TFS */ | |
1849 | intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ | |
1850 | (s->status[0] & (1 << 6)); /* EOC */ | |
1851 | intr |= (s->control[0] & (1 << 2)) && /* TUS */ | |
1852 | (s->status[0] & (1 << 1)); /* TUR */ | |
1853 | intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ | |
1854 | ||
2115c019 AZ |
1855 | qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); |
1856 | qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); | |
c1713132 AZ |
1857 | |
1858 | qemu_set_irq(s->irq, intr && s->enable); | |
1859 | } | |
1860 | ||
1861 | #define ICCR0 0x00 /* FICP Control register 0 */ | |
1862 | #define ICCR1 0x04 /* FICP Control register 1 */ | |
1863 | #define ICCR2 0x08 /* FICP Control register 2 */ | |
1864 | #define ICDR 0x0c /* FICP Data register */ | |
1865 | #define ICSR0 0x14 /* FICP Status register 0 */ | |
1866 | #define ICSR1 0x18 /* FICP Status register 1 */ | |
1867 | #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ | |
1868 | ||
a8170e5e | 1869 | static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, |
adfc39ea | 1870 | unsigned size) |
c1713132 | 1871 | { |
bc24a225 | 1872 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 | 1873 | uint8_t ret; |
c1713132 AZ |
1874 | |
1875 | switch (addr) { | |
1876 | case ICCR0: | |
1877 | return s->control[0]; | |
1878 | case ICCR1: | |
1879 | return s->control[1]; | |
1880 | case ICCR2: | |
1881 | return s->control[2]; | |
1882 | case ICDR: | |
1883 | s->status[0] &= ~0x01; | |
1884 | s->status[1] &= ~0x72; | |
1885 | if (s->rx_len) { | |
1886 | s->rx_len --; | |
1887 | ret = s->rx_fifo[s->rx_start ++]; | |
1888 | s->rx_start &= 63; | |
1889 | pxa2xx_fir_update(s); | |
1890 | return ret; | |
1891 | } | |
a89f364a | 1892 | printf("%s: Rx FIFO underrun.\n", __func__); |
c1713132 AZ |
1893 | break; |
1894 | case ICSR0: | |
1895 | return s->status[0]; | |
1896 | case ICSR1: | |
1897 | return s->status[1] | (1 << 3); /* TNF */ | |
1898 | case ICFOR: | |
1899 | return s->rx_len; | |
1900 | default: | |
fc417e5b PMD |
1901 | qemu_log_mask(LOG_GUEST_ERROR, |
1902 | "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | |
1903 | __func__, addr); | |
c1713132 AZ |
1904 | break; |
1905 | } | |
1906 | return 0; | |
1907 | } | |
1908 | ||
a8170e5e | 1909 | static void pxa2xx_fir_write(void *opaque, hwaddr addr, |
adfc39ea | 1910 | uint64_t value64, unsigned size) |
c1713132 | 1911 | { |
bc24a225 | 1912 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
adfc39ea | 1913 | uint32_t value = value64; |
c1713132 | 1914 | uint8_t ch; |
c1713132 AZ |
1915 | |
1916 | switch (addr) { | |
1917 | case ICCR0: | |
1918 | s->control[0] = value; | |
1919 | if (!(value & (1 << 4))) /* RXE */ | |
1920 | s->rx_len = s->rx_start = 0; | |
3ffd710e BS |
1921 | if (!(value & (1 << 3))) { /* TXE */ |
1922 | /* Nop */ | |
1923 | } | |
c1713132 AZ |
1924 | s->enable = value & 1; /* ITR */ |
1925 | if (!s->enable) | |
1926 | s->status[0] = 0; | |
1927 | pxa2xx_fir_update(s); | |
1928 | break; | |
1929 | case ICCR1: | |
1930 | s->control[1] = value; | |
1931 | break; | |
1932 | case ICCR2: | |
1933 | s->control[2] = value & 0x3f; | |
1934 | pxa2xx_fir_update(s); | |
1935 | break; | |
1936 | case ICDR: | |
becdfa00 | 1937 | if (s->control[2] & (1 << 2)) { /* TXP */ |
c1713132 | 1938 | ch = value; |
becdfa00 | 1939 | } else { |
c1713132 | 1940 | ch = ~value; |
becdfa00 | 1941 | } |
fa394ed6 | 1942 | if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ |
6ab3fc32 DB |
1943 | /* XXX this blocks entire thread. Rewrite to use |
1944 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 1945 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
becdfa00 | 1946 | } |
c1713132 AZ |
1947 | break; |
1948 | case ICSR0: | |
1949 | s->status[0] &= ~(value & 0x66); | |
1950 | pxa2xx_fir_update(s); | |
1951 | break; | |
1952 | case ICFOR: | |
1953 | break; | |
1954 | default: | |
fc417e5b PMD |
1955 | qemu_log_mask(LOG_GUEST_ERROR, |
1956 | "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | |
1957 | __func__, addr); | |
c1713132 AZ |
1958 | } |
1959 | } | |
1960 | ||
adfc39ea AK |
1961 | static const MemoryRegionOps pxa2xx_fir_ops = { |
1962 | .read = pxa2xx_fir_read, | |
1963 | .write = pxa2xx_fir_write, | |
1964 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
1965 | }; |
1966 | ||
1967 | static int pxa2xx_fir_is_empty(void *opaque) | |
1968 | { | |
bc24a225 | 1969 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 AZ |
1970 | return (s->rx_len < 64); |
1971 | } | |
1972 | ||
1973 | static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) | |
1974 | { | |
bc24a225 | 1975 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 AZ |
1976 | if (!(s->control[0] & (1 << 4))) /* RXE */ |
1977 | return; | |
1978 | ||
1979 | while (size --) { | |
1980 | s->status[1] |= 1 << 4; /* EOF */ | |
1981 | if (s->rx_len >= 64) { | |
1982 | s->status[1] |= 1 << 6; /* ROR */ | |
1983 | break; | |
1984 | } | |
1985 | ||
1986 | if (s->control[2] & (1 << 3)) /* RXP */ | |
1987 | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); | |
1988 | else | |
1989 | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); | |
1990 | } | |
1991 | ||
1992 | pxa2xx_fir_update(s); | |
1993 | } | |
1994 | ||
083b266f | 1995 | static void pxa2xx_fir_event(void *opaque, QEMUChrEvent event) |
c1713132 AZ |
1996 | { |
1997 | } | |
1998 | ||
1fd9f2df | 1999 | static void pxa2xx_fir_instance_init(Object *obj) |
aa941b94 | 2000 | { |
1fd9f2df PM |
2001 | PXA2xxFIrState *s = PXA2XX_FIR(obj); |
2002 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
aa941b94 | 2003 | |
81e0ab48 | 2004 | memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, |
1fd9f2df PM |
2005 | "pxa2xx-fir", 0x1000); |
2006 | sysbus_init_mmio(sbd, &s->iomem); | |
2007 | sysbus_init_irq(sbd, &s->irq); | |
2008 | sysbus_init_irq(sbd, &s->rx_dma); | |
2009 | sysbus_init_irq(sbd, &s->tx_dma); | |
aa941b94 AZ |
2010 | } |
2011 | ||
1fd9f2df | 2012 | static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) |
aa941b94 | 2013 | { |
1fd9f2df | 2014 | PXA2xxFIrState *s = PXA2XX_FIR(dev); |
aa941b94 | 2015 | |
fa394ed6 | 2016 | qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, |
81517ba3 AN |
2017 | pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, |
2018 | true); | |
1fd9f2df | 2019 | } |
aa941b94 | 2020 | |
1fd9f2df PM |
2021 | static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) |
2022 | { | |
2023 | PXA2xxFIrState *s = opaque; | |
aa941b94 | 2024 | |
8e079caf | 2025 | return s->rx_start < ARRAY_SIZE(s->rx_fifo); |
aa941b94 AZ |
2026 | } |
2027 | ||
1fd9f2df PM |
2028 | static const VMStateDescription pxa2xx_fir_vmsd = { |
2029 | .name = "pxa2xx-fir", | |
2030 | .version_id = 1, | |
2031 | .minimum_version_id = 1, | |
2032 | .fields = (VMStateField[]) { | |
2033 | VMSTATE_UINT32(enable, PXA2xxFIrState), | |
2034 | VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), | |
2035 | VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), | |
2036 | VMSTATE_UINT32(rx_len, PXA2xxFIrState), | |
2037 | VMSTATE_UINT32(rx_start, PXA2xxFIrState), | |
2038 | VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), | |
2039 | VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), | |
2040 | VMSTATE_END_OF_LIST() | |
2041 | } | |
2042 | }; | |
c1713132 | 2043 | |
1fd9f2df PM |
2044 | static Property pxa2xx_fir_properties[] = { |
2045 | DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), | |
2046 | DEFINE_PROP_END_OF_LIST(), | |
2047 | }; | |
c1713132 | 2048 | |
1fd9f2df PM |
2049 | static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) |
2050 | { | |
2051 | DeviceClass *dc = DEVICE_CLASS(klass); | |
c1713132 | 2052 | |
1fd9f2df PM |
2053 | dc->realize = pxa2xx_fir_realize; |
2054 | dc->vmsd = &pxa2xx_fir_vmsd; | |
4f67d30b | 2055 | device_class_set_props(dc, pxa2xx_fir_properties); |
1fd9f2df PM |
2056 | dc->reset = pxa2xx_fir_reset; |
2057 | } | |
c1713132 | 2058 | |
1fd9f2df PM |
2059 | static const TypeInfo pxa2xx_fir_info = { |
2060 | .name = TYPE_PXA2XX_FIR, | |
2061 | .parent = TYPE_SYS_BUS_DEVICE, | |
2062 | .instance_size = sizeof(PXA2xxFIrState), | |
2063 | .class_init = pxa2xx_fir_class_init, | |
2064 | .instance_init = pxa2xx_fir_instance_init, | |
2065 | }; | |
c1713132 | 2066 | |
1fd9f2df PM |
2067 | static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, |
2068 | hwaddr base, | |
2069 | qemu_irq irq, qemu_irq rx_dma, | |
2070 | qemu_irq tx_dma, | |
0ec7b3e7 | 2071 | Chardev *chr) |
1fd9f2df PM |
2072 | { |
2073 | DeviceState *dev; | |
2074 | SysBusDevice *sbd; | |
aa941b94 | 2075 | |
3e80f690 | 2076 | dev = qdev_new(TYPE_PXA2XX_FIR); |
1fd9f2df | 2077 | qdev_prop_set_chr(dev, "chardev", chr); |
1fd9f2df | 2078 | sbd = SYS_BUS_DEVICE(dev); |
3c6ef471 | 2079 | sysbus_realize_and_unref(sbd, &error_fatal); |
1fd9f2df PM |
2080 | sysbus_mmio_map(sbd, 0, base); |
2081 | sysbus_connect_irq(sbd, 0, irq); | |
2082 | sysbus_connect_irq(sbd, 1, rx_dma); | |
2083 | sysbus_connect_irq(sbd, 2, tx_dma); | |
2084 | return PXA2XX_FIR(dev); | |
c1713132 AZ |
2085 | } |
2086 | ||
38641a52 | 2087 | static void pxa2xx_reset(void *opaque, int line, int level) |
c1713132 | 2088 | { |
bc24a225 | 2089 | PXA2xxState *s = (PXA2xxState *) opaque; |
38641a52 | 2090 | |
c1713132 | 2091 | if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
43824588 | 2092 | cpu_reset(CPU(s->cpu)); |
c1713132 AZ |
2093 | /* TODO: reset peripherals */ |
2094 | } | |
2095 | } | |
2096 | ||
2097 | /* Initialise a PXA270 integrated chip (ARM based core). */ | |
a6dc4c2d | 2098 | PXA2xxState *pxa270_init(MemoryRegion *address_space, |
ba1ba5cc | 2099 | unsigned int sdram_size, const char *cpu_type) |
c1713132 | 2100 | { |
bc24a225 | 2101 | PXA2xxState *s; |
adfc39ea | 2102 | int i; |
751c6a17 | 2103 | DriveInfo *dinfo; |
b45c03f5 | 2104 | s = g_new0(PXA2xxState, 1); |
c1713132 | 2105 | |
ba1ba5cc | 2106 | if (strncmp(cpu_type, "pxa27", 5)) { |
c0dbca36 | 2107 | error_report("Machine requires a PXA27x processor"); |
4207117c AZ |
2108 | exit(1); |
2109 | } | |
8e953a65 | 2110 | |
ba1ba5cc | 2111 | s->cpu = ARM_CPU(cpu_create(cpu_type)); |
f3c7d038 | 2112 | s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); |
38641a52 | 2113 | |
d95b2f8d | 2114 | /* SDRAM & Internal Memory Storage */ |
98a99ce0 | 2115 | memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, |
f8ed85ac | 2116 | &error_fatal); |
adfc39ea | 2117 | memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
98a99ce0 | 2118 | memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, |
f8ed85ac | 2119 | &error_fatal); |
adfc39ea AK |
2120 | memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2121 | &s->internal); | |
d95b2f8d | 2122 | |
f161bcd0 | 2123 | s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); |
c1713132 | 2124 | |
e1f8c729 DES |
2125 | s->dma = pxa27x_dma_init(0x40000000, |
2126 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); | |
c1713132 | 2127 | |
797e9542 DES |
2128 | sysbus_create_varargs("pxa27x-timer", 0x40a00000, |
2129 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), | |
2130 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), | |
2131 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), | |
2132 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), | |
2133 | qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), | |
2134 | NULL); | |
a171fe39 | 2135 | |
55e5c285 | 2136 | s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); |
c1713132 | 2137 | |
751c6a17 | 2138 | dinfo = drive_get(IF_SD, 0, 0); |
a82929a2 TH |
2139 | if (!dinfo && !qtest_enabled()) { |
2140 | warn_report("missing SecureDigital device"); | |
e4bcb14c | 2141 | } |
fa1d36df | 2142 | s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, |
a82929a2 | 2143 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
2115c019 AZ |
2144 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2145 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), | |
2146 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); | |
a171fe39 | 2147 | |
fb50cfe4 | 2148 | for (i = 0; pxa270_serial[i].io_base; i++) { |
9bca0edb | 2149 | if (serial_hd(i)) { |
a6dc4c2d | 2150 | serial_mm_init(address_space, pxa270_serial[i].io_base, 2, |
fb50cfe4 | 2151 | qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), |
9bca0edb | 2152 | 14857000 / 16, serial_hd(i), |
fb50cfe4 RH |
2153 | DEVICE_NATIVE_ENDIAN); |
2154 | } else { | |
c1713132 | 2155 | break; |
fb50cfe4 RH |
2156 | } |
2157 | } | |
9bca0edb | 2158 | if (serial_hd(i)) |
adfc39ea | 2159 | s->fir = pxa2xx_fir_init(address_space, 0x40800000, |
e1f8c729 | 2160 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2115c019 AZ |
2161 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2162 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), | |
9bca0edb | 2163 | serial_hd(i)); |
c1713132 | 2164 | |
5a6fdd91 | 2165 | s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, |
e1f8c729 | 2166 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
a171fe39 | 2167 | |
c1713132 | 2168 | s->cm_base = 0x41300000; |
82d17978 | 2169 | s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
c1713132 | 2170 | s->clkcfg = 0x00000009; /* Turbo mode active */ |
2c9b15ca | 2171 | memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
adfc39ea | 2172 | memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
ae1f90de | 2173 | vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
c1713132 | 2174 | |
dc2a9045 | 2175 | pxa2xx_setup_cp14(s); |
c1713132 AZ |
2176 | |
2177 | s->mm_base = 0x48000000; | |
2178 | s->mm_regs[MDMRS >> 2] = 0x00020002; | |
2179 | s->mm_regs[MDREFR >> 2] = 0x03ca4000; | |
2180 | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ | |
2c9b15ca | 2181 | memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
adfc39ea | 2182 | memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
d102d495 | 2183 | vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
c1713132 | 2184 | |
2a163929 | 2185 | s->pm_base = 0x40f00000; |
2c9b15ca | 2186 | memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
adfc39ea | 2187 | memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
f0ab24ce | 2188 | vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2a163929 | 2189 | |
c1713132 | 2190 | for (i = 0; pxa27x_ssp[i].io_base; i ++); |
b45c03f5 | 2191 | s->ssp = g_new0(SSIBus *, i); |
c1713132 | 2192 | for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
a984a69e | 2193 | DeviceState *dev; |
12a82804 | 2194 | dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, |
e1f8c729 | 2195 | qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); |
02e2da45 | 2196 | s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
c1713132 AZ |
2197 | } |
2198 | ||
c92cfba8 EH |
2199 | sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2200 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); | |
a171fe39 | 2201 | |
354a8c06 BC |
2202 | s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2203 | s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); | |
a171fe39 | 2204 | |
548c6f18 | 2205 | sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, |
8a231487 | 2206 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
c1713132 | 2207 | |
e1f8c729 DES |
2208 | s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2209 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); | |
2210 | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, | |
2211 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); | |
c1713132 | 2212 | |
9c843933 | 2213 | s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, |
2115c019 AZ |
2214 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2215 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), | |
2216 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); | |
c1713132 | 2217 | |
6cd816b8 | 2218 | s->kp = pxa27x_keypad_init(address_space, 0x41500000, |
e1f8c729 | 2219 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
31b87f2e | 2220 | |
c1713132 | 2221 | /* GPIO1 resets the processor */ |
fe8f096b | 2222 | /* The handler can be overridden by board-specific code */ |
0bb53337 | 2223 | qdev_connect_gpio_out(s->gpio, 1, s->reset); |
c1713132 AZ |
2224 | return s; |
2225 | } | |
2226 | ||
2227 | /* Initialise a PXA255 integrated chip (ARM based core). */ | |
a6dc4c2d | 2228 | PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) |
c1713132 | 2229 | { |
bc24a225 | 2230 | PXA2xxState *s; |
adfc39ea | 2231 | int i; |
751c6a17 | 2232 | DriveInfo *dinfo; |
aaed909a | 2233 | |
b45c03f5 | 2234 | s = g_new0(PXA2xxState, 1); |
c1713132 | 2235 | |
ba1ba5cc | 2236 | s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); |
f3c7d038 | 2237 | s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); |
38641a52 | 2238 | |
d95b2f8d | 2239 | /* SDRAM & Internal Memory Storage */ |
98a99ce0 | 2240 | memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, |
f8ed85ac | 2241 | &error_fatal); |
adfc39ea | 2242 | memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
98a99ce0 | 2243 | memory_region_init_ram(&s->internal, NULL, "pxa255.internal", |
f8ed85ac | 2244 | PXA2XX_INTERNAL_SIZE, &error_fatal); |
adfc39ea AK |
2245 | memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2246 | &s->internal); | |
d95b2f8d | 2247 | |
f161bcd0 | 2248 | s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); |
c1713132 | 2249 | |
e1f8c729 DES |
2250 | s->dma = pxa255_dma_init(0x40000000, |
2251 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); | |
c1713132 | 2252 | |
797e9542 DES |
2253 | sysbus_create_varargs("pxa25x-timer", 0x40a00000, |
2254 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), | |
2255 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), | |
2256 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), | |
2257 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), | |
2258 | NULL); | |
a171fe39 | 2259 | |
55e5c285 | 2260 | s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); |
c1713132 | 2261 | |
751c6a17 | 2262 | dinfo = drive_get(IF_SD, 0, 0); |
a82929a2 TH |
2263 | if (!dinfo && !qtest_enabled()) { |
2264 | warn_report("missing SecureDigital device"); | |
e4bcb14c | 2265 | } |
fa1d36df | 2266 | s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, |
a82929a2 | 2267 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
2115c019 AZ |
2268 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2269 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), | |
2270 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); | |
a171fe39 | 2271 | |
fb50cfe4 | 2272 | for (i = 0; pxa255_serial[i].io_base; i++) { |
9bca0edb | 2273 | if (serial_hd(i)) { |
a6dc4c2d | 2274 | serial_mm_init(address_space, pxa255_serial[i].io_base, 2, |
fb50cfe4 | 2275 | qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), |
9bca0edb | 2276 | 14745600 / 16, serial_hd(i), |
fb50cfe4 | 2277 | DEVICE_NATIVE_ENDIAN); |
2d48377a | 2278 | } else { |
c1713132 | 2279 | break; |
2d48377a | 2280 | } |
fb50cfe4 | 2281 | } |
9bca0edb | 2282 | if (serial_hd(i)) |
adfc39ea | 2283 | s->fir = pxa2xx_fir_init(address_space, 0x40800000, |
e1f8c729 | 2284 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2115c019 AZ |
2285 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2286 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), | |
9bca0edb | 2287 | serial_hd(i)); |
c1713132 | 2288 | |
5a6fdd91 | 2289 | s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, |
e1f8c729 | 2290 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
a171fe39 | 2291 | |
c1713132 | 2292 | s->cm_base = 0x41300000; |
e9aff986 GR |
2293 | s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ |
2294 | s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ | |
2295 | ||
c1713132 | 2296 | s->clkcfg = 0x00000009; /* Turbo mode active */ |
2c9b15ca | 2297 | memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
adfc39ea | 2298 | memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
ae1f90de | 2299 | vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
c1713132 | 2300 | |
dc2a9045 | 2301 | pxa2xx_setup_cp14(s); |
c1713132 AZ |
2302 | |
2303 | s->mm_base = 0x48000000; | |
2304 | s->mm_regs[MDMRS >> 2] = 0x00020002; | |
2305 | s->mm_regs[MDREFR >> 2] = 0x03ca4000; | |
2306 | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ | |
2c9b15ca | 2307 | memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
adfc39ea | 2308 | memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
d102d495 | 2309 | vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
c1713132 | 2310 | |
2a163929 | 2311 | s->pm_base = 0x40f00000; |
2c9b15ca | 2312 | memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
adfc39ea | 2313 | memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
f0ab24ce | 2314 | vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2a163929 | 2315 | |
c1713132 | 2316 | for (i = 0; pxa255_ssp[i].io_base; i ++); |
b45c03f5 | 2317 | s->ssp = g_new0(SSIBus *, i); |
c1713132 | 2318 | for (i = 0; pxa255_ssp[i].io_base; i ++) { |
a984a69e | 2319 | DeviceState *dev; |
12a82804 | 2320 | dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, |
e1f8c729 | 2321 | qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); |
02e2da45 | 2322 | s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
c1713132 AZ |
2323 | } |
2324 | ||
354a8c06 BC |
2325 | s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2326 | s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); | |
a171fe39 | 2327 | |
548c6f18 | 2328 | sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, |
8a231487 | 2329 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
c1713132 | 2330 | |
e1f8c729 DES |
2331 | s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2332 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); | |
2333 | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, | |
2334 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); | |
c1713132 | 2335 | |
9c843933 | 2336 | s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, |
2115c019 AZ |
2337 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2338 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), | |
2339 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); | |
c1713132 AZ |
2340 | |
2341 | /* GPIO1 resets the processor */ | |
fe8f096b | 2342 | /* The handler can be overridden by board-specific code */ |
0bb53337 | 2343 | qdev_connect_gpio_out(s->gpio, 1, s->reset); |
c1713132 AZ |
2344 | return s; |
2345 | } | |
e3b42536 | 2346 | |
999e12bb AL |
2347 | static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) |
2348 | { | |
ce320346 | 2349 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2350 | |
ce320346 | 2351 | dc->reset = pxa2xx_ssp_reset; |
8e079caf | 2352 | dc->vmsd = &vmstate_pxa2xx_ssp; |
999e12bb AL |
2353 | } |
2354 | ||
8c43a6f0 | 2355 | static const TypeInfo pxa2xx_ssp_info = { |
12a82804 | 2356 | .name = TYPE_PXA2XX_SSP, |
39bffca2 AL |
2357 | .parent = TYPE_SYS_BUS_DEVICE, |
2358 | .instance_size = sizeof(PXA2xxSSPState), | |
0493a139 | 2359 | .instance_init = pxa2xx_ssp_init, |
39bffca2 | 2360 | .class_init = pxa2xx_ssp_class_init, |
999e12bb AL |
2361 | }; |
2362 | ||
83f7d43a | 2363 | static void pxa2xx_register_types(void) |
e3b42536 | 2364 | { |
39bffca2 AL |
2365 | type_register_static(&pxa2xx_i2c_slave_info); |
2366 | type_register_static(&pxa2xx_ssp_info); | |
2367 | type_register_static(&pxa2xx_i2c_info); | |
2368 | type_register_static(&pxa2xx_rtc_sysbus_info); | |
1fd9f2df | 2369 | type_register_static(&pxa2xx_fir_info); |
e3b42536 PB |
2370 | } |
2371 | ||
83f7d43a | 2372 | type_init(pxa2xx_register_types) |