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c1713132 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 processor support. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
c1713132 AZ |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
a8d25326 | 11 | #include "qemu-common.h" |
c0dbca36 | 12 | #include "qemu/error-report.h" |
0b8fa32f | 13 | #include "qemu/module.h" |
da34e65c | 14 | #include "qapi/error.h" |
4771d756 | 15 | #include "cpu.h" |
83c9f4ca | 16 | #include "hw/sysbus.h" |
d6454270 | 17 | #include "migration/vmstate.h" |
0d09e41a | 18 | #include "hw/arm/pxa.h" |
9c17d615 | 19 | #include "sysemu/sysemu.h" |
0d09e41a PB |
20 | #include "hw/char/serial.h" |
21 | #include "hw/i2c/i2c.h" | |
64552b6b | 22 | #include "hw/irq.h" |
8fd06719 | 23 | #include "hw/ssi/ssi.h" |
4d43a603 | 24 | #include "chardev/char-fe.h" |
9c17d615 | 25 | #include "sysemu/blockdev.h" |
a82929a2 | 26 | #include "sysemu/qtest.h" |
f348b6d1 | 27 | #include "qemu/cutils.h" |
c1713132 AZ |
28 | |
29 | static struct { | |
a8170e5e | 30 | hwaddr io_base; |
c1713132 AZ |
31 | int irqn; |
32 | } pxa255_serial[] = { | |
33 | { 0x40100000, PXA2XX_PIC_FFUART }, | |
34 | { 0x40200000, PXA2XX_PIC_BTUART }, | |
35 | { 0x40700000, PXA2XX_PIC_STUART }, | |
36 | { 0x41600000, PXA25X_PIC_HWUART }, | |
37 | { 0, 0 } | |
38 | }, pxa270_serial[] = { | |
39 | { 0x40100000, PXA2XX_PIC_FFUART }, | |
40 | { 0x40200000, PXA2XX_PIC_BTUART }, | |
41 | { 0x40700000, PXA2XX_PIC_STUART }, | |
42 | { 0, 0 } | |
43 | }; | |
44 | ||
fa58c156 | 45 | typedef struct PXASSPDef { |
a8170e5e | 46 | hwaddr io_base; |
c1713132 | 47 | int irqn; |
fa58c156 FB |
48 | } PXASSPDef; |
49 | ||
50 | #if 0 | |
51 | static PXASSPDef pxa250_ssp[] = { | |
c1713132 AZ |
52 | { 0x41000000, PXA2XX_PIC_SSP }, |
53 | { 0, 0 } | |
fa58c156 FB |
54 | }; |
55 | #endif | |
56 | ||
57 | static PXASSPDef pxa255_ssp[] = { | |
c1713132 AZ |
58 | { 0x41000000, PXA2XX_PIC_SSP }, |
59 | { 0x41400000, PXA25X_PIC_NSSP }, | |
60 | { 0, 0 } | |
fa58c156 FB |
61 | }; |
62 | ||
63 | #if 0 | |
64 | static PXASSPDef pxa26x_ssp[] = { | |
c1713132 AZ |
65 | { 0x41000000, PXA2XX_PIC_SSP }, |
66 | { 0x41400000, PXA25X_PIC_NSSP }, | |
67 | { 0x41500000, PXA26X_PIC_ASSP }, | |
68 | { 0, 0 } | |
fa58c156 FB |
69 | }; |
70 | #endif | |
71 | ||
72 | static PXASSPDef pxa27x_ssp[] = { | |
c1713132 AZ |
73 | { 0x41000000, PXA2XX_PIC_SSP }, |
74 | { 0x41700000, PXA27X_PIC_SSP2 }, | |
75 | { 0x41900000, PXA2XX_PIC_SSP3 }, | |
76 | { 0, 0 } | |
77 | }; | |
78 | ||
79 | #define PMCR 0x00 /* Power Manager Control register */ | |
80 | #define PSSR 0x04 /* Power Manager Sleep Status register */ | |
81 | #define PSPR 0x08 /* Power Manager Scratch-Pad register */ | |
82 | #define PWER 0x0c /* Power Manager Wake-Up Enable register */ | |
83 | #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ | |
84 | #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ | |
85 | #define PEDR 0x18 /* Power Manager Edge-Detect Status register */ | |
86 | #define PCFR 0x1c /* Power Manager General Configuration register */ | |
87 | #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ | |
88 | #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ | |
89 | #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ | |
90 | #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ | |
91 | #define RCSR 0x30 /* Reset Controller Status register */ | |
92 | #define PSLR 0x34 /* Power Manager Sleep Configuration register */ | |
93 | #define PTSR 0x38 /* Power Manager Standby Configuration register */ | |
94 | #define PVCR 0x40 /* Power Manager Voltage Change Control register */ | |
95 | #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ | |
96 | #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ | |
97 | #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ | |
98 | #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ | |
99 | #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ | |
100 | ||
a8170e5e | 101 | static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, |
adfc39ea | 102 | unsigned size) |
c1713132 | 103 | { |
bc24a225 | 104 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
105 | |
106 | switch (addr) { | |
107 | case PMCR ... PCMD31: | |
108 | if (addr & 3) | |
109 | goto fail; | |
110 | ||
111 | return s->pm_regs[addr >> 2]; | |
112 | default: | |
113 | fail: | |
a89f364a | 114 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
115 | break; |
116 | } | |
117 | return 0; | |
118 | } | |
119 | ||
a8170e5e | 120 | static void pxa2xx_pm_write(void *opaque, hwaddr addr, |
adfc39ea | 121 | uint64_t value, unsigned size) |
c1713132 | 122 | { |
bc24a225 | 123 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
124 | |
125 | switch (addr) { | |
126 | case PMCR: | |
afd4a652 PM |
127 | /* Clear the write-one-to-clear bits... */ |
128 | s->pm_regs[addr >> 2] &= ~(value & 0x2a); | |
129 | /* ...and set the plain r/w bits */ | |
7c64d297 | 130 | s->pm_regs[addr >> 2] &= ~0x15; |
c1713132 AZ |
131 | s->pm_regs[addr >> 2] |= value & 0x15; |
132 | break; | |
133 | ||
134 | case PSSR: /* Read-clean registers */ | |
135 | case RCSR: | |
136 | case PKSR: | |
137 | s->pm_regs[addr >> 2] &= ~value; | |
138 | break; | |
139 | ||
140 | default: /* Read-write registers */ | |
603ff776 | 141 | if (!(addr & 3)) { |
c1713132 AZ |
142 | s->pm_regs[addr >> 2] = value; |
143 | break; | |
144 | } | |
145 | ||
a89f364a | 146 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
147 | break; |
148 | } | |
149 | } | |
150 | ||
adfc39ea AK |
151 | static const MemoryRegionOps pxa2xx_pm_ops = { |
152 | .read = pxa2xx_pm_read, | |
153 | .write = pxa2xx_pm_write, | |
154 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
155 | }; |
156 | ||
f0ab24ce JQ |
157 | static const VMStateDescription vmstate_pxa2xx_pm = { |
158 | .name = "pxa2xx_pm", | |
159 | .version_id = 0, | |
160 | .minimum_version_id = 0, | |
8f1e884b | 161 | .fields = (VMStateField[]) { |
f0ab24ce JQ |
162 | VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40), |
163 | VMSTATE_END_OF_LIST() | |
164 | } | |
165 | }; | |
aa941b94 | 166 | |
c1713132 AZ |
167 | #define CCCR 0x00 /* Core Clock Configuration register */ |
168 | #define CKEN 0x04 /* Clock Enable register */ | |
169 | #define OSCC 0x08 /* Oscillator Configuration register */ | |
170 | #define CCSR 0x0c /* Core Clock Status register */ | |
171 | ||
a8170e5e | 172 | static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, |
adfc39ea | 173 | unsigned size) |
c1713132 | 174 | { |
bc24a225 | 175 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
176 | |
177 | switch (addr) { | |
178 | case CCCR: | |
179 | case CKEN: | |
180 | case OSCC: | |
181 | return s->cm_regs[addr >> 2]; | |
182 | ||
183 | case CCSR: | |
184 | return s->cm_regs[CCCR >> 2] | (3 << 28); | |
185 | ||
186 | default: | |
a89f364a | 187 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
188 | break; |
189 | } | |
190 | return 0; | |
191 | } | |
192 | ||
a8170e5e | 193 | static void pxa2xx_cm_write(void *opaque, hwaddr addr, |
adfc39ea | 194 | uint64_t value, unsigned size) |
c1713132 | 195 | { |
bc24a225 | 196 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
197 | |
198 | switch (addr) { | |
199 | case CCCR: | |
200 | case CKEN: | |
201 | s->cm_regs[addr >> 2] = value; | |
202 | break; | |
203 | ||
204 | case OSCC: | |
565d2895 | 205 | s->cm_regs[addr >> 2] &= ~0x6c; |
c1713132 | 206 | s->cm_regs[addr >> 2] |= value & 0x6e; |
565d2895 AZ |
207 | if ((value >> 1) & 1) /* OON */ |
208 | s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */ | |
c1713132 AZ |
209 | break; |
210 | ||
211 | default: | |
a89f364a | 212 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
213 | break; |
214 | } | |
215 | } | |
216 | ||
adfc39ea AK |
217 | static const MemoryRegionOps pxa2xx_cm_ops = { |
218 | .read = pxa2xx_cm_read, | |
219 | .write = pxa2xx_cm_write, | |
220 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
221 | }; |
222 | ||
ae1f90de JQ |
223 | static const VMStateDescription vmstate_pxa2xx_cm = { |
224 | .name = "pxa2xx_cm", | |
225 | .version_id = 0, | |
226 | .minimum_version_id = 0, | |
8f1e884b | 227 | .fields = (VMStateField[]) { |
ae1f90de JQ |
228 | VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4), |
229 | VMSTATE_UINT32(clkcfg, PXA2xxState), | |
230 | VMSTATE_UINT32(pmnc, PXA2xxState), | |
231 | VMSTATE_END_OF_LIST() | |
232 | } | |
233 | }; | |
aa941b94 | 234 | |
c4241c7d | 235 | static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri) |
c1713132 | 236 | { |
e2f8a44d | 237 | PXA2xxState *s = (PXA2xxState *)ri->opaque; |
c4241c7d | 238 | return s->clkcfg; |
e2f8a44d | 239 | } |
c1713132 | 240 | |
c4241c7d PM |
241 | static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, |
242 | uint64_t value) | |
e2f8a44d PM |
243 | { |
244 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
245 | s->clkcfg = value & 0xf; | |
246 | if (value & 2) { | |
247 | printf("%s: CPU frequency change attempt\n", __func__); | |
c1713132 | 248 | } |
c1713132 AZ |
249 | } |
250 | ||
c4241c7d PM |
251 | static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, |
252 | uint64_t value) | |
c1713132 | 253 | { |
e2f8a44d | 254 | PXA2xxState *s = (PXA2xxState *)ri->opaque; |
c1713132 AZ |
255 | static const char *pwrmode[8] = { |
256 | "Normal", "Idle", "Deep-idle", "Standby", | |
257 | "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", | |
258 | }; | |
259 | ||
e2f8a44d PM |
260 | if (value & 8) { |
261 | printf("%s: CPU voltage change attempt\n", __func__); | |
262 | } | |
263 | switch (value & 7) { | |
264 | case 0: | |
265 | /* Do nothing */ | |
c1713132 AZ |
266 | break; |
267 | ||
e2f8a44d PM |
268 | case 1: |
269 | /* Idle */ | |
43a32ed6 | 270 | if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */ |
c3affe56 | 271 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
e2f8a44d PM |
272 | break; |
273 | } | |
274 | /* Fall through. */ | |
275 | ||
276 | case 2: | |
277 | /* Deep-Idle */ | |
c3affe56 | 278 | cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT); |
e2f8a44d PM |
279 | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
280 | goto message; | |
281 | ||
282 | case 3: | |
4cc35614 PM |
283 | s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; |
284 | s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; | |
137feaa9 | 285 | s->cpu->env.cp15.sctlr_ns = 0; |
7ebd5f2e | 286 | s->cpu->env.cp15.cpacr_el1 = 0; |
7dd8c9af | 287 | s->cpu->env.cp15.ttbr0_el[1] = 0; |
0c17d68c | 288 | s->cpu->env.cp15.dacr_ns = 0; |
e2f8a44d PM |
289 | s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
290 | s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ | |
291 | ||
292 | /* | |
293 | * The scratch-pad register is almost universally used | |
294 | * for storing the return address on suspend. For the | |
295 | * lack of a resuming bootloader, perform a jump | |
296 | * directly to that address. | |
297 | */ | |
298 | memset(s->cpu->env.regs, 0, 4 * 15); | |
299 | s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; | |
c1713132 AZ |
300 | |
301 | #if 0 | |
e2f8a44d PM |
302 | buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ |
303 | cpu_physical_memory_write(0, &buffer, 4); | |
304 | buffer = s->pm_regs[PSPR >> 2]; | |
305 | cpu_physical_memory_write(8, &buffer, 4); | |
c1713132 AZ |
306 | #endif |
307 | ||
e2f8a44d | 308 | /* Suspend */ |
4917cf44 | 309 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); |
c1713132 | 310 | |
e2f8a44d | 311 | goto message; |
c1713132 AZ |
312 | |
313 | default: | |
e2f8a44d PM |
314 | message: |
315 | printf("%s: machine entered %s mode\n", __func__, | |
316 | pwrmode[value & 7]); | |
c1713132 | 317 | } |
c1713132 AZ |
318 | } |
319 | ||
c4241c7d | 320 | static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri) |
dc2a9045 PM |
321 | { |
322 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
c4241c7d | 323 | return s->pmnc; |
dc2a9045 PM |
324 | } |
325 | ||
c4241c7d PM |
326 | static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
327 | uint64_t value) | |
dc2a9045 PM |
328 | { |
329 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
330 | s->pmnc = value; | |
dc2a9045 PM |
331 | } |
332 | ||
c4241c7d | 333 | static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
dc2a9045 PM |
334 | { |
335 | PXA2xxState *s = (PXA2xxState *)ri->opaque; | |
336 | if (s->pmnc & 1) { | |
c4241c7d | 337 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
dc2a9045 | 338 | } else { |
c4241c7d | 339 | return 0; |
dc2a9045 | 340 | } |
dc2a9045 PM |
341 | } |
342 | ||
343 | static const ARMCPRegInfo pxa_cp_reginfo[] = { | |
f565235b PM |
344 | /* cp14 crm==1: perf registers */ |
345 | { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0, | |
14c3032a | 346 | .access = PL1_RW, .type = ARM_CP_IO, |
dc2a9045 PM |
347 | .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write }, |
348 | { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, | |
14c3032a | 349 | .access = PL1_RW, .type = ARM_CP_IO, |
dc2a9045 | 350 | .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore }, |
f565235b | 351 | { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 352 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 353 | { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 354 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 355 | { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0, |
dc2a9045 | 356 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b PM |
357 | /* cp14 crm==2: performance count registers */ |
358 | { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0, | |
dc2a9045 | 359 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f565235b | 360 | { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0, |
dc2a9045 PM |
361 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
362 | { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0, | |
363 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
364 | { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, | |
365 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
e2f8a44d PM |
366 | /* cp14 crn==6: CLKCFG */ |
367 | { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
14c3032a | 368 | .access = PL1_RW, .type = ARM_CP_IO, |
e2f8a44d PM |
369 | .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, |
370 | /* cp14 crn==7: PWRMODE */ | |
371 | { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, | |
14c3032a | 372 | .access = PL1_RW, .type = ARM_CP_IO, |
e2f8a44d | 373 | .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, |
dc2a9045 PM |
374 | REGINFO_SENTINEL |
375 | }; | |
376 | ||
377 | static void pxa2xx_setup_cp14(PXA2xxState *s) | |
378 | { | |
379 | define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s); | |
380 | } | |
381 | ||
c1713132 AZ |
382 | #define MDCNFG 0x00 /* SDRAM Configuration register */ |
383 | #define MDREFR 0x04 /* SDRAM Refresh Control register */ | |
384 | #define MSC0 0x08 /* Static Memory Control register 0 */ | |
385 | #define MSC1 0x0c /* Static Memory Control register 1 */ | |
386 | #define MSC2 0x10 /* Static Memory Control register 2 */ | |
387 | #define MECR 0x14 /* Expansion Memory Bus Config register */ | |
388 | #define SXCNFG 0x1c /* Synchronous Static Memory Config register */ | |
389 | #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ | |
390 | #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ | |
391 | #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ | |
392 | #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ | |
393 | #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ | |
394 | #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ | |
395 | #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ | |
396 | #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ | |
397 | #define ARB_CNTL 0x48 /* Arbiter Control register */ | |
398 | #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ | |
399 | #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ | |
400 | #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ | |
401 | #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ | |
402 | #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ | |
403 | #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ | |
404 | #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ | |
405 | ||
a8170e5e | 406 | static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, |
adfc39ea | 407 | unsigned size) |
c1713132 | 408 | { |
bc24a225 | 409 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
410 | |
411 | switch (addr) { | |
412 | case MDCNFG ... SA1110: | |
413 | if ((addr & 3) == 0) | |
414 | return s->mm_regs[addr >> 2]; | |
edd7541b | 415 | /* fall through */ |
c1713132 | 416 | default: |
a89f364a | 417 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
418 | break; |
419 | } | |
420 | return 0; | |
421 | } | |
422 | ||
a8170e5e | 423 | static void pxa2xx_mm_write(void *opaque, hwaddr addr, |
adfc39ea | 424 | uint64_t value, unsigned size) |
c1713132 | 425 | { |
bc24a225 | 426 | PXA2xxState *s = (PXA2xxState *) opaque; |
c1713132 AZ |
427 | |
428 | switch (addr) { | |
429 | case MDCNFG ... SA1110: | |
430 | if ((addr & 3) == 0) { | |
431 | s->mm_regs[addr >> 2] = value; | |
432 | break; | |
433 | } | |
434 | ||
435 | default: | |
a89f364a | 436 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
437 | break; |
438 | } | |
439 | } | |
440 | ||
adfc39ea AK |
441 | static const MemoryRegionOps pxa2xx_mm_ops = { |
442 | .read = pxa2xx_mm_read, | |
443 | .write = pxa2xx_mm_write, | |
444 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
445 | }; |
446 | ||
d102d495 JQ |
447 | static const VMStateDescription vmstate_pxa2xx_mm = { |
448 | .name = "pxa2xx_mm", | |
449 | .version_id = 0, | |
450 | .minimum_version_id = 0, | |
8f1e884b | 451 | .fields = (VMStateField[]) { |
d102d495 JQ |
452 | VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a), |
453 | VMSTATE_END_OF_LIST() | |
454 | } | |
455 | }; | |
aa941b94 | 456 | |
12a82804 AF |
457 | #define TYPE_PXA2XX_SSP "pxa2xx-ssp" |
458 | #define PXA2XX_SSP(obj) \ | |
459 | OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP) | |
460 | ||
c1713132 | 461 | /* Synchronous Serial Ports */ |
a984a69e | 462 | typedef struct { |
12a82804 AF |
463 | /*< private >*/ |
464 | SysBusDevice parent_obj; | |
465 | /*< public >*/ | |
466 | ||
9c843933 | 467 | MemoryRegion iomem; |
c1713132 | 468 | qemu_irq irq; |
8e079caf | 469 | uint32_t enable; |
a984a69e | 470 | SSIBus *bus; |
c1713132 AZ |
471 | |
472 | uint32_t sscr[2]; | |
473 | uint32_t sspsp; | |
474 | uint32_t ssto; | |
475 | uint32_t ssitr; | |
476 | uint32_t sssr; | |
477 | uint8_t sstsa; | |
478 | uint8_t ssrsa; | |
479 | uint8_t ssacd; | |
480 | ||
481 | uint32_t rx_fifo[16]; | |
8e079caf PM |
482 | uint32_t rx_level; |
483 | uint32_t rx_start; | |
a984a69e | 484 | } PXA2xxSSPState; |
c1713132 | 485 | |
8e079caf PM |
486 | static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id) |
487 | { | |
488 | PXA2xxSSPState *s = opaque; | |
489 | ||
490 | return s->rx_start < sizeof(s->rx_fifo); | |
491 | } | |
492 | ||
493 | static const VMStateDescription vmstate_pxa2xx_ssp = { | |
494 | .name = "pxa2xx-ssp", | |
495 | .version_id = 1, | |
496 | .minimum_version_id = 1, | |
497 | .fields = (VMStateField[]) { | |
498 | VMSTATE_UINT32(enable, PXA2xxSSPState), | |
499 | VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2), | |
500 | VMSTATE_UINT32(sspsp, PXA2xxSSPState), | |
501 | VMSTATE_UINT32(ssto, PXA2xxSSPState), | |
502 | VMSTATE_UINT32(ssitr, PXA2xxSSPState), | |
503 | VMSTATE_UINT32(sssr, PXA2xxSSPState), | |
504 | VMSTATE_UINT8(sstsa, PXA2xxSSPState), | |
505 | VMSTATE_UINT8(ssrsa, PXA2xxSSPState), | |
506 | VMSTATE_UINT8(ssacd, PXA2xxSSPState), | |
507 | VMSTATE_UINT32(rx_level, PXA2xxSSPState), | |
508 | VMSTATE_UINT32(rx_start, PXA2xxSSPState), | |
509 | VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate), | |
510 | VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16), | |
511 | VMSTATE_END_OF_LIST() | |
512 | } | |
513 | }; | |
514 | ||
c1713132 AZ |
515 | #define SSCR0 0x00 /* SSP Control register 0 */ |
516 | #define SSCR1 0x04 /* SSP Control register 1 */ | |
517 | #define SSSR 0x08 /* SSP Status register */ | |
518 | #define SSITR 0x0c /* SSP Interrupt Test register */ | |
519 | #define SSDR 0x10 /* SSP Data register */ | |
520 | #define SSTO 0x28 /* SSP Time-Out register */ | |
521 | #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ | |
522 | #define SSTSA 0x30 /* SSP TX Time Slot Active register */ | |
523 | #define SSRSA 0x34 /* SSP RX Time Slot Active register */ | |
524 | #define SSTSS 0x38 /* SSP Time Slot Status register */ | |
525 | #define SSACD 0x3c /* SSP Audio Clock Divider register */ | |
526 | ||
527 | /* Bitfields for above registers */ | |
528 | #define SSCR0_SPI(x) (((x) & 0x30) == 0x00) | |
529 | #define SSCR0_SSP(x) (((x) & 0x30) == 0x10) | |
530 | #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) | |
531 | #define SSCR0_PSP(x) (((x) & 0x30) == 0x30) | |
532 | #define SSCR0_SSE (1 << 7) | |
533 | #define SSCR0_RIM (1 << 22) | |
534 | #define SSCR0_TIM (1 << 23) | |
43a32ed6 | 535 | #define SSCR0_MOD (1U << 31) |
c1713132 AZ |
536 | #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
537 | #define SSCR1_RIE (1 << 0) | |
538 | #define SSCR1_TIE (1 << 1) | |
539 | #define SSCR1_LBM (1 << 2) | |
540 | #define SSCR1_MWDS (1 << 5) | |
541 | #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) | |
542 | #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) | |
543 | #define SSCR1_EFWR (1 << 14) | |
544 | #define SSCR1_PINTE (1 << 18) | |
545 | #define SSCR1_TINTE (1 << 19) | |
546 | #define SSCR1_RSRE (1 << 20) | |
547 | #define SSCR1_TSRE (1 << 21) | |
548 | #define SSCR1_EBCEI (1 << 29) | |
549 | #define SSITR_INT (7 << 5) | |
550 | #define SSSR_TNF (1 << 2) | |
551 | #define SSSR_RNE (1 << 3) | |
552 | #define SSSR_TFS (1 << 5) | |
553 | #define SSSR_RFS (1 << 6) | |
554 | #define SSSR_ROR (1 << 7) | |
555 | #define SSSR_PINT (1 << 18) | |
556 | #define SSSR_TINT (1 << 19) | |
557 | #define SSSR_EOC (1 << 20) | |
558 | #define SSSR_TUR (1 << 21) | |
559 | #define SSSR_BCE (1 << 23) | |
560 | #define SSSR_RW 0x00bc0080 | |
561 | ||
bc24a225 | 562 | static void pxa2xx_ssp_int_update(PXA2xxSSPState *s) |
c1713132 AZ |
563 | { |
564 | int level = 0; | |
565 | ||
566 | level |= s->ssitr & SSITR_INT; | |
567 | level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI); | |
568 | level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM); | |
569 | level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); | |
570 | level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE); | |
571 | level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE); | |
572 | level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM); | |
573 | level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE); | |
574 | level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE); | |
575 | qemu_set_irq(s->irq, !!level); | |
576 | } | |
577 | ||
bc24a225 | 578 | static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) |
c1713132 AZ |
579 | { |
580 | s->sssr &= ~(0xf << 12); /* Clear RFL */ | |
581 | s->sssr &= ~(0xf << 8); /* Clear TFL */ | |
7d147689 | 582 | s->sssr &= ~SSSR_TFS; |
c1713132 AZ |
583 | s->sssr &= ~SSSR_TNF; |
584 | if (s->enable) { | |
585 | s->sssr |= ((s->rx_level - 1) & 0xf) << 12; | |
586 | if (s->rx_level >= SSCR1_RFT(s->sscr[1])) | |
587 | s->sssr |= SSSR_RFS; | |
588 | else | |
589 | s->sssr &= ~SSSR_RFS; | |
c1713132 AZ |
590 | if (s->rx_level) |
591 | s->sssr |= SSSR_RNE; | |
592 | else | |
593 | s->sssr &= ~SSSR_RNE; | |
7d147689 BS |
594 | /* TX FIFO is never filled, so it is always in underrun |
595 | condition if SSP is enabled */ | |
596 | s->sssr |= SSSR_TFS; | |
c1713132 AZ |
597 | s->sssr |= SSSR_TNF; |
598 | } | |
599 | ||
600 | pxa2xx_ssp_int_update(s); | |
601 | } | |
602 | ||
a8170e5e | 603 | static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, |
9c843933 | 604 | unsigned size) |
c1713132 | 605 | { |
bc24a225 | 606 | PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
c1713132 | 607 | uint32_t retval; |
c1713132 AZ |
608 | |
609 | switch (addr) { | |
610 | case SSCR0: | |
611 | return s->sscr[0]; | |
612 | case SSCR1: | |
613 | return s->sscr[1]; | |
614 | case SSPSP: | |
615 | return s->sspsp; | |
616 | case SSTO: | |
617 | return s->ssto; | |
618 | case SSITR: | |
619 | return s->ssitr; | |
620 | case SSSR: | |
621 | return s->sssr | s->ssitr; | |
622 | case SSDR: | |
623 | if (!s->enable) | |
624 | return 0xffffffff; | |
625 | if (s->rx_level < 1) { | |
a89f364a | 626 | printf("%s: SSP Rx Underrun\n", __func__); |
c1713132 AZ |
627 | return 0xffffffff; |
628 | } | |
629 | s->rx_level --; | |
630 | retval = s->rx_fifo[s->rx_start ++]; | |
631 | s->rx_start &= 0xf; | |
632 | pxa2xx_ssp_fifo_update(s); | |
633 | return retval; | |
634 | case SSTSA: | |
635 | return s->sstsa; | |
636 | case SSRSA: | |
637 | return s->ssrsa; | |
638 | case SSTSS: | |
639 | return 0; | |
640 | case SSACD: | |
641 | return s->ssacd; | |
642 | default: | |
a89f364a | 643 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
644 | break; |
645 | } | |
646 | return 0; | |
647 | } | |
648 | ||
a8170e5e | 649 | static void pxa2xx_ssp_write(void *opaque, hwaddr addr, |
9c843933 | 650 | uint64_t value64, unsigned size) |
c1713132 | 651 | { |
bc24a225 | 652 | PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; |
9c843933 | 653 | uint32_t value = value64; |
c1713132 AZ |
654 | |
655 | switch (addr) { | |
656 | case SSCR0: | |
657 | s->sscr[0] = value & 0xc7ffffff; | |
658 | s->enable = value & SSCR0_SSE; | |
659 | if (value & SSCR0_MOD) | |
a89f364a | 660 | printf("%s: Attempt to use network mode\n", __func__); |
c1713132 | 661 | if (s->enable && SSCR0_DSS(value) < 4) |
a89f364a | 662 | printf("%s: Wrong data size: %i bits\n", __func__, |
c1713132 AZ |
663 | SSCR0_DSS(value)); |
664 | if (!(value & SSCR0_SSE)) { | |
665 | s->sssr = 0; | |
666 | s->ssitr = 0; | |
667 | s->rx_level = 0; | |
668 | } | |
669 | pxa2xx_ssp_fifo_update(s); | |
670 | break; | |
671 | ||
672 | case SSCR1: | |
673 | s->sscr[1] = value; | |
674 | if (value & (SSCR1_LBM | SSCR1_EFWR)) | |
a89f364a | 675 | printf("%s: Attempt to use SSP test mode\n", __func__); |
c1713132 AZ |
676 | pxa2xx_ssp_fifo_update(s); |
677 | break; | |
678 | ||
679 | case SSPSP: | |
680 | s->sspsp = value; | |
681 | break; | |
682 | ||
683 | case SSTO: | |
684 | s->ssto = value; | |
685 | break; | |
686 | ||
687 | case SSITR: | |
688 | s->ssitr = value & SSITR_INT; | |
689 | pxa2xx_ssp_int_update(s); | |
690 | break; | |
691 | ||
692 | case SSSR: | |
693 | s->sssr &= ~(value & SSSR_RW); | |
694 | pxa2xx_ssp_int_update(s); | |
695 | break; | |
696 | ||
697 | case SSDR: | |
698 | if (SSCR0_UWIRE(s->sscr[0])) { | |
699 | if (s->sscr[1] & SSCR1_MWDS) | |
700 | value &= 0xffff; | |
701 | else | |
702 | value &= 0xff; | |
703 | } else | |
704 | /* Note how 32bits overflow does no harm here */ | |
705 | value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; | |
706 | ||
707 | /* Data goes from here to the Tx FIFO and is shifted out from | |
708 | * there directly to the slave, no need to buffer it. | |
709 | */ | |
710 | if (s->enable) { | |
a984a69e PB |
711 | uint32_t readval; |
712 | readval = ssi_transfer(s->bus, value); | |
c1713132 | 713 | if (s->rx_level < 0x10) { |
a984a69e PB |
714 | s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; |
715 | } else { | |
c1713132 | 716 | s->sssr |= SSSR_ROR; |
a984a69e | 717 | } |
c1713132 AZ |
718 | } |
719 | pxa2xx_ssp_fifo_update(s); | |
720 | break; | |
721 | ||
722 | case SSTSA: | |
723 | s->sstsa = value; | |
724 | break; | |
725 | ||
726 | case SSRSA: | |
727 | s->ssrsa = value; | |
728 | break; | |
729 | ||
730 | case SSACD: | |
731 | s->ssacd = value; | |
732 | break; | |
733 | ||
734 | default: | |
a89f364a | 735 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
736 | break; |
737 | } | |
738 | } | |
739 | ||
9c843933 AK |
740 | static const MemoryRegionOps pxa2xx_ssp_ops = { |
741 | .read = pxa2xx_ssp_read, | |
742 | .write = pxa2xx_ssp_write, | |
743 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
744 | }; |
745 | ||
ce320346 PM |
746 | static void pxa2xx_ssp_reset(DeviceState *d) |
747 | { | |
748 | PXA2xxSSPState *s = PXA2XX_SSP(d); | |
749 | ||
750 | s->enable = 0; | |
751 | s->sscr[0] = s->sscr[1] = 0; | |
752 | s->sspsp = 0; | |
753 | s->ssto = 0; | |
754 | s->ssitr = 0; | |
755 | s->sssr = 0; | |
756 | s->sstsa = 0; | |
757 | s->ssrsa = 0; | |
758 | s->ssacd = 0; | |
759 | s->rx_start = s->rx_level = 0; | |
760 | } | |
761 | ||
0493a139 | 762 | static void pxa2xx_ssp_init(Object *obj) |
a984a69e | 763 | { |
0493a139 SS |
764 | DeviceState *dev = DEVICE(obj); |
765 | PXA2xxSSPState *s = PXA2XX_SSP(obj); | |
766 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
12a82804 | 767 | sysbus_init_irq(sbd, &s->irq); |
a984a69e | 768 | |
0493a139 | 769 | memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s, |
64bde0f3 | 770 | "pxa2xx-ssp", 0x1000); |
12a82804 | 771 | sysbus_init_mmio(sbd, &s->iomem); |
a984a69e | 772 | |
12a82804 | 773 | s->bus = ssi_create_bus(dev, "ssi"); |
a984a69e PB |
774 | } |
775 | ||
c1713132 AZ |
776 | /* Real-Time Clock */ |
777 | #define RCNR 0x00 /* RTC Counter register */ | |
778 | #define RTAR 0x04 /* RTC Alarm register */ | |
779 | #define RTSR 0x08 /* RTC Status register */ | |
780 | #define RTTR 0x0c /* RTC Timer Trim register */ | |
781 | #define RDCR 0x10 /* RTC Day Counter register */ | |
782 | #define RYCR 0x14 /* RTC Year Counter register */ | |
783 | #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ | |
784 | #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ | |
785 | #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ | |
786 | #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ | |
787 | #define SWCR 0x28 /* RTC Stopwatch Counter register */ | |
788 | #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ | |
789 | #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ | |
790 | #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ | |
791 | #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ | |
792 | ||
548c6f18 AF |
793 | #define TYPE_PXA2XX_RTC "pxa2xx_rtc" |
794 | #define PXA2XX_RTC(obj) \ | |
795 | OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC) | |
796 | ||
8a231487 | 797 | typedef struct { |
548c6f18 AF |
798 | /*< private >*/ |
799 | SysBusDevice parent_obj; | |
800 | /*< public >*/ | |
801 | ||
9c843933 | 802 | MemoryRegion iomem; |
8a231487 AZ |
803 | uint32_t rttr; |
804 | uint32_t rtsr; | |
805 | uint32_t rtar; | |
806 | uint32_t rdar1; | |
807 | uint32_t rdar2; | |
808 | uint32_t ryar1; | |
809 | uint32_t ryar2; | |
810 | uint32_t swar1; | |
811 | uint32_t swar2; | |
812 | uint32_t piar; | |
813 | uint32_t last_rcnr; | |
814 | uint32_t last_rdcr; | |
815 | uint32_t last_rycr; | |
816 | uint32_t last_swcr; | |
817 | uint32_t last_rtcpicr; | |
818 | int64_t last_hz; | |
819 | int64_t last_sw; | |
820 | int64_t last_pi; | |
821 | QEMUTimer *rtc_hz; | |
822 | QEMUTimer *rtc_rdal1; | |
823 | QEMUTimer *rtc_rdal2; | |
824 | QEMUTimer *rtc_swal1; | |
825 | QEMUTimer *rtc_swal2; | |
826 | QEMUTimer *rtc_pi; | |
827 | qemu_irq rtc_irq; | |
828 | } PXA2xxRTCState; | |
829 | ||
830 | static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s) | |
c1713132 | 831 | { |
e1f8c729 | 832 | qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553)); |
c1713132 AZ |
833 | } |
834 | ||
8a231487 | 835 | static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s) |
c1713132 | 836 | { |
884f17c2 | 837 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
838 | s->last_rcnr += ((rt - s->last_hz) << 15) / |
839 | (1000 * ((s->rttr & 0xffff) + 1)); | |
840 | s->last_rdcr += ((rt - s->last_hz) << 15) / | |
841 | (1000 * ((s->rttr & 0xffff) + 1)); | |
842 | s->last_hz = rt; | |
843 | } | |
844 | ||
8a231487 | 845 | static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s) |
c1713132 | 846 | { |
884f17c2 | 847 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
848 | if (s->rtsr & (1 << 12)) |
849 | s->last_swcr += (rt - s->last_sw) / 10; | |
850 | s->last_sw = rt; | |
851 | } | |
852 | ||
8a231487 | 853 | static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s) |
c1713132 | 854 | { |
884f17c2 | 855 | int64_t rt = qemu_clock_get_ms(rtc_clock); |
c1713132 AZ |
856 | if (s->rtsr & (1 << 15)) |
857 | s->last_swcr += rt - s->last_pi; | |
858 | s->last_pi = rt; | |
859 | } | |
860 | ||
8a231487 | 861 | static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s, |
c1713132 AZ |
862 | uint32_t rtsr) |
863 | { | |
864 | if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) | |
bc72ad67 | 865 | timer_mod(s->rtc_hz, s->last_hz + |
c1713132 AZ |
866 | (((s->rtar - s->last_rcnr) * 1000 * |
867 | ((s->rttr & 0xffff) + 1)) >> 15)); | |
868 | else | |
bc72ad67 | 869 | timer_del(s->rtc_hz); |
c1713132 AZ |
870 | |
871 | if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) | |
bc72ad67 | 872 | timer_mod(s->rtc_rdal1, s->last_hz + |
c1713132 AZ |
873 | (((s->rdar1 - s->last_rdcr) * 1000 * |
874 | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ | |
875 | else | |
bc72ad67 | 876 | timer_del(s->rtc_rdal1); |
c1713132 AZ |
877 | |
878 | if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) | |
bc72ad67 | 879 | timer_mod(s->rtc_rdal2, s->last_hz + |
c1713132 AZ |
880 | (((s->rdar2 - s->last_rdcr) * 1000 * |
881 | ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ | |
882 | else | |
bc72ad67 | 883 | timer_del(s->rtc_rdal2); |
c1713132 AZ |
884 | |
885 | if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) | |
bc72ad67 | 886 | timer_mod(s->rtc_swal1, s->last_sw + |
c1713132 AZ |
887 | (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
888 | else | |
bc72ad67 | 889 | timer_del(s->rtc_swal1); |
c1713132 AZ |
890 | |
891 | if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) | |
bc72ad67 | 892 | timer_mod(s->rtc_swal2, s->last_sw + |
c1713132 AZ |
893 | (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
894 | else | |
bc72ad67 | 895 | timer_del(s->rtc_swal2); |
c1713132 AZ |
896 | |
897 | if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) | |
bc72ad67 | 898 | timer_mod(s->rtc_pi, s->last_pi + |
c1713132 AZ |
899 | (s->piar & 0xffff) - s->last_rtcpicr); |
900 | else | |
bc72ad67 | 901 | timer_del(s->rtc_pi); |
c1713132 AZ |
902 | } |
903 | ||
904 | static inline void pxa2xx_rtc_hz_tick(void *opaque) | |
905 | { | |
8a231487 | 906 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
907 | s->rtsr |= (1 << 0); |
908 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
909 | pxa2xx_rtc_int_update(s); | |
910 | } | |
911 | ||
912 | static inline void pxa2xx_rtc_rdal1_tick(void *opaque) | |
913 | { | |
8a231487 | 914 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
915 | s->rtsr |= (1 << 4); |
916 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
917 | pxa2xx_rtc_int_update(s); | |
918 | } | |
919 | ||
920 | static inline void pxa2xx_rtc_rdal2_tick(void *opaque) | |
921 | { | |
8a231487 | 922 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
923 | s->rtsr |= (1 << 6); |
924 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
925 | pxa2xx_rtc_int_update(s); | |
926 | } | |
927 | ||
928 | static inline void pxa2xx_rtc_swal1_tick(void *opaque) | |
929 | { | |
8a231487 | 930 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
931 | s->rtsr |= (1 << 8); |
932 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
933 | pxa2xx_rtc_int_update(s); | |
934 | } | |
935 | ||
936 | static inline void pxa2xx_rtc_swal2_tick(void *opaque) | |
937 | { | |
8a231487 | 938 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
939 | s->rtsr |= (1 << 10); |
940 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
941 | pxa2xx_rtc_int_update(s); | |
942 | } | |
943 | ||
944 | static inline void pxa2xx_rtc_pi_tick(void *opaque) | |
945 | { | |
8a231487 | 946 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
947 | s->rtsr |= (1 << 13); |
948 | pxa2xx_rtc_piupdate(s); | |
949 | s->last_rtcpicr = 0; | |
950 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
951 | pxa2xx_rtc_int_update(s); | |
952 | } | |
953 | ||
a8170e5e | 954 | static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, |
9c843933 | 955 | unsigned size) |
c1713132 | 956 | { |
8a231487 | 957 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 AZ |
958 | |
959 | switch (addr) { | |
960 | case RTTR: | |
961 | return s->rttr; | |
962 | case RTSR: | |
963 | return s->rtsr; | |
964 | case RTAR: | |
965 | return s->rtar; | |
966 | case RDAR1: | |
967 | return s->rdar1; | |
968 | case RDAR2: | |
969 | return s->rdar2; | |
970 | case RYAR1: | |
971 | return s->ryar1; | |
972 | case RYAR2: | |
973 | return s->ryar2; | |
974 | case SWAR1: | |
975 | return s->swar1; | |
976 | case SWAR2: | |
977 | return s->swar2; | |
978 | case PIAR: | |
979 | return s->piar; | |
980 | case RCNR: | |
884f17c2 AB |
981 | return s->last_rcnr + |
982 | ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / | |
983 | (1000 * ((s->rttr & 0xffff) + 1)); | |
c1713132 | 984 | case RDCR: |
884f17c2 AB |
985 | return s->last_rdcr + |
986 | ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / | |
987 | (1000 * ((s->rttr & 0xffff) + 1)); | |
c1713132 AZ |
988 | case RYCR: |
989 | return s->last_rycr; | |
990 | case SWCR: | |
991 | if (s->rtsr & (1 << 12)) | |
884f17c2 AB |
992 | return s->last_swcr + |
993 | (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10; | |
c1713132 AZ |
994 | else |
995 | return s->last_swcr; | |
996 | default: | |
a89f364a | 997 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
998 | break; |
999 | } | |
1000 | return 0; | |
1001 | } | |
1002 | ||
a8170e5e | 1003 | static void pxa2xx_rtc_write(void *opaque, hwaddr addr, |
9c843933 | 1004 | uint64_t value64, unsigned size) |
c1713132 | 1005 | { |
8a231487 | 1006 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
9c843933 | 1007 | uint32_t value = value64; |
c1713132 AZ |
1008 | |
1009 | switch (addr) { | |
1010 | case RTTR: | |
43a32ed6 | 1011 | if (!(s->rttr & (1U << 31))) { |
c1713132 AZ |
1012 | pxa2xx_rtc_hzupdate(s); |
1013 | s->rttr = value; | |
1014 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1015 | } | |
1016 | break; | |
1017 | ||
1018 | case RTSR: | |
1019 | if ((s->rtsr ^ value) & (1 << 15)) | |
1020 | pxa2xx_rtc_piupdate(s); | |
1021 | ||
1022 | if ((s->rtsr ^ value) & (1 << 12)) | |
1023 | pxa2xx_rtc_swupdate(s); | |
1024 | ||
1025 | if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) | |
1026 | pxa2xx_rtc_alarm_update(s, value); | |
1027 | ||
1028 | s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); | |
1029 | pxa2xx_rtc_int_update(s); | |
1030 | break; | |
1031 | ||
1032 | case RTAR: | |
1033 | s->rtar = value; | |
1034 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1035 | break; | |
1036 | ||
1037 | case RDAR1: | |
1038 | s->rdar1 = value; | |
1039 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1040 | break; | |
1041 | ||
1042 | case RDAR2: | |
1043 | s->rdar2 = value; | |
1044 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1045 | break; | |
1046 | ||
1047 | case RYAR1: | |
1048 | s->ryar1 = value; | |
1049 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1050 | break; | |
1051 | ||
1052 | case RYAR2: | |
1053 | s->ryar2 = value; | |
1054 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1055 | break; | |
1056 | ||
1057 | case SWAR1: | |
1058 | pxa2xx_rtc_swupdate(s); | |
1059 | s->swar1 = value; | |
1060 | s->last_swcr = 0; | |
1061 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1062 | break; | |
1063 | ||
1064 | case SWAR2: | |
1065 | s->swar2 = value; | |
1066 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1067 | break; | |
1068 | ||
1069 | case PIAR: | |
1070 | s->piar = value; | |
1071 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1072 | break; | |
1073 | ||
1074 | case RCNR: | |
1075 | pxa2xx_rtc_hzupdate(s); | |
1076 | s->last_rcnr = value; | |
1077 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1078 | break; | |
1079 | ||
1080 | case RDCR: | |
1081 | pxa2xx_rtc_hzupdate(s); | |
1082 | s->last_rdcr = value; | |
1083 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1084 | break; | |
1085 | ||
1086 | case RYCR: | |
1087 | s->last_rycr = value; | |
1088 | break; | |
1089 | ||
1090 | case SWCR: | |
1091 | pxa2xx_rtc_swupdate(s); | |
1092 | s->last_swcr = value; | |
1093 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1094 | break; | |
1095 | ||
1096 | case RTCPICR: | |
1097 | pxa2xx_rtc_piupdate(s); | |
1098 | s->last_rtcpicr = value & 0xffff; | |
1099 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1100 | break; | |
1101 | ||
1102 | default: | |
a89f364a | 1103 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
1104 | } |
1105 | } | |
1106 | ||
9c843933 AK |
1107 | static const MemoryRegionOps pxa2xx_rtc_ops = { |
1108 | .read = pxa2xx_rtc_read, | |
1109 | .write = pxa2xx_rtc_write, | |
1110 | .endianness = DEVICE_NATIVE_ENDIAN, | |
aa941b94 AZ |
1111 | }; |
1112 | ||
16fb31a3 | 1113 | static void pxa2xx_rtc_init(Object *obj) |
c1713132 | 1114 | { |
16fb31a3 XZ |
1115 | PXA2xxRTCState *s = PXA2XX_RTC(obj); |
1116 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
f6503059 | 1117 | struct tm tm; |
c1713132 AZ |
1118 | int wom; |
1119 | ||
1120 | s->rttr = 0x7fff; | |
1121 | s->rtsr = 0; | |
1122 | ||
f6503059 AZ |
1123 | qemu_get_timedate(&tm, 0); |
1124 | wom = ((tm.tm_mday - 1) / 7) + 1; | |
1125 | ||
0cd2df75 | 1126 | s->last_rcnr = (uint32_t) mktimegm(&tm); |
f6503059 AZ |
1127 | s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) | |
1128 | (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec; | |
1129 | s->last_rycr = ((tm.tm_year + 1900) << 9) | | |
1130 | ((tm.tm_mon + 1) << 5) | tm.tm_mday; | |
1131 | s->last_swcr = (tm.tm_hour << 19) | | |
1132 | (tm.tm_min << 13) | (tm.tm_sec << 7); | |
c1713132 | 1133 | s->last_rtcpicr = 0; |
884f17c2 AB |
1134 | s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock); |
1135 | ||
1136 | s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s); | |
1137 | s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s); | |
1138 | s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s); | |
1139 | s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s); | |
1140 | s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s); | |
1141 | s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s); | |
e1f8c729 | 1142 | |
8a231487 AZ |
1143 | sysbus_init_irq(dev, &s->rtc_irq); |
1144 | ||
16fb31a3 | 1145 | memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s, |
64bde0f3 | 1146 | "pxa2xx-rtc", 0x10000); |
750ecd44 | 1147 | sysbus_init_mmio(dev, &s->iomem); |
c1713132 AZ |
1148 | } |
1149 | ||
44b1ff31 | 1150 | static int pxa2xx_rtc_pre_save(void *opaque) |
aa941b94 | 1151 | { |
8a231487 | 1152 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
c1713132 | 1153 | |
aa941b94 AZ |
1154 | pxa2xx_rtc_hzupdate(s); |
1155 | pxa2xx_rtc_piupdate(s); | |
1156 | pxa2xx_rtc_swupdate(s); | |
44b1ff31 DDAG |
1157 | |
1158 | return 0; | |
8a231487 | 1159 | } |
aa941b94 | 1160 | |
8a231487 | 1161 | static int pxa2xx_rtc_post_load(void *opaque, int version_id) |
aa941b94 | 1162 | { |
8a231487 | 1163 | PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; |
aa941b94 AZ |
1164 | |
1165 | pxa2xx_rtc_alarm_update(s, s->rtsr); | |
1166 | ||
1167 | return 0; | |
1168 | } | |
c1713132 | 1169 | |
8a231487 AZ |
1170 | static const VMStateDescription vmstate_pxa2xx_rtc_regs = { |
1171 | .name = "pxa2xx_rtc", | |
1172 | .version_id = 0, | |
1173 | .minimum_version_id = 0, | |
8a231487 AZ |
1174 | .pre_save = pxa2xx_rtc_pre_save, |
1175 | .post_load = pxa2xx_rtc_post_load, | |
1176 | .fields = (VMStateField[]) { | |
1177 | VMSTATE_UINT32(rttr, PXA2xxRTCState), | |
1178 | VMSTATE_UINT32(rtsr, PXA2xxRTCState), | |
1179 | VMSTATE_UINT32(rtar, PXA2xxRTCState), | |
1180 | VMSTATE_UINT32(rdar1, PXA2xxRTCState), | |
1181 | VMSTATE_UINT32(rdar2, PXA2xxRTCState), | |
1182 | VMSTATE_UINT32(ryar1, PXA2xxRTCState), | |
1183 | VMSTATE_UINT32(ryar2, PXA2xxRTCState), | |
1184 | VMSTATE_UINT32(swar1, PXA2xxRTCState), | |
1185 | VMSTATE_UINT32(swar2, PXA2xxRTCState), | |
1186 | VMSTATE_UINT32(piar, PXA2xxRTCState), | |
1187 | VMSTATE_UINT32(last_rcnr, PXA2xxRTCState), | |
1188 | VMSTATE_UINT32(last_rdcr, PXA2xxRTCState), | |
1189 | VMSTATE_UINT32(last_rycr, PXA2xxRTCState), | |
1190 | VMSTATE_UINT32(last_swcr, PXA2xxRTCState), | |
1191 | VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState), | |
1192 | VMSTATE_INT64(last_hz, PXA2xxRTCState), | |
1193 | VMSTATE_INT64(last_sw, PXA2xxRTCState), | |
1194 | VMSTATE_INT64(last_pi, PXA2xxRTCState), | |
1195 | VMSTATE_END_OF_LIST(), | |
1196 | }, | |
1197 | }; | |
1198 | ||
999e12bb AL |
1199 | static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data) |
1200 | { | |
39bffca2 | 1201 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1202 | |
39bffca2 AL |
1203 | dc->desc = "PXA2xx RTC Controller"; |
1204 | dc->vmsd = &vmstate_pxa2xx_rtc_regs; | |
999e12bb AL |
1205 | } |
1206 | ||
8c43a6f0 | 1207 | static const TypeInfo pxa2xx_rtc_sysbus_info = { |
548c6f18 | 1208 | .name = TYPE_PXA2XX_RTC, |
39bffca2 AL |
1209 | .parent = TYPE_SYS_BUS_DEVICE, |
1210 | .instance_size = sizeof(PXA2xxRTCState), | |
16fb31a3 | 1211 | .instance_init = pxa2xx_rtc_init, |
39bffca2 | 1212 | .class_init = pxa2xx_rtc_sysbus_class_init, |
8a231487 AZ |
1213 | }; |
1214 | ||
3f582262 | 1215 | /* I2C Interface */ |
96dca6b9 AF |
1216 | |
1217 | #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave" | |
1218 | #define PXA2XX_I2C_SLAVE(obj) \ | |
1219 | OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE) | |
1220 | ||
1221 | typedef struct PXA2xxI2CSlaveState { | |
1222 | I2CSlave parent_obj; | |
1223 | ||
e3b42536 PB |
1224 | PXA2xxI2CState *host; |
1225 | } PXA2xxI2CSlaveState; | |
1226 | ||
5354c21e AF |
1227 | #define TYPE_PXA2XX_I2C "pxa2xx_i2c" |
1228 | #define PXA2XX_I2C(obj) \ | |
1229 | OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C) | |
1230 | ||
bc24a225 | 1231 | struct PXA2xxI2CState { |
5354c21e AF |
1232 | /*< private >*/ |
1233 | SysBusDevice parent_obj; | |
1234 | /*< public >*/ | |
1235 | ||
9c843933 | 1236 | MemoryRegion iomem; |
e3b42536 | 1237 | PXA2xxI2CSlaveState *slave; |
a5c82852 | 1238 | I2CBus *bus; |
3f582262 | 1239 | qemu_irq irq; |
c8ba63f8 DES |
1240 | uint32_t offset; |
1241 | uint32_t region_size; | |
3f582262 AZ |
1242 | |
1243 | uint16_t control; | |
1244 | uint16_t status; | |
1245 | uint8_t ibmr; | |
1246 | uint8_t data; | |
1247 | }; | |
1248 | ||
1249 | #define IBMR 0x80 /* I2C Bus Monitor register */ | |
1250 | #define IDBR 0x88 /* I2C Data Buffer register */ | |
1251 | #define ICR 0x90 /* I2C Control register */ | |
1252 | #define ISR 0x98 /* I2C Status register */ | |
1253 | #define ISAR 0xa0 /* I2C Slave Address register */ | |
1254 | ||
bc24a225 | 1255 | static void pxa2xx_i2c_update(PXA2xxI2CState *s) |
3f582262 AZ |
1256 | { |
1257 | uint16_t level = 0; | |
1258 | level |= s->status & s->control & (1 << 10); /* BED */ | |
1259 | level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */ | |
1260 | level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */ | |
1261 | level |= s->status & (1 << 9); /* SAD */ | |
1262 | qemu_set_irq(s->irq, !!level); | |
1263 | } | |
1264 | ||
1265 | /* These are only stubs now. */ | |
d307c28c | 1266 | static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event) |
3f582262 | 1267 | { |
96dca6b9 | 1268 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1269 | PXA2xxI2CState *s = slave->host; |
3f582262 AZ |
1270 | |
1271 | switch (event) { | |
1272 | case I2C_START_SEND: | |
1273 | s->status |= (1 << 9); /* set SAD */ | |
1274 | s->status &= ~(1 << 0); /* clear RWM */ | |
1275 | break; | |
1276 | case I2C_START_RECV: | |
1277 | s->status |= (1 << 9); /* set SAD */ | |
1278 | s->status |= 1 << 0; /* set RWM */ | |
1279 | break; | |
1280 | case I2C_FINISH: | |
1281 | s->status |= (1 << 4); /* set SSD */ | |
1282 | break; | |
1283 | case I2C_NACK: | |
1284 | s->status |= 1 << 1; /* set ACKNAK */ | |
1285 | break; | |
1286 | } | |
1287 | pxa2xx_i2c_update(s); | |
d307c28c CM |
1288 | |
1289 | return 0; | |
3f582262 AZ |
1290 | } |
1291 | ||
2ac4c5f4 | 1292 | static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c) |
3f582262 | 1293 | { |
96dca6b9 | 1294 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1295 | PXA2xxI2CState *s = slave->host; |
96dca6b9 AF |
1296 | |
1297 | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { | |
3f582262 | 1298 | return 0; |
96dca6b9 | 1299 | } |
3f582262 AZ |
1300 | |
1301 | if (s->status & (1 << 0)) { /* RWM */ | |
1302 | s->status |= 1 << 6; /* set ITE */ | |
1303 | } | |
1304 | pxa2xx_i2c_update(s); | |
1305 | ||
1306 | return s->data; | |
1307 | } | |
1308 | ||
9e07bdf8 | 1309 | static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data) |
3f582262 | 1310 | { |
96dca6b9 | 1311 | PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c); |
e3b42536 | 1312 | PXA2xxI2CState *s = slave->host; |
96dca6b9 AF |
1313 | |
1314 | if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) { | |
3f582262 | 1315 | return 1; |
96dca6b9 | 1316 | } |
3f582262 AZ |
1317 | |
1318 | if (!(s->status & (1 << 0))) { /* RWM */ | |
1319 | s->status |= 1 << 7; /* set IRF */ | |
1320 | s->data = data; | |
1321 | } | |
1322 | pxa2xx_i2c_update(s); | |
1323 | ||
1324 | return 1; | |
1325 | } | |
1326 | ||
a8170e5e | 1327 | static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, |
9c843933 | 1328 | unsigned size) |
3f582262 | 1329 | { |
bc24a225 | 1330 | PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
96dca6b9 | 1331 | I2CSlave *slave; |
3f582262 | 1332 | |
ed005253 | 1333 | addr -= s->offset; |
3f582262 AZ |
1334 | switch (addr) { |
1335 | case ICR: | |
1336 | return s->control; | |
1337 | case ISR: | |
1338 | return s->status | (i2c_bus_busy(s->bus) << 2); | |
1339 | case ISAR: | |
96dca6b9 AF |
1340 | slave = I2C_SLAVE(s->slave); |
1341 | return slave->address; | |
3f582262 AZ |
1342 | case IDBR: |
1343 | return s->data; | |
1344 | case IBMR: | |
1345 | if (s->status & (1 << 2)) | |
1346 | s->ibmr ^= 3; /* Fake SCL and SDA pin changes */ | |
1347 | else | |
1348 | s->ibmr = 0; | |
1349 | return s->ibmr; | |
1350 | default: | |
a89f364a | 1351 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
3f582262 AZ |
1352 | break; |
1353 | } | |
1354 | return 0; | |
1355 | } | |
1356 | ||
a8170e5e | 1357 | static void pxa2xx_i2c_write(void *opaque, hwaddr addr, |
9c843933 | 1358 | uint64_t value64, unsigned size) |
3f582262 | 1359 | { |
bc24a225 | 1360 | PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; |
9c843933 | 1361 | uint32_t value = value64; |
3f582262 | 1362 | int ack; |
3f582262 | 1363 | |
ed005253 | 1364 | addr -= s->offset; |
3f582262 AZ |
1365 | switch (addr) { |
1366 | case ICR: | |
1367 | s->control = value & 0xfff7; | |
1368 | if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */ | |
1369 | /* TODO: slave mode */ | |
1370 | if (value & (1 << 0)) { /* START condition */ | |
1371 | if (s->data & 1) | |
1372 | s->status |= 1 << 0; /* set RWM */ | |
1373 | else | |
1374 | s->status &= ~(1 << 0); /* clear RWM */ | |
1375 | ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1); | |
1376 | } else { | |
1377 | if (s->status & (1 << 0)) { /* RWM */ | |
1378 | s->data = i2c_recv(s->bus); | |
1379 | if (value & (1 << 2)) /* ACKNAK */ | |
1380 | i2c_nack(s->bus); | |
1381 | ack = 1; | |
1382 | } else | |
1383 | ack = !i2c_send(s->bus, s->data); | |
1384 | } | |
1385 | ||
1386 | if (value & (1 << 1)) /* STOP condition */ | |
1387 | i2c_end_transfer(s->bus); | |
1388 | ||
1389 | if (ack) { | |
1390 | if (value & (1 << 0)) /* START condition */ | |
1391 | s->status |= 1 << 6; /* set ITE */ | |
1392 | else | |
1393 | if (s->status & (1 << 0)) /* RWM */ | |
1394 | s->status |= 1 << 7; /* set IRF */ | |
1395 | else | |
1396 | s->status |= 1 << 6; /* set ITE */ | |
1397 | s->status &= ~(1 << 1); /* clear ACKNAK */ | |
1398 | } else { | |
1399 | s->status |= 1 << 6; /* set ITE */ | |
1400 | s->status |= 1 << 10; /* set BED */ | |
1401 | s->status |= 1 << 1; /* set ACKNAK */ | |
1402 | } | |
1403 | } | |
1404 | if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */ | |
1405 | if (value & (1 << 4)) /* MA */ | |
1406 | i2c_end_transfer(s->bus); | |
1407 | pxa2xx_i2c_update(s); | |
1408 | break; | |
1409 | ||
1410 | case ISR: | |
1411 | s->status &= ~(value & 0x07f0); | |
1412 | pxa2xx_i2c_update(s); | |
1413 | break; | |
1414 | ||
1415 | case ISAR: | |
96dca6b9 | 1416 | i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f); |
3f582262 AZ |
1417 | break; |
1418 | ||
1419 | case IDBR: | |
1420 | s->data = value & 0xff; | |
1421 | break; | |
1422 | ||
1423 | default: | |
a89f364a | 1424 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
3f582262 AZ |
1425 | } |
1426 | } | |
1427 | ||
9c843933 AK |
1428 | static const MemoryRegionOps pxa2xx_i2c_ops = { |
1429 | .read = pxa2xx_i2c_read, | |
1430 | .write = pxa2xx_i2c_write, | |
1431 | .endianness = DEVICE_NATIVE_ENDIAN, | |
3f582262 AZ |
1432 | }; |
1433 | ||
0211364d JQ |
1434 | static const VMStateDescription vmstate_pxa2xx_i2c_slave = { |
1435 | .name = "pxa2xx_i2c_slave", | |
1436 | .version_id = 1, | |
1437 | .minimum_version_id = 1, | |
8f1e884b | 1438 | .fields = (VMStateField[]) { |
96dca6b9 | 1439 | VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState), |
0211364d JQ |
1440 | VMSTATE_END_OF_LIST() |
1441 | } | |
1442 | }; | |
aa941b94 | 1443 | |
0211364d JQ |
1444 | static const VMStateDescription vmstate_pxa2xx_i2c = { |
1445 | .name = "pxa2xx_i2c", | |
1446 | .version_id = 1, | |
1447 | .minimum_version_id = 1, | |
8f1e884b | 1448 | .fields = (VMStateField[]) { |
0211364d JQ |
1449 | VMSTATE_UINT16(control, PXA2xxI2CState), |
1450 | VMSTATE_UINT16(status, PXA2xxI2CState), | |
1451 | VMSTATE_UINT8(ibmr, PXA2xxI2CState), | |
1452 | VMSTATE_UINT8(data, PXA2xxI2CState), | |
1453 | VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState, | |
20bcf73f | 1454 | vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState), |
0211364d JQ |
1455 | VMSTATE_END_OF_LIST() |
1456 | } | |
1457 | }; | |
aa941b94 | 1458 | |
999e12bb | 1459 | static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data) |
b5ea9327 AL |
1460 | { |
1461 | I2CSlaveClass *k = I2C_SLAVE_CLASS(klass); | |
1462 | ||
b5ea9327 AL |
1463 | k->event = pxa2xx_i2c_event; |
1464 | k->recv = pxa2xx_i2c_rx; | |
1465 | k->send = pxa2xx_i2c_tx; | |
1466 | } | |
1467 | ||
8c43a6f0 | 1468 | static const TypeInfo pxa2xx_i2c_slave_info = { |
96dca6b9 | 1469 | .name = TYPE_PXA2XX_I2C_SLAVE, |
39bffca2 AL |
1470 | .parent = TYPE_I2C_SLAVE, |
1471 | .instance_size = sizeof(PXA2xxI2CSlaveState), | |
1472 | .class_init = pxa2xx_i2c_slave_class_init, | |
e3b42536 PB |
1473 | }; |
1474 | ||
a8170e5e | 1475 | PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, |
ed005253 | 1476 | qemu_irq irq, uint32_t region_size) |
3f582262 | 1477 | { |
e3b42536 | 1478 | DeviceState *dev; |
c8ba63f8 DES |
1479 | SysBusDevice *i2c_dev; |
1480 | PXA2xxI2CState *s; | |
a5c82852 | 1481 | I2CBus *i2cbus; |
c8ba63f8 | 1482 | |
5354c21e AF |
1483 | dev = qdev_create(NULL, TYPE_PXA2XX_I2C); |
1484 | qdev_prop_set_uint32(dev, "size", region_size + 1); | |
1485 | qdev_prop_set_uint32(dev, "offset", base & region_size); | |
1486 | qdev_init_nofail(dev); | |
c8ba63f8 | 1487 | |
5354c21e | 1488 | i2c_dev = SYS_BUS_DEVICE(dev); |
c8ba63f8 DES |
1489 | sysbus_mmio_map(i2c_dev, 0, base & ~region_size); |
1490 | sysbus_connect_irq(i2c_dev, 0, irq); | |
e3b42536 | 1491 | |
5354c21e | 1492 | s = PXA2XX_I2C(i2c_dev); |
c701b35b | 1493 | /* FIXME: Should the slave device really be on a separate bus? */ |
be2f78b6 | 1494 | i2cbus = i2c_init_bus(dev, "dummy"); |
96dca6b9 AF |
1495 | dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0); |
1496 | s->slave = PXA2XX_I2C_SLAVE(dev); | |
e3b42536 | 1497 | s->slave->host = s; |
3f582262 | 1498 | |
c8ba63f8 DES |
1499 | return s; |
1500 | } | |
1501 | ||
16fb31a3 | 1502 | static void pxa2xx_i2c_initfn(Object *obj) |
c8ba63f8 | 1503 | { |
16fb31a3 XZ |
1504 | DeviceState *dev = DEVICE(obj); |
1505 | PXA2xxI2CState *s = PXA2XX_I2C(obj); | |
1506 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
c8ba63f8 | 1507 | |
08426da7 | 1508 | s->bus = i2c_init_bus(dev, NULL); |
3f582262 | 1509 | |
16fb31a3 | 1510 | memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s, |
64bde0f3 | 1511 | "pxa2xx-i2c", s->region_size); |
5354c21e AF |
1512 | sysbus_init_mmio(sbd, &s->iomem); |
1513 | sysbus_init_irq(sbd, &s->irq); | |
3f582262 AZ |
1514 | } |
1515 | ||
a5c82852 | 1516 | I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s) |
3f582262 AZ |
1517 | { |
1518 | return s->bus; | |
1519 | } | |
1520 | ||
999e12bb AL |
1521 | static Property pxa2xx_i2c_properties[] = { |
1522 | DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000), | |
1523 | DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0), | |
1524 | DEFINE_PROP_END_OF_LIST(), | |
1525 | }; | |
1526 | ||
1527 | static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data) | |
1528 | { | |
39bffca2 | 1529 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1530 | |
39bffca2 AL |
1531 | dc->desc = "PXA2xx I2C Bus Controller"; |
1532 | dc->vmsd = &vmstate_pxa2xx_i2c; | |
1533 | dc->props = pxa2xx_i2c_properties; | |
999e12bb AL |
1534 | } |
1535 | ||
8c43a6f0 | 1536 | static const TypeInfo pxa2xx_i2c_info = { |
5354c21e | 1537 | .name = TYPE_PXA2XX_I2C, |
39bffca2 AL |
1538 | .parent = TYPE_SYS_BUS_DEVICE, |
1539 | .instance_size = sizeof(PXA2xxI2CState), | |
16fb31a3 | 1540 | .instance_init = pxa2xx_i2c_initfn, |
39bffca2 | 1541 | .class_init = pxa2xx_i2c_class_init, |
c8ba63f8 DES |
1542 | }; |
1543 | ||
c1713132 | 1544 | /* PXA Inter-IC Sound Controller */ |
bc24a225 | 1545 | static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s) |
c1713132 AZ |
1546 | { |
1547 | i2s->rx_len = 0; | |
1548 | i2s->tx_len = 0; | |
1549 | i2s->fifo_len = 0; | |
1550 | i2s->clk = 0x1a; | |
1551 | i2s->control[0] = 0x00; | |
1552 | i2s->control[1] = 0x00; | |
1553 | i2s->status = 0x00; | |
1554 | i2s->mask = 0x00; | |
1555 | } | |
1556 | ||
1557 | #define SACR_TFTH(val) ((val >> 8) & 0xf) | |
1558 | #define SACR_RFTH(val) ((val >> 12) & 0xf) | |
1559 | #define SACR_DREC(val) (val & (1 << 3)) | |
1560 | #define SACR_DPRL(val) (val & (1 << 4)) | |
1561 | ||
bc24a225 | 1562 | static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) |
c1713132 AZ |
1563 | { |
1564 | int rfs, tfs; | |
1565 | rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len && | |
1566 | !SACR_DREC(i2s->control[1]); | |
1567 | tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && | |
1568 | i2s->enable && !SACR_DPRL(i2s->control[1]); | |
1569 | ||
2115c019 AZ |
1570 | qemu_set_irq(i2s->rx_dma, rfs); |
1571 | qemu_set_irq(i2s->tx_dma, tfs); | |
c1713132 AZ |
1572 | |
1573 | i2s->status &= 0xe0; | |
59c0149b AZ |
1574 | if (i2s->fifo_len < 16 || !i2s->enable) |
1575 | i2s->status |= 1 << 0; /* TNF */ | |
c1713132 AZ |
1576 | if (i2s->rx_len) |
1577 | i2s->status |= 1 << 1; /* RNE */ | |
1578 | if (i2s->enable) | |
1579 | i2s->status |= 1 << 2; /* BSY */ | |
1580 | if (tfs) | |
1581 | i2s->status |= 1 << 3; /* TFS */ | |
1582 | if (rfs) | |
1583 | i2s->status |= 1 << 4; /* RFS */ | |
1584 | if (!(i2s->tx_len && i2s->enable)) | |
1585 | i2s->status |= i2s->fifo_len << 8; /* TFL */ | |
1586 | i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ | |
1587 | ||
1588 | qemu_set_irq(i2s->irq, i2s->status & i2s->mask); | |
1589 | } | |
1590 | ||
1591 | #define SACR0 0x00 /* Serial Audio Global Control register */ | |
1592 | #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ | |
1593 | #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ | |
1594 | #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ | |
1595 | #define SAICR 0x18 /* Serial Audio Interrupt Clear register */ | |
1596 | #define SADIV 0x60 /* Serial Audio Clock Divider register */ | |
1597 | #define SADR 0x80 /* Serial Audio Data register */ | |
1598 | ||
a8170e5e | 1599 | static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, |
9c843933 | 1600 | unsigned size) |
c1713132 | 1601 | { |
bc24a225 | 1602 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 AZ |
1603 | |
1604 | switch (addr) { | |
1605 | case SACR0: | |
1606 | return s->control[0]; | |
1607 | case SACR1: | |
1608 | return s->control[1]; | |
1609 | case SASR0: | |
1610 | return s->status; | |
1611 | case SAIMR: | |
1612 | return s->mask; | |
1613 | case SAICR: | |
1614 | return 0; | |
1615 | case SADIV: | |
1616 | return s->clk; | |
1617 | case SADR: | |
1618 | if (s->rx_len > 0) { | |
1619 | s->rx_len --; | |
1620 | pxa2xx_i2s_update(s); | |
1621 | return s->codec_in(s->opaque); | |
1622 | } | |
1623 | return 0; | |
1624 | default: | |
a89f364a | 1625 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
1626 | break; |
1627 | } | |
1628 | return 0; | |
1629 | } | |
1630 | ||
a8170e5e | 1631 | static void pxa2xx_i2s_write(void *opaque, hwaddr addr, |
9c843933 | 1632 | uint64_t value, unsigned size) |
c1713132 | 1633 | { |
bc24a225 | 1634 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 | 1635 | uint32_t *sample; |
c1713132 AZ |
1636 | |
1637 | switch (addr) { | |
1638 | case SACR0: | |
1639 | if (value & (1 << 3)) /* RST */ | |
1640 | pxa2xx_i2s_reset(s); | |
1641 | s->control[0] = value & 0xff3d; | |
1642 | if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ | |
1643 | for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) | |
1644 | s->codec_out(s->opaque, *sample); | |
1645 | s->status &= ~(1 << 7); /* I2SOFF */ | |
1646 | } | |
1647 | if (value & (1 << 4)) /* EFWR */ | |
a89f364a | 1648 | printf("%s: Attempt to use special function\n", __func__); |
9dda2465 | 1649 | s->enable = (value & 9) == 1; /* ENB && !RST*/ |
c1713132 AZ |
1650 | pxa2xx_i2s_update(s); |
1651 | break; | |
1652 | case SACR1: | |
1653 | s->control[1] = value & 0x0039; | |
1654 | if (value & (1 << 5)) /* ENLBF */ | |
a89f364a | 1655 | printf("%s: Attempt to use loopback function\n", __func__); |
c1713132 AZ |
1656 | if (value & (1 << 4)) /* DPRL */ |
1657 | s->fifo_len = 0; | |
1658 | pxa2xx_i2s_update(s); | |
1659 | break; | |
1660 | case SAIMR: | |
1661 | s->mask = value & 0x0078; | |
1662 | pxa2xx_i2s_update(s); | |
1663 | break; | |
1664 | case SAICR: | |
1665 | s->status &= ~(value & (3 << 5)); | |
1666 | pxa2xx_i2s_update(s); | |
1667 | break; | |
1668 | case SADIV: | |
1669 | s->clk = value & 0x007f; | |
1670 | break; | |
1671 | case SADR: | |
1672 | if (s->tx_len && s->enable) { | |
1673 | s->tx_len --; | |
1674 | pxa2xx_i2s_update(s); | |
1675 | s->codec_out(s->opaque, value); | |
1676 | } else if (s->fifo_len < 16) { | |
1677 | s->fifo[s->fifo_len ++] = value; | |
1678 | pxa2xx_i2s_update(s); | |
1679 | } | |
1680 | break; | |
1681 | default: | |
a89f364a | 1682 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
1683 | } |
1684 | } | |
1685 | ||
9c843933 AK |
1686 | static const MemoryRegionOps pxa2xx_i2s_ops = { |
1687 | .read = pxa2xx_i2s_read, | |
1688 | .write = pxa2xx_i2s_write, | |
1689 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
1690 | }; |
1691 | ||
9f5dfe29 JQ |
1692 | static const VMStateDescription vmstate_pxa2xx_i2s = { |
1693 | .name = "pxa2xx_i2s", | |
1694 | .version_id = 0, | |
1695 | .minimum_version_id = 0, | |
8f1e884b | 1696 | .fields = (VMStateField[]) { |
9f5dfe29 JQ |
1697 | VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2), |
1698 | VMSTATE_UINT32(status, PXA2xxI2SState), | |
1699 | VMSTATE_UINT32(mask, PXA2xxI2SState), | |
1700 | VMSTATE_UINT32(clk, PXA2xxI2SState), | |
1701 | VMSTATE_INT32(enable, PXA2xxI2SState), | |
1702 | VMSTATE_INT32(rx_len, PXA2xxI2SState), | |
1703 | VMSTATE_INT32(tx_len, PXA2xxI2SState), | |
1704 | VMSTATE_INT32(fifo_len, PXA2xxI2SState), | |
1705 | VMSTATE_END_OF_LIST() | |
1706 | } | |
1707 | }; | |
aa941b94 | 1708 | |
c1713132 AZ |
1709 | static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1710 | { | |
bc24a225 | 1711 | PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; |
c1713132 AZ |
1712 | uint32_t *sample; |
1713 | ||
1714 | /* Signal FIFO errors */ | |
1715 | if (s->enable && s->tx_len) | |
1716 | s->status |= 1 << 5; /* TUR */ | |
1717 | if (s->enable && s->rx_len) | |
1718 | s->status |= 1 << 6; /* ROR */ | |
1719 | ||
1720 | /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to | |
1721 | * handle the cases where it makes a difference. */ | |
1722 | s->tx_len = tx - s->fifo_len; | |
1723 | s->rx_len = rx; | |
1724 | /* Note that is s->codec_out wasn't set, we wouldn't get called. */ | |
1725 | if (s->enable) | |
1726 | for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++) | |
1727 | s->codec_out(s->opaque, *sample); | |
1728 | pxa2xx_i2s_update(s); | |
1729 | } | |
1730 | ||
9c843933 | 1731 | static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, |
a8170e5e | 1732 | hwaddr base, |
2115c019 | 1733 | qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) |
c1713132 | 1734 | { |
b45c03f5 | 1735 | PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1); |
c1713132 | 1736 | |
c1713132 | 1737 | s->irq = irq; |
2115c019 AZ |
1738 | s->rx_dma = rx_dma; |
1739 | s->tx_dma = tx_dma; | |
c1713132 AZ |
1740 | s->data_req = pxa2xx_i2s_data_req; |
1741 | ||
1742 | pxa2xx_i2s_reset(s); | |
1743 | ||
2c9b15ca | 1744 | memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, |
9c843933 AK |
1745 | "pxa2xx-i2s", 0x100000); |
1746 | memory_region_add_subregion(sysmem, base, &s->iomem); | |
c1713132 | 1747 | |
9f5dfe29 | 1748 | vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); |
aa941b94 | 1749 | |
c1713132 AZ |
1750 | return s; |
1751 | } | |
1752 | ||
1753 | /* PXA Fast Infra-red Communications Port */ | |
1fd9f2df PM |
1754 | #define TYPE_PXA2XX_FIR "pxa2xx-fir" |
1755 | #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR) | |
1756 | ||
bc24a225 | 1757 | struct PXA2xxFIrState { |
1fd9f2df PM |
1758 | /*< private >*/ |
1759 | SysBusDevice parent_obj; | |
1760 | /*< public >*/ | |
1761 | ||
adfc39ea | 1762 | MemoryRegion iomem; |
c1713132 | 1763 | qemu_irq irq; |
2115c019 AZ |
1764 | qemu_irq rx_dma; |
1765 | qemu_irq tx_dma; | |
1fd9f2df | 1766 | uint32_t enable; |
becdfa00 | 1767 | CharBackend chr; |
c1713132 AZ |
1768 | |
1769 | uint8_t control[3]; | |
1770 | uint8_t status[2]; | |
1771 | ||
1fd9f2df PM |
1772 | uint32_t rx_len; |
1773 | uint32_t rx_start; | |
c1713132 AZ |
1774 | uint8_t rx_fifo[64]; |
1775 | }; | |
1776 | ||
1fd9f2df | 1777 | static void pxa2xx_fir_reset(DeviceState *d) |
c1713132 | 1778 | { |
1fd9f2df PM |
1779 | PXA2xxFIrState *s = PXA2XX_FIR(d); |
1780 | ||
c1713132 AZ |
1781 | s->control[0] = 0x00; |
1782 | s->control[1] = 0x00; | |
1783 | s->control[2] = 0x00; | |
1784 | s->status[0] = 0x00; | |
1785 | s->status[1] = 0x00; | |
1786 | s->enable = 0; | |
1787 | } | |
1788 | ||
bc24a225 | 1789 | static inline void pxa2xx_fir_update(PXA2xxFIrState *s) |
c1713132 AZ |
1790 | { |
1791 | static const int tresh[4] = { 8, 16, 32, 0 }; | |
1792 | int intr = 0; | |
1793 | if ((s->control[0] & (1 << 4)) && /* RXE */ | |
1794 | s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ | |
1795 | s->status[0] |= 1 << 4; /* RFS */ | |
1796 | else | |
1797 | s->status[0] &= ~(1 << 4); /* RFS */ | |
1798 | if (s->control[0] & (1 << 3)) /* TXE */ | |
1799 | s->status[0] |= 1 << 3; /* TFS */ | |
1800 | else | |
1801 | s->status[0] &= ~(1 << 3); /* TFS */ | |
1802 | if (s->rx_len) | |
1803 | s->status[1] |= 1 << 2; /* RNE */ | |
1804 | else | |
1805 | s->status[1] &= ~(1 << 2); /* RNE */ | |
1806 | if (s->control[0] & (1 << 4)) /* RXE */ | |
1807 | s->status[1] |= 1 << 0; /* RSY */ | |
1808 | else | |
1809 | s->status[1] &= ~(1 << 0); /* RSY */ | |
1810 | ||
1811 | intr |= (s->control[0] & (1 << 5)) && /* RIE */ | |
1812 | (s->status[0] & (1 << 4)); /* RFS */ | |
1813 | intr |= (s->control[0] & (1 << 6)) && /* TIE */ | |
1814 | (s->status[0] & (1 << 3)); /* TFS */ | |
1815 | intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ | |
1816 | (s->status[0] & (1 << 6)); /* EOC */ | |
1817 | intr |= (s->control[0] & (1 << 2)) && /* TUS */ | |
1818 | (s->status[0] & (1 << 1)); /* TUR */ | |
1819 | intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ | |
1820 | ||
2115c019 AZ |
1821 | qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); |
1822 | qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); | |
c1713132 AZ |
1823 | |
1824 | qemu_set_irq(s->irq, intr && s->enable); | |
1825 | } | |
1826 | ||
1827 | #define ICCR0 0x00 /* FICP Control register 0 */ | |
1828 | #define ICCR1 0x04 /* FICP Control register 1 */ | |
1829 | #define ICCR2 0x08 /* FICP Control register 2 */ | |
1830 | #define ICDR 0x0c /* FICP Data register */ | |
1831 | #define ICSR0 0x14 /* FICP Status register 0 */ | |
1832 | #define ICSR1 0x18 /* FICP Status register 1 */ | |
1833 | #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ | |
1834 | ||
a8170e5e | 1835 | static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, |
adfc39ea | 1836 | unsigned size) |
c1713132 | 1837 | { |
bc24a225 | 1838 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 | 1839 | uint8_t ret; |
c1713132 AZ |
1840 | |
1841 | switch (addr) { | |
1842 | case ICCR0: | |
1843 | return s->control[0]; | |
1844 | case ICCR1: | |
1845 | return s->control[1]; | |
1846 | case ICCR2: | |
1847 | return s->control[2]; | |
1848 | case ICDR: | |
1849 | s->status[0] &= ~0x01; | |
1850 | s->status[1] &= ~0x72; | |
1851 | if (s->rx_len) { | |
1852 | s->rx_len --; | |
1853 | ret = s->rx_fifo[s->rx_start ++]; | |
1854 | s->rx_start &= 63; | |
1855 | pxa2xx_fir_update(s); | |
1856 | return ret; | |
1857 | } | |
a89f364a | 1858 | printf("%s: Rx FIFO underrun.\n", __func__); |
c1713132 AZ |
1859 | break; |
1860 | case ICSR0: | |
1861 | return s->status[0]; | |
1862 | case ICSR1: | |
1863 | return s->status[1] | (1 << 3); /* TNF */ | |
1864 | case ICFOR: | |
1865 | return s->rx_len; | |
1866 | default: | |
a89f364a | 1867 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
1868 | break; |
1869 | } | |
1870 | return 0; | |
1871 | } | |
1872 | ||
a8170e5e | 1873 | static void pxa2xx_fir_write(void *opaque, hwaddr addr, |
adfc39ea | 1874 | uint64_t value64, unsigned size) |
c1713132 | 1875 | { |
bc24a225 | 1876 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
adfc39ea | 1877 | uint32_t value = value64; |
c1713132 | 1878 | uint8_t ch; |
c1713132 AZ |
1879 | |
1880 | switch (addr) { | |
1881 | case ICCR0: | |
1882 | s->control[0] = value; | |
1883 | if (!(value & (1 << 4))) /* RXE */ | |
1884 | s->rx_len = s->rx_start = 0; | |
3ffd710e BS |
1885 | if (!(value & (1 << 3))) { /* TXE */ |
1886 | /* Nop */ | |
1887 | } | |
c1713132 AZ |
1888 | s->enable = value & 1; /* ITR */ |
1889 | if (!s->enable) | |
1890 | s->status[0] = 0; | |
1891 | pxa2xx_fir_update(s); | |
1892 | break; | |
1893 | case ICCR1: | |
1894 | s->control[1] = value; | |
1895 | break; | |
1896 | case ICCR2: | |
1897 | s->control[2] = value & 0x3f; | |
1898 | pxa2xx_fir_update(s); | |
1899 | break; | |
1900 | case ICDR: | |
becdfa00 | 1901 | if (s->control[2] & (1 << 2)) { /* TXP */ |
c1713132 | 1902 | ch = value; |
becdfa00 | 1903 | } else { |
c1713132 | 1904 | ch = ~value; |
becdfa00 | 1905 | } |
fa394ed6 | 1906 | if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */ |
6ab3fc32 DB |
1907 | /* XXX this blocks entire thread. Rewrite to use |
1908 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 1909 | qemu_chr_fe_write_all(&s->chr, &ch, 1); |
becdfa00 | 1910 | } |
c1713132 AZ |
1911 | break; |
1912 | case ICSR0: | |
1913 | s->status[0] &= ~(value & 0x66); | |
1914 | pxa2xx_fir_update(s); | |
1915 | break; | |
1916 | case ICFOR: | |
1917 | break; | |
1918 | default: | |
a89f364a | 1919 | printf("%s: Bad register " REG_FMT "\n", __func__, addr); |
c1713132 AZ |
1920 | } |
1921 | } | |
1922 | ||
adfc39ea AK |
1923 | static const MemoryRegionOps pxa2xx_fir_ops = { |
1924 | .read = pxa2xx_fir_read, | |
1925 | .write = pxa2xx_fir_write, | |
1926 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
1927 | }; |
1928 | ||
1929 | static int pxa2xx_fir_is_empty(void *opaque) | |
1930 | { | |
bc24a225 | 1931 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 AZ |
1932 | return (s->rx_len < 64); |
1933 | } | |
1934 | ||
1935 | static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) | |
1936 | { | |
bc24a225 | 1937 | PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; |
c1713132 AZ |
1938 | if (!(s->control[0] & (1 << 4))) /* RXE */ |
1939 | return; | |
1940 | ||
1941 | while (size --) { | |
1942 | s->status[1] |= 1 << 4; /* EOF */ | |
1943 | if (s->rx_len >= 64) { | |
1944 | s->status[1] |= 1 << 6; /* ROR */ | |
1945 | break; | |
1946 | } | |
1947 | ||
1948 | if (s->control[2] & (1 << 3)) /* RXP */ | |
1949 | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++); | |
1950 | else | |
1951 | s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++); | |
1952 | } | |
1953 | ||
1954 | pxa2xx_fir_update(s); | |
1955 | } | |
1956 | ||
1957 | static void pxa2xx_fir_event(void *opaque, int event) | |
1958 | { | |
1959 | } | |
1960 | ||
1fd9f2df | 1961 | static void pxa2xx_fir_instance_init(Object *obj) |
aa941b94 | 1962 | { |
1fd9f2df PM |
1963 | PXA2xxFIrState *s = PXA2XX_FIR(obj); |
1964 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
aa941b94 | 1965 | |
81e0ab48 | 1966 | memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s, |
1fd9f2df PM |
1967 | "pxa2xx-fir", 0x1000); |
1968 | sysbus_init_mmio(sbd, &s->iomem); | |
1969 | sysbus_init_irq(sbd, &s->irq); | |
1970 | sysbus_init_irq(sbd, &s->rx_dma); | |
1971 | sysbus_init_irq(sbd, &s->tx_dma); | |
aa941b94 AZ |
1972 | } |
1973 | ||
1fd9f2df | 1974 | static void pxa2xx_fir_realize(DeviceState *dev, Error **errp) |
aa941b94 | 1975 | { |
1fd9f2df | 1976 | PXA2xxFIrState *s = PXA2XX_FIR(dev); |
aa941b94 | 1977 | |
fa394ed6 | 1978 | qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty, |
81517ba3 AN |
1979 | pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL, |
1980 | true); | |
1fd9f2df | 1981 | } |
aa941b94 | 1982 | |
1fd9f2df PM |
1983 | static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id) |
1984 | { | |
1985 | PXA2xxFIrState *s = opaque; | |
aa941b94 | 1986 | |
8e079caf | 1987 | return s->rx_start < ARRAY_SIZE(s->rx_fifo); |
aa941b94 AZ |
1988 | } |
1989 | ||
1fd9f2df PM |
1990 | static const VMStateDescription pxa2xx_fir_vmsd = { |
1991 | .name = "pxa2xx-fir", | |
1992 | .version_id = 1, | |
1993 | .minimum_version_id = 1, | |
1994 | .fields = (VMStateField[]) { | |
1995 | VMSTATE_UINT32(enable, PXA2xxFIrState), | |
1996 | VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3), | |
1997 | VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2), | |
1998 | VMSTATE_UINT32(rx_len, PXA2xxFIrState), | |
1999 | VMSTATE_UINT32(rx_start, PXA2xxFIrState), | |
2000 | VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate), | |
2001 | VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64), | |
2002 | VMSTATE_END_OF_LIST() | |
2003 | } | |
2004 | }; | |
c1713132 | 2005 | |
1fd9f2df PM |
2006 | static Property pxa2xx_fir_properties[] = { |
2007 | DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr), | |
2008 | DEFINE_PROP_END_OF_LIST(), | |
2009 | }; | |
c1713132 | 2010 | |
1fd9f2df PM |
2011 | static void pxa2xx_fir_class_init(ObjectClass *klass, void *data) |
2012 | { | |
2013 | DeviceClass *dc = DEVICE_CLASS(klass); | |
c1713132 | 2014 | |
1fd9f2df PM |
2015 | dc->realize = pxa2xx_fir_realize; |
2016 | dc->vmsd = &pxa2xx_fir_vmsd; | |
2017 | dc->props = pxa2xx_fir_properties; | |
2018 | dc->reset = pxa2xx_fir_reset; | |
2019 | } | |
c1713132 | 2020 | |
1fd9f2df PM |
2021 | static const TypeInfo pxa2xx_fir_info = { |
2022 | .name = TYPE_PXA2XX_FIR, | |
2023 | .parent = TYPE_SYS_BUS_DEVICE, | |
2024 | .instance_size = sizeof(PXA2xxFIrState), | |
2025 | .class_init = pxa2xx_fir_class_init, | |
2026 | .instance_init = pxa2xx_fir_instance_init, | |
2027 | }; | |
c1713132 | 2028 | |
1fd9f2df PM |
2029 | static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, |
2030 | hwaddr base, | |
2031 | qemu_irq irq, qemu_irq rx_dma, | |
2032 | qemu_irq tx_dma, | |
0ec7b3e7 | 2033 | Chardev *chr) |
1fd9f2df PM |
2034 | { |
2035 | DeviceState *dev; | |
2036 | SysBusDevice *sbd; | |
aa941b94 | 2037 | |
1fd9f2df PM |
2038 | dev = qdev_create(NULL, TYPE_PXA2XX_FIR); |
2039 | qdev_prop_set_chr(dev, "chardev", chr); | |
2040 | qdev_init_nofail(dev); | |
2041 | sbd = SYS_BUS_DEVICE(dev); | |
2042 | sysbus_mmio_map(sbd, 0, base); | |
2043 | sysbus_connect_irq(sbd, 0, irq); | |
2044 | sysbus_connect_irq(sbd, 1, rx_dma); | |
2045 | sysbus_connect_irq(sbd, 2, tx_dma); | |
2046 | return PXA2XX_FIR(dev); | |
c1713132 AZ |
2047 | } |
2048 | ||
38641a52 | 2049 | static void pxa2xx_reset(void *opaque, int line, int level) |
c1713132 | 2050 | { |
bc24a225 | 2051 | PXA2xxState *s = (PXA2xxState *) opaque; |
38641a52 | 2052 | |
c1713132 | 2053 | if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
43824588 | 2054 | cpu_reset(CPU(s->cpu)); |
c1713132 AZ |
2055 | /* TODO: reset peripherals */ |
2056 | } | |
2057 | } | |
2058 | ||
2059 | /* Initialise a PXA270 integrated chip (ARM based core). */ | |
a6dc4c2d | 2060 | PXA2xxState *pxa270_init(MemoryRegion *address_space, |
ba1ba5cc | 2061 | unsigned int sdram_size, const char *cpu_type) |
c1713132 | 2062 | { |
bc24a225 | 2063 | PXA2xxState *s; |
adfc39ea | 2064 | int i; |
751c6a17 | 2065 | DriveInfo *dinfo; |
b45c03f5 | 2066 | s = g_new0(PXA2xxState, 1); |
c1713132 | 2067 | |
ba1ba5cc | 2068 | if (strncmp(cpu_type, "pxa27", 5)) { |
c0dbca36 | 2069 | error_report("Machine requires a PXA27x processor"); |
4207117c AZ |
2070 | exit(1); |
2071 | } | |
8e953a65 | 2072 | |
ba1ba5cc | 2073 | s->cpu = ARM_CPU(cpu_create(cpu_type)); |
f3c7d038 | 2074 | s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); |
38641a52 | 2075 | |
d95b2f8d | 2076 | /* SDRAM & Internal Memory Storage */ |
98a99ce0 | 2077 | memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, |
f8ed85ac | 2078 | &error_fatal); |
adfc39ea | 2079 | memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
98a99ce0 | 2080 | memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, |
f8ed85ac | 2081 | &error_fatal); |
adfc39ea AK |
2082 | memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2083 | &s->internal); | |
d95b2f8d | 2084 | |
f161bcd0 | 2085 | s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); |
c1713132 | 2086 | |
e1f8c729 DES |
2087 | s->dma = pxa27x_dma_init(0x40000000, |
2088 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); | |
c1713132 | 2089 | |
797e9542 DES |
2090 | sysbus_create_varargs("pxa27x-timer", 0x40a00000, |
2091 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), | |
2092 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), | |
2093 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), | |
2094 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), | |
2095 | qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), | |
2096 | NULL); | |
a171fe39 | 2097 | |
55e5c285 | 2098 | s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121); |
c1713132 | 2099 | |
751c6a17 | 2100 | dinfo = drive_get(IF_SD, 0, 0); |
a82929a2 TH |
2101 | if (!dinfo && !qtest_enabled()) { |
2102 | warn_report("missing SecureDigital device"); | |
e4bcb14c | 2103 | } |
fa1d36df | 2104 | s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, |
a82929a2 | 2105 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
2115c019 AZ |
2106 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2107 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), | |
2108 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); | |
a171fe39 | 2109 | |
fb50cfe4 | 2110 | for (i = 0; pxa270_serial[i].io_base; i++) { |
9bca0edb | 2111 | if (serial_hd(i)) { |
a6dc4c2d | 2112 | serial_mm_init(address_space, pxa270_serial[i].io_base, 2, |
fb50cfe4 | 2113 | qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), |
9bca0edb | 2114 | 14857000 / 16, serial_hd(i), |
fb50cfe4 RH |
2115 | DEVICE_NATIVE_ENDIAN); |
2116 | } else { | |
c1713132 | 2117 | break; |
fb50cfe4 RH |
2118 | } |
2119 | } | |
9bca0edb | 2120 | if (serial_hd(i)) |
adfc39ea | 2121 | s->fir = pxa2xx_fir_init(address_space, 0x40800000, |
e1f8c729 | 2122 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2115c019 AZ |
2123 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2124 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), | |
9bca0edb | 2125 | serial_hd(i)); |
c1713132 | 2126 | |
5a6fdd91 | 2127 | s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, |
e1f8c729 | 2128 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
a171fe39 | 2129 | |
c1713132 | 2130 | s->cm_base = 0x41300000; |
82d17978 | 2131 | s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ |
c1713132 | 2132 | s->clkcfg = 0x00000009; /* Turbo mode active */ |
2c9b15ca | 2133 | memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
adfc39ea | 2134 | memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
ae1f90de | 2135 | vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
c1713132 | 2136 | |
dc2a9045 | 2137 | pxa2xx_setup_cp14(s); |
c1713132 AZ |
2138 | |
2139 | s->mm_base = 0x48000000; | |
2140 | s->mm_regs[MDMRS >> 2] = 0x00020002; | |
2141 | s->mm_regs[MDREFR >> 2] = 0x03ca4000; | |
2142 | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ | |
2c9b15ca | 2143 | memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
adfc39ea | 2144 | memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
d102d495 | 2145 | vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
c1713132 | 2146 | |
2a163929 | 2147 | s->pm_base = 0x40f00000; |
2c9b15ca | 2148 | memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
adfc39ea | 2149 | memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
f0ab24ce | 2150 | vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2a163929 | 2151 | |
c1713132 | 2152 | for (i = 0; pxa27x_ssp[i].io_base; i ++); |
b45c03f5 | 2153 | s->ssp = g_new0(SSIBus *, i); |
c1713132 | 2154 | for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
a984a69e | 2155 | DeviceState *dev; |
12a82804 | 2156 | dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base, |
e1f8c729 | 2157 | qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn)); |
02e2da45 | 2158 | s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
c1713132 AZ |
2159 | } |
2160 | ||
c92cfba8 EH |
2161 | sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2162 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); | |
a171fe39 | 2163 | |
354a8c06 BC |
2164 | s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2165 | s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); | |
a171fe39 | 2166 | |
548c6f18 | 2167 | sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, |
8a231487 | 2168 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
c1713132 | 2169 | |
e1f8c729 DES |
2170 | s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2171 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); | |
2172 | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, | |
2173 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); | |
c1713132 | 2174 | |
9c843933 | 2175 | s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, |
2115c019 AZ |
2176 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2177 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), | |
2178 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); | |
c1713132 | 2179 | |
6cd816b8 | 2180 | s->kp = pxa27x_keypad_init(address_space, 0x41500000, |
e1f8c729 | 2181 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); |
31b87f2e | 2182 | |
c1713132 | 2183 | /* GPIO1 resets the processor */ |
fe8f096b | 2184 | /* The handler can be overridden by board-specific code */ |
0bb53337 | 2185 | qdev_connect_gpio_out(s->gpio, 1, s->reset); |
c1713132 AZ |
2186 | return s; |
2187 | } | |
2188 | ||
2189 | /* Initialise a PXA255 integrated chip (ARM based core). */ | |
a6dc4c2d | 2190 | PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) |
c1713132 | 2191 | { |
bc24a225 | 2192 | PXA2xxState *s; |
adfc39ea | 2193 | int i; |
751c6a17 | 2194 | DriveInfo *dinfo; |
aaed909a | 2195 | |
b45c03f5 | 2196 | s = g_new0(PXA2xxState, 1); |
c1713132 | 2197 | |
ba1ba5cc | 2198 | s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255"))); |
f3c7d038 | 2199 | s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0); |
38641a52 | 2200 | |
d95b2f8d | 2201 | /* SDRAM & Internal Memory Storage */ |
98a99ce0 | 2202 | memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, |
f8ed85ac | 2203 | &error_fatal); |
adfc39ea | 2204 | memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); |
98a99ce0 | 2205 | memory_region_init_ram(&s->internal, NULL, "pxa255.internal", |
f8ed85ac | 2206 | PXA2XX_INTERNAL_SIZE, &error_fatal); |
adfc39ea AK |
2207 | memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, |
2208 | &s->internal); | |
d95b2f8d | 2209 | |
f161bcd0 | 2210 | s->pic = pxa2xx_pic_init(0x40d00000, s->cpu); |
c1713132 | 2211 | |
e1f8c729 DES |
2212 | s->dma = pxa255_dma_init(0x40000000, |
2213 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); | |
c1713132 | 2214 | |
797e9542 DES |
2215 | sysbus_create_varargs("pxa25x-timer", 0x40a00000, |
2216 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0), | |
2217 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1), | |
2218 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2), | |
2219 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), | |
2220 | NULL); | |
a171fe39 | 2221 | |
55e5c285 | 2222 | s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85); |
c1713132 | 2223 | |
751c6a17 | 2224 | dinfo = drive_get(IF_SD, 0, 0); |
a82929a2 TH |
2225 | if (!dinfo && !qtest_enabled()) { |
2226 | warn_report("missing SecureDigital device"); | |
e4bcb14c | 2227 | } |
fa1d36df | 2228 | s->mmc = pxa2xx_mmci_init(address_space, 0x41100000, |
a82929a2 | 2229 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
2115c019 AZ |
2230 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), |
2231 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), | |
2232 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); | |
a171fe39 | 2233 | |
fb50cfe4 | 2234 | for (i = 0; pxa255_serial[i].io_base; i++) { |
9bca0edb | 2235 | if (serial_hd(i)) { |
a6dc4c2d | 2236 | serial_mm_init(address_space, pxa255_serial[i].io_base, 2, |
fb50cfe4 | 2237 | qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), |
9bca0edb | 2238 | 14745600 / 16, serial_hd(i), |
fb50cfe4 | 2239 | DEVICE_NATIVE_ENDIAN); |
2d48377a | 2240 | } else { |
c1713132 | 2241 | break; |
2d48377a | 2242 | } |
fb50cfe4 | 2243 | } |
9bca0edb | 2244 | if (serial_hd(i)) |
adfc39ea | 2245 | s->fir = pxa2xx_fir_init(address_space, 0x40800000, |
e1f8c729 | 2246 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), |
2115c019 AZ |
2247 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), |
2248 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), | |
9bca0edb | 2249 | serial_hd(i)); |
c1713132 | 2250 | |
5a6fdd91 | 2251 | s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, |
e1f8c729 | 2252 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); |
a171fe39 | 2253 | |
c1713132 | 2254 | s->cm_base = 0x41300000; |
e9aff986 GR |
2255 | s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */ |
2256 | s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */ | |
2257 | ||
c1713132 | 2258 | s->clkcfg = 0x00000009; /* Turbo mode active */ |
2c9b15ca | 2259 | memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); |
adfc39ea | 2260 | memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); |
ae1f90de | 2261 | vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); |
c1713132 | 2262 | |
dc2a9045 | 2263 | pxa2xx_setup_cp14(s); |
c1713132 AZ |
2264 | |
2265 | s->mm_base = 0x48000000; | |
2266 | s->mm_regs[MDMRS >> 2] = 0x00020002; | |
2267 | s->mm_regs[MDREFR >> 2] = 0x03ca4000; | |
2268 | s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ | |
2c9b15ca | 2269 | memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); |
adfc39ea | 2270 | memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); |
d102d495 | 2271 | vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); |
c1713132 | 2272 | |
2a163929 | 2273 | s->pm_base = 0x40f00000; |
2c9b15ca | 2274 | memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); |
adfc39ea | 2275 | memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); |
f0ab24ce | 2276 | vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); |
2a163929 | 2277 | |
c1713132 | 2278 | for (i = 0; pxa255_ssp[i].io_base; i ++); |
b45c03f5 | 2279 | s->ssp = g_new0(SSIBus *, i); |
c1713132 | 2280 | for (i = 0; pxa255_ssp[i].io_base; i ++) { |
a984a69e | 2281 | DeviceState *dev; |
12a82804 | 2282 | dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base, |
e1f8c729 | 2283 | qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn)); |
02e2da45 | 2284 | s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); |
c1713132 AZ |
2285 | } |
2286 | ||
c92cfba8 EH |
2287 | sysbus_create_simple("sysbus-ohci", 0x4c000000, |
2288 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); | |
a171fe39 | 2289 | |
354a8c06 BC |
2290 | s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); |
2291 | s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); | |
a171fe39 | 2292 | |
548c6f18 | 2293 | sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, |
8a231487 | 2294 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); |
c1713132 | 2295 | |
e1f8c729 DES |
2296 | s->i2c[0] = pxa2xx_i2c_init(0x40301600, |
2297 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff); | |
2298 | s->i2c[1] = pxa2xx_i2c_init(0x40f00100, | |
2299 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); | |
c1713132 | 2300 | |
9c843933 | 2301 | s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, |
2115c019 AZ |
2302 | qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), |
2303 | qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), | |
2304 | qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); | |
c1713132 AZ |
2305 | |
2306 | /* GPIO1 resets the processor */ | |
fe8f096b | 2307 | /* The handler can be overridden by board-specific code */ |
0bb53337 | 2308 | qdev_connect_gpio_out(s->gpio, 1, s->reset); |
c1713132 AZ |
2309 | return s; |
2310 | } | |
e3b42536 | 2311 | |
999e12bb AL |
2312 | static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data) |
2313 | { | |
ce320346 | 2314 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2315 | |
ce320346 | 2316 | dc->reset = pxa2xx_ssp_reset; |
8e079caf | 2317 | dc->vmsd = &vmstate_pxa2xx_ssp; |
999e12bb AL |
2318 | } |
2319 | ||
8c43a6f0 | 2320 | static const TypeInfo pxa2xx_ssp_info = { |
12a82804 | 2321 | .name = TYPE_PXA2XX_SSP, |
39bffca2 AL |
2322 | .parent = TYPE_SYS_BUS_DEVICE, |
2323 | .instance_size = sizeof(PXA2xxSSPState), | |
0493a139 | 2324 | .instance_init = pxa2xx_ssp_init, |
39bffca2 | 2325 | .class_init = pxa2xx_ssp_class_init, |
999e12bb AL |
2326 | }; |
2327 | ||
83f7d43a | 2328 | static void pxa2xx_register_types(void) |
e3b42536 | 2329 | { |
39bffca2 AL |
2330 | type_register_static(&pxa2xx_i2c_slave_info); |
2331 | type_register_static(&pxa2xx_ssp_info); | |
2332 | type_register_static(&pxa2xx_i2c_info); | |
2333 | type_register_static(&pxa2xx_rtc_sysbus_info); | |
1fd9f2df | 2334 | type_register_static(&pxa2xx_fir_info); |
e3b42536 PB |
2335 | } |
2336 | ||
83f7d43a | 2337 | type_init(pxa2xx_register_types) |