[mirror_qemu.git] / hw / arm / pxa2xx_gpio.c

/*
 * Intel XScale PXA255/270 GPIO controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"
#include "qemu/log.h"

#define PXA2XX_GPIO_BANKS	4

#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
#define PXA2XX_GPIO(obj) \
    OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)

typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    qemu_irq irq0, irq1, irqX;
    int lines;
    int ncpu;
    ARMCPU *cpu;

    /* XXX: GNU C vectors are more suitable */
    uint32_t ilevel[PXA2XX_GPIO_BANKS];
    uint32_t olevel[PXA2XX_GPIO_BANKS];
    uint32_t dir[PXA2XX_GPIO_BANKS];
    uint32_t rising[PXA2XX_GPIO_BANKS];
    uint32_t falling[PXA2XX_GPIO_BANKS];
    uint32_t status[PXA2XX_GPIO_BANKS];
    uint32_t gafr[PXA2XX_GPIO_BANKS * 2];

    uint32_t prev_level[PXA2XX_GPIO_BANKS];
    qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
    qemu_irq read_notify;
};

static struct {
    enum {
        GPIO_NONE,
        GPLR,
        GPSR,
        GPCR,
        GPDR,
        GRER,
        GFER,
        GEDR,
        GAFR_L,
        GAFR_U,
    } reg;
    int bank;
} pxa2xx_gpio_regs[0x200] = {
    [0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3)	\
    [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },

    PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
    PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
    PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
    PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
    PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
    PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
    PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
    PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
    PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};

static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
    if (s->status[0] & (1 << 0))
        qemu_irq_raise(s->irq0);
    else
        qemu_irq_lower(s->irq0);

    if (s->status[0] & (1 << 1))
        qemu_irq_raise(s->irq1);
    else
        qemu_irq_lower(s->irq1);

    if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
        qemu_irq_raise(s->irqX);
    else
        qemu_irq_lower(s->irqX);
}

/* Bitmap of pins used as standby and sleep wake-up sources.  */
static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
    0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};

static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    CPUState *cpu = CPU(s->cpu);
    int bank;
    uint32_t mask;

    if (line >= s->lines) {
        printf("%s: No GPIO pin %i\n", __func__, line);
        return;
    }

    bank = line >> 5;
    mask = 1U << (line & 31);

    if (level) {
        s->status[bank] |= s->rising[bank] & mask &
                ~s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] |= mask;
    } else {
        s->status[bank] |= s->falling[bank] & mask &
                s->ilevel[bank] & ~s->dir[bank];
        s->ilevel[bank] &= ~mask;
    }

    if (s->status[bank] & mask)
        pxa2xx_gpio_irq_update(s);

    /* Wake-up GPIOs */
    if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
    }
}

static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
    uint32_t level, diff;
    int i, bit, line;
    for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
        level = s->olevel[i] & s->dir[i];

        for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
            bit = ctz32(diff);
            line = bit + 32 * i;
            qemu_set_irq(s->handler[line], (level >> bit) & 1);
        }

        s->prev_level[i] = level;
    }
}

static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
                                 unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    uint32_t ret;
    int bank;
    if (offset >= 0x200)
        return 0;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        return s->dir[bank];

    case GPSR:		/* GPIO Pin-Output Set registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPSR\n");
        return 0;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx GPIO: read from write only register GPCR\n");
        return 0;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        return s->rising[bank];

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        return s->falling[bank];

    case GAFR_L:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2];

    case GAFR_U:	/* GPIO Alternate Function registers */
        return s->gafr[bank * 2 + 1];

    case GPLR:		/* GPIO Pin-Level registers */
        ret = (s->olevel[bank] & s->dir[bank]) |
                (s->ilevel[bank] & ~s->dir[bank]);
        qemu_irq_raise(s->read_notify);
        return ret;

    case GEDR:		/* GPIO Edge Detect Status registers */
        return s->status[bank];

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }

    return 0;
}

static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
    int bank;
    if (offset >= 0x200)
        return;

    bank = pxa2xx_gpio_regs[offset].bank;
    switch (pxa2xx_gpio_regs[offset].reg) {
    case GPDR:		/* GPIO Pin-Direction registers */
        s->dir[bank] = value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPSR:		/* GPIO Pin-Output Set registers */
        s->olevel[bank] |= value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GPCR:		/* GPIO Pin-Output Clear registers */
        s->olevel[bank] &= ~value;
        pxa2xx_gpio_handler_update(s);
        break;

    case GRER:		/* GPIO Rising-Edge Detect Enable registers */
        s->rising[bank] = value;
        break;

    case GFER:		/* GPIO Falling-Edge Detect Enable registers */
        s->falling[bank] = value;
        break;

    case GAFR_L:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2] = value;
        break;

    case GAFR_U:	/* GPIO Alternate Function registers */
        s->gafr[bank * 2 + 1] = value;
        break;

    case GEDR:		/* GPIO Edge Detect Status registers */
        s->status[bank] &= ~value;
        pxa2xx_gpio_irq_update(s);
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
    }
}

static const MemoryRegionOps pxa_gpio_ops = {
    .read = pxa2xx_gpio_read,
    .write = pxa2xx_gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines)
{
    CPUState *cs = CPU(cpu);
    DeviceState *dev;

    dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
    qdev_prop_set_int32(dev, "lines", lines);
    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
    qdev_init_nofail(dev);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
                    qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));

    return dev;
}

static void pxa2xx_gpio_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(sbd);
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
                          s, "pxa2xx-gpio", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq0);
    sysbus_init_irq(sbd, &s->irq1);
    sysbus_init_irq(sbd, &s->irqX);
}

static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));

    qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
    qdev_init_gpio_out(dev, s->handler, s->lines);
}

/*
 * Registers a callback to notify on GPLR reads.  This normally
 * shouldn't be needed but it is used for the hack on Spitz machines.
 */
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
{
    PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);

    s->read_notify = handler;
}

static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
    .name = "pxa2xx-gpio",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
        VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
        VMSTATE_END_OF_LIST(),
    },
};

static Property pxa2xx_gpio_properties[] = {
    DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
    DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx GPIO controller";
    dc->props = pxa2xx_gpio_properties;
    dc->vmsd = &vmstate_pxa2xx_gpio_regs;
    dc->realize = pxa2xx_gpio_realize;
}

static const TypeInfo pxa2xx_gpio_info = {
    .name          = TYPE_PXA2XX_GPIO,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxGPIOInfo),
    .instance_init = pxa2xx_gpio_initfn,
    .class_init    = pxa2xx_gpio_class_init,
};

static void pxa2xx_gpio_register_types(void)
{
    type_register_static(&pxa2xx_gpio_info);
}

type_init(pxa2xx_gpio_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 GPIO controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPL.
	8	*/
	9
12b16722	10	#include "qemu/osdep.h"
33c11879	11	#include "cpu.h"
83c9f4ca PB	12	#include "hw/hw.h"
83c9f4ca PB	13	#include "hw/sysbus.h"
0d09e41a	14	#include "hw/arm/pxa.h"
03dd024f	15	#include "qemu/log.h"
c1713132 AZ	16
	17	#define PXA2XX_GPIO_BANKS 4
	18
922bb317 AF	19	#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
	20	#define PXA2XX_GPIO(obj) \
	21	OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
	22
0bb53337	23	typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
bc24a225	24	struct PXA2xxGPIOInfo {
922bb317 AF	25	/< private >/
	26	SysBusDevice parent_obj;
	27	/< public >/
	28
55a8b801	29	MemoryRegion iomem;
0bb53337	30	qemu_irq irq0, irq1, irqX;
c1713132	31	int lines;
0bb53337	32	int ncpu;
95d42bb5	33	ARMCPU *cpu;
c1713132 AZ	34
	35	/* XXX: GNU C vectors are more suitable */
	36	uint32_t ilevel[PXA2XX_GPIO_BANKS];
	37	uint32_t olevel[PXA2XX_GPIO_BANKS];
	38	uint32_t dir[PXA2XX_GPIO_BANKS];
	39	uint32_t rising[PXA2XX_GPIO_BANKS];
	40	uint32_t falling[PXA2XX_GPIO_BANKS];
	41	uint32_t status[PXA2XX_GPIO_BANKS];
	42	uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
	43
	44	uint32_t prev_level[PXA2XX_GPIO_BANKS];
38641a52 AZ	45	qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
38641a52 AZ	46	qemu_irq read_notify;
c1713132 AZ	47	};
	48
	49	static struct {
	50	enum {
	51	GPIO_NONE,
	52	GPLR,
	53	GPSR,
	54	GPCR,
	55	GPDR,
	56	GRER,
	57	GFER,
	58	GEDR,
	59	GAFR_L,
	60	GAFR_U,
	61	} reg;
	62	int bank;
	63	} pxa2xx_gpio_regs[0x200] = {
	64	[0 ... 0x1ff] = { GPIO_NONE, 0 },
	65	#define PXA2XX_REG(reg, a0, a1, a2, a3) \
5fafdf24	66	[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
c1713132 AZ	67
	68	PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
	69	PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
	70	PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
	71	PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
	72	PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
	73	PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
	74	PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
	75	PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
	76	PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
	77	};
	78
bc24a225	79	static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
c1713132 AZ	80	{
c1713132 AZ	81	if (s->status[0] & (1 << 0))
0bb53337	82	qemu_irq_raise(s->irq0);
c1713132	83	else
0bb53337	84	qemu_irq_lower(s->irq0);
c1713132 AZ	85
c1713132 AZ	86	if (s->status[0] & (1 << 1))
0bb53337	87	qemu_irq_raise(s->irq1);
c1713132	88	else
0bb53337	89	qemu_irq_lower(s->irq1);
c1713132 AZ	90
c1713132 AZ	91	if ((s->status[0] & ~3) \| s->status[1] \| s->status[2] \| s->status[3])
0bb53337	92	qemu_irq_raise(s->irqX);
c1713132	93	else
0bb53337	94	qemu_irq_lower(s->irqX);
c1713132 AZ	95	}
	96
	97	/* Bitmap of pins used as standby and sleep wake-up sources. */
38641a52	98	static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
c1713132 AZ	99	0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
	100	};
	101
38641a52	102	static void pxa2xx_gpio_set(void *opaque, int line, int level)
c1713132	103	{
bc24a225	104	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
259186a7	105	CPUState *cpu = CPU(s->cpu);
c1713132 AZ	106	int bank;
	107	uint32_t mask;
	108
	109	if (line >= s->lines) {
a89f364a	110	printf("%s: No GPIO pin %i\n", __func__, line);
c1713132 AZ	111	return;
	112	}
	113
	114	bank = line >> 5;
43a32ed6	115	mask = 1U << (line & 31);
c1713132 AZ	116
	117	if (level) {
	118	s->status[bank] \|= s->rising[bank] & mask &
	119	~s->ilevel[bank] & ~s->dir[bank];
	120	s->ilevel[bank] \|= mask;
	121	} else {
	122	s->status[bank] \|= s->falling[bank] & mask &
	123	s->ilevel[bank] & ~s->dir[bank];
	124	s->ilevel[bank] &= ~mask;
	125	}
	126
	127	if (s->status[bank] & mask)
	128	pxa2xx_gpio_irq_update(s);
	129
	130	/* Wake-up GPIOs */
259186a7	131	if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
c3affe56	132	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
95d42bb5	133	}
c1713132 AZ	134	}
c1713132 AZ	135
bc24a225	136	static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
c1713132 AZ	137	uint32_t level, diff;
	138	int i, bit, line;
	139	for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
	140	level = s->olevel[i] & s->dir[i];
	141
	142	for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
786a4ea8	143	bit = ctz32(diff);
c1713132	144	line = bit + 32 * i;
38641a52	145	qemu_set_irq(s->handler[line], (level >> bit) & 1);
c1713132 AZ	146	}
	147
	148	s->prev_level[i] = level;
	149	}
	150	}
	151
a8170e5e	152	static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
55a8b801	153	unsigned size)
c1713132	154	{
bc24a225	155	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132 AZ	156	uint32_t ret;
c1713132 AZ	157	int bank;
c1713132 AZ	158	if (offset >= 0x200)
	159	return 0;
	160
	161	bank = pxa2xx_gpio_regs[offset].bank;
	162	switch (pxa2xx_gpio_regs[offset].reg) {
	163	case GPDR: /* GPIO Pin-Direction registers */
	164	return s->dir[bank];
	165
2b76bdc9	166	case GPSR: /* GPIO Pin-Output Set registers */
ab7a0f0b PM	167	qemu_log_mask(LOG_GUEST_ERROR,
	168	"pxa2xx GPIO: read from write only register GPSR\n");
	169	return 0;
2b76bdc9	170
e1dad5a6	171	case GPCR: /* GPIO Pin-Output Clear registers */
ab7a0f0b PM	172	qemu_log_mask(LOG_GUEST_ERROR,
	173	"pxa2xx GPIO: read from write only register GPCR\n");
	174	return 0;
e1dad5a6	175
c1713132 AZ	176	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	177	return s->rising[bank];
	178
	179	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	180	return s->falling[bank];
	181
	182	case GAFR_L: /* GPIO Alternate Function registers */
	183	return s->gafr[bank * 2];
	184
	185	case GAFR_U: /* GPIO Alternate Function registers */
	186	return s->gafr[bank * 2 + 1];
	187
	188	case GPLR: /* GPIO Pin-Level registers */
	189	ret = (s->olevel[bank] & s->dir[bank]) \|
	190	(s->ilevel[bank] & ~s->dir[bank]);
38641a52	191	qemu_irq_raise(s->read_notify);
c1713132 AZ	192	return ret;
	193
	194	case GEDR: /* GPIO Edge Detect Status registers */
	195	return s->status[bank];
	196
	197	default:
a89f364a	198	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	199	}
	200
	201	return 0;
	202	}
	203
a8170e5e	204	static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
55a8b801	205	uint64_t value, unsigned size)
c1713132	206	{
bc24a225	207	PXA2xxGPIOInfo s = (PXA2xxGPIOInfo ) opaque;
c1713132	208	int bank;
c1713132 AZ	209	if (offset >= 0x200)
	210	return;
	211
	212	bank = pxa2xx_gpio_regs[offset].bank;
	213	switch (pxa2xx_gpio_regs[offset].reg) {
	214	case GPDR: /* GPIO Pin-Direction registers */
	215	s->dir[bank] = value;
	216	pxa2xx_gpio_handler_update(s);
	217	break;
	218
	219	case GPSR: /* GPIO Pin-Output Set registers */
	220	s->olevel[bank] \|= value;
	221	pxa2xx_gpio_handler_update(s);
	222	break;
	223
	224	case GPCR: /* GPIO Pin-Output Clear registers */
	225	s->olevel[bank] &= ~value;
	226	pxa2xx_gpio_handler_update(s);
	227	break;
	228
	229	case GRER: /* GPIO Rising-Edge Detect Enable registers */
	230	s->rising[bank] = value;
	231	break;
	232
	233	case GFER: /* GPIO Falling-Edge Detect Enable registers */
	234	s->falling[bank] = value;
	235	break;
	236
	237	case GAFR_L: /* GPIO Alternate Function registers */
	238	s->gafr[bank * 2] = value;
	239	break;
	240
	241	case GAFR_U: /* GPIO Alternate Function registers */
	242	s->gafr[bank * 2 + 1] = value;
	243	break;
	244
	245	case GEDR: /* GPIO Edge Detect Status registers */
	246	s->status[bank] &= ~value;
	247	pxa2xx_gpio_irq_update(s);
	248	break;
	249
	250	default:
a89f364a	251	hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
c1713132 AZ	252	}
	253	}
	254
55a8b801 BC	255	static const MemoryRegionOps pxa_gpio_ops = {
	256	.read = pxa2xx_gpio_read,
	257	.write = pxa2xx_gpio_write,
	258	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	259	};
c1713132 AZ	260
a8170e5e	261	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	262	ARMCPU cpu, DeviceState pic, int lines)
aa941b94	263	{
55e5c285	264	CPUState *cs = CPU(cpu);
0bb53337	265	DeviceState *dev;
aa941b94	266
922bb317	267	dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
0bb53337	268	qdev_prop_set_int32(dev, "lines", lines);
55e5c285	269	qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
0bb53337	270	qdev_init_nofail(dev);
aa941b94	271
1356b98d AF	272	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1356b98d AF	273	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
e1f8c729	274	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
1356b98d	275	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
e1f8c729	276	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
1356b98d	277	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
e1f8c729	278	qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
aa941b94	279
0bb53337	280	return dev;
aa941b94 AZ	281	}
aa941b94 AZ	282
f79a7ff1	283	static void pxa2xx_gpio_initfn(Object *obj)
c1713132	284	{
f79a7ff1	285	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
922bb317 AF	286	DeviceState *dev = DEVICE(sbd);
922bb317 AF	287	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
c1713132	288
f79a7ff1 XZ	289	memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
f79a7ff1 XZ	290	s, "pxa2xx-gpio", 0x1000);
922bb317 AF	291	sysbus_init_mmio(sbd, &s->iomem);
	292	sysbus_init_irq(sbd, &s->irq0);
	293	sysbus_init_irq(sbd, &s->irq1);
	294	sysbus_init_irq(sbd, &s->irqX);
f79a7ff1	295	}
c1713132	296
f79a7ff1 XZ	297	static void pxa2xx_gpio_realize(DeviceState dev, Error *errp)
	298	{
	299	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
	300
	301	s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
	302
	303	qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
	304	qdev_init_gpio_out(dev, s->handler, s->lines);
c1713132 AZ	305	}
	306
	307	/*
	308	* Registers a callback to notify on GPLR reads. This normally
	309	* shouldn't be needed but it is used for the hack on Spitz machines.
	310	*/
0bb53337	311	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
38641a52	312	{
922bb317 AF	313	PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
922bb317 AF	314
c1713132	315	s->read_notify = handler;
c1713132	316	}
0bb53337 DES	317
	318	static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
	319	.name = "pxa2xx-gpio",
	320	.version_id = 1,
	321	.minimum_version_id = 1,
8f1e884b	322	.fields = (VMStateField[]) {
0bb53337 DES	323	VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	324	VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	325	VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	326	VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	327	VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	328	VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
	329	VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
166fa999	330	VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
0bb53337 DES	331	VMSTATE_END_OF_LIST(),
	332	},
	333	};
	334
999e12bb AL	335	static Property pxa2xx_gpio_properties[] = {
	336	DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
	337	DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
	338	DEFINE_PROP_END_OF_LIST(),
	339	};
	340
	341	static void pxa2xx_gpio_class_init(ObjectClass klass, void data)
	342	{
39bffca2	343	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	344
39bffca2 AL	345	dc->desc = "PXA2xx GPIO controller";
39bffca2 AL	346	dc->props = pxa2xx_gpio_properties;
166fa999	347	dc->vmsd = &vmstate_pxa2xx_gpio_regs;
f79a7ff1	348	dc->realize = pxa2xx_gpio_realize;
999e12bb AL	349	}
999e12bb AL	350
8c43a6f0	351	static const TypeInfo pxa2xx_gpio_info = {
922bb317	352	.name = TYPE_PXA2XX_GPIO,
39bffca2 AL	353	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	354	.instance_size = sizeof(PXA2xxGPIOInfo),
f79a7ff1	355	.instance_init = pxa2xx_gpio_initfn,
39bffca2	356	.class_init = pxa2xx_gpio_class_init,
0bb53337 DES	357	};
0bb53337 DES	358
83f7d43a	359	static void pxa2xx_gpio_register_types(void)
0bb53337	360	{
39bffca2	361	type_register_static(&pxa2xx_gpio_info);
0bb53337	362	}
83f7d43a AF	363
83f7d43a AF	364	type_init(pxa2xx_gpio_register_types)