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Commit | Line | Data |
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c1713132 AZ |
1 | /* |
2 | * Intel XScale PXA255/270 GPIO controller emulation. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <balrog@zabor.org> | |
6 | * | |
7 | * This code is licensed under the GPL. | |
8 | */ | |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
33c11879 | 11 | #include "cpu.h" |
64552b6b | 12 | #include "hw/irq.h" |
a27bd6c7 | 13 | #include "hw/qdev-properties.h" |
83c9f4ca | 14 | #include "hw/sysbus.h" |
d6454270 | 15 | #include "migration/vmstate.h" |
0d09e41a | 16 | #include "hw/arm/pxa.h" |
3e80f690 | 17 | #include "qapi/error.h" |
03dd024f | 18 | #include "qemu/log.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
db1015e9 | 20 | #include "qom/object.h" |
c1713132 AZ |
21 | |
22 | #define PXA2XX_GPIO_BANKS 4 | |
23 | ||
922bb317 | 24 | #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" |
8063396b | 25 | OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO) |
922bb317 | 26 | |
bc24a225 | 27 | struct PXA2xxGPIOInfo { |
922bb317 AF |
28 | /*< private >*/ |
29 | SysBusDevice parent_obj; | |
30 | /*< public >*/ | |
31 | ||
55a8b801 | 32 | MemoryRegion iomem; |
0bb53337 | 33 | qemu_irq irq0, irq1, irqX; |
c1713132 | 34 | int lines; |
0bb53337 | 35 | int ncpu; |
95d42bb5 | 36 | ARMCPU *cpu; |
c1713132 AZ |
37 | |
38 | /* XXX: GNU C vectors are more suitable */ | |
39 | uint32_t ilevel[PXA2XX_GPIO_BANKS]; | |
40 | uint32_t olevel[PXA2XX_GPIO_BANKS]; | |
41 | uint32_t dir[PXA2XX_GPIO_BANKS]; | |
42 | uint32_t rising[PXA2XX_GPIO_BANKS]; | |
43 | uint32_t falling[PXA2XX_GPIO_BANKS]; | |
44 | uint32_t status[PXA2XX_GPIO_BANKS]; | |
45 | uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; | |
46 | ||
47 | uint32_t prev_level[PXA2XX_GPIO_BANKS]; | |
38641a52 AZ |
48 | qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; |
49 | qemu_irq read_notify; | |
c1713132 AZ |
50 | }; |
51 | ||
52 | static struct { | |
53 | enum { | |
54 | GPIO_NONE, | |
55 | GPLR, | |
56 | GPSR, | |
57 | GPCR, | |
58 | GPDR, | |
59 | GRER, | |
60 | GFER, | |
61 | GEDR, | |
62 | GAFR_L, | |
63 | GAFR_U, | |
64 | } reg; | |
65 | int bank; | |
66 | } pxa2xx_gpio_regs[0x200] = { | |
67 | [0 ... 0x1ff] = { GPIO_NONE, 0 }, | |
68 | #define PXA2XX_REG(reg, a0, a1, a2, a3) \ | |
5fafdf24 | 69 | [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, |
c1713132 AZ |
70 | |
71 | PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) | |
72 | PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) | |
73 | PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) | |
74 | PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) | |
75 | PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) | |
76 | PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) | |
77 | PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) | |
78 | PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) | |
79 | PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) | |
80 | }; | |
81 | ||
bc24a225 | 82 | static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) |
c1713132 AZ |
83 | { |
84 | if (s->status[0] & (1 << 0)) | |
0bb53337 | 85 | qemu_irq_raise(s->irq0); |
c1713132 | 86 | else |
0bb53337 | 87 | qemu_irq_lower(s->irq0); |
c1713132 AZ |
88 | |
89 | if (s->status[0] & (1 << 1)) | |
0bb53337 | 90 | qemu_irq_raise(s->irq1); |
c1713132 | 91 | else |
0bb53337 | 92 | qemu_irq_lower(s->irq1); |
c1713132 AZ |
93 | |
94 | if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) | |
0bb53337 | 95 | qemu_irq_raise(s->irqX); |
c1713132 | 96 | else |
0bb53337 | 97 | qemu_irq_lower(s->irqX); |
c1713132 AZ |
98 | } |
99 | ||
100 | /* Bitmap of pins used as standby and sleep wake-up sources. */ | |
38641a52 | 101 | static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { |
c1713132 AZ |
102 | 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, |
103 | }; | |
104 | ||
38641a52 | 105 | static void pxa2xx_gpio_set(void *opaque, int line, int level) |
c1713132 | 106 | { |
bc24a225 | 107 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
259186a7 | 108 | CPUState *cpu = CPU(s->cpu); |
c1713132 AZ |
109 | int bank; |
110 | uint32_t mask; | |
111 | ||
112 | if (line >= s->lines) { | |
a89f364a | 113 | printf("%s: No GPIO pin %i\n", __func__, line); |
c1713132 AZ |
114 | return; |
115 | } | |
116 | ||
117 | bank = line >> 5; | |
43a32ed6 | 118 | mask = 1U << (line & 31); |
c1713132 AZ |
119 | |
120 | if (level) { | |
121 | s->status[bank] |= s->rising[bank] & mask & | |
122 | ~s->ilevel[bank] & ~s->dir[bank]; | |
123 | s->ilevel[bank] |= mask; | |
124 | } else { | |
125 | s->status[bank] |= s->falling[bank] & mask & | |
126 | s->ilevel[bank] & ~s->dir[bank]; | |
127 | s->ilevel[bank] &= ~mask; | |
128 | } | |
129 | ||
130 | if (s->status[bank] & mask) | |
131 | pxa2xx_gpio_irq_update(s); | |
132 | ||
133 | /* Wake-up GPIOs */ | |
259186a7 | 134 | if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { |
c3affe56 | 135 | cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
95d42bb5 | 136 | } |
c1713132 AZ |
137 | } |
138 | ||
bc24a225 | 139 | static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { |
c1713132 AZ |
140 | uint32_t level, diff; |
141 | int i, bit, line; | |
142 | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { | |
143 | level = s->olevel[i] & s->dir[i]; | |
144 | ||
145 | for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { | |
786a4ea8 | 146 | bit = ctz32(diff); |
c1713132 | 147 | line = bit + 32 * i; |
38641a52 | 148 | qemu_set_irq(s->handler[line], (level >> bit) & 1); |
c1713132 AZ |
149 | } |
150 | ||
151 | s->prev_level[i] = level; | |
152 | } | |
153 | } | |
154 | ||
a8170e5e | 155 | static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, |
55a8b801 | 156 | unsigned size) |
c1713132 | 157 | { |
bc24a225 | 158 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
c1713132 AZ |
159 | uint32_t ret; |
160 | int bank; | |
c1713132 AZ |
161 | if (offset >= 0x200) |
162 | return 0; | |
163 | ||
164 | bank = pxa2xx_gpio_regs[offset].bank; | |
165 | switch (pxa2xx_gpio_regs[offset].reg) { | |
166 | case GPDR: /* GPIO Pin-Direction registers */ | |
167 | return s->dir[bank]; | |
168 | ||
2b76bdc9 | 169 | case GPSR: /* GPIO Pin-Output Set registers */ |
ab7a0f0b PM |
170 | qemu_log_mask(LOG_GUEST_ERROR, |
171 | "pxa2xx GPIO: read from write only register GPSR\n"); | |
172 | return 0; | |
2b76bdc9 | 173 | |
e1dad5a6 | 174 | case GPCR: /* GPIO Pin-Output Clear registers */ |
ab7a0f0b PM |
175 | qemu_log_mask(LOG_GUEST_ERROR, |
176 | "pxa2xx GPIO: read from write only register GPCR\n"); | |
177 | return 0; | |
e1dad5a6 | 178 | |
c1713132 AZ |
179 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
180 | return s->rising[bank]; | |
181 | ||
182 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ | |
183 | return s->falling[bank]; | |
184 | ||
185 | case GAFR_L: /* GPIO Alternate Function registers */ | |
186 | return s->gafr[bank * 2]; | |
187 | ||
188 | case GAFR_U: /* GPIO Alternate Function registers */ | |
189 | return s->gafr[bank * 2 + 1]; | |
190 | ||
191 | case GPLR: /* GPIO Pin-Level registers */ | |
192 | ret = (s->olevel[bank] & s->dir[bank]) | | |
193 | (s->ilevel[bank] & ~s->dir[bank]); | |
38641a52 | 194 | qemu_irq_raise(s->read_notify); |
c1713132 AZ |
195 | return ret; |
196 | ||
197 | case GEDR: /* GPIO Edge Detect Status registers */ | |
198 | return s->status[bank]; | |
199 | ||
200 | default: | |
5a0001ec PMD |
201 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
202 | __func__, offset); | |
c1713132 AZ |
203 | } |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
a8170e5e | 208 | static void pxa2xx_gpio_write(void *opaque, hwaddr offset, |
55a8b801 | 209 | uint64_t value, unsigned size) |
c1713132 | 210 | { |
bc24a225 | 211 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
c1713132 | 212 | int bank; |
c1713132 AZ |
213 | if (offset >= 0x200) |
214 | return; | |
215 | ||
216 | bank = pxa2xx_gpio_regs[offset].bank; | |
217 | switch (pxa2xx_gpio_regs[offset].reg) { | |
218 | case GPDR: /* GPIO Pin-Direction registers */ | |
219 | s->dir[bank] = value; | |
220 | pxa2xx_gpio_handler_update(s); | |
221 | break; | |
222 | ||
223 | case GPSR: /* GPIO Pin-Output Set registers */ | |
224 | s->olevel[bank] |= value; | |
225 | pxa2xx_gpio_handler_update(s); | |
226 | break; | |
227 | ||
228 | case GPCR: /* GPIO Pin-Output Clear registers */ | |
229 | s->olevel[bank] &= ~value; | |
230 | pxa2xx_gpio_handler_update(s); | |
231 | break; | |
232 | ||
233 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ | |
234 | s->rising[bank] = value; | |
235 | break; | |
236 | ||
237 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ | |
238 | s->falling[bank] = value; | |
239 | break; | |
240 | ||
241 | case GAFR_L: /* GPIO Alternate Function registers */ | |
242 | s->gafr[bank * 2] = value; | |
243 | break; | |
244 | ||
245 | case GAFR_U: /* GPIO Alternate Function registers */ | |
246 | s->gafr[bank * 2 + 1] = value; | |
247 | break; | |
248 | ||
249 | case GEDR: /* GPIO Edge Detect Status registers */ | |
250 | s->status[bank] &= ~value; | |
251 | pxa2xx_gpio_irq_update(s); | |
252 | break; | |
253 | ||
254 | default: | |
5a0001ec PMD |
255 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
256 | __func__, offset); | |
c1713132 AZ |
257 | } |
258 | } | |
259 | ||
55a8b801 BC |
260 | static const MemoryRegionOps pxa_gpio_ops = { |
261 | .read = pxa2xx_gpio_read, | |
262 | .write = pxa2xx_gpio_write, | |
263 | .endianness = DEVICE_NATIVE_ENDIAN, | |
c1713132 AZ |
264 | }; |
265 | ||
a8170e5e | 266 | DeviceState *pxa2xx_gpio_init(hwaddr base, |
55e5c285 | 267 | ARMCPU *cpu, DeviceState *pic, int lines) |
aa941b94 | 268 | { |
55e5c285 | 269 | CPUState *cs = CPU(cpu); |
0bb53337 | 270 | DeviceState *dev; |
aa941b94 | 271 | |
3e80f690 | 272 | dev = qdev_new(TYPE_PXA2XX_GPIO); |
0bb53337 | 273 | qdev_prop_set_int32(dev, "lines", lines); |
55e5c285 | 274 | qdev_prop_set_int32(dev, "ncpu", cs->cpu_index); |
3c6ef471 | 275 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
aa941b94 | 276 | |
1356b98d AF |
277 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
278 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | |
e1f8c729 | 279 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); |
1356b98d | 280 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, |
e1f8c729 | 281 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); |
1356b98d | 282 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, |
e1f8c729 | 283 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); |
aa941b94 | 284 | |
0bb53337 | 285 | return dev; |
aa941b94 AZ |
286 | } |
287 | ||
f79a7ff1 | 288 | static void pxa2xx_gpio_initfn(Object *obj) |
c1713132 | 289 | { |
f79a7ff1 | 290 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
922bb317 AF |
291 | DeviceState *dev = DEVICE(sbd); |
292 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); | |
c1713132 | 293 | |
f79a7ff1 XZ |
294 | memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops, |
295 | s, "pxa2xx-gpio", 0x1000); | |
922bb317 AF |
296 | sysbus_init_mmio(sbd, &s->iomem); |
297 | sysbus_init_irq(sbd, &s->irq0); | |
298 | sysbus_init_irq(sbd, &s->irq1); | |
299 | sysbus_init_irq(sbd, &s->irqX); | |
f79a7ff1 | 300 | } |
c1713132 | 301 | |
f79a7ff1 XZ |
302 | static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp) |
303 | { | |
304 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); | |
305 | ||
306 | s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu)); | |
307 | ||
308 | qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); | |
309 | qdev_init_gpio_out(dev, s->handler, s->lines); | |
c1713132 AZ |
310 | } |
311 | ||
312 | /* | |
313 | * Registers a callback to notify on GPLR reads. This normally | |
314 | * shouldn't be needed but it is used for the hack on Spitz machines. | |
315 | */ | |
0bb53337 | 316 | void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) |
38641a52 | 317 | { |
922bb317 AF |
318 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); |
319 | ||
c1713132 | 320 | s->read_notify = handler; |
c1713132 | 321 | } |
0bb53337 DES |
322 | |
323 | static const VMStateDescription vmstate_pxa2xx_gpio_regs = { | |
324 | .name = "pxa2xx-gpio", | |
325 | .version_id = 1, | |
326 | .minimum_version_id = 1, | |
8f1e884b | 327 | .fields = (VMStateField[]) { |
0bb53337 DES |
328 | VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
329 | VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), | |
330 | VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), | |
331 | VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), | |
332 | VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), | |
333 | VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), | |
334 | VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), | |
166fa999 | 335 | VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
0bb53337 DES |
336 | VMSTATE_END_OF_LIST(), |
337 | }, | |
338 | }; | |
339 | ||
999e12bb AL |
340 | static Property pxa2xx_gpio_properties[] = { |
341 | DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), | |
342 | DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0), | |
343 | DEFINE_PROP_END_OF_LIST(), | |
344 | }; | |
345 | ||
346 | static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) | |
347 | { | |
39bffca2 | 348 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 349 | |
39bffca2 | 350 | dc->desc = "PXA2xx GPIO controller"; |
4f67d30b | 351 | device_class_set_props(dc, pxa2xx_gpio_properties); |
166fa999 | 352 | dc->vmsd = &vmstate_pxa2xx_gpio_regs; |
f79a7ff1 | 353 | dc->realize = pxa2xx_gpio_realize; |
999e12bb AL |
354 | } |
355 | ||
8c43a6f0 | 356 | static const TypeInfo pxa2xx_gpio_info = { |
922bb317 | 357 | .name = TYPE_PXA2XX_GPIO, |
39bffca2 AL |
358 | .parent = TYPE_SYS_BUS_DEVICE, |
359 | .instance_size = sizeof(PXA2xxGPIOInfo), | |
f79a7ff1 | 360 | .instance_init = pxa2xx_gpio_initfn, |
39bffca2 | 361 | .class_init = pxa2xx_gpio_class_init, |
0bb53337 DES |
362 | }; |
363 | ||
83f7d43a | 364 | static void pxa2xx_gpio_register_types(void) |
0bb53337 | 365 | { |
39bffca2 | 366 | type_register_static(&pxa2xx_gpio_info); |
0bb53337 | 367 | } |
83f7d43a AF |
368 | |
369 | type_init(pxa2xx_gpio_register_types) |