[mirror_qemu.git] / hw / arm / pxa2xx_pic.c

/*
 * Intel XScale PXA Programmable Interrupt Controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
#include "target/arm/cpregs.h"

#define ICIP	0x00	/* Interrupt Controller IRQ Pending register */
#define ICMR	0x04	/* Interrupt Controller Mask register */
#define ICLR	0x08	/* Interrupt Controller Level register */
#define ICFP	0x0c	/* Interrupt Controller FIQ Pending register */
#define ICPR	0x10	/* Interrupt Controller Pending register */
#define ICCR	0x14	/* Interrupt Controller Control register */
#define ICHP	0x18	/* Interrupt Controller Highest Priority register */
#define IPR0	0x1c	/* Interrupt Controller Priority register 0 */
#define IPR31	0x98	/* Interrupt Controller Priority register 31 */
#define ICIP2	0x9c	/* Interrupt Controller IRQ Pending register 2 */
#define ICMR2	0xa0	/* Interrupt Controller Mask register 2 */
#define ICLR2	0xa4	/* Interrupt Controller Level register 2 */
#define ICFP2	0xa8	/* Interrupt Controller FIQ Pending register 2 */
#define ICPR2	0xac	/* Interrupt Controller Pending register 2 */
#define IPR32	0xb0	/* Interrupt Controller Priority register 32 */
#define IPR39	0xcc	/* Interrupt Controller Priority register 39 */

#define PXA2XX_PIC_SRCS	40

#define TYPE_PXA2XX_PIC "pxa2xx_pic"
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPICState, PXA2XX_PIC)

struct PXA2xxPICState {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    ARMCPU *cpu;
    uint32_t int_enabled[2];
    uint32_t int_pending[2];
    uint32_t is_fiq[2];
    uint32_t int_idle;
    uint32_t priority[PXA2XX_PIC_SRCS];
};

static void pxa2xx_pic_update(void *opaque)
{
    uint32_t mask[2];
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
    CPUState *cpu = CPU(s->cpu);

    if (cpu->halted) {
        mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
        mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
        if (mask[0] || mask[1]) {
            cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
        }
    }

    mask[0] = s->int_pending[0] & s->int_enabled[0];
    mask[1] = s->int_pending[1] & s->int_enabled[1];

    if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
    } else {
        cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
    }

    if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
        cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
    }
}

/* Note: Here level means state of the signal on a pin, not
 * IRQ/FIQ distinction as in PXA Developer Manual.  */
static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;
    int int_set = (irq >= 32);
    irq &= 31;

    if (level)
        s->int_pending[int_set] |= 1 << irq;
    else
        s->int_pending[int_set] &= ~(1 << irq);

    pxa2xx_pic_update(opaque);
}

static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
    int i, int_set, irq;
    uint32_t bit, mask[2];
    uint32_t ichp = 0x003f003f;	/* Both IDs invalid */

    mask[0] = s->int_pending[0] & s->int_enabled[0];
    mask[1] = s->int_pending[1] & s->int_enabled[1];

    for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
        irq = s->priority[i] & 0x3f;
        if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
            /* Source peripheral ID is valid.  */
            bit = 1 << (irq & 31);
            int_set = (irq >= 32);

            if (mask[int_set] & bit & s->is_fiq[int_set]) {
                /* FIQ asserted */
                ichp &= 0xffff0000;
                ichp |= (1 << 15) | irq;
            }

            if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
                /* IRQ asserted */
                ichp &= 0x0000ffff;
                ichp |= (1U << 31) | (irq << 16);
            }
        }
    }

    return ichp;
}

static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
                                    unsigned size)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;

    switch (offset) {
    case ICIP:	/* IRQ Pending register */
        return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
    case ICIP2:	/* IRQ Pending register 2 */
        return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
    case ICMR:	/* Mask register */
        return s->int_enabled[0];
    case ICMR2:	/* Mask register 2 */
        return s->int_enabled[1];
    case ICLR:	/* Level register */
        return s->is_fiq[0];
    case ICLR2:	/* Level register 2 */
        return s->is_fiq[1];
    case ICCR:	/* Idle mask */
        return (s->int_idle == 0);
    case ICFP:	/* FIQ Pending register */
        return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
    case ICFP2:	/* FIQ Pending register 2 */
        return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
    case ICPR:	/* Pending register */
        return s->int_pending[0];
    case ICPR2:	/* Pending register 2 */
        return s->int_pending[1];
    case IPR0  ... IPR31:
        return s->priority[0  + ((offset - IPR0 ) >> 2)];
    case IPR32 ... IPR39:
        return s->priority[32 + ((offset - IPR32) >> 2)];
    case ICHP:	/* Highest Priority register */
        return pxa2xx_pic_highest(s);
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
                      "\n", offset);
        return 0;
    }
}

static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
                                 uint64_t value, unsigned size)
{
    PXA2xxPICState *s = (PXA2xxPICState *) opaque;

    switch (offset) {
    case ICMR:	/* Mask register */
        s->int_enabled[0] = value;
        break;
    case ICMR2:	/* Mask register 2 */
        s->int_enabled[1] = value;
        break;
    case ICLR:	/* Level register */
        s->is_fiq[0] = value;
        break;
    case ICLR2:	/* Level register 2 */
        s->is_fiq[1] = value;
        break;
    case ICCR:	/* Idle mask */
        s->int_idle = (value & 1) ? 0 : ~0;
        break;
    case IPR0  ... IPR31:
        s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
        break;
    case IPR32 ... IPR39:
        s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pxa2xx_pic_mem_write: bad register offset 0x%"
                      HWADDR_PRIx "\n", offset);
        return;
    }
    pxa2xx_pic_update(opaque);
}

/* Interrupt Controller Coprocessor Space Register Mapping */
static const int pxa2xx_cp_reg_map[0x10] = {
    [0x0 ... 0xf] = -1,
    [0x0] = ICIP,
    [0x1] = ICMR,
    [0x2] = ICLR,
    [0x3] = ICFP,
    [0x4] = ICPR,
    [0x5] = ICHP,
    [0x6] = ICIP2,
    [0x7] = ICMR2,
    [0x8] = ICLR2,
    [0x9] = ICFP2,
    [0xa] = ICPR2,
};

static uint64_t pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
    int offset = pxa2xx_cp_reg_map[ri->crn];
    return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
}

static void pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
{
    int offset = pxa2xx_cp_reg_map[ri->crn];
    pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
}

#define REGINFO_FOR_PIC_CP(NAME, CRN) \
    { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
      .access = PL1_RW, .type = ARM_CP_IO, \
      .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }

static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
    REGINFO_FOR_PIC_CP("ICIP", 0),
    REGINFO_FOR_PIC_CP("ICMR", 1),
    REGINFO_FOR_PIC_CP("ICLR", 2),
    REGINFO_FOR_PIC_CP("ICFP", 3),
    REGINFO_FOR_PIC_CP("ICPR", 4),
    REGINFO_FOR_PIC_CP("ICHP", 5),
    REGINFO_FOR_PIC_CP("ICIP2", 6),
    REGINFO_FOR_PIC_CP("ICMR2", 7),
    REGINFO_FOR_PIC_CP("ICLR2", 8),
    REGINFO_FOR_PIC_CP("ICFP2", 9),
    REGINFO_FOR_PIC_CP("ICPR2", 0xa),
};

static const MemoryRegionOps pxa2xx_pic_ops = {
    .read = pxa2xx_pic_mem_read,
    .write = pxa2xx_pic_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pxa2xx_pic_post_load(void *opaque, int version_id)
{
    pxa2xx_pic_update(opaque);
    return 0;
}

DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
{
    DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
    PXA2xxPICState *s = PXA2XX_PIC(dev);

    s->cpu = cpu;

    s->int_pending[0] = 0;
    s->int_pending[1] = 0;
    s->int_enabled[0] = 0;
    s->int_enabled[1] = 0;
    s->is_fiq[0] = 0;
    s->is_fiq[1] = 0;

    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

    qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);

    /* Enable IC memory-mapped registers access.  */
    memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
                          "pxa2xx-pic", 0x00100000);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);

    /* Enable IC coprocessor access.  */
    define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);

    return dev;
}

static const VMStateDescription vmstate_pxa2xx_pic_regs = {
    .name = "pxa2xx_pic",
    .version_id = 0,
    .minimum_version_id = 0,
    .post_load = pxa2xx_pic_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
        VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
        VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
        VMSTATE_UINT32(int_idle, PXA2xxPICState),
        VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
        VMSTATE_END_OF_LIST(),
    },
};

static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA2xx PIC";
    dc->vmsd = &vmstate_pxa2xx_pic_regs;
}

static const TypeInfo pxa2xx_pic_info = {
    .name          = TYPE_PXA2XX_PIC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxPICState),
    .class_init    = pxa2xx_pic_class_init,
};

static void pxa2xx_pic_register_types(void)
{
    type_register_static(&pxa2xx_pic_info);
}

type_init(pxa2xx_pic_register_types)
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA Programmable Interrupt Controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <balrog@zabor.org>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
12b16722	11	#include "qemu/osdep.h"
3e80f690	12	#include "qapi/error.h"
0b8fa32f	13	#include "qemu/module.h"
e53652eb	14	#include "qemu/log.h"
4771d756	15	#include "cpu.h"
0d09e41a	16	#include "hw/arm/pxa.h"
83c9f4ca	17	#include "hw/sysbus.h"
d6454270	18	#include "migration/vmstate.h"
db1015e9	19	#include "qom/object.h"
cf7c6d10	20	#include "target/arm/cpregs.h"
c1713132 AZ	21
	22	#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
	23	#define ICMR 0x04 /* Interrupt Controller Mask register */
	24	#define ICLR 0x08 /* Interrupt Controller Level register */
	25	#define ICFP 0x0c /* Interrupt Controller FIQ Pending register */
	26	#define ICPR 0x10 /* Interrupt Controller Pending register */
	27	#define ICCR 0x14 /* Interrupt Controller Control register */
	28	#define ICHP 0x18 /* Interrupt Controller Highest Priority register */
	29	#define IPR0 0x1c /* Interrupt Controller Priority register 0 */
	30	#define IPR31 0x98 /* Interrupt Controller Priority register 31 */
	31	#define ICIP2 0x9c /* Interrupt Controller IRQ Pending register 2 */
	32	#define ICMR2 0xa0 /* Interrupt Controller Mask register 2 */
	33	#define ICLR2 0xa4 /* Interrupt Controller Level register 2 */
	34	#define ICFP2 0xa8 /* Interrupt Controller FIQ Pending register 2 */
	35	#define ICPR2 0xac /* Interrupt Controller Pending register 2 */
	36	#define IPR32 0xb0 /* Interrupt Controller Priority register 32 */
	37	#define IPR39 0xcc /* Interrupt Controller Priority register 39 */
	38
	39	#define PXA2XX_PIC_SRCS 40
	40
6050ed5f	41	#define TYPE_PXA2XX_PIC "pxa2xx_pic"
8063396b	42	OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPICState, PXA2XX_PIC)
6050ed5f	43
db1015e9	44	struct PXA2xxPICState {
6050ed5f AF	45	/< private >/
	46	SysBusDevice parent_obj;
	47	/< public >/
	48
90e8e5a3	49	MemoryRegion iomem;
e9d872cf	50	ARMCPU *cpu;
c1713132 AZ	51	uint32_t int_enabled[2];
	52	uint32_t int_pending[2];
	53	uint32_t is_fiq[2];
	54	uint32_t int_idle;
	55	uint32_t priority[PXA2XX_PIC_SRCS];
db1015e9	56	};
c1713132 AZ	57
	58	static void pxa2xx_pic_update(void *opaque)
	59	{
	60	uint32_t mask[2];
bc24a225	61	PXA2xxPICState s = (PXA2xxPICState ) opaque;
259186a7	62	CPUState *cpu = CPU(s->cpu);
c1713132	63
259186a7	64	if (cpu->halted) {
c1713132 AZ	65	mask[0] = s->int_pending[0] & (s->int_enabled[0] \| s->int_idle);
c1713132 AZ	66	mask[1] = s->int_pending[1] & (s->int_enabled[1] \| s->int_idle);
e9d872cf	67	if (mask[0] \|\| mask[1]) {
c3affe56	68	cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
e9d872cf	69	}
c1713132 AZ	70	}
	71
	72	mask[0] = s->int_pending[0] & s->int_enabled[0];
	73	mask[1] = s->int_pending[1] & s->int_enabled[1];
	74
e9d872cf	75	if ((mask[0] & s->is_fiq[0]) \|\| (mask[1] & s->is_fiq[1])) {
c3affe56	76	cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
e9d872cf	77	} else {
d8ed887b	78	cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
e9d872cf	79	}
c1713132	80
e9d872cf	81	if ((mask[0] & ~s->is_fiq[0]) \|\| (mask[1] & ~s->is_fiq[1])) {
c3affe56	82	cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
e9d872cf	83	} else {
d8ed887b	84	cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
e9d872cf	85	}
c1713132 AZ	86	}
	87
	88	/* Note: Here level means state of the signal on a pin, not
	89	* IRQ/FIQ distinction as in PXA Developer Manual. */
	90	static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
	91	{
bc24a225	92	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	93	int int_set = (irq >= 32);
	94	irq &= 31;
	95
	96	if (level)
	97	s->int_pending[int_set] \|= 1 << irq;
	98	else
	99	s->int_pending[int_set] &= ~(1 << irq);
	100
	101	pxa2xx_pic_update(opaque);
	102	}
	103
bc24a225	104	static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
c1713132 AZ	105	int i, int_set, irq;
	106	uint32_t bit, mask[2];
	107	uint32_t ichp = 0x003f003f; /* Both IDs invalid */
	108
	109	mask[0] = s->int_pending[0] & s->int_enabled[0];
	110	mask[1] = s->int_pending[1] & s->int_enabled[1];
	111
	112	for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
	113	irq = s->priority[i] & 0x3f;
43a32ed6	114	if ((s->priority[i] & (1U << 31)) && irq < PXA2XX_PIC_SRCS) {
c1713132 AZ	115	/* Source peripheral ID is valid. */
	116	bit = 1 << (irq & 31);
	117	int_set = (irq >= 32);
	118
	119	if (mask[int_set] & bit & s->is_fiq[int_set]) {
	120	/* FIQ asserted */
	121	ichp &= 0xffff0000;
	122	ichp \|= (1 << 15) \| irq;
	123	}
	124
	125	if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
	126	/* IRQ asserted */
	127	ichp &= 0x0000ffff;
43a32ed6	128	ichp \|= (1U << 31) \| (irq << 16);
c1713132 AZ	129	}
	130	}
	131	}
	132
	133	return ichp;
	134	}
	135
a8170e5e	136	static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
90e8e5a3	137	unsigned size)
c1713132	138	{
bc24a225	139	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	140
	141	switch (offset) {
	142	case ICIP: /* IRQ Pending register */
	143	return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
	144	case ICIP2: /* IRQ Pending register 2 */
	145	return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
	146	case ICMR: /* Mask register */
	147	return s->int_enabled[0];
	148	case ICMR2: /* Mask register 2 */
	149	return s->int_enabled[1];
	150	case ICLR: /* Level register */
	151	return s->is_fiq[0];
	152	case ICLR2: /* Level register 2 */
	153	return s->is_fiq[1];
	154	case ICCR: /* Idle mask */
	155	return (s->int_idle == 0);
	156	case ICFP: /* FIQ Pending register */
	157	return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
	158	case ICFP2: /* FIQ Pending register 2 */
	159	return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
	160	case ICPR: /* Pending register */
	161	return s->int_pending[0];
	162	case ICPR2: /* Pending register 2 */
	163	return s->int_pending[1];
	164	case IPR0 ... IPR31:
	165	return s->priority[0 + ((offset - IPR0 ) >> 2)];
	166	case IPR32 ... IPR39:
	167	return s->priority[32 + ((offset - IPR32) >> 2)];
	168	case ICHP: /* Highest Priority register */
	169	return pxa2xx_pic_highest(s);
	170	default:
e53652eb PM	171	qemu_log_mask(LOG_GUEST_ERROR,
	172	"pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
	173	"\n", offset);
c1713132 AZ	174	return 0;
	175	}
	176	}
	177
a8170e5e	178	static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
90e8e5a3	179	uint64_t value, unsigned size)
c1713132	180	{
bc24a225	181	PXA2xxPICState s = (PXA2xxPICState ) opaque;
c1713132 AZ	182
	183	switch (offset) {
	184	case ICMR: /* Mask register */
	185	s->int_enabled[0] = value;
	186	break;
	187	case ICMR2: /* Mask register 2 */
	188	s->int_enabled[1] = value;
	189	break;
	190	case ICLR: /* Level register */
	191	s->is_fiq[0] = value;
	192	break;
	193	case ICLR2: /* Level register 2 */
	194	s->is_fiq[1] = value;
	195	break;
	196	case ICCR: /* Idle mask */
	197	s->int_idle = (value & 1) ? 0 : ~0;
	198	break;
	199	case IPR0 ... IPR31:
	200	s->priority[0 + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
	201	break;
	202	case IPR32 ... IPR39:
	203	s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
	204	break;
	205	default:
e53652eb PM	206	qemu_log_mask(LOG_GUEST_ERROR,
	207	"pxa2xx_pic_mem_write: bad register offset 0x%"
	208	HWADDR_PRIx "\n", offset);
c1713132 AZ	209	return;
	210	}
	211	pxa2xx_pic_update(opaque);
	212	}
	213
	214	/* Interrupt Controller Coprocessor Space Register Mapping */
	215	static const int pxa2xx_cp_reg_map[0x10] = {
	216	[0x0 ... 0xf] = -1,
	217	[0x0] = ICIP,
	218	[0x1] = ICMR,
	219	[0x2] = ICLR,
	220	[0x3] = ICFP,
	221	[0x4] = ICPR,
	222	[0x5] = ICHP,
	223	[0x6] = ICIP2,
	224	[0x7] = ICMR2,
	225	[0x8] = ICLR2,
	226	[0x9] = ICFP2,
	227	[0xa] = ICPR2,
	228	};
	229
c4241c7d	230	static uint64_t pxa2xx_pic_cp_read(CPUARMState env, const ARMCPRegInfo ri)
c1713132	231	{
9ee703b0	232	int offset = pxa2xx_cp_reg_map[ri->crn];
c4241c7d	233	return pxa2xx_pic_mem_read(ri->opaque, offset, 4);
c1713132 AZ	234	}
c1713132 AZ	235
c4241c7d PM	236	static void pxa2xx_pic_cp_write(CPUARMState env, const ARMCPRegInfo ri,
c4241c7d PM	237	uint64_t value)
c1713132	238	{
9ee703b0 PM	239	int offset = pxa2xx_cp_reg_map[ri->crn];
9ee703b0 PM	240	pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
c1713132 AZ	241	}
c1713132 AZ	242
9ee703b0 PM	243	#define REGINFO_FOR_PIC_CP(NAME, CRN) \
9ee703b0 PM	244	{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
14c3032a	245	.access = PL1_RW, .type = ARM_CP_IO, \
9ee703b0 PM	246	.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
	247
	248	static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
	249	REGINFO_FOR_PIC_CP("ICIP", 0),
	250	REGINFO_FOR_PIC_CP("ICMR", 1),
	251	REGINFO_FOR_PIC_CP("ICLR", 2),
	252	REGINFO_FOR_PIC_CP("ICFP", 3),
	253	REGINFO_FOR_PIC_CP("ICPR", 4),
	254	REGINFO_FOR_PIC_CP("ICHP", 5),
	255	REGINFO_FOR_PIC_CP("ICIP2", 6),
	256	REGINFO_FOR_PIC_CP("ICMR2", 7),
	257	REGINFO_FOR_PIC_CP("ICLR2", 8),
	258	REGINFO_FOR_PIC_CP("ICFP2", 9),
	259	REGINFO_FOR_PIC_CP("ICPR2", 0xa),
9ee703b0 PM	260	};
9ee703b0 PM	261
90e8e5a3 BC	262	static const MemoryRegionOps pxa2xx_pic_ops = {
	263	.read = pxa2xx_pic_mem_read,
	264	.write = pxa2xx_pic_mem_write,
	265	.endianness = DEVICE_NATIVE_ENDIAN,
c1713132 AZ	266	};
c1713132 AZ	267
e1f8c729	268	static int pxa2xx_pic_post_load(void *opaque, int version_id)
aa941b94	269	{
aa941b94 AZ	270	pxa2xx_pic_update(opaque);
	271	return 0;
	272	}
	273
a8170e5e	274	DeviceState pxa2xx_pic_init(hwaddr base, ARMCPU cpu)
c1713132	275	{
3e80f690	276	DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
6050ed5f	277	PXA2xxPICState *s = PXA2XX_PIC(dev);
c1713132	278
e9d872cf	279	s->cpu = cpu;
c1713132 AZ	280
	281	s->int_pending[0] = 0;
	282	s->int_pending[1] = 0;
	283	s->int_enabled[0] = 0;
	284	s->int_enabled[1] = 0;
	285	s->is_fiq[0] = 0;
	286	s->is_fiq[1] = 0;
	287
3c6ef471	288	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
e1f8c729 DES	289
e1f8c729 DES	290	qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
c1713132 AZ	291
c1713132 AZ	292	/* Enable IC memory-mapped registers access. */
64bde0f3	293	memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
90e8e5a3	294	"pxa2xx-pic", 0x00100000);
1356b98d AF	295	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1356b98d AF	296	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
c1713132 AZ	297
c1713132 AZ	298	/* Enable IC coprocessor access. */
6050ed5f	299	define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
c1713132	300
e1f8c729 DES	301	return dev;
	302	}
	303
cfa52e09	304	static const VMStateDescription vmstate_pxa2xx_pic_regs = {
e1f8c729 DES	305	.name = "pxa2xx_pic",
	306	.version_id = 0,
	307	.minimum_version_id = 0,
e1f8c729 DES	308	.post_load = pxa2xx_pic_post_load,
	309	.fields = (VMStateField[]) {
	310	VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
	311	VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
	312	VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
	313	VMSTATE_UINT32(int_idle, PXA2xxPICState),
	314	VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
	315	VMSTATE_END_OF_LIST(),
	316	},
	317	};
aa941b94	318
999e12bb AL	319	static void pxa2xx_pic_class_init(ObjectClass klass, void data)
999e12bb AL	320	{
39bffca2	321	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	322
39bffca2 AL	323	dc->desc = "PXA2xx PIC";
39bffca2 AL	324	dc->vmsd = &vmstate_pxa2xx_pic_regs;
999e12bb AL	325	}
999e12bb AL	326
8c43a6f0	327	static const TypeInfo pxa2xx_pic_info = {
6050ed5f	328	.name = TYPE_PXA2XX_PIC,
39bffca2 AL	329	.parent = TYPE_SYS_BUS_DEVICE,
	330	.instance_size = sizeof(PXA2xxPICState),
	331	.class_init = pxa2xx_pic_class_init,
e1f8c729 DES	332	};
e1f8c729 DES	333
83f7d43a	334	static void pxa2xx_pic_register_types(void)
e1f8c729	335	{
39bffca2	336	type_register_static(&pxa2xx_pic_info);
c1713132	337	}
83f7d43a AF	338
83f7d43a AF	339	type_init(pxa2xx_pic_register_types)