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1df7d1f9 AB |
1 | /* |
2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
4 | * | |
5 | * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft | |
6 | * Written by Andrew Baumann | |
7 | * | |
bade5816 PE |
8 | * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti |
9 | * Upstream code cleanup (c) 2018 Pekka Enberg | |
10 | * | |
6111a0c0 PMD |
11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
12 | * See the COPYING file in the top-level directory. | |
1df7d1f9 AB |
13 | */ |
14 | ||
c964b660 | 15 | #include "qemu/osdep.h" |
ff3dcf28 | 16 | #include "qemu/units.h" |
f5bb124e | 17 | #include "qemu/cutils.h" |
da34e65c | 18 | #include "qapi/error.h" |
4771d756 | 19 | #include "cpu.h" |
1df7d1f9 | 20 | #include "hw/arm/bcm2836.h" |
cd6c9977 | 21 | #include "hw/registerfields.h" |
1df7d1f9 AB |
22 | #include "qemu/error-report.h" |
23 | #include "hw/boards.h" | |
24 | #include "hw/loader.h" | |
12ec8bd5 | 25 | #include "hw/arm/boot.h" |
1df7d1f9 AB |
26 | #include "sysemu/sysemu.h" |
27 | ||
28 | #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ | |
29 | #define MVBAR_ADDR 0x400 /* secure vectors */ | |
30 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | |
bade5816 PE |
31 | #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ |
32 | #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | |
ff72cb6b | 33 | #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ |
1df7d1f9 | 34 | |
918c81a5 PMD |
35 | /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ |
36 | #define MACH_TYPE_BCM2708 3138 | |
1df7d1f9 | 37 | |
cb57df6f PMD |
38 | typedef struct RaspiMachineState { |
39 | /*< private >*/ | |
40 | MachineState parent_obj; | |
41 | /*< public >*/ | |
926dcdf0 | 42 | BCM283XState soc; |
cb57df6f PMD |
43 | } RaspiMachineState; |
44 | ||
45 | typedef struct RaspiMachineClass { | |
46 | /*< private >*/ | |
47 | MachineClass parent_obj; | |
48 | /*< public >*/ | |
c318c66c | 49 | uint32_t board_rev; |
cb57df6f PMD |
50 | } RaspiMachineClass; |
51 | ||
52 | #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") | |
53 | #define RASPI_MACHINE(obj) \ | |
54 | OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE) | |
55 | ||
56 | #define RASPI_MACHINE_CLASS(klass) \ | |
57 | OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE) | |
58 | #define RASPI_MACHINE_GET_CLASS(obj) \ | |
59 | OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE) | |
1df7d1f9 | 60 | |
cd6c9977 PMD |
61 | /* |
62 | * Board revision codes: | |
63 | * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ | |
64 | */ | |
65 | FIELD(REV_CODE, REVISION, 0, 4); | |
66 | FIELD(REV_CODE, TYPE, 4, 8); | |
67 | FIELD(REV_CODE, PROCESSOR, 12, 4); | |
68 | FIELD(REV_CODE, MANUFACTURER, 16, 4); | |
69 | FIELD(REV_CODE, MEMORY_SIZE, 20, 3); | |
70 | FIELD(REV_CODE, STYLE, 23, 1); | |
71 | ||
f5bb124e PMD |
72 | static uint64_t board_ram_size(uint32_t board_rev) |
73 | { | |
74 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ | |
75 | return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); | |
76 | } | |
77 | ||
cd6c9977 PMD |
78 | static int board_processor_id(uint32_t board_rev) |
79 | { | |
80 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ | |
81 | return FIELD_EX32(board_rev, REV_CODE, PROCESSOR); | |
82 | } | |
83 | ||
84 | static int board_version(uint32_t board_rev) | |
85 | { | |
86 | return board_processor_id(board_rev) + 1; | |
87 | } | |
88 | ||
2e664b45 PMD |
89 | static const char *board_soc_type(uint32_t board_rev) |
90 | { | |
91 | static const char *soc_types[] = { | |
92 | NULL, TYPE_BCM2836, TYPE_BCM2837, | |
93 | }; | |
94 | int proc_id = board_processor_id(board_rev); | |
95 | ||
96 | if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) { | |
97 | error_report("Unsupported processor id '%d' (board revision: 0x%x)", | |
98 | proc_id, board_rev); | |
99 | exit(1); | |
100 | } | |
101 | return soc_types[proc_id]; | |
102 | } | |
103 | ||
759f0f87 PMD |
104 | static int cores_count(uint32_t board_rev) |
105 | { | |
106 | static const int soc_cores_count[] = { | |
107 | 0, BCM283X_NCPUS, BCM283X_NCPUS, | |
108 | }; | |
109 | int proc_id = board_processor_id(board_rev); | |
110 | ||
111 | if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) { | |
112 | error_report("Unsupported processor id '%d' (board revision: 0x%x)", | |
113 | proc_id, board_rev); | |
114 | exit(1); | |
115 | } | |
116 | return soc_cores_count[proc_id]; | |
117 | } | |
118 | ||
98b541e1 PMD |
119 | static const char *board_type(uint32_t board_rev) |
120 | { | |
121 | static const char *types[] = { | |
122 | "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", | |
123 | "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", | |
124 | }; | |
125 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ | |
126 | int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); | |
127 | if (bt >= ARRAY_SIZE(types) || !types[bt]) { | |
128 | return "Unknown"; | |
129 | } | |
130 | return types[bt]; | |
131 | } | |
132 | ||
1df7d1f9 AB |
133 | static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) |
134 | { | |
135 | static const uint32_t smpboot[] = { | |
136 | 0xe1a0e00f, /* mov lr, pc */ | |
137 | 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ | |
138 | 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ | |
139 | 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ | |
140 | 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ | |
141 | 0xe320f001, /* 1: yield */ | |
142 | 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ | |
143 | 0xe3530000, /* cmp r3, #0 ;spin while zero */ | |
144 | 0x0afffffb, /* beq 1b */ | |
145 | 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ | |
146 | 0xe12fff13, /* bx r3 ;jump to target */ | |
147 | 0x400000cc, /* (constant: mailbox 3 read/clear base) */ | |
148 | }; | |
149 | ||
150 | /* check that we don't overrun board setup vectors */ | |
151 | QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); | |
152 | /* check that board setup address is correctly relocated */ | |
153 | QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 | |
154 | || (BOARDSETUP_ADDR >> 4) >= 0x100); | |
155 | ||
0f073693 PMD |
156 | rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), |
157 | info->smp_loader_start, | |
158 | arm_boot_address_space(cpu, info)); | |
1df7d1f9 AB |
159 | } |
160 | ||
ff72cb6b PM |
161 | static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) |
162 | { | |
0f073693 | 163 | AddressSpace *as = arm_boot_address_space(cpu, info); |
ff72cb6b PM |
164 | /* Unlike the AArch32 version we don't need to call the board setup hook. |
165 | * The mechanism for doing the spin-table is also entirely different. | |
166 | * We must have four 64-bit fields at absolute addresses | |
167 | * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for | |
168 | * our CPUs, and which we must ensure are zero initialized before | |
169 | * the primary CPU goes into the kernel. We put these variables inside | |
170 | * a rom blob, so that the reset for ROM contents zeroes them for us. | |
171 | */ | |
172 | static const uint32_t smpboot[] = { | |
173 | 0xd2801b05, /* mov x5, 0xd8 */ | |
174 | 0xd53800a6, /* mrs x6, mpidr_el1 */ | |
175 | 0x924004c6, /* and x6, x6, #0x3 */ | |
176 | 0xd503205f, /* spin: wfe */ | |
177 | 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ | |
178 | 0xb4ffffc4, /* cbz x4, spin */ | |
179 | 0xd2800000, /* mov x0, #0x0 */ | |
180 | 0xd2800001, /* mov x1, #0x0 */ | |
181 | 0xd2800002, /* mov x2, #0x0 */ | |
182 | 0xd2800003, /* mov x3, #0x0 */ | |
183 | 0xd61f0080, /* br x4 */ | |
184 | }; | |
185 | ||
186 | static const uint64_t spintables[] = { | |
187 | 0, 0, 0, 0 | |
188 | }; | |
189 | ||
0f073693 PMD |
190 | rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), |
191 | info->smp_loader_start, as); | |
192 | rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), | |
193 | SPINTABLE_ADDR, as); | |
ff72cb6b PM |
194 | } |
195 | ||
1df7d1f9 AB |
196 | static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) |
197 | { | |
198 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); | |
199 | } | |
200 | ||
201 | static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) | |
202 | { | |
203 | CPUState *cs = CPU(cpu); | |
204 | cpu_set_pc(cs, info->smp_loader_start); | |
205 | } | |
206 | ||
207 | static void setup_boot(MachineState *machine, int version, size_t ram_size) | |
208 | { | |
209 | static struct arm_boot_info binfo; | |
210 | int r; | |
211 | ||
918c81a5 | 212 | binfo.board_id = MACH_TYPE_BCM2708; |
1df7d1f9 | 213 | binfo.ram_size = ram_size; |
cc7d44c2 | 214 | binfo.nb_cpus = machine->smp.cpus; |
01e02f5a PM |
215 | |
216 | if (version <= 2) { | |
217 | /* The rpi1 and 2 require some custom setup code to run in Secure | |
218 | * mode before booting a kernel (to set up the SMC vectors so | |
219 | * that we get a no-op SMC; this is used by Linux to call the | |
220 | * firmware for some cache maintenance operations. | |
221 | * The rpi3 doesn't need this. | |
222 | */ | |
223 | binfo.board_setup_addr = BOARDSETUP_ADDR; | |
224 | binfo.write_board_setup = write_board_setup; | |
225 | binfo.secure_board_setup = true; | |
226 | binfo.secure_boot = true; | |
227 | } | |
1df7d1f9 | 228 | |
bade5816 PE |
229 | /* Pi2 and Pi3 requires SMP setup */ |
230 | if (version >= 2) { | |
1df7d1f9 | 231 | binfo.smp_loader_start = SMPBOOT_ADDR; |
ff72cb6b PM |
232 | if (version == 2) { |
233 | binfo.write_secondary_boot = write_smpboot; | |
234 | } else { | |
235 | binfo.write_secondary_boot = write_smpboot64; | |
236 | } | |
1df7d1f9 AB |
237 | binfo.secondary_cpu_reset_hook = reset_secondary; |
238 | } | |
239 | ||
240 | /* If the user specified a "firmware" image (e.g. UEFI), we bypass | |
241 | * the normal Linux boot process | |
242 | */ | |
243 | if (machine->firmware) { | |
bade5816 | 244 | hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2; |
1df7d1f9 | 245 | /* load the firmware image (typically kernel.img) */ |
bade5816 PE |
246 | r = load_image_targphys(machine->firmware, firmware_addr, |
247 | ram_size - firmware_addr); | |
1df7d1f9 AB |
248 | if (r < 0) { |
249 | error_report("Failed to load firmware from %s", machine->firmware); | |
250 | exit(1); | |
251 | } | |
252 | ||
bade5816 | 253 | binfo.entry = firmware_addr; |
1df7d1f9 | 254 | binfo.firmware_loaded = true; |
1df7d1f9 AB |
255 | } |
256 | ||
2744ece8 | 257 | arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); |
1df7d1f9 AB |
258 | } |
259 | ||
13c4e2c0 | 260 | static void raspi_machine_init(MachineState *machine) |
1df7d1f9 | 261 | { |
c318c66c | 262 | RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); |
cb57df6f | 263 | RaspiMachineState *s = RASPI_MACHINE(machine); |
c318c66c | 264 | uint32_t board_rev = mc->board_rev; |
cd6c9977 | 265 | int version = board_version(board_rev); |
f5bb124e | 266 | uint64_t ram_size = board_ram_size(board_rev); |
5e9c2a8d | 267 | uint32_t vcram_size; |
a55b53a2 AB |
268 | DriveInfo *di; |
269 | BlockBackend *blk; | |
270 | BusState *bus; | |
271 | DeviceState *carddev; | |
1df7d1f9 | 272 | |
f5bb124e PMD |
273 | if (machine->ram_size != ram_size) { |
274 | char *size_str = size_to_str(ram_size); | |
275 | error_report("Invalid RAM size, should be %s", size_str); | |
276 | g_free(size_str); | |
ff3dcf28 PM |
277 | exit(1); |
278 | } | |
279 | ||
1df7d1f9 | 280 | /* FIXME: Remove when we have custom CPU address space support */ |
a4317ae8 IM |
281 | memory_region_add_subregion_overlap(get_system_memory(), 0, |
282 | machine->ram, 0); | |
1df7d1f9 AB |
283 | |
284 | /* Setup the SOC */ | |
9fc7fc4d MA |
285 | object_initialize_child(OBJECT(machine), "soc", &s->soc, |
286 | board_soc_type(board_rev)); | |
d2623129 | 287 | object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram)); |
bade5816 | 288 | object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", |
f0afa731 | 289 | &error_abort); |
ce189ab2 | 290 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); |
1df7d1f9 | 291 | |
a55b53a2 AB |
292 | /* Create and plug in the SD cards */ |
293 | di = drive_get_next(IF_SD); | |
294 | blk = di ? blk_by_legacy_dinfo(di) : NULL; | |
295 | bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); | |
296 | if (bus == NULL) { | |
297 | error_report("No SD bus found in SOC object"); | |
298 | exit(1); | |
299 | } | |
3e80f690 | 300 | carddev = qdev_new(TYPE_SD_CARD); |
a55b53a2 | 301 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); |
3e80f690 | 302 | qdev_realize_and_unref(carddev, bus, &error_fatal); |
a55b53a2 | 303 | |
c5c6c47c MAL |
304 | vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size", |
305 | &error_abort); | |
bade5816 PE |
306 | setup_boot(machine, version, machine->ram_size - vcram_size); |
307 | } | |
308 | ||
a03bde36 | 309 | static void raspi_machine_class_init(ObjectClass *oc, void *data) |
1df7d1f9 | 310 | { |
cb57df6f | 311 | MachineClass *mc = MACHINE_CLASS(oc); |
c318c66c PMD |
312 | RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); |
313 | uint32_t board_rev = (uint32_t)(uintptr_t)data; | |
cb57df6f | 314 | |
c318c66c | 315 | rmc->board_rev = board_rev; |
98b541e1 | 316 | mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); |
13c4e2c0 | 317 | mc->init = raspi_machine_init; |
1df7d1f9 AB |
318 | mc->block_default_type = IF_SD; |
319 | mc->no_parallel = 1; | |
320 | mc->no_floppy = 1; | |
321 | mc->no_cdrom = 1; | |
759f0f87 | 322 | mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); |
975f3402 | 323 | mc->default_ram_size = board_ram_size(board_rev); |
a4317ae8 | 324 | mc->default_ram_id = "ram"; |
a03bde36 PMD |
325 | if (board_version(board_rev) == 2) { |
326 | mc->ignore_memory_transaction_failures = true; | |
327 | } | |
1df7d1f9 | 328 | }; |
1c3db49d | 329 | |
cb57df6f PMD |
330 | static const TypeInfo raspi_machine_types[] = { |
331 | { | |
332 | .name = MACHINE_TYPE_NAME("raspi2"), | |
333 | .parent = TYPE_RASPI_MACHINE, | |
a03bde36 | 334 | .class_init = raspi_machine_class_init, |
c318c66c | 335 | .class_data = (void *)0xa21041, |
cb57df6f PMD |
336 | #ifdef TARGET_AARCH64 |
337 | }, { | |
338 | .name = MACHINE_TYPE_NAME("raspi3"), | |
339 | .parent = TYPE_RASPI_MACHINE, | |
a03bde36 | 340 | .class_init = raspi_machine_class_init, |
c318c66c | 341 | .class_data = (void *)0xa02082, |
cb57df6f PMD |
342 | #endif |
343 | }, { | |
344 | .name = TYPE_RASPI_MACHINE, | |
345 | .parent = TYPE_MACHINE, | |
346 | .instance_size = sizeof(RaspiMachineState), | |
347 | .class_size = sizeof(RaspiMachineClass), | |
348 | .abstract = true, | |
349 | } | |
350 | }; | |
351 | ||
352 | DEFINE_TYPES(raspi_machine_types) |