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Commit | Line | Data |
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1df7d1f9 AB |
1 | /* |
2 | * Raspberry Pi emulation (c) 2012 Gregory Estrade | |
3 | * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous | |
4 | * | |
5 | * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft | |
6 | * Written by Andrew Baumann | |
7 | * | |
bade5816 PE |
8 | * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti |
9 | * Upstream code cleanup (c) 2018 Pekka Enberg | |
10 | * | |
6111a0c0 PMD |
11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
12 | * See the COPYING file in the top-level directory. | |
1df7d1f9 AB |
13 | */ |
14 | ||
c964b660 | 15 | #include "qemu/osdep.h" |
ff3dcf28 | 16 | #include "qemu/units.h" |
f5bb124e | 17 | #include "qemu/cutils.h" |
da34e65c | 18 | #include "qapi/error.h" |
0acbdb4c | 19 | #include "hw/arm/boot.h" |
1df7d1f9 | 20 | #include "hw/arm/bcm2836.h" |
7785e8ea | 21 | #include "hw/arm/bcm2838.h" |
08df0676 | 22 | #include "hw/arm/raspi_platform.h" |
cd6c9977 | 23 | #include "hw/registerfields.h" |
1df7d1f9 AB |
24 | #include "qemu/error-report.h" |
25 | #include "hw/boards.h" | |
26 | #include "hw/loader.h" | |
12ec8bd5 | 27 | #include "hw/arm/boot.h" |
db1015e9 | 28 | #include "qom/object.h" |
1df7d1f9 | 29 | |
08df0676 SK |
30 | #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") |
31 | OBJECT_DECLARE_SIMPLE_TYPE(RaspiMachineState, RASPI_MACHINE) | |
32 | ||
1df7d1f9 AB |
33 | #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ |
34 | #define MVBAR_ADDR 0x400 /* secure vectors */ | |
35 | #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ | |
bade5816 PE |
36 | #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ |
37 | #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ | |
ff72cb6b | 38 | #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ |
1df7d1f9 | 39 | |
db1015e9 | 40 | struct RaspiMachineState { |
cb57df6f | 41 | /*< private >*/ |
08df0676 | 42 | RaspiBaseMachineState parent_obj; |
cb57df6f | 43 | /*< public >*/ |
926dcdf0 | 44 | BCM283XState soc; |
db1015e9 | 45 | }; |
1df7d1f9 | 46 | |
cd6c9977 PMD |
47 | /* |
48 | * Board revision codes: | |
49 | * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ | |
50 | */ | |
51 | FIELD(REV_CODE, REVISION, 0, 4); | |
52 | FIELD(REV_CODE, TYPE, 4, 8); | |
53 | FIELD(REV_CODE, PROCESSOR, 12, 4); | |
54 | FIELD(REV_CODE, MANUFACTURER, 16, 4); | |
55 | FIELD(REV_CODE, MEMORY_SIZE, 20, 3); | |
56 | FIELD(REV_CODE, STYLE, 23, 1); | |
57 | ||
696788d6 | 58 | typedef enum RaspiProcessorId { |
df6cf08d | 59 | PROCESSOR_ID_BCM2835 = 0, |
696788d6 PMD |
60 | PROCESSOR_ID_BCM2836 = 1, |
61 | PROCESSOR_ID_BCM2837 = 2, | |
7785e8ea | 62 | PROCESSOR_ID_BCM2838 = 3, |
696788d6 PMD |
63 | } RaspiProcessorId; |
64 | ||
65 | static const struct { | |
66 | const char *type; | |
67 | int cores_count; | |
68 | } soc_property[] = { | |
df6cf08d | 69 | [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1}, |
696788d6 PMD |
70 | [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, |
71 | [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, | |
7785e8ea | 72 | [PROCESSOR_ID_BCM2838] = {TYPE_BCM2838, BCM283X_NCPUS}, |
696788d6 PMD |
73 | }; |
74 | ||
bf1da4b3 | 75 | uint64_t board_ram_size(uint32_t board_rev) |
f5bb124e PMD |
76 | { |
77 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ | |
78 | return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); | |
79 | } | |
80 | ||
696788d6 | 81 | static RaspiProcessorId board_processor_id(uint32_t board_rev) |
cd6c9977 | 82 | { |
696788d6 PMD |
83 | int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR); |
84 | ||
cd6c9977 | 85 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ |
696788d6 PMD |
86 | assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type); |
87 | ||
88 | return proc_id; | |
cd6c9977 PMD |
89 | } |
90 | ||
7785e8ea | 91 | const char *board_soc_type(uint32_t board_rev) |
2e664b45 | 92 | { |
696788d6 | 93 | return soc_property[board_processor_id(board_rev)].type; |
2e664b45 PMD |
94 | } |
95 | ||
759f0f87 PMD |
96 | static int cores_count(uint32_t board_rev) |
97 | { | |
696788d6 | 98 | return soc_property[board_processor_id(board_rev)].cores_count; |
759f0f87 PMD |
99 | } |
100 | ||
98b541e1 PMD |
101 | static const char *board_type(uint32_t board_rev) |
102 | { | |
103 | static const char *types[] = { | |
104 | "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", | |
105 | "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", | |
106 | }; | |
107 | assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ | |
108 | int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); | |
109 | if (bt >= ARRAY_SIZE(types) || !types[bt]) { | |
110 | return "Unknown"; | |
111 | } | |
112 | return types[bt]; | |
113 | } | |
114 | ||
1df7d1f9 AB |
115 | static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) |
116 | { | |
0acbdb4c PM |
117 | static const ARMInsnFixup smpboot[] = { |
118 | { 0xe1a0e00f }, /* mov lr, pc */ | |
119 | { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADDR */ | |
120 | { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ | |
121 | { 0xe7e10050 }, /* ubfx r0, r0, #0, #2 ;extract LSB */ | |
122 | { 0xe59f5014 }, /* ldr r5, =0x400000CC ;load mbox base */ | |
123 | { 0xe320f001 }, /* 1: yield */ | |
124 | { 0xe7953200 }, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core */ | |
125 | { 0xe3530000 }, /* cmp r3, #0 ;spin while zero */ | |
126 | { 0x0afffffb }, /* beq 1b */ | |
127 | { 0xe7853200 }, /* str r3, [r5, r0, lsl #4] ;clear mbox */ | |
128 | { 0xe12fff13 }, /* bx r3 ;jump to target */ | |
129 | { 0x400000cc }, /* (constant: mailbox 3 read/clear base) */ | |
130 | { 0, FIXUP_TERMINATOR } | |
1df7d1f9 | 131 | }; |
0acbdb4c | 132 | static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; |
1df7d1f9 AB |
133 | |
134 | /* check that we don't overrun board setup vectors */ | |
135 | QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); | |
136 | /* check that board setup address is correctly relocated */ | |
137 | QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0 | |
138 | || (BOARDSETUP_ADDR >> 4) >= 0x100); | |
139 | ||
0acbdb4c PM |
140 | arm_write_bootloader("raspi_smpboot", arm_boot_address_space(cpu, info), |
141 | info->smp_loader_start, smpboot, fixupcontext); | |
1df7d1f9 AB |
142 | } |
143 | ||
ff72cb6b PM |
144 | static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) |
145 | { | |
0f073693 | 146 | AddressSpace *as = arm_boot_address_space(cpu, info); |
ff72cb6b PM |
147 | /* Unlike the AArch32 version we don't need to call the board setup hook. |
148 | * The mechanism for doing the spin-table is also entirely different. | |
149 | * We must have four 64-bit fields at absolute addresses | |
150 | * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for | |
151 | * our CPUs, and which we must ensure are zero initialized before | |
152 | * the primary CPU goes into the kernel. We put these variables inside | |
153 | * a rom blob, so that the reset for ROM contents zeroes them for us. | |
154 | */ | |
0acbdb4c PM |
155 | static const ARMInsnFixup smpboot[] = { |
156 | { 0xd2801b05 }, /* mov x5, 0xd8 */ | |
157 | { 0xd53800a6 }, /* mrs x6, mpidr_el1 */ | |
158 | { 0x924004c6 }, /* and x6, x6, #0x3 */ | |
159 | { 0xd503205f }, /* spin: wfe */ | |
160 | { 0xf86678a4 }, /* ldr x4, [x5,x6,lsl #3] */ | |
161 | { 0xb4ffffc4 }, /* cbz x4, spin */ | |
162 | { 0xd2800000 }, /* mov x0, #0x0 */ | |
163 | { 0xd2800001 }, /* mov x1, #0x0 */ | |
164 | { 0xd2800002 }, /* mov x2, #0x0 */ | |
165 | { 0xd2800003 }, /* mov x3, #0x0 */ | |
166 | { 0xd61f0080 }, /* br x4 */ | |
167 | { 0, FIXUP_TERMINATOR } | |
ff72cb6b | 168 | }; |
0acbdb4c | 169 | static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; |
ff72cb6b PM |
170 | |
171 | static const uint64_t spintables[] = { | |
172 | 0, 0, 0, 0 | |
173 | }; | |
174 | ||
0acbdb4c PM |
175 | arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, |
176 | smpboot, fixupcontext); | |
0f073693 PMD |
177 | rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables), |
178 | SPINTABLE_ADDR, as); | |
ff72cb6b PM |
179 | } |
180 | ||
1df7d1f9 AB |
181 | static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) |
182 | { | |
183 | arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); | |
184 | } | |
185 | ||
186 | static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) | |
187 | { | |
188 | CPUState *cs = CPU(cpu); | |
189 | cpu_set_pc(cs, info->smp_loader_start); | |
190 | } | |
191 | ||
08df0676 SK |
192 | static void setup_boot(MachineState *machine, ARMCPU *cpu, |
193 | RaspiProcessorId processor_id, size_t ram_size) | |
1df7d1f9 | 194 | { |
08df0676 | 195 | RaspiBaseMachineState *s = RASPI_BASE_MACHINE(machine); |
1df7d1f9 AB |
196 | int r; |
197 | ||
0f15c6e3 | 198 | s->binfo.ram_size = ram_size; |
01e02f5a | 199 | |
cdfaa57d PMD |
200 | if (processor_id <= PROCESSOR_ID_BCM2836) { |
201 | /* | |
202 | * The BCM2835 and BCM2836 require some custom setup code to run | |
203 | * in Secure mode before booting a kernel (to set up the SMC vectors | |
204 | * so that we get a no-op SMC; this is used by Linux to call the | |
01e02f5a | 205 | * firmware for some cache maintenance operations. |
cdfaa57d | 206 | * The BCM2837 doesn't need this. |
01e02f5a | 207 | */ |
0f15c6e3 PMD |
208 | s->binfo.board_setup_addr = BOARDSETUP_ADDR; |
209 | s->binfo.write_board_setup = write_board_setup; | |
210 | s->binfo.secure_board_setup = true; | |
211 | s->binfo.secure_boot = true; | |
01e02f5a | 212 | } |
1df7d1f9 | 213 | |
cdfaa57d PMD |
214 | /* BCM2836 and BCM2837 requires SMP setup */ |
215 | if (processor_id >= PROCESSOR_ID_BCM2836) { | |
0f15c6e3 | 216 | s->binfo.smp_loader_start = SMPBOOT_ADDR; |
cdfaa57d | 217 | if (processor_id == PROCESSOR_ID_BCM2836) { |
0f15c6e3 | 218 | s->binfo.write_secondary_boot = write_smpboot; |
ff72cb6b | 219 | } else { |
0f15c6e3 | 220 | s->binfo.write_secondary_boot = write_smpboot64; |
ff72cb6b | 221 | } |
0f15c6e3 | 222 | s->binfo.secondary_cpu_reset_hook = reset_secondary; |
1df7d1f9 AB |
223 | } |
224 | ||
225 | /* If the user specified a "firmware" image (e.g. UEFI), we bypass | |
226 | * the normal Linux boot process | |
227 | */ | |
228 | if (machine->firmware) { | |
1af70269 PMD |
229 | hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836 |
230 | ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3; | |
1df7d1f9 | 231 | /* load the firmware image (typically kernel.img) */ |
bade5816 PE |
232 | r = load_image_targphys(machine->firmware, firmware_addr, |
233 | ram_size - firmware_addr); | |
1df7d1f9 AB |
234 | if (r < 0) { |
235 | error_report("Failed to load firmware from %s", machine->firmware); | |
236 | exit(1); | |
237 | } | |
238 | ||
0f15c6e3 PMD |
239 | s->binfo.entry = firmware_addr; |
240 | s->binfo.firmware_loaded = true; | |
1df7d1f9 AB |
241 | } |
242 | ||
08df0676 | 243 | arm_load_kernel(cpu, machine, &s->binfo); |
1df7d1f9 AB |
244 | } |
245 | ||
7785e8ea | 246 | void raspi_base_machine_init(MachineState *machine, |
08df0676 | 247 | BCM283XBaseState *soc) |
1df7d1f9 | 248 | { |
08df0676 | 249 | RaspiBaseMachineClass *mc = RASPI_BASE_MACHINE_GET_CLASS(machine); |
c318c66c | 250 | uint32_t board_rev = mc->board_rev; |
f5bb124e | 251 | uint64_t ram_size = board_ram_size(board_rev); |
7785e8ea SK |
252 | uint32_t vcram_base, vcram_size; |
253 | size_t boot_ram_size; | |
a55b53a2 AB |
254 | DriveInfo *di; |
255 | BlockBackend *blk; | |
256 | BusState *bus; | |
257 | DeviceState *carddev; | |
1df7d1f9 | 258 | |
f5bb124e PMD |
259 | if (machine->ram_size != ram_size) { |
260 | char *size_str = size_to_str(ram_size); | |
261 | error_report("Invalid RAM size, should be %s", size_str); | |
262 | g_free(size_str); | |
ff3dcf28 PM |
263 | exit(1); |
264 | } | |
265 | ||
1df7d1f9 | 266 | /* FIXME: Remove when we have custom CPU address space support */ |
a4317ae8 IM |
267 | memory_region_add_subregion_overlap(get_system_memory(), 0, |
268 | machine->ram, 0); | |
1df7d1f9 AB |
269 | |
270 | /* Setup the SOC */ | |
08df0676 SK |
271 | object_property_add_const_link(OBJECT(soc), "ram", OBJECT(machine->ram)); |
272 | object_property_set_int(OBJECT(soc), "board-rev", board_rev, | |
f0afa731 | 273 | &error_abort); |
08df0676 | 274 | object_property_set_str(OBJECT(soc), "command-line", |
f802ff1e | 275 | machine->kernel_cmdline, &error_abort); |
08df0676 | 276 | qdev_realize(DEVICE(soc), NULL, &error_fatal); |
1df7d1f9 | 277 | |
a55b53a2 | 278 | /* Create and plug in the SD cards */ |
64eaa820 | 279 | di = drive_get(IF_SD, 0, 0); |
a55b53a2 | 280 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
08df0676 | 281 | bus = qdev_get_child_bus(DEVICE(soc), "sd-bus"); |
a55b53a2 AB |
282 | if (bus == NULL) { |
283 | error_report("No SD bus found in SOC object"); | |
284 | exit(1); | |
285 | } | |
3e80f690 | 286 | carddev = qdev_new(TYPE_SD_CARD); |
934df912 | 287 | qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); |
3e80f690 | 288 | qdev_realize_and_unref(carddev, bus, &error_fatal); |
a55b53a2 | 289 | |
08df0676 | 290 | vcram_size = object_property_get_uint(OBJECT(soc), "vcram-size", |
c5c6c47c | 291 | &error_abort); |
7785e8ea SK |
292 | vcram_base = object_property_get_uint(OBJECT(soc), "vcram-base", |
293 | &error_abort); | |
294 | ||
295 | if (vcram_base == 0) { | |
296 | vcram_base = ram_size - vcram_size; | |
297 | } | |
298 | boot_ram_size = MIN(vcram_base, UPPER_RAM_BASE - vcram_size); | |
299 | ||
08df0676 | 300 | setup_boot(machine, &soc->cpu[0].core, board_processor_id(board_rev), |
7785e8ea | 301 | boot_ram_size); |
bade5816 PE |
302 | } |
303 | ||
7785e8ea | 304 | void raspi_machine_init(MachineState *machine) |
08df0676 SK |
305 | { |
306 | RaspiMachineState *s = RASPI_MACHINE(machine); | |
307 | RaspiBaseMachineState *s_base = RASPI_BASE_MACHINE(machine); | |
308 | RaspiBaseMachineClass *mc = RASPI_BASE_MACHINE_GET_CLASS(machine); | |
309 | BCM283XState *soc = &s->soc; | |
310 | ||
311 | s_base->binfo.board_id = MACH_TYPE_BCM2708; | |
312 | ||
313 | object_initialize_child(OBJECT(machine), "soc", soc, | |
314 | board_soc_type(mc->board_rev)); | |
315 | raspi_base_machine_init(machine, &soc->parent_obj); | |
316 | } | |
317 | ||
318 | void raspi_machine_class_common_init(MachineClass *mc, | |
319 | uint32_t board_rev) | |
1df7d1f9 | 320 | { |
62f06f71 PMD |
321 | mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)", |
322 | board_type(board_rev), | |
323 | FIELD_EX32(board_rev, REV_CODE, REVISION)); | |
1df7d1f9 AB |
324 | mc->block_default_type = IF_SD; |
325 | mc->no_parallel = 1; | |
326 | mc->no_floppy = 1; | |
327 | mc->no_cdrom = 1; | |
759f0f87 | 328 | mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); |
975f3402 | 329 | mc->default_ram_size = board_ram_size(board_rev); |
a4317ae8 | 330 | mc->default_ram_id = "ram"; |
1df7d1f9 | 331 | }; |
1c3db49d | 332 | |
08df0676 SK |
333 | static void raspi_machine_class_init(MachineClass *mc, |
334 | uint32_t board_rev) | |
335 | { | |
336 | raspi_machine_class_common_init(mc, board_rev); | |
337 | mc->init = raspi_machine_init; | |
338 | }; | |
339 | ||
3c8f9927 PMD |
340 | static void raspi0_machine_class_init(ObjectClass *oc, void *data) |
341 | { | |
342 | MachineClass *mc = MACHINE_CLASS(oc); | |
08df0676 | 343 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
3c8f9927 PMD |
344 | |
345 | rmc->board_rev = 0x920092; /* Revision 1.2 */ | |
08df0676 | 346 | raspi_machine_class_init(mc, rmc->board_rev); |
3c8f9927 PMD |
347 | }; |
348 | ||
ac6bc6eb PMD |
349 | static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) |
350 | { | |
351 | MachineClass *mc = MACHINE_CLASS(oc); | |
08df0676 | 352 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
ac6bc6eb PMD |
353 | |
354 | rmc->board_rev = 0x900021; /* Revision 1.1 */ | |
08df0676 | 355 | raspi_machine_class_init(mc, rmc->board_rev); |
ac6bc6eb PMD |
356 | }; |
357 | ||
f0eeb4b6 PMD |
358 | static void raspi2b_machine_class_init(ObjectClass *oc, void *data) |
359 | { | |
360 | MachineClass *mc = MACHINE_CLASS(oc); | |
08df0676 | 361 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
f0eeb4b6 PMD |
362 | |
363 | rmc->board_rev = 0xa21041; | |
08df0676 | 364 | raspi_machine_class_init(mc, rmc->board_rev); |
f0eeb4b6 PMD |
365 | }; |
366 | ||
367 | #ifdef TARGET_AARCH64 | |
5be94252 PMD |
368 | static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) |
369 | { | |
370 | MachineClass *mc = MACHINE_CLASS(oc); | |
08df0676 | 371 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
5be94252 PMD |
372 | |
373 | rmc->board_rev = 0x9020e0; /* Revision 1.0 */ | |
08df0676 | 374 | raspi_machine_class_init(mc, rmc->board_rev); |
5be94252 PMD |
375 | }; |
376 | ||
f0eeb4b6 PMD |
377 | static void raspi3b_machine_class_init(ObjectClass *oc, void *data) |
378 | { | |
379 | MachineClass *mc = MACHINE_CLASS(oc); | |
08df0676 | 380 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
f0eeb4b6 PMD |
381 | |
382 | rmc->board_rev = 0xa02082; | |
08df0676 | 383 | raspi_machine_class_init(mc, rmc->board_rev); |
f0eeb4b6 PMD |
384 | }; |
385 | #endif /* TARGET_AARCH64 */ | |
386 | ||
cb57df6f PMD |
387 | static const TypeInfo raspi_machine_types[] = { |
388 | { | |
3c8f9927 PMD |
389 | .name = MACHINE_TYPE_NAME("raspi0"), |
390 | .parent = TYPE_RASPI_MACHINE, | |
391 | .class_init = raspi0_machine_class_init, | |
392 | }, { | |
ac6bc6eb PMD |
393 | .name = MACHINE_TYPE_NAME("raspi1ap"), |
394 | .parent = TYPE_RASPI_MACHINE, | |
395 | .class_init = raspi1ap_machine_class_init, | |
396 | }, { | |
aa35ec22 | 397 | .name = MACHINE_TYPE_NAME("raspi2b"), |
cb57df6f | 398 | .parent = TYPE_RASPI_MACHINE, |
f0eeb4b6 | 399 | .class_init = raspi2b_machine_class_init, |
cb57df6f | 400 | #ifdef TARGET_AARCH64 |
5be94252 PMD |
401 | }, { |
402 | .name = MACHINE_TYPE_NAME("raspi3ap"), | |
403 | .parent = TYPE_RASPI_MACHINE, | |
404 | .class_init = raspi3ap_machine_class_init, | |
cb57df6f | 405 | }, { |
aa35ec22 | 406 | .name = MACHINE_TYPE_NAME("raspi3b"), |
cb57df6f | 407 | .parent = TYPE_RASPI_MACHINE, |
f0eeb4b6 | 408 | .class_init = raspi3b_machine_class_init, |
cb57df6f PMD |
409 | #endif |
410 | }, { | |
411 | .name = TYPE_RASPI_MACHINE, | |
08df0676 | 412 | .parent = TYPE_RASPI_BASE_MACHINE, |
cb57df6f | 413 | .instance_size = sizeof(RaspiMachineState), |
08df0676 SK |
414 | .abstract = true, |
415 | }, { | |
416 | .name = TYPE_RASPI_BASE_MACHINE, | |
417 | .parent = TYPE_MACHINE, | |
418 | .instance_size = sizeof(RaspiBaseMachineState), | |
419 | .class_size = sizeof(RaspiBaseMachineClass), | |
cb57df6f PMD |
420 | .abstract = true, |
421 | } | |
422 | }; | |
423 | ||
424 | DEFINE_TYPES(raspi_machine_types) |