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64580903 HZ |
1 | /* |
2 | * ARM SBSA Reference Platform emulation | |
3 | * | |
4 | * Copyright (c) 2018 Linaro Limited | |
5 | * Written by Hongbo Zhang <hongbo.zhang@linaro.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
e9fdf453 | 21 | #include "qemu-common.h" |
64580903 HZ |
22 | #include "qapi/error.h" |
23 | #include "qemu/error-report.h" | |
24 | #include "qemu/units.h" | |
e9fdf453 | 25 | #include "sysemu/device_tree.h" |
64580903 | 26 | #include "sysemu/numa.h" |
54d31236 | 27 | #include "sysemu/runstate.h" |
64580903 HZ |
28 | #include "sysemu/sysemu.h" |
29 | #include "exec/address-spaces.h" | |
30 | #include "exec/hwaddr.h" | |
31 | #include "kvm_arm.h" | |
32 | #include "hw/arm/boot.h" | |
e9fdf453 | 33 | #include "hw/block/flash.h" |
64580903 | 34 | #include "hw/boards.h" |
e9fdf453 HZ |
35 | #include "hw/ide/internal.h" |
36 | #include "hw/ide/ahci_internal.h" | |
64580903 | 37 | #include "hw/intc/arm_gicv3_common.h" |
e9fdf453 HZ |
38 | #include "hw/loader.h" |
39 | #include "hw/pci-host/gpex.h" | |
a27bd6c7 | 40 | #include "hw/qdev-properties.h" |
e9fdf453 | 41 | #include "hw/usb.h" |
d8f6d15f | 42 | #include "hw/char/pl011.h" |
baabe7d0 | 43 | #include "hw/watchdog/sbsa_gwdt.h" |
e9fdf453 | 44 | #include "net/net.h" |
db1015e9 | 45 | #include "qom/object.h" |
64580903 HZ |
46 | |
47 | #define RAMLIMIT_GB 8192 | |
48 | #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) | |
49 | ||
e9fdf453 HZ |
50 | #define NUM_IRQS 256 |
51 | #define NUM_SMMU_IRQS 4 | |
52 | #define NUM_SATA_PORTS 6 | |
53 | ||
54 | #define VIRTUAL_PMU_IRQ 7 | |
55 | #define ARCH_GIC_MAINT_IRQ 9 | |
56 | #define ARCH_TIMER_VIRT_IRQ 11 | |
57 | #define ARCH_TIMER_S_EL1_IRQ 13 | |
58 | #define ARCH_TIMER_NS_EL1_IRQ 14 | |
59 | #define ARCH_TIMER_NS_EL2_IRQ 10 | |
60 | ||
64580903 HZ |
61 | enum { |
62 | SBSA_FLASH, | |
63 | SBSA_MEM, | |
64 | SBSA_CPUPERIPHS, | |
65 | SBSA_GIC_DIST, | |
66 | SBSA_GIC_REDIST, | |
3f462bf0 | 67 | SBSA_SECURE_EC, |
baabe7d0 SM |
68 | SBSA_GWDT, |
69 | SBSA_GWDT_REFRESH, | |
70 | SBSA_GWDT_CONTROL, | |
64580903 HZ |
71 | SBSA_SMMU, |
72 | SBSA_UART, | |
73 | SBSA_RTC, | |
74 | SBSA_PCIE, | |
75 | SBSA_PCIE_MMIO, | |
76 | SBSA_PCIE_MMIO_HIGH, | |
77 | SBSA_PCIE_PIO, | |
78 | SBSA_PCIE_ECAM, | |
79 | SBSA_GPIO, | |
80 | SBSA_SECURE_UART, | |
81 | SBSA_SECURE_UART_MM, | |
82 | SBSA_SECURE_MEM, | |
83 | SBSA_AHCI, | |
84 | SBSA_EHCI, | |
85 | }; | |
86 | ||
db1015e9 | 87 | struct SBSAMachineState { |
64580903 HZ |
88 | MachineState parent; |
89 | struct arm_boot_info bootinfo; | |
90 | int smp_cpus; | |
91 | void *fdt; | |
92 | int fdt_size; | |
93 | int psci_conduit; | |
48ba18e6 | 94 | DeviceState *gic; |
e9fdf453 | 95 | PFlashCFI01 *flash[2]; |
db1015e9 | 96 | }; |
64580903 HZ |
97 | |
98 | #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") | |
8063396b | 99 | OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState, SBSA_MACHINE) |
64580903 HZ |
100 | |
101 | static const MemMapEntry sbsa_ref_memmap[] = { | |
102 | /* 512M boot ROM */ | |
103 | [SBSA_FLASH] = { 0, 0x20000000 }, | |
104 | /* 512M secure memory */ | |
105 | [SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 }, | |
106 | /* Space reserved for CPU peripheral devices */ | |
107 | [SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 }, | |
108 | [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, | |
109 | [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, | |
3f462bf0 | 110 | [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, |
baabe7d0 SM |
111 | [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, |
112 | [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, | |
64580903 HZ |
113 | [SBSA_UART] = { 0x60000000, 0x00001000 }, |
114 | [SBSA_RTC] = { 0x60010000, 0x00001000 }, | |
115 | [SBSA_GPIO] = { 0x60020000, 0x00001000 }, | |
116 | [SBSA_SECURE_UART] = { 0x60030000, 0x00001000 }, | |
117 | [SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 }, | |
118 | [SBSA_SMMU] = { 0x60050000, 0x00020000 }, | |
119 | /* Space here reserved for more SMMUs */ | |
120 | [SBSA_AHCI] = { 0x60100000, 0x00010000 }, | |
121 | [SBSA_EHCI] = { 0x60110000, 0x00010000 }, | |
122 | /* Space here reserved for other devices */ | |
123 | [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, | |
124 | /* 32-bit address PCIE MMIO space */ | |
125 | [SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 }, | |
126 | /* 256M PCIE ECAM space */ | |
127 | [SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 }, | |
128 | /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */ | |
129 | [SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL }, | |
130 | [SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES }, | |
131 | }; | |
132 | ||
e9fdf453 HZ |
133 | static const int sbsa_ref_irqmap[] = { |
134 | [SBSA_UART] = 1, | |
135 | [SBSA_RTC] = 2, | |
136 | [SBSA_PCIE] = 3, /* ... to 6 */ | |
137 | [SBSA_GPIO] = 7, | |
138 | [SBSA_SECURE_UART] = 8, | |
139 | [SBSA_SECURE_UART_MM] = 9, | |
140 | [SBSA_AHCI] = 10, | |
141 | [SBSA_EHCI] = 11, | |
04788fd5 | 142 | [SBSA_SMMU] = 12, /* ... to 15 */ |
baabe7d0 | 143 | [SBSA_GWDT] = 16, |
e9fdf453 HZ |
144 | }; |
145 | ||
999f6ebd LL |
146 | static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) |
147 | { | |
148 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | |
149 | return arm_cpu_mp_affinity(idx, clustersz); | |
150 | } | |
151 | ||
e9fdf453 HZ |
152 | /* |
153 | * Firmware on this machine only uses ACPI table to load OS, these limited | |
154 | * device tree nodes are just to let firmware know the info which varies from | |
155 | * command line parameters, so it is not necessary to be fully compatible | |
156 | * with the kernel CPU and NUMA binding rules. | |
157 | */ | |
158 | static void create_fdt(SBSAMachineState *sms) | |
159 | { | |
160 | void *fdt = create_device_tree(&sms->fdt_size); | |
161 | const MachineState *ms = MACHINE(sms); | |
aa570207 | 162 | int nb_numa_nodes = ms->numa_state->num_nodes; |
e9fdf453 HZ |
163 | int cpu; |
164 | ||
165 | if (!fdt) { | |
166 | error_report("create_device_tree() failed"); | |
167 | exit(1); | |
168 | } | |
169 | ||
170 | sms->fdt = fdt; | |
171 | ||
172 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,sbsa-ref"); | |
173 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
174 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
175 | ||
118154b7 | 176 | if (ms->numa_state->have_numa_distance) { |
e9fdf453 HZ |
177 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); |
178 | uint32_t *matrix = g_malloc0(size); | |
179 | int idx, i, j; | |
180 | ||
181 | for (i = 0; i < nb_numa_nodes; i++) { | |
182 | for (j = 0; j < nb_numa_nodes; j++) { | |
183 | idx = (i * nb_numa_nodes + j) * 3; | |
184 | matrix[idx + 0] = cpu_to_be32(i); | |
185 | matrix[idx + 1] = cpu_to_be32(j); | |
7e721e7b TX |
186 | matrix[idx + 2] = |
187 | cpu_to_be32(ms->numa_state->nodes[i].distance[j]); | |
e9fdf453 HZ |
188 | } |
189 | } | |
190 | ||
191 | qemu_fdt_add_subnode(fdt, "/distance-map"); | |
192 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | |
193 | matrix, size); | |
194 | g_free(matrix); | |
195 | } | |
196 | ||
999f6ebd LL |
197 | /* |
198 | * From Documentation/devicetree/bindings/arm/cpus.yaml | |
199 | * On ARM v8 64-bit systems this property is required | |
200 | * and matches the MPIDR_EL1 register affinity bits. | |
201 | * | |
202 | * * If cpus node's #address-cells property is set to 2 | |
203 | * | |
204 | * The first reg cell bits [7:0] must be set to | |
205 | * bits [39:32] of MPIDR_EL1. | |
206 | * | |
207 | * The second reg cell bits [23:0] must be set to | |
208 | * bits [23:0] of MPIDR_EL1. | |
209 | */ | |
e9fdf453 | 210 | qemu_fdt_add_subnode(sms->fdt, "/cpus"); |
999f6ebd LL |
211 | qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#address-cells", 2); |
212 | qemu_fdt_setprop_cell(sms->fdt, "/cpus", "#size-cells", 0x0); | |
e9fdf453 HZ |
213 | |
214 | for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) { | |
215 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | |
216 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
217 | CPUState *cs = CPU(armcpu); | |
999f6ebd | 218 | uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu); |
e9fdf453 HZ |
219 | |
220 | qemu_fdt_add_subnode(sms->fdt, nodename); | |
999f6ebd | 221 | qemu_fdt_setprop_u64(sms->fdt, nodename, "reg", mpidr); |
e9fdf453 HZ |
222 | |
223 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { | |
224 | qemu_fdt_setprop_cell(sms->fdt, nodename, "numa-node-id", | |
225 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); | |
226 | } | |
227 | ||
228 | g_free(nodename); | |
229 | } | |
230 | } | |
231 | ||
232 | #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) | |
233 | ||
234 | static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, | |
235 | const char *name, | |
236 | const char *alias_prop_name) | |
237 | { | |
238 | /* | |
239 | * Create a single flash device. We use the same parameters as | |
240 | * the flash devices on the Versatile Express board. | |
241 | */ | |
df707969 | 242 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
e9fdf453 HZ |
243 | |
244 | qdev_prop_set_uint64(dev, "sector-length", SBSA_FLASH_SECTOR_SIZE); | |
245 | qdev_prop_set_uint8(dev, "width", 4); | |
246 | qdev_prop_set_uint8(dev, "device-width", 2); | |
247 | qdev_prop_set_bit(dev, "big-endian", false); | |
248 | qdev_prop_set_uint16(dev, "id0", 0x89); | |
249 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
250 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
251 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
252 | qdev_prop_set_string(dev, "name", name); | |
d2623129 | 253 | object_property_add_child(OBJECT(sms), name, OBJECT(dev)); |
e9fdf453 | 254 | object_property_add_alias(OBJECT(sms), alias_prop_name, |
d2623129 | 255 | OBJECT(dev), "drive"); |
e9fdf453 HZ |
256 | return PFLASH_CFI01(dev); |
257 | } | |
258 | ||
259 | static void sbsa_flash_create(SBSAMachineState *sms) | |
260 | { | |
261 | sms->flash[0] = sbsa_flash_create1(sms, "sbsa.flash0", "pflash0"); | |
262 | sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); | |
263 | } | |
264 | ||
265 | static void sbsa_flash_map1(PFlashCFI01 *flash, | |
266 | hwaddr base, hwaddr size, | |
267 | MemoryRegion *sysmem) | |
268 | { | |
269 | DeviceState *dev = DEVICE(flash); | |
270 | ||
4cdd0a77 | 271 | assert(QEMU_IS_ALIGNED(size, SBSA_FLASH_SECTOR_SIZE)); |
e9fdf453 HZ |
272 | assert(size / SBSA_FLASH_SECTOR_SIZE <= UINT32_MAX); |
273 | qdev_prop_set_uint32(dev, "num-blocks", size / SBSA_FLASH_SECTOR_SIZE); | |
3c6ef471 | 274 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9fdf453 HZ |
275 | |
276 | memory_region_add_subregion(sysmem, base, | |
277 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), | |
278 | 0)); | |
279 | } | |
280 | ||
281 | static void sbsa_flash_map(SBSAMachineState *sms, | |
282 | MemoryRegion *sysmem, | |
283 | MemoryRegion *secure_sysmem) | |
284 | { | |
285 | /* | |
286 | * Map two flash devices to fill the SBSA_FLASH space in the memmap. | |
287 | * sysmem is the system memory space. secure_sysmem is the secure view | |
288 | * of the system, and the first flash device should be made visible only | |
289 | * there. The second flash device is visible to both secure and nonsecure. | |
e9fdf453 HZ |
290 | */ |
291 | hwaddr flashsize = sbsa_ref_memmap[SBSA_FLASH].size / 2; | |
292 | hwaddr flashbase = sbsa_ref_memmap[SBSA_FLASH].base; | |
293 | ||
294 | sbsa_flash_map1(sms->flash[0], flashbase, flashsize, | |
295 | secure_sysmem); | |
296 | sbsa_flash_map1(sms->flash[1], flashbase + flashsize, flashsize, | |
297 | sysmem); | |
298 | } | |
299 | ||
300 | static bool sbsa_firmware_init(SBSAMachineState *sms, | |
301 | MemoryRegion *sysmem, | |
302 | MemoryRegion *secure_sysmem) | |
303 | { | |
304 | int i; | |
305 | BlockBackend *pflash_blk0; | |
306 | ||
307 | /* Map legacy -drive if=pflash to machine properties */ | |
308 | for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { | |
309 | pflash_cfi01_legacy_drive(sms->flash[i], | |
310 | drive_get(IF_PFLASH, 0, i)); | |
311 | } | |
312 | ||
313 | sbsa_flash_map(sms, sysmem, secure_sysmem); | |
314 | ||
315 | pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); | |
316 | ||
317 | if (bios_name) { | |
318 | char *fname; | |
319 | MemoryRegion *mr; | |
320 | int image_size; | |
321 | ||
322 | if (pflash_blk0) { | |
323 | error_report("The contents of the first flash device may be " | |
324 | "specified with -bios or with -drive if=pflash... " | |
325 | "but you cannot use both options at once"); | |
326 | exit(1); | |
327 | } | |
328 | ||
329 | /* Fall back to -bios */ | |
330 | ||
331 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
332 | if (!fname) { | |
333 | error_report("Could not find ROM image '%s'", bios_name); | |
334 | exit(1); | |
335 | } | |
336 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(sms->flash[0]), 0); | |
337 | image_size = load_image_mr(fname, mr); | |
338 | g_free(fname); | |
339 | if (image_size < 0) { | |
340 | error_report("Could not load ROM image '%s'", bios_name); | |
341 | exit(1); | |
342 | } | |
343 | } | |
344 | ||
345 | return pflash_blk0 || bios_name; | |
346 | } | |
347 | ||
348 | static void create_secure_ram(SBSAMachineState *sms, | |
349 | MemoryRegion *secure_sysmem) | |
350 | { | |
351 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
352 | hwaddr base = sbsa_ref_memmap[SBSA_SECURE_MEM].base; | |
353 | hwaddr size = sbsa_ref_memmap[SBSA_SECURE_MEM].size; | |
354 | ||
355 | memory_region_init_ram(secram, NULL, "sbsa-ref.secure-ram", size, | |
356 | &error_fatal); | |
357 | memory_region_add_subregion(secure_sysmem, base, secram); | |
358 | } | |
359 | ||
48ba18e6 | 360 | static void create_gic(SBSAMachineState *sms) |
e9fdf453 | 361 | { |
cc7d44c2 | 362 | unsigned int smp_cpus = MACHINE(sms)->smp.cpus; |
e9fdf453 HZ |
363 | SysBusDevice *gicbusdev; |
364 | const char *gictype; | |
365 | uint32_t redist0_capacity, redist0_count; | |
366 | int i; | |
367 | ||
368 | gictype = gicv3_class_name(); | |
369 | ||
3e80f690 | 370 | sms->gic = qdev_new(gictype); |
48ba18e6 PMD |
371 | qdev_prop_set_uint32(sms->gic, "revision", 3); |
372 | qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); | |
e9fdf453 HZ |
373 | /* |
374 | * Note that the num-irq property counts both internal and external | |
375 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
376 | */ | |
48ba18e6 PMD |
377 | qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); |
378 | qdev_prop_set_bit(sms->gic, "has-security-extensions", true); | |
e9fdf453 HZ |
379 | |
380 | redist0_capacity = | |
381 | sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
382 | redist0_count = MIN(smp_cpus, redist0_capacity); | |
383 | ||
48ba18e6 PMD |
384 | qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1); |
385 | qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count); | |
e9fdf453 | 386 | |
48ba18e6 | 387 | gicbusdev = SYS_BUS_DEVICE(sms->gic); |
3c6ef471 | 388 | sysbus_realize_and_unref(gicbusdev, &error_fatal); |
e9fdf453 HZ |
389 | sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); |
390 | sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); | |
391 | ||
392 | /* | |
393 | * Wire the outputs from each CPU's generic timer and the GICv3 | |
394 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | |
395 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | |
396 | */ | |
397 | for (i = 0; i < smp_cpus; i++) { | |
398 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
399 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; | |
400 | int irq; | |
401 | /* | |
402 | * Mapping from the output timer irq lines from the CPU to the | |
403 | * GIC PPI inputs used for this board. | |
404 | */ | |
405 | const int timer_irq[] = { | |
406 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
407 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
408 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
409 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
410 | }; | |
411 | ||
412 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
413 | qdev_connect_gpio_out(cpudev, irq, | |
48ba18e6 | 414 | qdev_get_gpio_in(sms->gic, |
e9fdf453 HZ |
415 | ppibase + timer_irq[irq])); |
416 | } | |
417 | ||
418 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, | |
48ba18e6 | 419 | qdev_get_gpio_in(sms->gic, ppibase |
e9fdf453 HZ |
420 | + ARCH_GIC_MAINT_IRQ)); |
421 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, | |
48ba18e6 | 422 | qdev_get_gpio_in(sms->gic, ppibase |
e9fdf453 HZ |
423 | + VIRTUAL_PMU_IRQ)); |
424 | ||
425 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
426 | sysbus_connect_irq(gicbusdev, i + smp_cpus, | |
427 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
428 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, | |
429 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
430 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | |
431 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
432 | } | |
e9fdf453 HZ |
433 | } |
434 | ||
48ba18e6 | 435 | static void create_uart(const SBSAMachineState *sms, int uart, |
e9fdf453 HZ |
436 | MemoryRegion *mem, Chardev *chr) |
437 | { | |
438 | hwaddr base = sbsa_ref_memmap[uart].base; | |
439 | int irq = sbsa_ref_irqmap[uart]; | |
3e80f690 | 440 | DeviceState *dev = qdev_new(TYPE_PL011); |
e9fdf453 HZ |
441 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
442 | ||
443 | qdev_prop_set_chr(dev, "chardev", chr); | |
3c6ef471 | 444 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9fdf453 HZ |
445 | memory_region_add_subregion(mem, base, |
446 | sysbus_mmio_get_region(s, 0)); | |
48ba18e6 | 447 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); |
e9fdf453 HZ |
448 | } |
449 | ||
48ba18e6 | 450 | static void create_rtc(const SBSAMachineState *sms) |
e9fdf453 HZ |
451 | { |
452 | hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; | |
453 | int irq = sbsa_ref_irqmap[SBSA_RTC]; | |
454 | ||
48ba18e6 | 455 | sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); |
e9fdf453 HZ |
456 | } |
457 | ||
baabe7d0 SM |
458 | static void create_wdt(const SBSAMachineState *sms) |
459 | { | |
460 | hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; | |
461 | hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; | |
462 | DeviceState *dev = qdev_new(TYPE_WDT_SBSA); | |
463 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
464 | int irq = sbsa_ref_irqmap[SBSA_GWDT]; | |
465 | ||
466 | sysbus_realize_and_unref(s, &error_fatal); | |
467 | sysbus_mmio_map(s, 0, rbase); | |
468 | sysbus_mmio_map(s, 1, cbase); | |
469 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); | |
470 | } | |
471 | ||
e9fdf453 HZ |
472 | static DeviceState *gpio_key_dev; |
473 | static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) | |
474 | { | |
475 | /* use gpio Pin 3 for power button event */ | |
476 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); | |
477 | } | |
478 | ||
479 | static Notifier sbsa_ref_powerdown_notifier = { | |
480 | .notify = sbsa_ref_powerdown_req | |
481 | }; | |
482 | ||
48ba18e6 | 483 | static void create_gpio(const SBSAMachineState *sms) |
e9fdf453 HZ |
484 | { |
485 | DeviceState *pl061_dev; | |
486 | hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; | |
487 | int irq = sbsa_ref_irqmap[SBSA_GPIO]; | |
488 | ||
48ba18e6 PMD |
489 | pl061_dev = sysbus_create_simple("pl061", base, |
490 | qdev_get_gpio_in(sms->gic, irq)); | |
e9fdf453 HZ |
491 | |
492 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, | |
493 | qdev_get_gpio_in(pl061_dev, 3)); | |
494 | ||
495 | /* connect powerdown request */ | |
496 | qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); | |
497 | } | |
498 | ||
48ba18e6 | 499 | static void create_ahci(const SBSAMachineState *sms) |
e9fdf453 HZ |
500 | { |
501 | hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; | |
502 | int irq = sbsa_ref_irqmap[SBSA_AHCI]; | |
503 | DeviceState *dev; | |
504 | DriveInfo *hd[NUM_SATA_PORTS]; | |
505 | SysbusAHCIState *sysahci; | |
506 | AHCIState *ahci; | |
507 | int i; | |
508 | ||
3e80f690 | 509 | dev = qdev_new("sysbus-ahci"); |
e9fdf453 | 510 | qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); |
3c6ef471 | 511 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9fdf453 | 512 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
48ba18e6 | 513 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); |
e9fdf453 HZ |
514 | |
515 | sysahci = SYSBUS_AHCI(dev); | |
516 | ahci = &sysahci->ahci; | |
517 | ide_drive_get(hd, ARRAY_SIZE(hd)); | |
518 | for (i = 0; i < ahci->ports; i++) { | |
519 | if (hd[i] == NULL) { | |
520 | continue; | |
521 | } | |
522 | ide_create_drive(&ahci->dev[i].port, 0, hd[i]); | |
523 | } | |
524 | } | |
525 | ||
48ba18e6 | 526 | static void create_ehci(const SBSAMachineState *sms) |
e9fdf453 HZ |
527 | { |
528 | hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; | |
529 | int irq = sbsa_ref_irqmap[SBSA_EHCI]; | |
530 | ||
48ba18e6 PMD |
531 | sysbus_create_simple("platform-ehci-usb", base, |
532 | qdev_get_gpio_in(sms->gic, irq)); | |
e9fdf453 HZ |
533 | } |
534 | ||
48ba18e6 | 535 | static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) |
e9fdf453 HZ |
536 | { |
537 | hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; | |
538 | int irq = sbsa_ref_irqmap[SBSA_SMMU]; | |
539 | DeviceState *dev; | |
540 | int i; | |
541 | ||
3e80f690 | 542 | dev = qdev_new("arm-smmuv3"); |
e9fdf453 | 543 | |
5325cc34 | 544 | object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), |
e9fdf453 | 545 | &error_abort); |
3c6ef471 | 546 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9fdf453 HZ |
547 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
548 | for (i = 0; i < NUM_SMMU_IRQS; i++) { | |
48ba18e6 | 549 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
b8bf3472 | 550 | qdev_get_gpio_in(sms->gic, irq + i)); |
e9fdf453 HZ |
551 | } |
552 | } | |
553 | ||
48ba18e6 | 554 | static void create_pcie(SBSAMachineState *sms) |
e9fdf453 HZ |
555 | { |
556 | hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; | |
557 | hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; | |
558 | hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base; | |
559 | hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size; | |
560 | hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base; | |
561 | hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size; | |
562 | hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base; | |
563 | int irq = sbsa_ref_irqmap[SBSA_PCIE]; | |
564 | MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg; | |
565 | MemoryRegion *ecam_alias, *ecam_reg; | |
566 | DeviceState *dev; | |
567 | PCIHostState *pci; | |
568 | int i; | |
569 | ||
3e80f690 | 570 | dev = qdev_new(TYPE_GPEX_HOST); |
3c6ef471 | 571 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e9fdf453 HZ |
572 | |
573 | /* Map ECAM space */ | |
574 | ecam_alias = g_new0(MemoryRegion, 1); | |
575 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
576 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
577 | ecam_reg, 0, size_ecam); | |
578 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
579 | ||
580 | /* Map the MMIO space */ | |
581 | mmio_alias = g_new0(MemoryRegion, 1); | |
582 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
583 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
584 | mmio_reg, base_mmio, size_mmio); | |
585 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
586 | ||
587 | /* Map the MMIO_HIGH space */ | |
588 | mmio_alias_high = g_new0(MemoryRegion, 1); | |
589 | memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high", | |
590 | mmio_reg, base_mmio_high, size_mmio_high); | |
591 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
592 | mmio_alias_high); | |
593 | ||
594 | /* Map IO port space */ | |
595 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); | |
596 | ||
597 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
48ba18e6 | 598 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
870f0051 | 599 | qdev_get_gpio_in(sms->gic, irq + i)); |
e9fdf453 HZ |
600 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
601 | } | |
602 | ||
603 | pci = PCI_HOST_BRIDGE(dev); | |
604 | if (pci->bus) { | |
605 | for (i = 0; i < nb_nics; i++) { | |
606 | NICInfo *nd = &nd_table[i]; | |
607 | ||
608 | if (!nd->model) { | |
609 | nd->model = g_strdup("e1000e"); | |
610 | } | |
611 | ||
612 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
613 | } | |
614 | } | |
615 | ||
616 | pci_create_simple(pci->bus, -1, "VGA"); | |
617 | ||
48ba18e6 | 618 | create_smmu(sms, pci->bus); |
e9fdf453 HZ |
619 | } |
620 | ||
621 | static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) | |
622 | { | |
623 | const SBSAMachineState *board = container_of(binfo, SBSAMachineState, | |
624 | bootinfo); | |
625 | ||
626 | *fdt_size = board->fdt_size; | |
627 | return board->fdt; | |
628 | } | |
629 | ||
3f462bf0 GG |
630 | static void create_secure_ec(MemoryRegion *mem) |
631 | { | |
632 | hwaddr base = sbsa_ref_memmap[SBSA_SECURE_EC].base; | |
633 | DeviceState *dev = qdev_new("sbsa-ec"); | |
634 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
635 | ||
636 | memory_region_add_subregion(mem, base, | |
637 | sysbus_mmio_get_region(s, 0)); | |
638 | } | |
639 | ||
64580903 HZ |
640 | static void sbsa_ref_init(MachineState *machine) |
641 | { | |
cc7d44c2 LX |
642 | unsigned int smp_cpus = machine->smp.cpus; |
643 | unsigned int max_cpus = machine->smp.max_cpus; | |
64580903 HZ |
644 | SBSAMachineState *sms = SBSA_MACHINE(machine); |
645 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
646 | MemoryRegion *sysmem = get_system_memory(); | |
c8ead571 | 647 | MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); |
e9fdf453 | 648 | bool firmware_loaded; |
64580903 HZ |
649 | const CPUArchIdList *possible_cpus; |
650 | int n, sbsa_max_cpus; | |
651 | ||
652 | if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { | |
653 | error_report("sbsa-ref: CPU type other than the built-in " | |
654 | "cortex-a57 not supported"); | |
655 | exit(1); | |
656 | } | |
657 | ||
658 | if (kvm_enabled()) { | |
659 | error_report("sbsa-ref: KVM is not supported for this machine"); | |
660 | exit(1); | |
661 | } | |
662 | ||
e9fdf453 HZ |
663 | /* |
664 | * The Secure view of the world is the same as the NonSecure, | |
665 | * but with a few extra devices. Create it as a container region | |
666 | * containing the system memory at low priority; any secure-only | |
667 | * devices go in at higher priority and take precedence. | |
668 | */ | |
e9fdf453 HZ |
669 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", |
670 | UINT64_MAX); | |
671 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
672 | ||
c8ead571 | 673 | firmware_loaded = sbsa_firmware_init(sms, sysmem, secure_sysmem); |
e9fdf453 HZ |
674 | |
675 | if (machine->kernel_filename && firmware_loaded) { | |
676 | error_report("sbsa-ref: No fw_cfg device on this machine, " | |
677 | "so -kernel option is not supported when firmware loaded, " | |
678 | "please load OS from hard disk instead"); | |
679 | exit(1); | |
680 | } | |
681 | ||
64580903 HZ |
682 | /* |
683 | * This machine has EL3 enabled, external firmware should supply PSCI | |
684 | * implementation, so the QEMU's internal PSCI is disabled. | |
685 | */ | |
686 | sms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
687 | ||
688 | sbsa_max_cpus = sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; | |
689 | ||
690 | if (max_cpus > sbsa_max_cpus) { | |
691 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " | |
692 | "supported by machine 'sbsa-ref' (%d)", | |
693 | max_cpus, sbsa_max_cpus); | |
694 | exit(1); | |
695 | } | |
696 | ||
697 | sms->smp_cpus = smp_cpus; | |
698 | ||
699 | if (machine->ram_size > sbsa_ref_memmap[SBSA_MEM].size) { | |
700 | error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB); | |
701 | exit(1); | |
702 | } | |
703 | ||
704 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
705 | for (n = 0; n < possible_cpus->len; n++) { | |
706 | Object *cpuobj; | |
707 | CPUState *cs; | |
708 | ||
709 | if (n >= smp_cpus) { | |
710 | break; | |
711 | } | |
712 | ||
713 | cpuobj = object_new(possible_cpus->cpus[n].type); | |
5325cc34 MA |
714 | object_property_set_int(cpuobj, "mp-affinity", |
715 | possible_cpus->cpus[n].arch_id, NULL); | |
64580903 HZ |
716 | |
717 | cs = CPU(cpuobj); | |
718 | cs->cpu_index = n; | |
719 | ||
720 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), | |
721 | &error_fatal); | |
722 | ||
efba1595 | 723 | if (object_property_find(cpuobj, "reset-cbar")) { |
5325cc34 | 724 | object_property_set_int(cpuobj, "reset-cbar", |
64580903 | 725 | sbsa_ref_memmap[SBSA_CPUPERIPHS].base, |
5325cc34 | 726 | &error_abort); |
64580903 HZ |
727 | } |
728 | ||
5325cc34 | 729 | object_property_set_link(cpuobj, "memory", OBJECT(sysmem), |
64580903 HZ |
730 | &error_abort); |
731 | ||
5325cc34 MA |
732 | object_property_set_link(cpuobj, "secure-memory", |
733 | OBJECT(secure_sysmem), &error_abort); | |
64580903 | 734 | |
ce189ab2 | 735 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
64580903 HZ |
736 | object_unref(cpuobj); |
737 | } | |
738 | ||
3818ed92 IM |
739 | memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, |
740 | machine->ram); | |
64580903 | 741 | |
e9fdf453 HZ |
742 | create_fdt(sms); |
743 | ||
744 | create_secure_ram(sms, secure_sysmem); | |
745 | ||
48ba18e6 | 746 | create_gic(sms); |
e9fdf453 | 747 | |
48ba18e6 PMD |
748 | create_uart(sms, SBSA_UART, sysmem, serial_hd(0)); |
749 | create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); | |
e9fdf453 | 750 | /* Second secure UART for RAS and MM from EL0 */ |
48ba18e6 | 751 | create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); |
e9fdf453 | 752 | |
48ba18e6 | 753 | create_rtc(sms); |
e9fdf453 | 754 | |
baabe7d0 SM |
755 | create_wdt(sms); |
756 | ||
48ba18e6 | 757 | create_gpio(sms); |
e9fdf453 | 758 | |
48ba18e6 | 759 | create_ahci(sms); |
e9fdf453 | 760 | |
48ba18e6 | 761 | create_ehci(sms); |
e9fdf453 | 762 | |
48ba18e6 | 763 | create_pcie(sms); |
e9fdf453 | 764 | |
3f462bf0 GG |
765 | create_secure_ec(secure_sysmem); |
766 | ||
64580903 | 767 | sms->bootinfo.ram_size = machine->ram_size; |
64580903 HZ |
768 | sms->bootinfo.nb_cpus = smp_cpus; |
769 | sms->bootinfo.board_id = -1; | |
770 | sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base; | |
e9fdf453 HZ |
771 | sms->bootinfo.get_dtb = sbsa_ref_dtb; |
772 | sms->bootinfo.firmware_loaded = firmware_loaded; | |
2744ece8 | 773 | arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo); |
64580903 HZ |
774 | } |
775 | ||
64580903 HZ |
776 | static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms) |
777 | { | |
cc7d44c2 | 778 | unsigned int max_cpus = ms->smp.max_cpus; |
64580903 HZ |
779 | SBSAMachineState *sms = SBSA_MACHINE(ms); |
780 | int n; | |
781 | ||
782 | if (ms->possible_cpus) { | |
783 | assert(ms->possible_cpus->len == max_cpus); | |
784 | return ms->possible_cpus; | |
785 | } | |
786 | ||
787 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
788 | sizeof(CPUArchId) * max_cpus); | |
789 | ms->possible_cpus->len = max_cpus; | |
790 | for (n = 0; n < ms->possible_cpus->len; n++) { | |
791 | ms->possible_cpus->cpus[n].type = ms->cpu_type; | |
792 | ms->possible_cpus->cpus[n].arch_id = | |
793 | sbsa_ref_cpu_mp_affinity(sms, n); | |
794 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | |
795 | ms->possible_cpus->cpus[n].props.thread_id = n; | |
796 | } | |
797 | return ms->possible_cpus; | |
798 | } | |
799 | ||
800 | static CpuInstanceProperties | |
801 | sbsa_ref_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
802 | { | |
803 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
804 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
805 | ||
806 | assert(cpu_index < possible_cpus->len); | |
807 | return possible_cpus->cpus[cpu_index].props; | |
808 | } | |
809 | ||
810 | static int64_t | |
811 | sbsa_ref_get_default_cpu_node_id(const MachineState *ms, int idx) | |
812 | { | |
aa570207 | 813 | return idx % ms->numa_state->num_nodes; |
64580903 HZ |
814 | } |
815 | ||
e9fdf453 HZ |
816 | static void sbsa_ref_instance_init(Object *obj) |
817 | { | |
818 | SBSAMachineState *sms = SBSA_MACHINE(obj); | |
819 | ||
820 | sbsa_flash_create(sms); | |
821 | } | |
822 | ||
64580903 HZ |
823 | static void sbsa_ref_class_init(ObjectClass *oc, void *data) |
824 | { | |
825 | MachineClass *mc = MACHINE_CLASS(oc); | |
826 | ||
827 | mc->init = sbsa_ref_init; | |
828 | mc->desc = "QEMU 'SBSA Reference' ARM Virtual Machine"; | |
829 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a57"); | |
830 | mc->max_cpus = 512; | |
831 | mc->pci_allow_0_address = true; | |
832 | mc->minimum_page_bits = 12; | |
833 | mc->block_default_type = IF_IDE; | |
834 | mc->no_cdrom = 1; | |
835 | mc->default_ram_size = 1 * GiB; | |
3818ed92 | 836 | mc->default_ram_id = "sbsa-ref.ram"; |
64580903 HZ |
837 | mc->default_cpus = 4; |
838 | mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; | |
839 | mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; | |
840 | mc->get_default_cpu_node_id = sbsa_ref_get_default_cpu_node_id; | |
841 | } | |
842 | ||
843 | static const TypeInfo sbsa_ref_info = { | |
844 | .name = TYPE_SBSA_MACHINE, | |
845 | .parent = TYPE_MACHINE, | |
e9fdf453 | 846 | .instance_init = sbsa_ref_instance_init, |
64580903 HZ |
847 | .class_init = sbsa_ref_class_init, |
848 | .instance_size = sizeof(SBSAMachineState), | |
849 | }; | |
850 | ||
851 | static void sbsa_ref_machine_init(void) | |
852 | { | |
853 | type_register_static(&sbsa_ref_info); | |
854 | } | |
855 | ||
856 | type_init(sbsa_ref_machine_init); |