[mirror_qemu.git] / hw / arm / smmuv3-internal.h

/*
 * ARM SMMUv3 support - Internal API
 *
 * Copyright (C) 2014-2016 Broadcom Corporation
 * Copyright (c) 2017 Red Hat, Inc.
 * Written by Prem Mallappa, Eric Auger
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HW_ARM_SMMUV3_INTERNAL_H
#define HW_ARM_SMMUV3_INTERNAL_H

#include "hw/arm/smmu-common.h"

typedef enum SMMUTranslationStatus {
    SMMU_TRANS_DISABLE,
    SMMU_TRANS_ABORT,
    SMMU_TRANS_BYPASS,
    SMMU_TRANS_ERROR,
    SMMU_TRANS_SUCCESS,
} SMMUTranslationStatus;

/* MMIO Registers */

REG32(IDR0,                0x0)
    FIELD(IDR0, S1P,         1 , 1)
    FIELD(IDR0, TTF,         2 , 2)
    FIELD(IDR0, COHACC,      4 , 1)
    FIELD(IDR0, ASID16,      12, 1)
    FIELD(IDR0, TTENDIAN,    21, 2)
    FIELD(IDR0, STALL_MODEL, 24, 2)
    FIELD(IDR0, TERM_MODEL,  26, 1)
    FIELD(IDR0, STLEVEL,     27, 2)

REG32(IDR1,                0x4)
    FIELD(IDR1, SIDSIZE,      0 , 6)
    FIELD(IDR1, EVENTQS,      16, 5)
    FIELD(IDR1, CMDQS,        21, 5)

#define SMMU_IDR1_SIDSIZE 16
#define SMMU_CMDQS   19
#define SMMU_EVENTQS 19

REG32(IDR2,                0x8)
REG32(IDR3,                0xc)
     FIELD(IDR3, HAD,         2, 1);
     FIELD(IDR3, RIL,        10, 1);
REG32(IDR4,                0x10)
REG32(IDR5,                0x14)
     FIELD(IDR5, OAS,         0, 3);
     FIELD(IDR5, GRAN4K,      4, 1);
     FIELD(IDR5, GRAN16K,     5, 1);
     FIELD(IDR5, GRAN64K,     6, 1);

#define SMMU_IDR5_OAS 4

REG32(IIDR,                0x18)
REG32(AIDR,                0x1c)
REG32(CR0,                 0x20)
    FIELD(CR0, SMMU_ENABLE,   0, 1)
    FIELD(CR0, EVENTQEN,      2, 1)
    FIELD(CR0, CMDQEN,        3, 1)

#define SMMU_CR0_RESERVED 0xFFFFFC20

REG32(CR0ACK,              0x24)
REG32(CR1,                 0x28)
REG32(CR2,                 0x2c)
REG32(STATUSR,             0x40)
REG32(IRQ_CTRL,            0x50)
    FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
    FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
    FIELD(IRQ_CTRL, EVENTQ_IRQEN,        2, 1)

REG32(IRQ_CTRL_ACK,        0x54)
REG32(GERROR,              0x60)
    FIELD(GERROR, CMDQ_ERR,           0, 1)
    FIELD(GERROR, EVENTQ_ABT_ERR,     2, 1)
    FIELD(GERROR, PRIQ_ABT_ERR,       3, 1)
    FIELD(GERROR, MSI_CMDQ_ABT_ERR,   4, 1)
    FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
    FIELD(GERROR, MSI_PRIQ_ABT_ERR,   6, 1)
    FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
    FIELD(GERROR, MSI_SFM_ERR,        8, 1)

REG32(GERRORN,             0x64)

#define A_GERROR_IRQ_CFG0  0x68 /* 64b */
REG32(GERROR_IRQ_CFG1, 0x70)
REG32(GERROR_IRQ_CFG2, 0x74)

#define A_STRTAB_BASE      0x80 /* 64b */

#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0

REG32(STRTAB_BASE_CFG,     0x88)
    FIELD(STRTAB_BASE_CFG, FMT,      16, 2)
    FIELD(STRTAB_BASE_CFG, SPLIT,    6 , 5)
    FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)

#define A_CMDQ_BASE        0x90 /* 64b */
REG32(CMDQ_PROD,           0x98)
REG32(CMDQ_CONS,           0x9c)
    FIELD(CMDQ_CONS, ERR, 24, 7)

#define A_EVENTQ_BASE      0xa0 /* 64b */
REG32(EVENTQ_PROD,         0xa8)
REG32(EVENTQ_CONS,         0xac)

#define A_EVENTQ_IRQ_CFG0  0xb0 /* 64b */
REG32(EVENTQ_IRQ_CFG1,     0xb8)
REG32(EVENTQ_IRQ_CFG2,     0xbc)

#define A_IDREGS           0xfd0

static inline int smmu_enabled(SMMUv3State *s)
{
    return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
}

/* Command Queue Entry */
typedef struct Cmd {
    uint32_t word[4];
} Cmd;

/* Event Queue Entry */
typedef struct Evt  {
    uint32_t word[8];
} Evt;

static inline uint32_t smmuv3_idreg(int regoffset)
{
    /*
     * Return the value of the Primecell/Corelink ID registers at the
     * specified offset from the first ID register.
     * These value indicate an ARM implementation of MMU600 p1
     */
    static const uint8_t smmuv3_ids[] = {
        0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
    };
    return smmuv3_ids[regoffset / 4];
}

static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
{
    return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
}

static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
{
    return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
}

/* Queue Handling */

#define Q_BASE(q)          ((q)->base & SMMU_BASE_ADDR_MASK)
#define WRAP_MASK(q)       (1 << (q)->log2size)
#define INDEX_MASK(q)      (((1 << (q)->log2size)) - 1)
#define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)

#define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
#define Q_PROD(q) ((q)->prod & INDEX_MASK(q))

#define Q_CONS_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
#define Q_PROD_ENTRY(q)  (Q_BASE(q) + (q)->entry_size * Q_PROD(q))

#define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
#define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)

static inline bool smmuv3_q_full(SMMUQueue *q)
{
    return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
}

static inline bool smmuv3_q_empty(SMMUQueue *q)
{
    return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
}

static inline void queue_prod_incr(SMMUQueue *q)
{
    q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
}

static inline void queue_cons_incr(SMMUQueue *q)
{
    /*
     * We have to use deposit for the CONS registers to preserve
     * the ERR field in the high bits.
     */
    q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
}

static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
{
    return FIELD_EX32(s->cr[0], CR0, CMDQEN);
}

static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
{
    return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
}

static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
{
    s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
}

/* Commands */

typedef enum SMMUCommandType {
    SMMU_CMD_NONE            = 0x00,
    SMMU_CMD_PREFETCH_CONFIG       ,
    SMMU_CMD_PREFETCH_ADDR,
    SMMU_CMD_CFGI_STE,
    SMMU_CMD_CFGI_STE_RANGE,
    SMMU_CMD_CFGI_CD,
    SMMU_CMD_CFGI_CD_ALL,
    SMMU_CMD_CFGI_ALL,
    SMMU_CMD_TLBI_NH_ALL     = 0x10,
    SMMU_CMD_TLBI_NH_ASID,
    SMMU_CMD_TLBI_NH_VA,
    SMMU_CMD_TLBI_NH_VAA,
    SMMU_CMD_TLBI_EL3_ALL    = 0x18,
    SMMU_CMD_TLBI_EL3_VA     = 0x1a,
    SMMU_CMD_TLBI_EL2_ALL    = 0x20,
    SMMU_CMD_TLBI_EL2_ASID,
    SMMU_CMD_TLBI_EL2_VA,
    SMMU_CMD_TLBI_EL2_VAA,
    SMMU_CMD_TLBI_S12_VMALL  = 0x28,
    SMMU_CMD_TLBI_S2_IPA     = 0x2a,
    SMMU_CMD_TLBI_NSNH_ALL   = 0x30,
    SMMU_CMD_ATC_INV         = 0x40,
    SMMU_CMD_PRI_RESP,
    SMMU_CMD_RESUME          = 0x44,
    SMMU_CMD_STALL_TERM,
    SMMU_CMD_SYNC,
} SMMUCommandType;

static const char *cmd_stringify[] = {
    [SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
    [SMMU_CMD_PREFETCH_ADDR]   = "SMMU_CMD_PREFETCH_ADDR",
    [SMMU_CMD_CFGI_STE]        = "SMMU_CMD_CFGI_STE",
    [SMMU_CMD_CFGI_STE_RANGE]  = "SMMU_CMD_CFGI_STE_RANGE",
    [SMMU_CMD_CFGI_CD]         = "SMMU_CMD_CFGI_CD",
    [SMMU_CMD_CFGI_CD_ALL]     = "SMMU_CMD_CFGI_CD_ALL",
    [SMMU_CMD_CFGI_ALL]        = "SMMU_CMD_CFGI_ALL",
    [SMMU_CMD_TLBI_NH_ALL]     = "SMMU_CMD_TLBI_NH_ALL",
    [SMMU_CMD_TLBI_NH_ASID]    = "SMMU_CMD_TLBI_NH_ASID",
    [SMMU_CMD_TLBI_NH_VA]      = "SMMU_CMD_TLBI_NH_VA",
    [SMMU_CMD_TLBI_NH_VAA]     = "SMMU_CMD_TLBI_NH_VAA",
    [SMMU_CMD_TLBI_EL3_ALL]    = "SMMU_CMD_TLBI_EL3_ALL",
    [SMMU_CMD_TLBI_EL3_VA]     = "SMMU_CMD_TLBI_EL3_VA",
    [SMMU_CMD_TLBI_EL2_ALL]    = "SMMU_CMD_TLBI_EL2_ALL",
    [SMMU_CMD_TLBI_EL2_ASID]   = "SMMU_CMD_TLBI_EL2_ASID",
    [SMMU_CMD_TLBI_EL2_VA]     = "SMMU_CMD_TLBI_EL2_VA",
    [SMMU_CMD_TLBI_EL2_VAA]    = "SMMU_CMD_TLBI_EL2_VAA",
    [SMMU_CMD_TLBI_S12_VMALL]  = "SMMU_CMD_TLBI_S12_VMALL",
    [SMMU_CMD_TLBI_S2_IPA]     = "SMMU_CMD_TLBI_S2_IPA",
    [SMMU_CMD_TLBI_NSNH_ALL]   = "SMMU_CMD_TLBI_NSNH_ALL",
    [SMMU_CMD_ATC_INV]         = "SMMU_CMD_ATC_INV",
    [SMMU_CMD_PRI_RESP]        = "SMMU_CMD_PRI_RESP",
    [SMMU_CMD_RESUME]          = "SMMU_CMD_RESUME",
    [SMMU_CMD_STALL_TERM]      = "SMMU_CMD_STALL_TERM",
    [SMMU_CMD_SYNC]            = "SMMU_CMD_SYNC",
};

static inline const char *smmu_cmd_string(SMMUCommandType type)
{
    if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
        return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
    } else {
        return "INVALID";
    }
}

/* CMDQ fields */

typedef enum {
    SMMU_CERROR_NONE = 0,
    SMMU_CERROR_ILL,
    SMMU_CERROR_ABT,
    SMMU_CERROR_ATC_INV_SYNC,
} SMMUCmdError;

enum { /* Command completion notification */
    CMD_SYNC_SIG_NONE,
    CMD_SYNC_SIG_IRQ,
    CMD_SYNC_SIG_SEV,
};

#define CMD_TYPE(x)         extract32((x)->word[0], 0 , 8)
#define CMD_NUM(x)          extract32((x)->word[0], 12 , 5)
#define CMD_SCALE(x)        extract32((x)->word[0], 20 , 5)
#define CMD_SSEC(x)         extract32((x)->word[0], 10, 1)
#define CMD_SSV(x)          extract32((x)->word[0], 11, 1)
#define CMD_RESUME_AC(x)    extract32((x)->word[0], 12, 1)
#define CMD_RESUME_AB(x)    extract32((x)->word[0], 13, 1)
#define CMD_SYNC_CS(x)      extract32((x)->word[0], 12, 2)
#define CMD_SSID(x)         extract32((x)->word[0], 12, 20)
#define CMD_SID(x)          ((x)->word[1])
#define CMD_VMID(x)         extract32((x)->word[1], 0 , 16)
#define CMD_ASID(x)         extract32((x)->word[1], 16, 16)
#define CMD_RESUME_STAG(x)  extract32((x)->word[2], 0 , 16)
#define CMD_RESP(x)         extract32((x)->word[2], 11, 2)
#define CMD_LEAF(x)         extract32((x)->word[2], 0 , 1)
#define CMD_TTL(x)          extract32((x)->word[2], 8 , 2)
#define CMD_TG(x)           extract32((x)->word[2], 10, 2)
#define CMD_STE_RANGE(x)    extract32((x)->word[2], 0 , 5)
#define CMD_ADDR(x) ({                                        \
            uint64_t high = (uint64_t)(x)->word[3];           \
            uint64_t low = extract32((x)->word[2], 12, 20);    \
            uint64_t addr = high << 32 | (low << 12);         \
            addr;                                             \
        })

#define SMMU_FEATURE_2LVL_STE (1 << 0)

/* Events */

typedef enum SMMUEventType {
    SMMU_EVT_NONE               = 0x00,
    SMMU_EVT_F_UUT                    ,
    SMMU_EVT_C_BAD_STREAMID           ,
    SMMU_EVT_F_STE_FETCH              ,
    SMMU_EVT_C_BAD_STE                ,
    SMMU_EVT_F_BAD_ATS_TREQ           ,
    SMMU_EVT_F_STREAM_DISABLED        ,
    SMMU_EVT_F_TRANS_FORBIDDEN        ,
    SMMU_EVT_C_BAD_SUBSTREAMID        ,
    SMMU_EVT_F_CD_FETCH               ,
    SMMU_EVT_C_BAD_CD                 ,
    SMMU_EVT_F_WALK_EABT              ,
    SMMU_EVT_F_TRANSLATION      = 0x10,
    SMMU_EVT_F_ADDR_SIZE              ,
    SMMU_EVT_F_ACCESS                 ,
    SMMU_EVT_F_PERMISSION             ,
    SMMU_EVT_F_TLB_CONFLICT     = 0x20,
    SMMU_EVT_F_CFG_CONFLICT           ,
    SMMU_EVT_E_PAGE_REQ         = 0x24,
} SMMUEventType;

static const char *event_stringify[] = {
    [SMMU_EVT_NONE]                     = "no recorded event",
    [SMMU_EVT_F_UUT]                    = "SMMU_EVT_F_UUT",
    [SMMU_EVT_C_BAD_STREAMID]           = "SMMU_EVT_C_BAD_STREAMID",
    [SMMU_EVT_F_STE_FETCH]              = "SMMU_EVT_F_STE_FETCH",
    [SMMU_EVT_C_BAD_STE]                = "SMMU_EVT_C_BAD_STE",
    [SMMU_EVT_F_BAD_ATS_TREQ]           = "SMMU_EVT_F_BAD_ATS_TREQ",
    [SMMU_EVT_F_STREAM_DISABLED]        = "SMMU_EVT_F_STREAM_DISABLED",
    [SMMU_EVT_F_TRANS_FORBIDDEN]        = "SMMU_EVT_F_TRANS_FORBIDDEN",
    [SMMU_EVT_C_BAD_SUBSTREAMID]        = "SMMU_EVT_C_BAD_SUBSTREAMID",
    [SMMU_EVT_F_CD_FETCH]               = "SMMU_EVT_F_CD_FETCH",
    [SMMU_EVT_C_BAD_CD]                 = "SMMU_EVT_C_BAD_CD",
    [SMMU_EVT_F_WALK_EABT]              = "SMMU_EVT_F_WALK_EABT",
    [SMMU_EVT_F_TRANSLATION]            = "SMMU_EVT_F_TRANSLATION",
    [SMMU_EVT_F_ADDR_SIZE]              = "SMMU_EVT_F_ADDR_SIZE",
    [SMMU_EVT_F_ACCESS]                 = "SMMU_EVT_F_ACCESS",
    [SMMU_EVT_F_PERMISSION]             = "SMMU_EVT_F_PERMISSION",
    [SMMU_EVT_F_TLB_CONFLICT]           = "SMMU_EVT_F_TLB_CONFLICT",
    [SMMU_EVT_F_CFG_CONFLICT]           = "SMMU_EVT_F_CFG_CONFLICT",
    [SMMU_EVT_E_PAGE_REQ]               = "SMMU_EVT_E_PAGE_REQ",
};

static inline const char *smmu_event_string(SMMUEventType type)
{
    if (type < ARRAY_SIZE(event_stringify)) {
        return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
    } else {
        return "INVALID";
    }
}

/*  Encode an event record */
typedef struct SMMUEventInfo {
    SMMUEventType type;
    uint32_t sid;
    bool recorded;
    bool inval_ste_allowed;
    union {
        struct {
            uint32_t ssid;
            bool ssv;
            dma_addr_t addr;
            bool rnw;
            bool pnu;
            bool ind;
       } f_uut;
       struct SSIDInfo {
            uint32_t ssid;
            bool ssv;
       } c_bad_streamid;
       struct SSIDAddrInfo {
            uint32_t ssid;
            bool ssv;
            dma_addr_t addr;
       } f_ste_fetch;
       struct SSIDInfo c_bad_ste;
       struct {
            dma_addr_t addr;
            bool rnw;
       } f_transl_forbidden;
       struct {
            uint32_t ssid;
       } c_bad_substream;
       struct SSIDAddrInfo f_cd_fetch;
       struct SSIDInfo c_bad_cd;
       struct FullInfo {
            bool stall;
            uint16_t stag;
            uint32_t ssid;
            bool ssv;
            bool s2;
            dma_addr_t addr;
            bool rnw;
            bool pnu;
            bool ind;
            uint8_t class;
            dma_addr_t addr2;
       } f_walk_eabt;
       struct FullInfo f_translation;
       struct FullInfo f_addr_size;
       struct FullInfo f_access;
       struct FullInfo f_permission;
       struct SSIDInfo f_cfg_conflict;
       /**
        * not supported yet:
        * F_BAD_ATS_TREQ
        * F_BAD_ATS_TREQ
        * F_TLB_CONFLICT
        * E_PAGE_REQUEST
        * IMPDEF_EVENTn
        */
    } u;
} SMMUEventInfo;

/* EVTQ fields */

#define EVT_Q_OVERFLOW        (1 << 31)

#define EVT_SET_TYPE(x, v)  ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
#define EVT_SET_SSV(x, v)   ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
#define EVT_SET_SSID(x, v)  ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
#define EVT_SET_SID(x, v)   ((x)->word[1] = v)
#define EVT_SET_STAG(x, v)  ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
#define EVT_SET_PNU(x, v)   ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
#define EVT_SET_IND(x, v)   ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
#define EVT_SET_RNW(x, v)   ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
#define EVT_SET_S2(x, v)    ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
#define EVT_SET_ADDR(x, addr)                             \
    do {                                                  \
            (x)->word[5] = (uint32_t)(addr >> 32);        \
            (x)->word[4] = (uint32_t)(addr & 0xffffffff); \
    } while (0)
#define EVT_SET_ADDR2(x, addr)                            \
    do {                                                  \
            (x)->word[7] = (uint32_t)(addr >> 32);        \
            (x)->word[6] = (uint32_t)(addr & 0xffffffff); \
    } while (0)

void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);

/* Configuration Data */

/* STE Level 1 Descriptor */
typedef struct STEDesc {
    uint32_t word[2];
} STEDesc;

/* CD Level 1 Descriptor */
typedef struct CDDesc {
    uint32_t word[2];
} CDDesc;

/* Stream Table Entry(STE) */
typedef struct STE {
    uint32_t word[16];
} STE;

/* Context Descriptor(CD) */
typedef struct CD {
    uint32_t word[16];
} CD;

/* STE fields */

#define STE_VALID(x)   extract32((x)->word[0], 0, 1)

#define STE_CONFIG(x)  extract32((x)->word[0], 1, 3)
#define STE_CFG_S1_ENABLED(config) (config & 0x1)
#define STE_CFG_S2_ENABLED(config) (config & 0x2)
#define STE_CFG_ABORT(config)      (!(config & 0x4))
#define STE_CFG_BYPASS(config)     (config == 0x4)

#define STE_S1FMT(x)       extract32((x)->word[0], 4 , 2)
#define STE_S1CDMAX(x)     extract32((x)->word[1], 27, 5)
#define STE_S1STALLD(x)    extract32((x)->word[2], 27, 1)
#define STE_EATS(x)        extract32((x)->word[2], 28, 2)
#define STE_STRW(x)        extract32((x)->word[2], 30, 2)
#define STE_S2VMID(x)      extract32((x)->word[4], 0 , 16)
#define STE_S2T0SZ(x)      extract32((x)->word[5], 0 , 6)
#define STE_S2SL0(x)       extract32((x)->word[5], 6 , 2)
#define STE_S2TG(x)        extract32((x)->word[5], 14, 2)
#define STE_S2PS(x)        extract32((x)->word[5], 16, 3)
#define STE_S2AA64(x)      extract32((x)->word[5], 19, 1)
#define STE_S2HD(x)        extract32((x)->word[5], 24, 1)
#define STE_S2HA(x)        extract32((x)->word[5], 25, 1)
#define STE_S2S(x)         extract32((x)->word[5], 26, 1)
#define STE_CTXPTR(x)                                           \
    ({                                                          \
        unsigned long addr;                                     \
        addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32;  \
        addr |= (uint64_t)((x)->word[0] & 0xffffffc0);          \
        addr;                                                   \
    })

#define STE_S2TTB(x)                                            \
    ({                                                          \
        unsigned long addr;                                     \
        addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32;  \
        addr |= (uint64_t)((x)->word[6] & 0xfffffff0);          \
        addr;                                                   \
    })

static inline int oas2bits(int oas_field)
{
    switch (oas_field) {
    case 0:
        return 32;
    case 1:
        return 36;
    case 2:
        return 40;
    case 3:
        return 42;
    case 4:
        return 44;
    case 5:
        return 48;
    }
    return -1;
}

static inline int pa_range(STE *ste)
{
    int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);

    if (!STE_S2AA64(ste)) {
        return 40;
    }

    return oas2bits(oas_field);
}

#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)

/* CD fields */

#define CD_VALID(x)   extract32((x)->word[0], 31, 1)
#define CD_ASID(x)    extract32((x)->word[1], 16, 16)
#define CD_TTB(x, sel)                                      \
    ({                                                      \
        uint64_t hi, lo;                                    \
        hi = extract32((x)->word[(sel) * 2 + 3], 0, 19);    \
        hi <<= 32;                                          \
        lo = (x)->word[(sel) * 2 + 2] & ~0xfULL;            \
        hi | lo;                                            \
    })
#define CD_HAD(x, sel)   extract32((x)->word[(sel) * 2 + 2], 1, 1)

#define CD_TSZ(x, sel)   extract32((x)->word[0], (16 * (sel)) + 0, 6)
#define CD_TG(x, sel)    extract32((x)->word[0], (16 * (sel)) + 6, 2)
#define CD_EPD(x, sel)   extract32((x)->word[0], (16 * (sel)) + 14, 1)
#define CD_ENDI(x)       extract32((x)->word[0], 15, 1)
#define CD_IPS(x)        extract32((x)->word[1], 0 , 3)
#define CD_TBI(x)        extract32((x)->word[1], 6 , 2)
#define CD_HD(x)         extract32((x)->word[1], 10 , 1)
#define CD_HA(x)         extract32((x)->word[1], 11 , 1)
#define CD_S(x)          extract32((x)->word[1], 12, 1)
#define CD_R(x)          extract32((x)->word[1], 13, 1)
#define CD_A(x)          extract32((x)->word[1], 14, 1)
#define CD_AARCH64(x)    extract32((x)->word[1], 9 , 1)

/**
 * tg2granule - Decodes the CD translation granule size field according
 * to the ttbr in use
 * @bits: TG0/1 fields
 * @ttbr: ttbr index in use
 */
static inline int tg2granule(int bits, int ttbr)
{
    switch (bits) {
    case 0:
        return ttbr ? 0  : 12;
    case 1:
        return ttbr ? 14 : 16;
    case 2:
        return ttbr ? 12 : 14;
    case 3:
        return ttbr ? 16 :  0;
    default:
        return 0;
    }
}

static inline uint64_t l1std_l2ptr(STEDesc *desc)
{
    uint64_t hi, lo;

    hi = desc->word[1];
    lo = desc->word[0] & ~0x1fULL;
    return hi << 32 | lo;
}

#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))

#endif
Commit	Line	Data
10a83cb9 PM	1	/*
	2	* ARM SMMUv3 support - Internal API
	3	*
	4	* Copyright (C) 2014-2016 Broadcom Corporation
	5	* Copyright (c) 2017 Red Hat, Inc.
	6	* Written by Prem Mallappa, Eric Auger
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along
	18	* with this program; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
58ea30f5 MA	21	#ifndef HW_ARM_SMMUV3_INTERNAL_H
58ea30f5 MA	22	#define HW_ARM_SMMUV3_INTERNAL_H
10a83cb9 PM	23
	24	#include "hw/arm/smmu-common.h"
	25
9122bea9 JH	26	typedef enum SMMUTranslationStatus {
	27	SMMU_TRANS_DISABLE,
	28	SMMU_TRANS_ABORT,
	29	SMMU_TRANS_BYPASS,
	30	SMMU_TRANS_ERROR,
	31	SMMU_TRANS_SUCCESS,
	32	} SMMUTranslationStatus;
	33
10a83cb9 PM	34	/* MMIO Registers */
	35
	36	REG32(IDR0, 0x0)
	37	FIELD(IDR0, S1P, 1 , 1)
	38	FIELD(IDR0, TTF, 2 , 2)
	39	FIELD(IDR0, COHACC, 4 , 1)
	40	FIELD(IDR0, ASID16, 12, 1)
	41	FIELD(IDR0, TTENDIAN, 21, 2)
	42	FIELD(IDR0, STALL_MODEL, 24, 2)
	43	FIELD(IDR0, TERM_MODEL, 26, 1)
	44	FIELD(IDR0, STLEVEL, 27, 2)
	45
	46	REG32(IDR1, 0x4)
	47	FIELD(IDR1, SIDSIZE, 0 , 6)
	48	FIELD(IDR1, EVENTQS, 16, 5)
	49	FIELD(IDR1, CMDQS, 21, 5)
	50
	51	#define SMMU_IDR1_SIDSIZE 16
	52	#define SMMU_CMDQS 19
	53	#define SMMU_EVENTQS 19
	54
	55	REG32(IDR2, 0x8)
	56	REG32(IDR3, 0xc)
e7c3b9d9	57	FIELD(IDR3, HAD, 2, 1);
de206dfd	58	FIELD(IDR3, RIL, 10, 1);
10a83cb9 PM	59	REG32(IDR4, 0x10)
	60	REG32(IDR5, 0x14)
	61	FIELD(IDR5, OAS, 0, 3);
	62	FIELD(IDR5, GRAN4K, 4, 1);
	63	FIELD(IDR5, GRAN16K, 5, 1);
	64	FIELD(IDR5, GRAN64K, 6, 1);
	65
	66	#define SMMU_IDR5_OAS 4
	67
f0ec277c	68	REG32(IIDR, 0x18)
5888f0ad	69	REG32(AIDR, 0x1c)
10a83cb9 PM	70	REG32(CR0, 0x20)
	71	FIELD(CR0, SMMU_ENABLE, 0, 1)
	72	FIELD(CR0, EVENTQEN, 2, 1)
	73	FIELD(CR0, CMDQEN, 3, 1)
	74
fae4be38 EA	75	#define SMMU_CR0_RESERVED 0xFFFFFC20
fae4be38 EA	76
10a83cb9 PM	77	REG32(CR0ACK, 0x24)
	78	REG32(CR1, 0x28)
	79	REG32(CR2, 0x2c)
	80	REG32(STATUSR, 0x40)
	81	REG32(IRQ_CTRL, 0x50)
	82	FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
	83	FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
	84	FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1)
	85
	86	REG32(IRQ_CTRL_ACK, 0x54)
	87	REG32(GERROR, 0x60)
	88	FIELD(GERROR, CMDQ_ERR, 0, 1)
	89	FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1)
	90	FIELD(GERROR, PRIQ_ABT_ERR, 3, 1)
	91	FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1)
	92	FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
	93	FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1)
	94	FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
	95	FIELD(GERROR, MSI_SFM_ERR, 8, 1)
	96
	97	REG32(GERRORN, 0x64)
	98
	99	#define A_GERROR_IRQ_CFG0 0x68 /* 64b */
	100	REG32(GERROR_IRQ_CFG1, 0x70)
	101	REG32(GERROR_IRQ_CFG2, 0x74)
	102
	103	#define A_STRTAB_BASE 0x80 /* 64b */
	104
3293b9f5	105	#define SMMU_BASE_ADDR_MASK 0xfffffffffffc0
10a83cb9 PM	106
	107	REG32(STRTAB_BASE_CFG, 0x88)
	108	FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
	109	FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5)
	110	FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
	111
	112	#define A_CMDQ_BASE 0x90 /* 64b */
	113	REG32(CMDQ_PROD, 0x98)
	114	REG32(CMDQ_CONS, 0x9c)
	115	FIELD(CMDQ_CONS, ERR, 24, 7)
	116
	117	#define A_EVENTQ_BASE 0xa0 /* 64b */
	118	REG32(EVENTQ_PROD, 0xa8)
	119	REG32(EVENTQ_CONS, 0xac)
	120
	121	#define A_EVENTQ_IRQ_CFG0 0xb0 /* 64b */
	122	REG32(EVENTQ_IRQ_CFG1, 0xb8)
	123	REG32(EVENTQ_IRQ_CFG2, 0xbc)
	124
	125	#define A_IDREGS 0xfd0
	126
	127	static inline int smmu_enabled(SMMUv3State *s)
	128	{
	129	return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
	130	}
	131
	132	/* Command Queue Entry */
	133	typedef struct Cmd {
	134	uint32_t word[4];
	135	} Cmd;
	136
	137	/* Event Queue Entry */
	138	typedef struct Evt {
	139	uint32_t word[8];
	140	} Evt;
	141
	142	static inline uint32_t smmuv3_idreg(int regoffset)
	143	{
	144	/*
	145	* Return the value of the Primecell/Corelink ID registers at the
	146	* specified offset from the first ID register.
	147	* These value indicate an ARM implementation of MMU600 p1
	148	*/
	149	static const uint8_t smmuv3_ids[] = {
	150	0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
	151	};
	152	return smmuv3_ids[regoffset / 4];
	153	}
	154
6a736033 EA	155	static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
	156	{
	157	return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
	158	}
	159
	160	static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
	161	{
	162	return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
	163	}
	164
dadd1a08 EA	165	/* Queue Handling */
	166
	167	#define Q_BASE(q) ((q)->base & SMMU_BASE_ADDR_MASK)
	168	#define WRAP_MASK(q) (1 << (q)->log2size)
	169	#define INDEX_MASK(q) (((1 << (q)->log2size)) - 1)
	170	#define WRAP_INDEX_MASK(q) ((1 << ((q)->log2size + 1)) - 1)
	171
	172	#define Q_CONS(q) ((q)->cons & INDEX_MASK(q))
	173	#define Q_PROD(q) ((q)->prod & INDEX_MASK(q))
	174
	175	#define Q_CONS_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_CONS(q))
	176	#define Q_PROD_ENTRY(q) (Q_BASE(q) + (q)->entry_size * Q_PROD(q))
	177
	178	#define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size)
	179	#define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size)
	180
	181	static inline bool smmuv3_q_full(SMMUQueue *q)
	182	{
	183	return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) == WRAP_MASK(q);
	184	}
	185
	186	static inline bool smmuv3_q_empty(SMMUQueue *q)
	187	{
	188	return (q->cons & WRAP_INDEX_MASK(q)) == (q->prod & WRAP_INDEX_MASK(q));
	189	}
	190
	191	static inline void queue_prod_incr(SMMUQueue *q)
	192	{
	193	q->prod = (q->prod + 1) & WRAP_INDEX_MASK(q);
	194	}
	195
	196	static inline void queue_cons_incr(SMMUQueue *q)
	197	{
	198	/*
	199	* We have to use deposit for the CONS registers to preserve
	200	* the ERR field in the high bits.
	201	*/
	202	q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1);
	203	}
	204
	205	static inline bool smmuv3_cmdq_enabled(SMMUv3State *s)
	206	{
	207	return FIELD_EX32(s->cr[0], CR0, CMDQEN);
	208	}
	209
	210	static inline bool smmuv3_eventq_enabled(SMMUv3State *s)
	211	{
	212	return FIELD_EX32(s->cr[0], CR0, EVENTQEN);
	213	}
	214
	215	static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type)
	216	{
	217	s->cmdq.cons = FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type);
	218	}
	219
dadd1a08 EA	220	/* Commands */
	221
	222	typedef enum SMMUCommandType {
	223	SMMU_CMD_NONE = 0x00,
	224	SMMU_CMD_PREFETCH_CONFIG ,
	225	SMMU_CMD_PREFETCH_ADDR,
	226	SMMU_CMD_CFGI_STE,
	227	SMMU_CMD_CFGI_STE_RANGE,
	228	SMMU_CMD_CFGI_CD,
	229	SMMU_CMD_CFGI_CD_ALL,
	230	SMMU_CMD_CFGI_ALL,
	231	SMMU_CMD_TLBI_NH_ALL = 0x10,
	232	SMMU_CMD_TLBI_NH_ASID,
	233	SMMU_CMD_TLBI_NH_VA,
	234	SMMU_CMD_TLBI_NH_VAA,
	235	SMMU_CMD_TLBI_EL3_ALL = 0x18,
	236	SMMU_CMD_TLBI_EL3_VA = 0x1a,
	237	SMMU_CMD_TLBI_EL2_ALL = 0x20,
	238	SMMU_CMD_TLBI_EL2_ASID,
	239	SMMU_CMD_TLBI_EL2_VA,
	240	SMMU_CMD_TLBI_EL2_VAA,
	241	SMMU_CMD_TLBI_S12_VMALL = 0x28,
	242	SMMU_CMD_TLBI_S2_IPA = 0x2a,
	243	SMMU_CMD_TLBI_NSNH_ALL = 0x30,
	244	SMMU_CMD_ATC_INV = 0x40,
	245	SMMU_CMD_PRI_RESP,
	246	SMMU_CMD_RESUME = 0x44,
	247	SMMU_CMD_STALL_TERM,
	248	SMMU_CMD_SYNC,
	249	} SMMUCommandType;
	250
	251	static const char *cmd_stringify[] = {
	252	[SMMU_CMD_PREFETCH_CONFIG] = "SMMU_CMD_PREFETCH_CONFIG",
	253	[SMMU_CMD_PREFETCH_ADDR] = "SMMU_CMD_PREFETCH_ADDR",
	254	[SMMU_CMD_CFGI_STE] = "SMMU_CMD_CFGI_STE",
	255	[SMMU_CMD_CFGI_STE_RANGE] = "SMMU_CMD_CFGI_STE_RANGE",
	256	[SMMU_CMD_CFGI_CD] = "SMMU_CMD_CFGI_CD",
	257	[SMMU_CMD_CFGI_CD_ALL] = "SMMU_CMD_CFGI_CD_ALL",
	258	[SMMU_CMD_CFGI_ALL] = "SMMU_CMD_CFGI_ALL",
	259	[SMMU_CMD_TLBI_NH_ALL] = "SMMU_CMD_TLBI_NH_ALL",
	260	[SMMU_CMD_TLBI_NH_ASID] = "SMMU_CMD_TLBI_NH_ASID",
	261	[SMMU_CMD_TLBI_NH_VA] = "SMMU_CMD_TLBI_NH_VA",
	262	[SMMU_CMD_TLBI_NH_VAA] = "SMMU_CMD_TLBI_NH_VAA",
	263	[SMMU_CMD_TLBI_EL3_ALL] = "SMMU_CMD_TLBI_EL3_ALL",
	264	[SMMU_CMD_TLBI_EL3_VA] = "SMMU_CMD_TLBI_EL3_VA",
	265	[SMMU_CMD_TLBI_EL2_ALL] = "SMMU_CMD_TLBI_EL2_ALL",
	266	[SMMU_CMD_TLBI_EL2_ASID] = "SMMU_CMD_TLBI_EL2_ASID",
	267	[SMMU_CMD_TLBI_EL2_VA] = "SMMU_CMD_TLBI_EL2_VA",
	268	[SMMU_CMD_TLBI_EL2_VAA] = "SMMU_CMD_TLBI_EL2_VAA",
	269	[SMMU_CMD_TLBI_S12_VMALL] = "SMMU_CMD_TLBI_S12_VMALL",
	270	[SMMU_CMD_TLBI_S2_IPA] = "SMMU_CMD_TLBI_S2_IPA",
	271	[SMMU_CMD_TLBI_NSNH_ALL] = "SMMU_CMD_TLBI_NSNH_ALL",
	272	[SMMU_CMD_ATC_INV] = "SMMU_CMD_ATC_INV",
	273	[SMMU_CMD_PRI_RESP] = "SMMU_CMD_PRI_RESP",
	274	[SMMU_CMD_RESUME] = "SMMU_CMD_RESUME",
	275	[SMMU_CMD_STALL_TERM] = "SMMU_CMD_STALL_TERM",
	276	[SMMU_CMD_SYNC] = "SMMU_CMD_SYNC",
	277	};
	278
	279	static inline const char *smmu_cmd_string(SMMUCommandType type)
	280	{
	281	if (type > SMMU_CMD_NONE && type < ARRAY_SIZE(cmd_stringify)) {
	282	return cmd_stringify[type] ? cmd_stringify[type] : "UNKNOWN";
	283	} else {
284	return "INVALID";
285	}
286	}
287
288	/* CMDQ fields */
289
290	typedef enum {
291	SMMU_CERROR_NONE = 0,
292	SMMU_CERROR_ILL,
293	SMMU_CERROR_ABT,
294	SMMU_CERROR_ATC_INV_SYNC,
295	} SMMUCmdError;
296
297	enum { /* Command completion notification */
298	CMD_SYNC_SIG_NONE,
299	CMD_SYNC_SIG_IRQ,
300	CMD_SYNC_SIG_SEV,
301	};
302
303	#define CMD_TYPE(x) extract32((x)->word[0], 0 , 8)
d5291561 EA	304	#define CMD_NUM(x) extract32((x)->word[0], 12 , 5)
d5291561 EA	305	#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5)
dadd1a08 EA	306	#define CMD_SSEC(x) extract32((x)->word[0], 10, 1)
	307	#define CMD_SSV(x) extract32((x)->word[0], 11, 1)
	308	#define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1)
	309	#define CMD_RESUME_AB(x) extract32((x)->word[0], 13, 1)
	310	#define CMD_SYNC_CS(x) extract32((x)->word[0], 12, 2)
	311	#define CMD_SSID(x) extract32((x)->word[0], 12, 20)
	312	#define CMD_SID(x) ((x)->word[1])
	313	#define CMD_VMID(x) extract32((x)->word[1], 0 , 16)
	314	#define CMD_ASID(x) extract32((x)->word[1], 16, 16)
	315	#define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16)
	316	#define CMD_RESP(x) extract32((x)->word[2], 11, 2)
	317	#define CMD_LEAF(x) extract32((x)->word[2], 0 , 1)
d5291561 EA	318	#define CMD_TTL(x) extract32((x)->word[2], 8 , 2)
d5291561 EA	319	#define CMD_TG(x) extract32((x)->word[2], 10, 2)
dadd1a08 EA	320	#define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5)
	321	#define CMD_ADDR(x) ({ \
	322	uint64_t high = (uint64_t)(x)->word[3]; \
	323	uint64_t low = extract32((x)->word[2], 12, 20); \
	324	uint64_t addr = high << 32 \| (low << 12); \
	325	addr; \
	326	})
	327
fae4be38	328	#define SMMU_FEATURE_2LVL_STE (1 << 0)
dadd1a08	329
bb981004 EA	330	/* Events */
	331
	332	typedef enum SMMUEventType {
9122bea9	333	SMMU_EVT_NONE = 0x00,
bb981004 EA	334	SMMU_EVT_F_UUT ,
	335	SMMU_EVT_C_BAD_STREAMID ,
	336	SMMU_EVT_F_STE_FETCH ,
	337	SMMU_EVT_C_BAD_STE ,
	338	SMMU_EVT_F_BAD_ATS_TREQ ,
	339	SMMU_EVT_F_STREAM_DISABLED ,
	340	SMMU_EVT_F_TRANS_FORBIDDEN ,
	341	SMMU_EVT_C_BAD_SUBSTREAMID ,
	342	SMMU_EVT_F_CD_FETCH ,
	343	SMMU_EVT_C_BAD_CD ,
	344	SMMU_EVT_F_WALK_EABT ,
	345	SMMU_EVT_F_TRANSLATION = 0x10,
	346	SMMU_EVT_F_ADDR_SIZE ,
	347	SMMU_EVT_F_ACCESS ,
	348	SMMU_EVT_F_PERMISSION ,
	349	SMMU_EVT_F_TLB_CONFLICT = 0x20,
	350	SMMU_EVT_F_CFG_CONFLICT ,
	351	SMMU_EVT_E_PAGE_REQ = 0x24,
	352	} SMMUEventType;
	353
	354	static const char *event_stringify[] = {
9122bea9	355	[SMMU_EVT_NONE] = "no recorded event",
bb981004 EA	356	[SMMU_EVT_F_UUT] = "SMMU_EVT_F_UUT",
	357	[SMMU_EVT_C_BAD_STREAMID] = "SMMU_EVT_C_BAD_STREAMID",
	358	[SMMU_EVT_F_STE_FETCH] = "SMMU_EVT_F_STE_FETCH",
	359	[SMMU_EVT_C_BAD_STE] = "SMMU_EVT_C_BAD_STE",
	360	[SMMU_EVT_F_BAD_ATS_TREQ] = "SMMU_EVT_F_BAD_ATS_TREQ",
	361	[SMMU_EVT_F_STREAM_DISABLED] = "SMMU_EVT_F_STREAM_DISABLED",
	362	[SMMU_EVT_F_TRANS_FORBIDDEN] = "SMMU_EVT_F_TRANS_FORBIDDEN",
	363	[SMMU_EVT_C_BAD_SUBSTREAMID] = "SMMU_EVT_C_BAD_SUBSTREAMID",
	364	[SMMU_EVT_F_CD_FETCH] = "SMMU_EVT_F_CD_FETCH",
	365	[SMMU_EVT_C_BAD_CD] = "SMMU_EVT_C_BAD_CD",
	366	[SMMU_EVT_F_WALK_EABT] = "SMMU_EVT_F_WALK_EABT",
	367	[SMMU_EVT_F_TRANSLATION] = "SMMU_EVT_F_TRANSLATION",
	368	[SMMU_EVT_F_ADDR_SIZE] = "SMMU_EVT_F_ADDR_SIZE",
	369	[SMMU_EVT_F_ACCESS] = "SMMU_EVT_F_ACCESS",
	370	[SMMU_EVT_F_PERMISSION] = "SMMU_EVT_F_PERMISSION",
	371	[SMMU_EVT_F_TLB_CONFLICT] = "SMMU_EVT_F_TLB_CONFLICT",
	372	[SMMU_EVT_F_CFG_CONFLICT] = "SMMU_EVT_F_CFG_CONFLICT",
	373	[SMMU_EVT_E_PAGE_REQ] = "SMMU_EVT_E_PAGE_REQ",
	374	};
	375
	376	static inline const char *smmu_event_string(SMMUEventType type)
	377	{
	378	if (type < ARRAY_SIZE(event_stringify)) {
	379	return event_stringify[type] ? event_stringify[type] : "UNKNOWN";
	380	} else {
	381	return "INVALID";
	382	}
	383	}
	384
	385	/* Encode an event record */
	386	typedef struct SMMUEventInfo {
	387	SMMUEventType type;
	388	uint32_t sid;
	389	bool recorded;
3499ec08	390	bool inval_ste_allowed;
bb981004 EA	391	union {
	392	struct {
	393	uint32_t ssid;
	394	bool ssv;
	395	dma_addr_t addr;
	396	bool rnw;
	397	bool pnu;
	398	bool ind;
	399	} f_uut;
	400	struct SSIDInfo {
	401	uint32_t ssid;
	402	bool ssv;
	403	} c_bad_streamid;
	404	struct SSIDAddrInfo {
	405	uint32_t ssid;
	406	bool ssv;
	407	dma_addr_t addr;
	408	} f_ste_fetch;
	409	struct SSIDInfo c_bad_ste;
	410	struct {
	411	dma_addr_t addr;
	412	bool rnw;
	413	} f_transl_forbidden;
	414	struct {
	415	uint32_t ssid;
	416	} c_bad_substream;
	417	struct SSIDAddrInfo f_cd_fetch;
	418	struct SSIDInfo c_bad_cd;
	419	struct FullInfo {
	420	bool stall;
	421	uint16_t stag;
	422	uint32_t ssid;
	423	bool ssv;
	424	bool s2;
	425	dma_addr_t addr;
	426	bool rnw;
	427	bool pnu;
	428	bool ind;
	429	uint8_t class;
	430	dma_addr_t addr2;
	431	} f_walk_eabt;
	432	struct FullInfo f_translation;
	433	struct FullInfo f_addr_size;
	434	struct FullInfo f_access;
	435	struct FullInfo f_permission;
	436	struct SSIDInfo f_cfg_conflict;
	437	/**
	438	* not supported yet:
	439	* F_BAD_ATS_TREQ
	440	* F_BAD_ATS_TREQ
	441	* F_TLB_CONFLICT
	442	* E_PAGE_REQUEST
	443	* IMPDEF_EVENTn
	444	*/
	445	} u;
	446	} SMMUEventInfo;
	447
	448	/* EVTQ fields */
	449
	450	#define EVT_Q_OVERFLOW (1 << 31)
	451
9f4d2a13 EA	452	#define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
	453	#define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
	454	#define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
	455	#define EVT_SET_SID(x, v) ((x)->word[1] = v)
	456	#define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
	457	#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
	458	#define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
	459	#define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
	460	#define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
	461	#define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
	462	#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
bb981004 EA	463	#define EVT_SET_ADDR(x, addr) \
	464	do { \
	465	(x)->word[5] = (uint32_t)(addr >> 32); \
	466	(x)->word[4] = (uint32_t)(addr & 0xffffffff); \
	467	} while (0)
	468	#define EVT_SET_ADDR2(x, addr) \
	469	do { \
a7f65ceb SV	470	(x)->word[7] = (uint32_t)(addr >> 32); \
a7f65ceb SV	471	(x)->word[6] = (uint32_t)(addr & 0xffffffff); \
bb981004 EA	472	} while (0)
	473
	474	void smmuv3_record_event(SMMUv3State s, SMMUEventInfo event);
	475
9bde7f06 EA	476	/* Configuration Data */
	477
	478	/* STE Level 1 Descriptor */
	479	typedef struct STEDesc {
	480	uint32_t word[2];
	481	} STEDesc;
	482
	483	/* CD Level 1 Descriptor */
	484	typedef struct CDDesc {
	485	uint32_t word[2];
	486	} CDDesc;
	487
	488	/* Stream Table Entry(STE) */
	489	typedef struct STE {
	490	uint32_t word[16];
	491	} STE;
	492
	493	/* Context Descriptor(CD) */
	494	typedef struct CD {
	495	uint32_t word[16];
	496	} CD;
	497
	498	/* STE fields */
	499
	500	#define STE_VALID(x) extract32((x)->word[0], 0, 1)
	501
	502	#define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
	503	#define STE_CFG_S1_ENABLED(config) (config & 0x1)
	504	#define STE_CFG_S2_ENABLED(config) (config & 0x2)
	505	#define STE_CFG_ABORT(config) (!(config & 0x4))
	506	#define STE_CFG_BYPASS(config) (config == 0x4)
	507
	508	#define STE_S1FMT(x) extract32((x)->word[0], 4 , 2)
	509	#define STE_S1CDMAX(x) extract32((x)->word[1], 27, 5)
	510	#define STE_S1STALLD(x) extract32((x)->word[2], 27, 1)
	511	#define STE_EATS(x) extract32((x)->word[2], 28, 2)
	512	#define STE_STRW(x) extract32((x)->word[2], 30, 2)
	513	#define STE_S2VMID(x) extract32((x)->word[4], 0 , 16)
	514	#define STE_S2T0SZ(x) extract32((x)->word[5], 0 , 6)
	515	#define STE_S2SL0(x) extract32((x)->word[5], 6 , 2)
	516	#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
	517	#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
	518	#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
	519	#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
	520	#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
	521	#define STE_S2S(x) extract32((x)->word[5], 26, 1)
	522	#define STE_CTXPTR(x) \
	523	({ \
	524	unsigned long addr; \
	525	addr = (uint64_t)extract32((x)->word[1], 0, 16) << 32; \
	526	addr \|= (uint64_t)((x)->word[0] & 0xffffffc0); \
	527	addr; \
	528	})
	529
	530	#define STE_S2TTB(x) \
	531	({ \
	532	unsigned long addr; \
	533	addr = (uint64_t)extract32((x)->word[7], 0, 16) << 32; \
	534	addr \|= (uint64_t)((x)->word[6] & 0xfffffff0); \
	535	addr; \
	536	})
	537
	538	static inline int oas2bits(int oas_field)
	539	{
540	switch (oas_field) {
541	case 0:
542	return 32;
543	case 1:
544	return 36;
545	case 2:
546	return 40;
547	case 3:
548	return 42;
549	case 4:
550	return 44;
551	case 5:
552	return 48;
553	}
554	return -1;
555	}
556
557	static inline int pa_range(STE *ste)
558	{
559	int oas_field = MIN(STE_S2PS(ste), SMMU_IDR5_OAS);
560
561	if (!STE_S2AA64(ste)) {
562	return 40;
563	}
564
565	return oas2bits(oas_field);
566	}
567
568	#define MAX_PA(ste) ((1 << pa_range(ste)) - 1)
569
570	/* CD fields */
571
1b41847a	572	#define CD_VALID(x) extract32((x)->word[0], 31, 1)
9bde7f06 EA	573	#define CD_ASID(x) extract32((x)->word[1], 16, 16)
	574	#define CD_TTB(x, sel) \
	575	({ \
	576	uint64_t hi, lo; \
	577	hi = extract32((x)->word[(sel) * 2 + 3], 0, 19); \
	578	hi <<= 32; \
	579	lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \
	580	hi \| lo; \
	581	})
e7c3b9d9	582	#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1)
9bde7f06 EA	583
	584	#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
	585	#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
	586	#define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1)
	587	#define CD_ENDI(x) extract32((x)->word[0], 15, 1)
	588	#define CD_IPS(x) extract32((x)->word[1], 0 , 3)
	589	#define CD_TBI(x) extract32((x)->word[1], 6 , 2)
	590	#define CD_HD(x) extract32((x)->word[1], 10 , 1)
	591	#define CD_HA(x) extract32((x)->word[1], 11 , 1)
	592	#define CD_S(x) extract32((x)->word[1], 12, 1)
	593	#define CD_R(x) extract32((x)->word[1], 13, 1)
	594	#define CD_A(x) extract32((x)->word[1], 14, 1)
	595	#define CD_AARCH64(x) extract32((x)->word[1], 9 , 1)
	596
9bde7f06 EA	597	/**
	598	* tg2granule - Decodes the CD translation granule size field according
	599	* to the ttbr in use
	600	* @bits: TG0/1 fields
	601	* @ttbr: ttbr index in use
	602	*/
	603	static inline int tg2granule(int bits, int ttbr)
	604	{
	605	switch (bits) {
	606	case 0:
	607	return ttbr ? 0 : 12;
	608	case 1:
	609	return ttbr ? 14 : 16;
	610	case 2:
	611	return ttbr ? 12 : 14;
	612	case 3:
	613	return ttbr ? 16 : 0;
	614	default:
	615	return 0;
	616	}
	617	}
	618
	619	static inline uint64_t l1std_l2ptr(STEDesc *desc)
	620	{
	621	uint64_t hi, lo;
	622
	623	hi = desc->word[1];
	624	lo = desc->word[0] & ~0x1fULL;
	625	return hi << 32 \| lo;
	626	}
	627
d9aad887	628	#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
9bde7f06	629
10a83cb9	630	#endif