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10a83cb9 PM |
1 | /* |
2 | * Copyright (C) 2014-2016 Broadcom Corporation | |
3 | * Copyright (c) 2017 Red Hat, Inc. | |
4 | * Written by Prem Mallappa, Eric Auger | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
744a790e | 20 | #include "qemu/bitops.h" |
64552b6b | 21 | #include "hw/irq.h" |
10a83cb9 | 22 | #include "hw/sysbus.h" |
d6454270 | 23 | #include "migration/vmstate.h" |
10a83cb9 PM |
24 | #include "hw/qdev-core.h" |
25 | #include "hw/pci/pci.h" | |
26 | #include "exec/address-spaces.h" | |
9122bea9 | 27 | #include "cpu.h" |
10a83cb9 PM |
28 | #include "trace.h" |
29 | #include "qemu/log.h" | |
30 | #include "qemu/error-report.h" | |
31 | #include "qapi/error.h" | |
32 | ||
33 | #include "hw/arm/smmuv3.h" | |
34 | #include "smmuv3-internal.h" | |
35 | ||
6a736033 EA |
36 | /** |
37 | * smmuv3_trigger_irq - pulse @irq if enabled and update | |
38 | * GERROR register in case of GERROR interrupt | |
39 | * | |
40 | * @irq: irq type | |
41 | * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR) | |
42 | */ | |
fae4be38 EA |
43 | static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, |
44 | uint32_t gerror_mask) | |
6a736033 EA |
45 | { |
46 | ||
47 | bool pulse = false; | |
48 | ||
49 | switch (irq) { | |
50 | case SMMU_IRQ_EVTQ: | |
51 | pulse = smmuv3_eventq_irq_enabled(s); | |
52 | break; | |
53 | case SMMU_IRQ_PRIQ: | |
54 | qemu_log_mask(LOG_UNIMP, "PRI not yet supported\n"); | |
55 | break; | |
56 | case SMMU_IRQ_CMD_SYNC: | |
57 | pulse = true; | |
58 | break; | |
59 | case SMMU_IRQ_GERROR: | |
60 | { | |
61 | uint32_t pending = s->gerror ^ s->gerrorn; | |
62 | uint32_t new_gerrors = ~pending & gerror_mask; | |
63 | ||
64 | if (!new_gerrors) { | |
65 | /* only toggle non pending errors */ | |
66 | return; | |
67 | } | |
68 | s->gerror ^= new_gerrors; | |
69 | trace_smmuv3_write_gerror(new_gerrors, s->gerror); | |
70 | ||
71 | pulse = smmuv3_gerror_irq_enabled(s); | |
72 | break; | |
73 | } | |
74 | } | |
75 | if (pulse) { | |
76 | trace_smmuv3_trigger_irq(irq); | |
77 | qemu_irq_pulse(s->irq[irq]); | |
78 | } | |
79 | } | |
80 | ||
fae4be38 | 81 | static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) |
6a736033 EA |
82 | { |
83 | uint32_t pending = s->gerror ^ s->gerrorn; | |
84 | uint32_t toggled = s->gerrorn ^ new_gerrorn; | |
85 | ||
86 | if (toggled & ~pending) { | |
87 | qemu_log_mask(LOG_GUEST_ERROR, | |
88 | "guest toggles non pending errors = 0x%x\n", | |
89 | toggled & ~pending); | |
90 | } | |
91 | ||
92 | /* | |
93 | * We do not raise any error in case guest toggles bits corresponding | |
94 | * to not active IRQs (CONSTRAINED UNPREDICTABLE) | |
95 | */ | |
96 | s->gerrorn = new_gerrorn; | |
97 | ||
98 | trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn); | |
99 | } | |
100 | ||
dadd1a08 EA |
101 | static inline MemTxResult queue_read(SMMUQueue *q, void *data) |
102 | { | |
103 | dma_addr_t addr = Q_CONS_ENTRY(q); | |
104 | ||
105 | return dma_memory_read(&address_space_memory, addr, data, q->entry_size); | |
106 | } | |
107 | ||
108 | static MemTxResult queue_write(SMMUQueue *q, void *data) | |
109 | { | |
110 | dma_addr_t addr = Q_PROD_ENTRY(q); | |
111 | MemTxResult ret; | |
112 | ||
113 | ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size); | |
114 | if (ret != MEMTX_OK) { | |
115 | return ret; | |
116 | } | |
117 | ||
118 | queue_prod_incr(q); | |
119 | return MEMTX_OK; | |
120 | } | |
121 | ||
bb981004 | 122 | static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt) |
dadd1a08 EA |
123 | { |
124 | SMMUQueue *q = &s->eventq; | |
bb981004 | 125 | MemTxResult r; |
dadd1a08 EA |
126 | |
127 | if (!smmuv3_eventq_enabled(s)) { | |
bb981004 | 128 | return MEMTX_ERROR; |
dadd1a08 EA |
129 | } |
130 | ||
131 | if (smmuv3_q_full(q)) { | |
bb981004 | 132 | return MEMTX_ERROR; |
dadd1a08 EA |
133 | } |
134 | ||
bb981004 EA |
135 | r = queue_write(q, evt); |
136 | if (r != MEMTX_OK) { | |
137 | return r; | |
138 | } | |
dadd1a08 | 139 | |
9f4d2a13 | 140 | if (!smmuv3_q_empty(q)) { |
dadd1a08 EA |
141 | smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0); |
142 | } | |
bb981004 EA |
143 | return MEMTX_OK; |
144 | } | |
145 | ||
146 | void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) | |
147 | { | |
24af32e0 | 148 | Evt evt = {}; |
bb981004 EA |
149 | MemTxResult r; |
150 | ||
151 | if (!smmuv3_eventq_enabled(s)) { | |
152 | return; | |
153 | } | |
154 | ||
155 | EVT_SET_TYPE(&evt, info->type); | |
156 | EVT_SET_SID(&evt, info->sid); | |
157 | ||
158 | switch (info->type) { | |
9122bea9 | 159 | case SMMU_EVT_NONE: |
bb981004 EA |
160 | return; |
161 | case SMMU_EVT_F_UUT: | |
162 | EVT_SET_SSID(&evt, info->u.f_uut.ssid); | |
163 | EVT_SET_SSV(&evt, info->u.f_uut.ssv); | |
164 | EVT_SET_ADDR(&evt, info->u.f_uut.addr); | |
165 | EVT_SET_RNW(&evt, info->u.f_uut.rnw); | |
166 | EVT_SET_PNU(&evt, info->u.f_uut.pnu); | |
167 | EVT_SET_IND(&evt, info->u.f_uut.ind); | |
168 | break; | |
169 | case SMMU_EVT_C_BAD_STREAMID: | |
170 | EVT_SET_SSID(&evt, info->u.c_bad_streamid.ssid); | |
171 | EVT_SET_SSV(&evt, info->u.c_bad_streamid.ssv); | |
172 | break; | |
173 | case SMMU_EVT_F_STE_FETCH: | |
174 | EVT_SET_SSID(&evt, info->u.f_ste_fetch.ssid); | |
175 | EVT_SET_SSV(&evt, info->u.f_ste_fetch.ssv); | |
b255cafb | 176 | EVT_SET_ADDR2(&evt, info->u.f_ste_fetch.addr); |
bb981004 EA |
177 | break; |
178 | case SMMU_EVT_C_BAD_STE: | |
179 | EVT_SET_SSID(&evt, info->u.c_bad_ste.ssid); | |
180 | EVT_SET_SSV(&evt, info->u.c_bad_ste.ssv); | |
181 | break; | |
182 | case SMMU_EVT_F_STREAM_DISABLED: | |
183 | break; | |
184 | case SMMU_EVT_F_TRANS_FORBIDDEN: | |
185 | EVT_SET_ADDR(&evt, info->u.f_transl_forbidden.addr); | |
186 | EVT_SET_RNW(&evt, info->u.f_transl_forbidden.rnw); | |
187 | break; | |
188 | case SMMU_EVT_C_BAD_SUBSTREAMID: | |
189 | EVT_SET_SSID(&evt, info->u.c_bad_substream.ssid); | |
190 | break; | |
191 | case SMMU_EVT_F_CD_FETCH: | |
192 | EVT_SET_SSID(&evt, info->u.f_cd_fetch.ssid); | |
193 | EVT_SET_SSV(&evt, info->u.f_cd_fetch.ssv); | |
194 | EVT_SET_ADDR(&evt, info->u.f_cd_fetch.addr); | |
195 | break; | |
196 | case SMMU_EVT_C_BAD_CD: | |
197 | EVT_SET_SSID(&evt, info->u.c_bad_cd.ssid); | |
198 | EVT_SET_SSV(&evt, info->u.c_bad_cd.ssv); | |
199 | break; | |
200 | case SMMU_EVT_F_WALK_EABT: | |
201 | case SMMU_EVT_F_TRANSLATION: | |
202 | case SMMU_EVT_F_ADDR_SIZE: | |
203 | case SMMU_EVT_F_ACCESS: | |
204 | case SMMU_EVT_F_PERMISSION: | |
205 | EVT_SET_STALL(&evt, info->u.f_walk_eabt.stall); | |
206 | EVT_SET_STAG(&evt, info->u.f_walk_eabt.stag); | |
207 | EVT_SET_SSID(&evt, info->u.f_walk_eabt.ssid); | |
208 | EVT_SET_SSV(&evt, info->u.f_walk_eabt.ssv); | |
209 | EVT_SET_S2(&evt, info->u.f_walk_eabt.s2); | |
210 | EVT_SET_ADDR(&evt, info->u.f_walk_eabt.addr); | |
211 | EVT_SET_RNW(&evt, info->u.f_walk_eabt.rnw); | |
212 | EVT_SET_PNU(&evt, info->u.f_walk_eabt.pnu); | |
213 | EVT_SET_IND(&evt, info->u.f_walk_eabt.ind); | |
214 | EVT_SET_CLASS(&evt, info->u.f_walk_eabt.class); | |
215 | EVT_SET_ADDR2(&evt, info->u.f_walk_eabt.addr2); | |
216 | break; | |
217 | case SMMU_EVT_F_CFG_CONFLICT: | |
218 | EVT_SET_SSID(&evt, info->u.f_cfg_conflict.ssid); | |
219 | EVT_SET_SSV(&evt, info->u.f_cfg_conflict.ssv); | |
220 | break; | |
221 | /* rest is not implemented */ | |
222 | case SMMU_EVT_F_BAD_ATS_TREQ: | |
223 | case SMMU_EVT_F_TLB_CONFLICT: | |
224 | case SMMU_EVT_E_PAGE_REQ: | |
225 | default: | |
226 | g_assert_not_reached(); | |
227 | } | |
228 | ||
229 | trace_smmuv3_record_event(smmu_event_string(info->type), info->sid); | |
230 | r = smmuv3_write_eventq(s, &evt); | |
231 | if (r != MEMTX_OK) { | |
232 | smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_EVENTQ_ABT_ERR_MASK); | |
233 | } | |
234 | info->recorded = true; | |
dadd1a08 EA |
235 | } |
236 | ||
10a83cb9 PM |
237 | static void smmuv3_init_regs(SMMUv3State *s) |
238 | { | |
239 | /** | |
240 | * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, | |
241 | * multi-level stream table | |
242 | */ | |
243 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */ | |
244 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */ | |
245 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ | |
246 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ | |
247 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */ | |
248 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */ | |
249 | /* terminated transaction will always be aborted/error returned */ | |
250 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1); | |
251 | /* 2-level stream table supported */ | |
252 | s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1); | |
253 | ||
254 | s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE); | |
255 | s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); | |
256 | s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); | |
257 | ||
de206dfd | 258 | s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); |
e7c3b9d9 EA |
259 | s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); |
260 | ||
10a83cb9 PM |
261 | /* 4K and 64K granule support */ |
262 | s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); | |
263 | s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); | |
264 | s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */ | |
265 | ||
266 | s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); | |
267 | s->cmdq.prod = 0; | |
268 | s->cmdq.cons = 0; | |
269 | s->cmdq.entry_size = sizeof(struct Cmd); | |
270 | s->eventq.base = deposit64(s->eventq.base, 0, 5, SMMU_EVENTQS); | |
271 | s->eventq.prod = 0; | |
272 | s->eventq.cons = 0; | |
273 | s->eventq.entry_size = sizeof(struct Evt); | |
274 | ||
275 | s->features = 0; | |
276 | s->sid_split = 0; | |
e7c3b9d9 | 277 | s->aidr = 0x1; |
10a83cb9 PM |
278 | } |
279 | ||
9bde7f06 EA |
280 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, |
281 | SMMUEventInfo *event) | |
282 | { | |
283 | int ret; | |
284 | ||
285 | trace_smmuv3_get_ste(addr); | |
286 | /* TODO: guarantee 64-bit single-copy atomicity */ | |
18610bfd | 287 | ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); |
9bde7f06 EA |
288 | if (ret != MEMTX_OK) { |
289 | qemu_log_mask(LOG_GUEST_ERROR, | |
290 | "Cannot fetch pte at address=0x%"PRIx64"\n", addr); | |
291 | event->type = SMMU_EVT_F_STE_FETCH; | |
292 | event->u.f_ste_fetch.addr = addr; | |
293 | return -EINVAL; | |
294 | } | |
295 | return 0; | |
296 | ||
297 | } | |
298 | ||
299 | /* @ssid > 0 not supported yet */ | |
300 | static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, | |
301 | CD *buf, SMMUEventInfo *event) | |
302 | { | |
303 | dma_addr_t addr = STE_CTXPTR(ste); | |
304 | int ret; | |
305 | ||
306 | trace_smmuv3_get_cd(addr); | |
307 | /* TODO: guarantee 64-bit single-copy atomicity */ | |
18610bfd | 308 | ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); |
9bde7f06 EA |
309 | if (ret != MEMTX_OK) { |
310 | qemu_log_mask(LOG_GUEST_ERROR, | |
311 | "Cannot fetch pte at address=0x%"PRIx64"\n", addr); | |
312 | event->type = SMMU_EVT_F_CD_FETCH; | |
313 | event->u.f_ste_fetch.addr = addr; | |
314 | return -EINVAL; | |
315 | } | |
316 | return 0; | |
317 | } | |
318 | ||
9122bea9 | 319 | /* Returns < 0 in case of invalid STE, 0 otherwise */ |
9bde7f06 EA |
320 | static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, |
321 | STE *ste, SMMUEventInfo *event) | |
322 | { | |
323 | uint32_t config; | |
9bde7f06 EA |
324 | |
325 | if (!STE_VALID(ste)) { | |
3499ec08 EA |
326 | if (!event->inval_ste_allowed) { |
327 | qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n"); | |
328 | } | |
9bde7f06 EA |
329 | goto bad_ste; |
330 | } | |
331 | ||
332 | config = STE_CONFIG(ste); | |
333 | ||
334 | if (STE_CFG_ABORT(config)) { | |
9122bea9 JH |
335 | cfg->aborted = true; |
336 | return 0; | |
9bde7f06 EA |
337 | } |
338 | ||
339 | if (STE_CFG_BYPASS(config)) { | |
340 | cfg->bypassed = true; | |
9122bea9 | 341 | return 0; |
9bde7f06 EA |
342 | } |
343 | ||
344 | if (STE_CFG_S2_ENABLED(config)) { | |
345 | qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); | |
346 | goto bad_ste; | |
347 | } | |
348 | ||
349 | if (STE_S1CDMAX(ste) != 0) { | |
350 | qemu_log_mask(LOG_UNIMP, | |
351 | "SMMUv3 does not support multiple context descriptors yet\n"); | |
352 | goto bad_ste; | |
353 | } | |
354 | ||
355 | if (STE_S1STALLD(ste)) { | |
356 | qemu_log_mask(LOG_UNIMP, | |
357 | "SMMUv3 S1 stalling fault model not allowed yet\n"); | |
358 | goto bad_ste; | |
359 | } | |
360 | return 0; | |
361 | ||
362 | bad_ste: | |
363 | event->type = SMMU_EVT_C_BAD_STE; | |
364 | return -EINVAL; | |
365 | } | |
366 | ||
367 | /** | |
368 | * smmu_find_ste - Return the stream table entry associated | |
369 | * to the sid | |
370 | * | |
371 | * @s: smmuv3 handle | |
372 | * @sid: stream ID | |
373 | * @ste: returned stream table entry | |
374 | * @event: handle to an event info | |
375 | * | |
376 | * Supports linear and 2-level stream table | |
377 | * Return 0 on success, -EINVAL otherwise | |
378 | */ | |
379 | static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, | |
380 | SMMUEventInfo *event) | |
381 | { | |
41678c33 | 382 | dma_addr_t addr, strtab_base; |
05ff2fb8 | 383 | uint32_t log2size; |
41678c33 | 384 | int strtab_size_shift; |
9bde7f06 EA |
385 | int ret; |
386 | ||
387 | trace_smmuv3_find_ste(sid, s->features, s->sid_split); | |
05ff2fb8 SV |
388 | log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); |
389 | /* | |
390 | * Check SID range against both guest-configured and implementation limits | |
391 | */ | |
392 | if (sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { | |
9bde7f06 EA |
393 | event->type = SMMU_EVT_C_BAD_STREAMID; |
394 | return -EINVAL; | |
395 | } | |
396 | if (s->features & SMMU_FEATURE_2LVL_STE) { | |
397 | int l1_ste_offset, l2_ste_offset, max_l2_ste, span; | |
41678c33 | 398 | dma_addr_t l1ptr, l2ptr; |
9bde7f06 EA |
399 | STEDesc l1std; |
400 | ||
41678c33 SV |
401 | /* |
402 | * Align strtab base address to table size. For this purpose, assume it | |
403 | * is not bounded by SMMU_IDR1_SIDSIZE. | |
404 | */ | |
405 | strtab_size_shift = MAX(5, (int)log2size - s->sid_split - 1 + 3); | |
406 | strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & | |
407 | ~MAKE_64BIT_MASK(0, strtab_size_shift); | |
9bde7f06 EA |
408 | l1_ste_offset = sid >> s->sid_split; |
409 | l2_ste_offset = sid & ((1 << s->sid_split) - 1); | |
410 | l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); | |
411 | /* TODO: guarantee 64-bit single-copy atomicity */ | |
18610bfd PMD |
412 | ret = dma_memory_read(&address_space_memory, l1ptr, &l1std, |
413 | sizeof(l1std)); | |
9bde7f06 EA |
414 | if (ret != MEMTX_OK) { |
415 | qemu_log_mask(LOG_GUEST_ERROR, | |
416 | "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); | |
417 | event->type = SMMU_EVT_F_STE_FETCH; | |
418 | event->u.f_ste_fetch.addr = l1ptr; | |
419 | return -EINVAL; | |
420 | } | |
421 | ||
422 | span = L1STD_SPAN(&l1std); | |
423 | ||
424 | if (!span) { | |
425 | /* l2ptr is not valid */ | |
3499ec08 EA |
426 | if (!event->inval_ste_allowed) { |
427 | qemu_log_mask(LOG_GUEST_ERROR, | |
428 | "invalid sid=%d (L1STD span=0)\n", sid); | |
429 | } | |
9bde7f06 EA |
430 | event->type = SMMU_EVT_C_BAD_STREAMID; |
431 | return -EINVAL; | |
432 | } | |
433 | max_l2_ste = (1 << span) - 1; | |
434 | l2ptr = l1std_l2ptr(&l1std); | |
435 | trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset, | |
436 | l2ptr, l2_ste_offset, max_l2_ste); | |
437 | if (l2_ste_offset > max_l2_ste) { | |
438 | qemu_log_mask(LOG_GUEST_ERROR, | |
439 | "l2_ste_offset=%d > max_l2_ste=%d\n", | |
440 | l2_ste_offset, max_l2_ste); | |
441 | event->type = SMMU_EVT_C_BAD_STE; | |
442 | return -EINVAL; | |
443 | } | |
444 | addr = l2ptr + l2_ste_offset * sizeof(*ste); | |
445 | } else { | |
41678c33 SV |
446 | strtab_size_shift = log2size + 5; |
447 | strtab_base = s->strtab_base & SMMU_BASE_ADDR_MASK & | |
448 | ~MAKE_64BIT_MASK(0, strtab_size_shift); | |
449 | addr = strtab_base + sid * sizeof(*ste); | |
9bde7f06 EA |
450 | } |
451 | ||
452 | if (smmu_get_ste(s, addr, ste, event)) { | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) | |
460 | { | |
461 | int ret = -EINVAL; | |
462 | int i; | |
463 | ||
464 | if (!CD_VALID(cd) || !CD_AARCH64(cd)) { | |
465 | goto bad_cd; | |
466 | } | |
467 | if (!CD_A(cd)) { | |
468 | goto bad_cd; /* SMMU_IDR0.TERM_MODEL == 1 */ | |
469 | } | |
470 | if (CD_S(cd)) { | |
471 | goto bad_cd; /* !STE_SECURE && SMMU_IDR0.STALL_MODEL == 1 */ | |
472 | } | |
473 | if (CD_HA(cd) || CD_HD(cd)) { | |
474 | goto bad_cd; /* HTTU = 0 */ | |
475 | } | |
476 | ||
477 | /* we support only those at the moment */ | |
478 | cfg->aa64 = true; | |
479 | cfg->stage = 1; | |
480 | ||
481 | cfg->oas = oas2bits(CD_IPS(cd)); | |
482 | cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); | |
483 | cfg->tbi = CD_TBI(cd); | |
484 | cfg->asid = CD_ASID(cd); | |
485 | ||
486 | trace_smmuv3_decode_cd(cfg->oas); | |
487 | ||
488 | /* decode data dependent on TT */ | |
489 | for (i = 0; i <= 1; i++) { | |
490 | int tg, tsz; | |
491 | SMMUTransTableInfo *tt = &cfg->tt[i]; | |
492 | ||
493 | cfg->tt[i].disabled = CD_EPD(cd, i); | |
494 | if (cfg->tt[i].disabled) { | |
495 | continue; | |
496 | } | |
497 | ||
498 | tsz = CD_TSZ(cd, i); | |
499 | if (tsz < 16 || tsz > 39) { | |
500 | goto bad_cd; | |
501 | } | |
502 | ||
503 | tg = CD_TG(cd, i); | |
504 | tt->granule_sz = tg2granule(tg, i); | |
505 | if ((tt->granule_sz != 12 && tt->granule_sz != 16) || CD_ENDI(cd)) { | |
506 | goto bad_cd; | |
507 | } | |
508 | ||
509 | tt->tsz = tsz; | |
510 | tt->ttb = CD_TTB(cd, i); | |
511 | if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) { | |
512 | goto bad_cd; | |
513 | } | |
e7c3b9d9 EA |
514 | tt->had = CD_HAD(cd, i); |
515 | trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had); | |
9bde7f06 EA |
516 | } |
517 | ||
518 | event->record_trans_faults = CD_R(cd); | |
519 | ||
520 | return 0; | |
521 | ||
522 | bad_cd: | |
523 | event->type = SMMU_EVT_C_BAD_CD; | |
524 | return ret; | |
525 | } | |
526 | ||
527 | /** | |
528 | * smmuv3_decode_config - Prepare the translation configuration | |
529 | * for the @mr iommu region | |
530 | * @mr: iommu memory region the translation config must be prepared for | |
531 | * @cfg: output translation configuration which is populated through | |
532 | * the different configuration decoding steps | |
533 | * @event: must be zero'ed by the caller | |
534 | * | |
9122bea9 | 535 | * return < 0 in case of config decoding error (@event is filled |
9bde7f06 EA |
536 | * accordingly). Return 0 otherwise. |
537 | */ | |
538 | static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, | |
539 | SMMUEventInfo *event) | |
540 | { | |
541 | SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); | |
542 | uint32_t sid = smmu_get_sid(sdev); | |
543 | SMMUv3State *s = sdev->smmu; | |
9122bea9 | 544 | int ret; |
9bde7f06 EA |
545 | STE ste; |
546 | CD cd; | |
547 | ||
9122bea9 JH |
548 | ret = smmu_find_ste(s, sid, &ste, event); |
549 | if (ret) { | |
9bde7f06 EA |
550 | return ret; |
551 | } | |
552 | ||
9122bea9 JH |
553 | ret = decode_ste(s, cfg, &ste, event); |
554 | if (ret) { | |
9bde7f06 EA |
555 | return ret; |
556 | } | |
557 | ||
9122bea9 JH |
558 | if (cfg->aborted || cfg->bypassed) { |
559 | return 0; | |
560 | } | |
561 | ||
562 | ret = smmu_get_cd(s, &ste, 0 /* ssid */, &cd, event); | |
563 | if (ret) { | |
9bde7f06 EA |
564 | return ret; |
565 | } | |
566 | ||
567 | return decode_cd(cfg, &cd, event); | |
568 | } | |
569 | ||
32cfd7f3 EA |
570 | /** |
571 | * smmuv3_get_config - Look up for a cached copy of configuration data for | |
572 | * @sdev and on cache miss performs a configuration structure decoding from | |
573 | * guest RAM. | |
574 | * | |
575 | * @sdev: SMMUDevice handle | |
576 | * @event: output event info | |
577 | * | |
578 | * The configuration cache contains data resulting from both STE and CD | |
579 | * decoding under the form of an SMMUTransCfg struct. The hash table is indexed | |
580 | * by the SMMUDevice handle. | |
581 | */ | |
582 | static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev, SMMUEventInfo *event) | |
583 | { | |
584 | SMMUv3State *s = sdev->smmu; | |
585 | SMMUState *bc = &s->smmu_state; | |
586 | SMMUTransCfg *cfg; | |
587 | ||
588 | cfg = g_hash_table_lookup(bc->configs, sdev); | |
589 | if (cfg) { | |
590 | sdev->cfg_cache_hits++; | |
591 | trace_smmuv3_config_cache_hit(smmu_get_sid(sdev), | |
592 | sdev->cfg_cache_hits, sdev->cfg_cache_misses, | |
593 | 100 * sdev->cfg_cache_hits / | |
594 | (sdev->cfg_cache_hits + sdev->cfg_cache_misses)); | |
595 | } else { | |
596 | sdev->cfg_cache_misses++; | |
597 | trace_smmuv3_config_cache_miss(smmu_get_sid(sdev), | |
598 | sdev->cfg_cache_hits, sdev->cfg_cache_misses, | |
599 | 100 * sdev->cfg_cache_hits / | |
600 | (sdev->cfg_cache_hits + sdev->cfg_cache_misses)); | |
601 | cfg = g_new0(SMMUTransCfg, 1); | |
602 | ||
603 | if (!smmuv3_decode_config(&sdev->iommu, cfg, event)) { | |
604 | g_hash_table_insert(bc->configs, sdev, cfg); | |
605 | } else { | |
606 | g_free(cfg); | |
607 | cfg = NULL; | |
608 | } | |
609 | } | |
610 | return cfg; | |
611 | } | |
612 | ||
613 | static void smmuv3_flush_config(SMMUDevice *sdev) | |
614 | { | |
615 | SMMUv3State *s = sdev->smmu; | |
616 | SMMUState *bc = &s->smmu_state; | |
617 | ||
618 | trace_smmuv3_config_cache_inv(smmu_get_sid(sdev)); | |
619 | g_hash_table_remove(bc->configs, sdev); | |
620 | } | |
621 | ||
9bde7f06 | 622 | static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, |
2c91bcf2 | 623 | IOMMUAccessFlags flag, int iommu_idx) |
9bde7f06 EA |
624 | { |
625 | SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); | |
626 | SMMUv3State *s = sdev->smmu; | |
627 | uint32_t sid = smmu_get_sid(sdev); | |
3499ec08 EA |
628 | SMMUEventInfo event = {.type = SMMU_EVT_NONE, |
629 | .sid = sid, | |
630 | .inval_ste_allowed = false}; | |
9bde7f06 | 631 | SMMUPTWEventInfo ptw_info = {}; |
9122bea9 | 632 | SMMUTranslationStatus status; |
cc27ed81 EA |
633 | SMMUState *bs = ARM_SMMU(s); |
634 | uint64_t page_mask, aligned_addr; | |
a7550158 | 635 | SMMUTLBEntry *cached_entry = NULL; |
cc27ed81 | 636 | SMMUTransTableInfo *tt; |
32cfd7f3 | 637 | SMMUTransCfg *cfg = NULL; |
9bde7f06 EA |
638 | IOMMUTLBEntry entry = { |
639 | .target_as = &address_space_memory, | |
640 | .iova = addr, | |
641 | .translated_addr = addr, | |
642 | .addr_mask = ~(hwaddr)0, | |
643 | .perm = IOMMU_NONE, | |
644 | }; | |
9bde7f06 | 645 | |
32cfd7f3 EA |
646 | qemu_mutex_lock(&s->mutex); |
647 | ||
9bde7f06 | 648 | if (!smmu_enabled(s)) { |
9122bea9 JH |
649 | status = SMMU_TRANS_DISABLE; |
650 | goto epilogue; | |
9bde7f06 EA |
651 | } |
652 | ||
32cfd7f3 EA |
653 | cfg = smmuv3_get_config(sdev, &event); |
654 | if (!cfg) { | |
9122bea9 JH |
655 | status = SMMU_TRANS_ERROR; |
656 | goto epilogue; | |
9bde7f06 EA |
657 | } |
658 | ||
32cfd7f3 | 659 | if (cfg->aborted) { |
9122bea9 JH |
660 | status = SMMU_TRANS_ABORT; |
661 | goto epilogue; | |
9bde7f06 EA |
662 | } |
663 | ||
32cfd7f3 | 664 | if (cfg->bypassed) { |
9122bea9 JH |
665 | status = SMMU_TRANS_BYPASS; |
666 | goto epilogue; | |
667 | } | |
668 | ||
cc27ed81 EA |
669 | tt = select_tt(cfg, addr); |
670 | if (!tt) { | |
671 | if (event.record_trans_faults) { | |
672 | event.type = SMMU_EVT_F_TRANSLATION; | |
673 | event.u.f_translation.addr = addr; | |
674 | event.u.f_translation.rnw = flag & 0x1; | |
675 | } | |
676 | status = SMMU_TRANS_ERROR; | |
677 | goto epilogue; | |
678 | } | |
679 | ||
680 | page_mask = (1ULL << (tt->granule_sz)) - 1; | |
681 | aligned_addr = addr & ~page_mask; | |
682 | ||
9e54dee7 | 683 | cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); |
cc27ed81 | 684 | if (cached_entry) { |
a7550158 | 685 | if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { |
cc27ed81 EA |
686 | status = SMMU_TRANS_ERROR; |
687 | if (event.record_trans_faults) { | |
688 | event.type = SMMU_EVT_F_PERMISSION; | |
689 | event.u.f_permission.addr = addr; | |
690 | event.u.f_permission.rnw = flag & 0x1; | |
691 | } | |
692 | } else { | |
693 | status = SMMU_TRANS_SUCCESS; | |
694 | } | |
695 | goto epilogue; | |
696 | } | |
697 | ||
a7550158 | 698 | cached_entry = g_new0(SMMUTLBEntry, 1); |
cc27ed81 EA |
699 | |
700 | if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { | |
701 | g_free(cached_entry); | |
9bde7f06 EA |
702 | switch (ptw_info.type) { |
703 | case SMMU_PTW_ERR_WALK_EABT: | |
704 | event.type = SMMU_EVT_F_WALK_EABT; | |
705 | event.u.f_walk_eabt.addr = addr; | |
706 | event.u.f_walk_eabt.rnw = flag & 0x1; | |
707 | event.u.f_walk_eabt.class = 0x1; | |
708 | event.u.f_walk_eabt.addr2 = ptw_info.addr; | |
709 | break; | |
710 | case SMMU_PTW_ERR_TRANSLATION: | |
711 | if (event.record_trans_faults) { | |
712 | event.type = SMMU_EVT_F_TRANSLATION; | |
713 | event.u.f_translation.addr = addr; | |
714 | event.u.f_translation.rnw = flag & 0x1; | |
715 | } | |
716 | break; | |
717 | case SMMU_PTW_ERR_ADDR_SIZE: | |
718 | if (event.record_trans_faults) { | |
719 | event.type = SMMU_EVT_F_ADDR_SIZE; | |
720 | event.u.f_addr_size.addr = addr; | |
721 | event.u.f_addr_size.rnw = flag & 0x1; | |
722 | } | |
723 | break; | |
724 | case SMMU_PTW_ERR_ACCESS: | |
725 | if (event.record_trans_faults) { | |
726 | event.type = SMMU_EVT_F_ACCESS; | |
727 | event.u.f_access.addr = addr; | |
728 | event.u.f_access.rnw = flag & 0x1; | |
729 | } | |
730 | break; | |
731 | case SMMU_PTW_ERR_PERMISSION: | |
732 | if (event.record_trans_faults) { | |
733 | event.type = SMMU_EVT_F_PERMISSION; | |
734 | event.u.f_permission.addr = addr; | |
735 | event.u.f_permission.rnw = flag & 0x1; | |
736 | } | |
737 | break; | |
738 | default: | |
739 | g_assert_not_reached(); | |
740 | } | |
9122bea9 JH |
741 | status = SMMU_TRANS_ERROR; |
742 | } else { | |
6808bca9 | 743 | smmu_iotlb_insert(bs, cfg, cached_entry); |
9122bea9 | 744 | status = SMMU_TRANS_SUCCESS; |
9bde7f06 | 745 | } |
9122bea9 JH |
746 | |
747 | epilogue: | |
32cfd7f3 | 748 | qemu_mutex_unlock(&s->mutex); |
9122bea9 JH |
749 | switch (status) { |
750 | case SMMU_TRANS_SUCCESS: | |
751 | entry.perm = flag; | |
a7550158 | 752 | entry.translated_addr = cached_entry->entry.translated_addr + |
9e54dee7 | 753 | (addr & cached_entry->entry.addr_mask); |
a7550158 | 754 | entry.addr_mask = cached_entry->entry.addr_mask; |
9122bea9 JH |
755 | trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr, |
756 | entry.translated_addr, entry.perm); | |
757 | break; | |
758 | case SMMU_TRANS_DISABLE: | |
759 | entry.perm = flag; | |
760 | entry.addr_mask = ~TARGET_PAGE_MASK; | |
761 | trace_smmuv3_translate_disable(mr->parent_obj.name, sid, addr, | |
762 | entry.perm); | |
763 | break; | |
764 | case SMMU_TRANS_BYPASS: | |
765 | entry.perm = flag; | |
766 | entry.addr_mask = ~TARGET_PAGE_MASK; | |
767 | trace_smmuv3_translate_bypass(mr->parent_obj.name, sid, addr, | |
768 | entry.perm); | |
769 | break; | |
770 | case SMMU_TRANS_ABORT: | |
771 | /* no event is recorded on abort */ | |
772 | trace_smmuv3_translate_abort(mr->parent_obj.name, sid, addr, | |
773 | entry.perm); | |
774 | break; | |
775 | case SMMU_TRANS_ERROR: | |
9bde7f06 | 776 | qemu_log_mask(LOG_GUEST_ERROR, |
9122bea9 JH |
777 | "%s translation failed for iova=0x%"PRIx64"(%s)\n", |
778 | mr->parent_obj.name, addr, smmu_event_string(event.type)); | |
9bde7f06 | 779 | smmuv3_record_event(s, &event); |
9122bea9 | 780 | break; |
9bde7f06 EA |
781 | } |
782 | ||
783 | return entry; | |
784 | } | |
785 | ||
832e4222 EA |
786 | /** |
787 | * smmuv3_notify_iova - call the notifier @n for a given | |
788 | * @asid and @iova tuple. | |
789 | * | |
790 | * @mr: IOMMU mr region handle | |
791 | * @n: notifier to be called | |
792 | * @asid: address space ID or negative value if we don't care | |
793 | * @iova: iova | |
d5291561 EA |
794 | * @tg: translation granule (if communicated through range invalidation) |
795 | * @num_pages: number of @granule sized pages (if tg != 0), otherwise 1 | |
832e4222 EA |
796 | */ |
797 | static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, | |
798 | IOMMUNotifier *n, | |
d5291561 EA |
799 | int asid, dma_addr_t iova, |
800 | uint8_t tg, uint64_t num_pages) | |
832e4222 EA |
801 | { |
802 | SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); | |
5039caf3 | 803 | IOMMUTLBEvent event; |
d5291561 | 804 | uint8_t granule = tg; |
832e4222 | 805 | |
d5291561 EA |
806 | if (!tg) { |
807 | SMMUEventInfo event = {.inval_ste_allowed = true}; | |
808 | SMMUTransCfg *cfg = smmuv3_get_config(sdev, &event); | |
809 | SMMUTransTableInfo *tt; | |
832e4222 | 810 | |
d5291561 EA |
811 | if (!cfg) { |
812 | return; | |
813 | } | |
832e4222 | 814 | |
d5291561 EA |
815 | if (asid >= 0 && cfg->asid != asid) { |
816 | return; | |
817 | } | |
818 | ||
819 | tt = select_tt(cfg, iova); | |
820 | if (!tt) { | |
821 | return; | |
822 | } | |
823 | granule = tt->granule_sz; | |
832e4222 EA |
824 | } |
825 | ||
5039caf3 EP |
826 | event.type = IOMMU_NOTIFIER_UNMAP; |
827 | event.entry.target_as = &address_space_memory; | |
828 | event.entry.iova = iova; | |
829 | event.entry.addr_mask = num_pages * (1 << granule) - 1; | |
830 | event.entry.perm = IOMMU_NONE; | |
832e4222 | 831 | |
5039caf3 | 832 | memory_region_notify_iommu_one(n, &event); |
832e4222 EA |
833 | } |
834 | ||
d5291561 EA |
835 | /* invalidate an asid/iova range tuple in all mr's */ |
836 | static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova, | |
837 | uint8_t tg, uint64_t num_pages) | |
832e4222 | 838 | { |
c6370441 | 839 | SMMUDevice *sdev; |
832e4222 | 840 | |
c6370441 EA |
841 | QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { |
842 | IOMMUMemoryRegion *mr = &sdev->iommu; | |
832e4222 EA |
843 | IOMMUNotifier *n; |
844 | ||
d5291561 EA |
845 | trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, |
846 | tg, num_pages); | |
832e4222 EA |
847 | |
848 | IOMMU_NOTIFIER_FOREACH(n, mr) { | |
d5291561 | 849 | smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); |
832e4222 EA |
850 | } |
851 | } | |
852 | } | |
853 | ||
c0f9ef70 EA |
854 | static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) |
855 | { | |
d5291561 | 856 | uint8_t scale = 0, num = 0, ttl = 0; |
c0f9ef70 EA |
857 | dma_addr_t addr = CMD_ADDR(cmd); |
858 | uint8_t type = CMD_TYPE(cmd); | |
859 | uint16_t vmid = CMD_VMID(cmd); | |
860 | bool leaf = CMD_LEAF(cmd); | |
d5291561 EA |
861 | uint8_t tg = CMD_TG(cmd); |
862 | hwaddr num_pages = 1; | |
c0f9ef70 EA |
863 | int asid = -1; |
864 | ||
d5291561 EA |
865 | if (tg) { |
866 | scale = CMD_SCALE(cmd); | |
867 | num = CMD_NUM(cmd); | |
868 | ttl = CMD_TTL(cmd); | |
744a790e | 869 | num_pages = (num + 1) * BIT_ULL(scale); |
d5291561 EA |
870 | } |
871 | ||
c0f9ef70 EA |
872 | if (type == SMMU_CMD_TLBI_NH_VA) { |
873 | asid = CMD_ASID(cmd); | |
874 | } | |
d5291561 EA |
875 | trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf); |
876 | smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); | |
877 | smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); | |
c0f9ef70 EA |
878 | } |
879 | ||
fae4be38 | 880 | static int smmuv3_cmdq_consume(SMMUv3State *s) |
dadd1a08 | 881 | { |
32cfd7f3 | 882 | SMMUState *bs = ARM_SMMU(s); |
dadd1a08 EA |
883 | SMMUCmdError cmd_error = SMMU_CERROR_NONE; |
884 | SMMUQueue *q = &s->cmdq; | |
885 | SMMUCommandType type = 0; | |
886 | ||
887 | if (!smmuv3_cmdq_enabled(s)) { | |
888 | return 0; | |
889 | } | |
890 | /* | |
891 | * some commands depend on register values, typically CR0. In case those | |
892 | * register values change while handling the command, spec says it | |
893 | * is UNPREDICTABLE whether the command is interpreted under the new | |
894 | * or old value. | |
895 | */ | |
896 | ||
897 | while (!smmuv3_q_empty(q)) { | |
898 | uint32_t pending = s->gerror ^ s->gerrorn; | |
899 | Cmd cmd; | |
900 | ||
901 | trace_smmuv3_cmdq_consume(Q_PROD(q), Q_CONS(q), | |
902 | Q_PROD_WRAP(q), Q_CONS_WRAP(q)); | |
903 | ||
904 | if (FIELD_EX32(pending, GERROR, CMDQ_ERR)) { | |
905 | break; | |
906 | } | |
907 | ||
908 | if (queue_read(q, &cmd) != MEMTX_OK) { | |
909 | cmd_error = SMMU_CERROR_ABT; | |
910 | break; | |
911 | } | |
912 | ||
913 | type = CMD_TYPE(&cmd); | |
914 | ||
915 | trace_smmuv3_cmdq_opcode(smmu_cmd_string(type)); | |
916 | ||
32cfd7f3 | 917 | qemu_mutex_lock(&s->mutex); |
dadd1a08 EA |
918 | switch (type) { |
919 | case SMMU_CMD_SYNC: | |
920 | if (CMD_SYNC_CS(&cmd) & CMD_SYNC_SIG_IRQ) { | |
921 | smmuv3_trigger_irq(s, SMMU_IRQ_CMD_SYNC, 0); | |
922 | } | |
923 | break; | |
924 | case SMMU_CMD_PREFETCH_CONFIG: | |
925 | case SMMU_CMD_PREFETCH_ADDR: | |
32cfd7f3 | 926 | break; |
dadd1a08 | 927 | case SMMU_CMD_CFGI_STE: |
32cfd7f3 EA |
928 | { |
929 | uint32_t sid = CMD_SID(&cmd); | |
930 | IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid); | |
931 | SMMUDevice *sdev; | |
932 | ||
933 | if (CMD_SSEC(&cmd)) { | |
934 | cmd_error = SMMU_CERROR_ILL; | |
935 | break; | |
936 | } | |
937 | ||
938 | if (!mr) { | |
939 | break; | |
940 | } | |
941 | ||
942 | trace_smmuv3_cmdq_cfgi_ste(sid); | |
943 | sdev = container_of(mr, SMMUDevice, iommu); | |
944 | smmuv3_flush_config(sdev); | |
945 | ||
946 | break; | |
947 | } | |
dadd1a08 | 948 | case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ |
32cfd7f3 EA |
949 | { |
950 | uint32_t start = CMD_SID(&cmd), end, i; | |
951 | uint8_t range = CMD_STE_RANGE(&cmd); | |
952 | ||
953 | if (CMD_SSEC(&cmd)) { | |
954 | cmd_error = SMMU_CERROR_ILL; | |
955 | break; | |
956 | } | |
957 | ||
958 | end = start + (1 << (range + 1)) - 1; | |
959 | trace_smmuv3_cmdq_cfgi_ste_range(start, end); | |
960 | ||
961 | for (i = start; i <= end; i++) { | |
962 | IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, i); | |
963 | SMMUDevice *sdev; | |
964 | ||
965 | if (!mr) { | |
966 | continue; | |
967 | } | |
968 | sdev = container_of(mr, SMMUDevice, iommu); | |
969 | smmuv3_flush_config(sdev); | |
970 | } | |
971 | break; | |
972 | } | |
dadd1a08 EA |
973 | case SMMU_CMD_CFGI_CD: |
974 | case SMMU_CMD_CFGI_CD_ALL: | |
32cfd7f3 EA |
975 | { |
976 | uint32_t sid = CMD_SID(&cmd); | |
977 | IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid); | |
978 | SMMUDevice *sdev; | |
979 | ||
980 | if (CMD_SSEC(&cmd)) { | |
981 | cmd_error = SMMU_CERROR_ILL; | |
982 | break; | |
983 | } | |
984 | ||
985 | if (!mr) { | |
986 | break; | |
987 | } | |
988 | ||
989 | trace_smmuv3_cmdq_cfgi_cd(sid); | |
990 | sdev = container_of(mr, SMMUDevice, iommu); | |
991 | smmuv3_flush_config(sdev); | |
992 | break; | |
993 | } | |
dadd1a08 | 994 | case SMMU_CMD_TLBI_NH_ASID: |
cc27ed81 EA |
995 | { |
996 | uint16_t asid = CMD_ASID(&cmd); | |
997 | ||
998 | trace_smmuv3_cmdq_tlbi_nh_asid(asid); | |
832e4222 | 999 | smmu_inv_notifiers_all(&s->smmu_state); |
cc27ed81 EA |
1000 | smmu_iotlb_inv_asid(bs, asid); |
1001 | break; | |
1002 | } | |
1003 | case SMMU_CMD_TLBI_NH_ALL: | |
1004 | case SMMU_CMD_TLBI_NSNH_ALL: | |
1005 | trace_smmuv3_cmdq_tlbi_nh(); | |
832e4222 | 1006 | smmu_inv_notifiers_all(&s->smmu_state); |
cc27ed81 EA |
1007 | smmu_iotlb_inv_all(bs); |
1008 | break; | |
dadd1a08 | 1009 | case SMMU_CMD_TLBI_NH_VAA: |
cc27ed81 | 1010 | case SMMU_CMD_TLBI_NH_VA: |
c0f9ef70 | 1011 | smmuv3_s1_range_inval(bs, &cmd); |
cc27ed81 | 1012 | break; |
dadd1a08 EA |
1013 | case SMMU_CMD_TLBI_EL3_ALL: |
1014 | case SMMU_CMD_TLBI_EL3_VA: | |
1015 | case SMMU_CMD_TLBI_EL2_ALL: | |
1016 | case SMMU_CMD_TLBI_EL2_ASID: | |
1017 | case SMMU_CMD_TLBI_EL2_VA: | |
1018 | case SMMU_CMD_TLBI_EL2_VAA: | |
1019 | case SMMU_CMD_TLBI_S12_VMALL: | |
1020 | case SMMU_CMD_TLBI_S2_IPA: | |
dadd1a08 EA |
1021 | case SMMU_CMD_ATC_INV: |
1022 | case SMMU_CMD_PRI_RESP: | |
1023 | case SMMU_CMD_RESUME: | |
1024 | case SMMU_CMD_STALL_TERM: | |
1025 | trace_smmuv3_unhandled_cmd(type); | |
1026 | break; | |
1027 | default: | |
1028 | cmd_error = SMMU_CERROR_ILL; | |
1029 | qemu_log_mask(LOG_GUEST_ERROR, | |
1030 | "Illegal command type: %d\n", CMD_TYPE(&cmd)); | |
1031 | break; | |
1032 | } | |
32cfd7f3 | 1033 | qemu_mutex_unlock(&s->mutex); |
dadd1a08 EA |
1034 | if (cmd_error) { |
1035 | break; | |
1036 | } | |
1037 | /* | |
1038 | * We only increment the cons index after the completion of | |
1039 | * the command. We do that because the SYNC returns immediately | |
1040 | * and does not check the completion of previous commands | |
1041 | */ | |
1042 | queue_cons_incr(q); | |
1043 | } | |
1044 | ||
1045 | if (cmd_error) { | |
1046 | trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error); | |
1047 | smmu_write_cmdq_err(s, cmd_error); | |
1048 | smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK); | |
1049 | } | |
1050 | ||
1051 | trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q), | |
1052 | Q_PROD_WRAP(q), Q_CONS_WRAP(q)); | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
fae4be38 EA |
1057 | static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset, |
1058 | uint64_t data, MemTxAttrs attrs) | |
1059 | { | |
1060 | switch (offset) { | |
1061 | case A_GERROR_IRQ_CFG0: | |
1062 | s->gerror_irq_cfg0 = data; | |
1063 | return MEMTX_OK; | |
1064 | case A_STRTAB_BASE: | |
1065 | s->strtab_base = data; | |
1066 | return MEMTX_OK; | |
1067 | case A_CMDQ_BASE: | |
1068 | s->cmdq.base = data; | |
1069 | s->cmdq.log2size = extract64(s->cmdq.base, 0, 5); | |
1070 | if (s->cmdq.log2size > SMMU_CMDQS) { | |
1071 | s->cmdq.log2size = SMMU_CMDQS; | |
1072 | } | |
1073 | return MEMTX_OK; | |
1074 | case A_EVENTQ_BASE: | |
1075 | s->eventq.base = data; | |
1076 | s->eventq.log2size = extract64(s->eventq.base, 0, 5); | |
1077 | if (s->eventq.log2size > SMMU_EVENTQS) { | |
1078 | s->eventq.log2size = SMMU_EVENTQS; | |
1079 | } | |
1080 | return MEMTX_OK; | |
1081 | case A_EVENTQ_IRQ_CFG0: | |
1082 | s->eventq_irq_cfg0 = data; | |
1083 | return MEMTX_OK; | |
1084 | default: | |
1085 | qemu_log_mask(LOG_UNIMP, | |
1086 | "%s Unexpected 64-bit access to 0x%"PRIx64" (WI)\n", | |
1087 | __func__, offset); | |
1088 | return MEMTX_OK; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | |
1093 | uint64_t data, MemTxAttrs attrs) | |
1094 | { | |
1095 | switch (offset) { | |
1096 | case A_CR0: | |
1097 | s->cr[0] = data; | |
1098 | s->cr0ack = data & ~SMMU_CR0_RESERVED; | |
1099 | /* in case the command queue has been enabled */ | |
1100 | smmuv3_cmdq_consume(s); | |
1101 | return MEMTX_OK; | |
1102 | case A_CR1: | |
1103 | s->cr[1] = data; | |
1104 | return MEMTX_OK; | |
1105 | case A_CR2: | |
1106 | s->cr[2] = data; | |
1107 | return MEMTX_OK; | |
1108 | case A_IRQ_CTRL: | |
1109 | s->irq_ctrl = data; | |
1110 | return MEMTX_OK; | |
1111 | case A_GERRORN: | |
1112 | smmuv3_write_gerrorn(s, data); | |
1113 | /* | |
1114 | * By acknowledging the CMDQ_ERR, SW may notify cmds can | |
1115 | * be processed again | |
1116 | */ | |
1117 | smmuv3_cmdq_consume(s); | |
1118 | return MEMTX_OK; | |
1119 | case A_GERROR_IRQ_CFG0: /* 64b */ | |
1120 | s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 0, 32, data); | |
1121 | return MEMTX_OK; | |
1122 | case A_GERROR_IRQ_CFG0 + 4: | |
1123 | s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 32, 32, data); | |
1124 | return MEMTX_OK; | |
1125 | case A_GERROR_IRQ_CFG1: | |
1126 | s->gerror_irq_cfg1 = data; | |
1127 | return MEMTX_OK; | |
1128 | case A_GERROR_IRQ_CFG2: | |
1129 | s->gerror_irq_cfg2 = data; | |
1130 | return MEMTX_OK; | |
1131 | case A_STRTAB_BASE: /* 64b */ | |
1132 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | |
1133 | return MEMTX_OK; | |
1134 | case A_STRTAB_BASE + 4: | |
1135 | s->strtab_base = deposit64(s->strtab_base, 32, 32, data); | |
1136 | return MEMTX_OK; | |
1137 | case A_STRTAB_BASE_CFG: | |
1138 | s->strtab_base_cfg = data; | |
1139 | if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) == 1) { | |
1140 | s->sid_split = FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); | |
1141 | s->features |= SMMU_FEATURE_2LVL_STE; | |
1142 | } | |
1143 | return MEMTX_OK; | |
1144 | case A_CMDQ_BASE: /* 64b */ | |
1145 | s->cmdq.base = deposit64(s->cmdq.base, 0, 32, data); | |
1146 | s->cmdq.log2size = extract64(s->cmdq.base, 0, 5); | |
1147 | if (s->cmdq.log2size > SMMU_CMDQS) { | |
1148 | s->cmdq.log2size = SMMU_CMDQS; | |
1149 | } | |
1150 | return MEMTX_OK; | |
1151 | case A_CMDQ_BASE + 4: /* 64b */ | |
1152 | s->cmdq.base = deposit64(s->cmdq.base, 32, 32, data); | |
1153 | return MEMTX_OK; | |
1154 | case A_CMDQ_PROD: | |
1155 | s->cmdq.prod = data; | |
1156 | smmuv3_cmdq_consume(s); | |
1157 | return MEMTX_OK; | |
1158 | case A_CMDQ_CONS: | |
1159 | s->cmdq.cons = data; | |
1160 | return MEMTX_OK; | |
1161 | case A_EVENTQ_BASE: /* 64b */ | |
1162 | s->eventq.base = deposit64(s->eventq.base, 0, 32, data); | |
1163 | s->eventq.log2size = extract64(s->eventq.base, 0, 5); | |
1164 | if (s->eventq.log2size > SMMU_EVENTQS) { | |
1165 | s->eventq.log2size = SMMU_EVENTQS; | |
1166 | } | |
1167 | return MEMTX_OK; | |
1168 | case A_EVENTQ_BASE + 4: | |
1169 | s->eventq.base = deposit64(s->eventq.base, 32, 32, data); | |
1170 | return MEMTX_OK; | |
1171 | case A_EVENTQ_PROD: | |
1172 | s->eventq.prod = data; | |
1173 | return MEMTX_OK; | |
1174 | case A_EVENTQ_CONS: | |
1175 | s->eventq.cons = data; | |
1176 | return MEMTX_OK; | |
1177 | case A_EVENTQ_IRQ_CFG0: /* 64b */ | |
1178 | s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 0, 32, data); | |
1179 | return MEMTX_OK; | |
1180 | case A_EVENTQ_IRQ_CFG0 + 4: | |
1181 | s->eventq_irq_cfg0 = deposit64(s->eventq_irq_cfg0, 32, 32, data); | |
1182 | return MEMTX_OK; | |
1183 | case A_EVENTQ_IRQ_CFG1: | |
1184 | s->eventq_irq_cfg1 = data; | |
1185 | return MEMTX_OK; | |
1186 | case A_EVENTQ_IRQ_CFG2: | |
1187 | s->eventq_irq_cfg2 = data; | |
1188 | return MEMTX_OK; | |
1189 | default: | |
1190 | qemu_log_mask(LOG_UNIMP, | |
1191 | "%s Unexpected 32-bit access to 0x%"PRIx64" (WI)\n", | |
1192 | __func__, offset); | |
1193 | return MEMTX_OK; | |
1194 | } | |
1195 | } | |
1196 | ||
10a83cb9 PM |
1197 | static MemTxResult smmu_write_mmio(void *opaque, hwaddr offset, uint64_t data, |
1198 | unsigned size, MemTxAttrs attrs) | |
1199 | { | |
fae4be38 EA |
1200 | SMMUState *sys = opaque; |
1201 | SMMUv3State *s = ARM_SMMUV3(sys); | |
1202 | MemTxResult r; | |
1203 | ||
1204 | /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */ | |
1205 | offset &= ~0x10000; | |
1206 | ||
1207 | switch (size) { | |
1208 | case 8: | |
1209 | r = smmu_writell(s, offset, data, attrs); | |
1210 | break; | |
1211 | case 4: | |
1212 | r = smmu_writel(s, offset, data, attrs); | |
1213 | break; | |
1214 | default: | |
1215 | r = MEMTX_ERROR; | |
1216 | break; | |
1217 | } | |
1218 | ||
1219 | trace_smmuv3_write_mmio(offset, data, size, r); | |
1220 | return r; | |
10a83cb9 PM |
1221 | } |
1222 | ||
1223 | static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset, | |
1224 | uint64_t *data, MemTxAttrs attrs) | |
1225 | { | |
1226 | switch (offset) { | |
1227 | case A_GERROR_IRQ_CFG0: | |
1228 | *data = s->gerror_irq_cfg0; | |
1229 | return MEMTX_OK; | |
1230 | case A_STRTAB_BASE: | |
1231 | *data = s->strtab_base; | |
1232 | return MEMTX_OK; | |
1233 | case A_CMDQ_BASE: | |
1234 | *data = s->cmdq.base; | |
1235 | return MEMTX_OK; | |
1236 | case A_EVENTQ_BASE: | |
1237 | *data = s->eventq.base; | |
1238 | return MEMTX_OK; | |
1239 | default: | |
1240 | *data = 0; | |
1241 | qemu_log_mask(LOG_UNIMP, | |
1242 | "%s Unexpected 64-bit access to 0x%"PRIx64" (RAZ)\n", | |
1243 | __func__, offset); | |
1244 | return MEMTX_OK; | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | |
1249 | uint64_t *data, MemTxAttrs attrs) | |
1250 | { | |
1251 | switch (offset) { | |
97fb318d | 1252 | case A_IDREGS ... A_IDREGS + 0x2f: |
10a83cb9 PM |
1253 | *data = smmuv3_idreg(offset - A_IDREGS); |
1254 | return MEMTX_OK; | |
1255 | case A_IDR0 ... A_IDR5: | |
1256 | *data = s->idr[(offset - A_IDR0) / 4]; | |
1257 | return MEMTX_OK; | |
1258 | case A_IIDR: | |
1259 | *data = s->iidr; | |
1260 | return MEMTX_OK; | |
5888f0ad EA |
1261 | case A_AIDR: |
1262 | *data = s->aidr; | |
1263 | return MEMTX_OK; | |
10a83cb9 PM |
1264 | case A_CR0: |
1265 | *data = s->cr[0]; | |
1266 | return MEMTX_OK; | |
1267 | case A_CR0ACK: | |
1268 | *data = s->cr0ack; | |
1269 | return MEMTX_OK; | |
1270 | case A_CR1: | |
1271 | *data = s->cr[1]; | |
1272 | return MEMTX_OK; | |
1273 | case A_CR2: | |
1274 | *data = s->cr[2]; | |
1275 | return MEMTX_OK; | |
1276 | case A_STATUSR: | |
1277 | *data = s->statusr; | |
1278 | return MEMTX_OK; | |
1279 | case A_IRQ_CTRL: | |
1280 | case A_IRQ_CTRL_ACK: | |
1281 | *data = s->irq_ctrl; | |
1282 | return MEMTX_OK; | |
1283 | case A_GERROR: | |
1284 | *data = s->gerror; | |
1285 | return MEMTX_OK; | |
1286 | case A_GERRORN: | |
1287 | *data = s->gerrorn; | |
1288 | return MEMTX_OK; | |
1289 | case A_GERROR_IRQ_CFG0: /* 64b */ | |
1290 | *data = extract64(s->gerror_irq_cfg0, 0, 32); | |
1291 | return MEMTX_OK; | |
1292 | case A_GERROR_IRQ_CFG0 + 4: | |
1293 | *data = extract64(s->gerror_irq_cfg0, 32, 32); | |
1294 | return MEMTX_OK; | |
1295 | case A_GERROR_IRQ_CFG1: | |
1296 | *data = s->gerror_irq_cfg1; | |
1297 | return MEMTX_OK; | |
1298 | case A_GERROR_IRQ_CFG2: | |
1299 | *data = s->gerror_irq_cfg2; | |
1300 | return MEMTX_OK; | |
1301 | case A_STRTAB_BASE: /* 64b */ | |
1302 | *data = extract64(s->strtab_base, 0, 32); | |
1303 | return MEMTX_OK; | |
1304 | case A_STRTAB_BASE + 4: /* 64b */ | |
1305 | *data = extract64(s->strtab_base, 32, 32); | |
1306 | return MEMTX_OK; | |
1307 | case A_STRTAB_BASE_CFG: | |
1308 | *data = s->strtab_base_cfg; | |
1309 | return MEMTX_OK; | |
1310 | case A_CMDQ_BASE: /* 64b */ | |
1311 | *data = extract64(s->cmdq.base, 0, 32); | |
1312 | return MEMTX_OK; | |
1313 | case A_CMDQ_BASE + 4: | |
1314 | *data = extract64(s->cmdq.base, 32, 32); | |
1315 | return MEMTX_OK; | |
1316 | case A_CMDQ_PROD: | |
1317 | *data = s->cmdq.prod; | |
1318 | return MEMTX_OK; | |
1319 | case A_CMDQ_CONS: | |
1320 | *data = s->cmdq.cons; | |
1321 | return MEMTX_OK; | |
1322 | case A_EVENTQ_BASE: /* 64b */ | |
1323 | *data = extract64(s->eventq.base, 0, 32); | |
1324 | return MEMTX_OK; | |
1325 | case A_EVENTQ_BASE + 4: /* 64b */ | |
1326 | *data = extract64(s->eventq.base, 32, 32); | |
1327 | return MEMTX_OK; | |
1328 | case A_EVENTQ_PROD: | |
1329 | *data = s->eventq.prod; | |
1330 | return MEMTX_OK; | |
1331 | case A_EVENTQ_CONS: | |
1332 | *data = s->eventq.cons; | |
1333 | return MEMTX_OK; | |
1334 | default: | |
1335 | *data = 0; | |
1336 | qemu_log_mask(LOG_UNIMP, | |
1337 | "%s unhandled 32-bit access at 0x%"PRIx64" (RAZ)\n", | |
1338 | __func__, offset); | |
1339 | return MEMTX_OK; | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | static MemTxResult smmu_read_mmio(void *opaque, hwaddr offset, uint64_t *data, | |
1344 | unsigned size, MemTxAttrs attrs) | |
1345 | { | |
1346 | SMMUState *sys = opaque; | |
1347 | SMMUv3State *s = ARM_SMMUV3(sys); | |
1348 | MemTxResult r; | |
1349 | ||
1350 | /* CONSTRAINED UNPREDICTABLE choice to have page0/1 be exact aliases */ | |
1351 | offset &= ~0x10000; | |
1352 | ||
1353 | switch (size) { | |
1354 | case 8: | |
1355 | r = smmu_readll(s, offset, data, attrs); | |
1356 | break; | |
1357 | case 4: | |
1358 | r = smmu_readl(s, offset, data, attrs); | |
1359 | break; | |
1360 | default: | |
1361 | r = MEMTX_ERROR; | |
1362 | break; | |
1363 | } | |
1364 | ||
1365 | trace_smmuv3_read_mmio(offset, *data, size, r); | |
1366 | return r; | |
1367 | } | |
1368 | ||
1369 | static const MemoryRegionOps smmu_mem_ops = { | |
1370 | .read_with_attrs = smmu_read_mmio, | |
1371 | .write_with_attrs = smmu_write_mmio, | |
1372 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1373 | .valid = { | |
1374 | .min_access_size = 4, | |
1375 | .max_access_size = 8, | |
1376 | }, | |
1377 | .impl = { | |
1378 | .min_access_size = 4, | |
1379 | .max_access_size = 8, | |
1380 | }, | |
1381 | }; | |
1382 | ||
1383 | static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) | |
1384 | { | |
1385 | int i; | |
1386 | ||
1387 | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { | |
1388 | sysbus_init_irq(dev, &s->irq[i]); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | static void smmu_reset(DeviceState *dev) | |
1393 | { | |
1394 | SMMUv3State *s = ARM_SMMUV3(dev); | |
1395 | SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); | |
1396 | ||
1397 | c->parent_reset(dev); | |
1398 | ||
1399 | smmuv3_init_regs(s); | |
1400 | } | |
1401 | ||
1402 | static void smmu_realize(DeviceState *d, Error **errp) | |
1403 | { | |
1404 | SMMUState *sys = ARM_SMMU(d); | |
1405 | SMMUv3State *s = ARM_SMMUV3(sys); | |
1406 | SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); | |
1407 | SysBusDevice *dev = SYS_BUS_DEVICE(d); | |
1408 | Error *local_err = NULL; | |
1409 | ||
1410 | c->parent_realize(d, &local_err); | |
1411 | if (local_err) { | |
1412 | error_propagate(errp, local_err); | |
1413 | return; | |
1414 | } | |
1415 | ||
32cfd7f3 EA |
1416 | qemu_mutex_init(&s->mutex); |
1417 | ||
10a83cb9 PM |
1418 | memory_region_init_io(&sys->iomem, OBJECT(s), |
1419 | &smmu_mem_ops, sys, TYPE_ARM_SMMUV3, 0x20000); | |
1420 | ||
1421 | sys->mrtypename = TYPE_SMMUV3_IOMMU_MEMORY_REGION; | |
1422 | ||
1423 | sysbus_init_mmio(dev, &sys->iomem); | |
1424 | ||
1425 | smmu_init_irq(s, dev); | |
1426 | } | |
1427 | ||
1428 | static const VMStateDescription vmstate_smmuv3_queue = { | |
1429 | .name = "smmuv3_queue", | |
1430 | .version_id = 1, | |
1431 | .minimum_version_id = 1, | |
1432 | .fields = (VMStateField[]) { | |
1433 | VMSTATE_UINT64(base, SMMUQueue), | |
1434 | VMSTATE_UINT32(prod, SMMUQueue), | |
1435 | VMSTATE_UINT32(cons, SMMUQueue), | |
1436 | VMSTATE_UINT8(log2size, SMMUQueue), | |
758b71f7 | 1437 | VMSTATE_END_OF_LIST(), |
10a83cb9 PM |
1438 | }, |
1439 | }; | |
1440 | ||
1441 | static const VMStateDescription vmstate_smmuv3 = { | |
1442 | .name = "smmuv3", | |
1443 | .version_id = 1, | |
1444 | .minimum_version_id = 1, | |
a55aab61 | 1445 | .priority = MIG_PRI_IOMMU, |
10a83cb9 PM |
1446 | .fields = (VMStateField[]) { |
1447 | VMSTATE_UINT32(features, SMMUv3State), | |
1448 | VMSTATE_UINT8(sid_size, SMMUv3State), | |
1449 | VMSTATE_UINT8(sid_split, SMMUv3State), | |
1450 | ||
1451 | VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3), | |
1452 | VMSTATE_UINT32(cr0ack, SMMUv3State), | |
1453 | VMSTATE_UINT32(statusr, SMMUv3State), | |
1454 | VMSTATE_UINT32(irq_ctrl, SMMUv3State), | |
1455 | VMSTATE_UINT32(gerror, SMMUv3State), | |
1456 | VMSTATE_UINT32(gerrorn, SMMUv3State), | |
1457 | VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State), | |
1458 | VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State), | |
1459 | VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State), | |
1460 | VMSTATE_UINT64(strtab_base, SMMUv3State), | |
1461 | VMSTATE_UINT32(strtab_base_cfg, SMMUv3State), | |
1462 | VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State), | |
1463 | VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State), | |
1464 | VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State), | |
1465 | ||
1466 | VMSTATE_STRUCT(cmdq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue), | |
1467 | VMSTATE_STRUCT(eventq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQueue), | |
1468 | ||
1469 | VMSTATE_END_OF_LIST(), | |
1470 | }, | |
1471 | }; | |
1472 | ||
1473 | static void smmuv3_instance_init(Object *obj) | |
1474 | { | |
1475 | /* Nothing much to do here as of now */ | |
1476 | } | |
1477 | ||
1478 | static void smmuv3_class_init(ObjectClass *klass, void *data) | |
1479 | { | |
1480 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1481 | SMMUv3Class *c = ARM_SMMUV3_CLASS(klass); | |
1482 | ||
1483 | dc->vmsd = &vmstate_smmuv3; | |
1484 | device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset); | |
1485 | c->parent_realize = dc->realize; | |
1486 | dc->realize = smmu_realize; | |
1487 | } | |
1488 | ||
549d4005 EA |
1489 | static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, |
1490 | IOMMUNotifierFlag old, | |
1491 | IOMMUNotifierFlag new, | |
1492 | Error **errp) | |
0d1ac82e | 1493 | { |
832e4222 EA |
1494 | SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); |
1495 | SMMUv3State *s3 = sdev->smmu; | |
1496 | SMMUState *s = &(s3->smmu_state); | |
832e4222 EA |
1497 | |
1498 | if (new & IOMMU_NOTIFIER_MAP) { | |
549d4005 EA |
1499 | error_setg(errp, |
1500 | "device %02x.%02x.%x requires iommu MAP notifier which is " | |
1501 | "not currently supported", pci_bus_num(sdev->bus), | |
1502 | PCI_SLOT(sdev->devfn), PCI_FUNC(sdev->devfn)); | |
1503 | return -EINVAL; | |
832e4222 EA |
1504 | } |
1505 | ||
0d1ac82e | 1506 | if (old == IOMMU_NOTIFIER_NONE) { |
832e4222 | 1507 | trace_smmuv3_notify_flag_add(iommu->parent_obj.name); |
c6370441 EA |
1508 | QLIST_INSERT_HEAD(&s->devices_with_notifiers, sdev, next); |
1509 | } else if (new == IOMMU_NOTIFIER_NONE) { | |
1510 | trace_smmuv3_notify_flag_del(iommu->parent_obj.name); | |
1511 | QLIST_REMOVE(sdev, next); | |
0d1ac82e | 1512 | } |
549d4005 | 1513 | return 0; |
0d1ac82e EA |
1514 | } |
1515 | ||
10a83cb9 PM |
1516 | static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass, |
1517 | void *data) | |
1518 | { | |
9bde7f06 EA |
1519 | IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); |
1520 | ||
1521 | imrc->translate = smmuv3_translate; | |
0d1ac82e | 1522 | imrc->notify_flag_changed = smmuv3_notify_flag_changed; |
10a83cb9 PM |
1523 | } |
1524 | ||
1525 | static const TypeInfo smmuv3_type_info = { | |
1526 | .name = TYPE_ARM_SMMUV3, | |
1527 | .parent = TYPE_ARM_SMMU, | |
1528 | .instance_size = sizeof(SMMUv3State), | |
1529 | .instance_init = smmuv3_instance_init, | |
1530 | .class_size = sizeof(SMMUv3Class), | |
1531 | .class_init = smmuv3_class_init, | |
1532 | }; | |
1533 | ||
1534 | static const TypeInfo smmuv3_iommu_memory_region_info = { | |
1535 | .parent = TYPE_IOMMU_MEMORY_REGION, | |
1536 | .name = TYPE_SMMUV3_IOMMU_MEMORY_REGION, | |
1537 | .class_init = smmuv3_iommu_memory_region_class_init, | |
1538 | }; | |
1539 | ||
1540 | static void smmuv3_register_types(void) | |
1541 | { | |
1542 | type_register(&smmuv3_type_info); | |
1543 | type_register(&smmuv3_iommu_memory_region_info); | |
1544 | } | |
1545 | ||
1546 | type_init(smmuv3_register_types) | |
1547 |