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Commit | Line | Data |
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9ee6e8bb | 1 | /* |
1654b2d6 | 2 | * Luminary Micro Stellaris peripherals |
9ee6e8bb PB |
3 | * |
4 | * Copyright (c) 2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
9ee6e8bb PB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
83c9f4ca | 12 | #include "hw/sysbus.h" |
8fd06719 | 13 | #include "hw/ssi/ssi.h" |
bd2be150 PM |
14 | #include "hw/arm/arm.h" |
15 | #include "hw/devices.h" | |
1de7afc9 | 16 | #include "qemu/timer.h" |
0d09e41a | 17 | #include "hw/i2c/i2c.h" |
1422e32d | 18 | #include "net/net.h" |
83c9f4ca | 19 | #include "hw/boards.h" |
03dd024f | 20 | #include "qemu/log.h" |
022c62cb | 21 | #include "exec/address-spaces.h" |
d69ffb5b | 22 | #include "sysemu/sysemu.h" |
f04d4465 | 23 | #include "hw/arm/armv7m.h" |
f0d1d2c1 | 24 | #include "hw/char/pl011.h" |
aecfbbc9 | 25 | #include "hw/misc/unimp.h" |
ba1ba5cc | 26 | #include "cpu.h" |
9ee6e8bb | 27 | |
cf0dbb21 PB |
28 | #define GPIO_A 0 |
29 | #define GPIO_B 1 | |
30 | #define GPIO_C 2 | |
31 | #define GPIO_D 3 | |
32 | #define GPIO_E 4 | |
33 | #define GPIO_F 5 | |
34 | #define GPIO_G 6 | |
35 | ||
36 | #define BP_OLED_I2C 0x01 | |
37 | #define BP_OLED_SSI 0x02 | |
38 | #define BP_GAMEPAD 0x04 | |
39 | ||
8b47b7da AF |
40 | #define NUM_IRQ_LINES 64 |
41 | ||
9ee6e8bb PB |
42 | typedef const struct { |
43 | const char *name; | |
44 | uint32_t did0; | |
45 | uint32_t did1; | |
46 | uint32_t dc0; | |
47 | uint32_t dc1; | |
48 | uint32_t dc2; | |
49 | uint32_t dc3; | |
50 | uint32_t dc4; | |
cf0dbb21 | 51 | uint32_t peripherals; |
9ee6e8bb PB |
52 | } stellaris_board_info; |
53 | ||
54 | /* General purpose timer module. */ | |
55 | ||
8ef1d394 AF |
56 | #define TYPE_STELLARIS_GPTM "stellaris-gptm" |
57 | #define STELLARIS_GPTM(obj) \ | |
58 | OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM) | |
59 | ||
9ee6e8bb | 60 | typedef struct gptm_state { |
8ef1d394 AF |
61 | SysBusDevice parent_obj; |
62 | ||
2443fa27 | 63 | MemoryRegion iomem; |
9ee6e8bb PB |
64 | uint32_t config; |
65 | uint32_t mode[2]; | |
66 | uint32_t control; | |
67 | uint32_t state; | |
68 | uint32_t mask; | |
69 | uint32_t load[2]; | |
70 | uint32_t match[2]; | |
71 | uint32_t prescale[2]; | |
72 | uint32_t match_prescale[2]; | |
73 | uint32_t rtc; | |
74 | int64_t tick[2]; | |
75 | struct gptm_state *opaque[2]; | |
9ee6e8bb PB |
76 | QEMUTimer *timer[2]; |
77 | /* The timers have an alternate output used to trigger the ADC. */ | |
78 | qemu_irq trigger; | |
79 | qemu_irq irq; | |
80 | } gptm_state; | |
81 | ||
82 | static void gptm_update_irq(gptm_state *s) | |
83 | { | |
84 | int level; | |
85 | level = (s->state & s->mask) != 0; | |
86 | qemu_set_irq(s->irq, level); | |
87 | } | |
88 | ||
89 | static void gptm_stop(gptm_state *s, int n) | |
90 | { | |
bc72ad67 | 91 | timer_del(s->timer[n]); |
9ee6e8bb PB |
92 | } |
93 | ||
94 | static void gptm_reload(gptm_state *s, int n, int reset) | |
95 | { | |
96 | int64_t tick; | |
97 | if (reset) | |
bc72ad67 | 98 | tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
9ee6e8bb PB |
99 | else |
100 | tick = s->tick[n]; | |
101 | ||
102 | if (s->config == 0) { | |
103 | /* 32-bit CountDown. */ | |
104 | uint32_t count; | |
105 | count = s->load[0] | (s->load[1] << 16); | |
e57ec016 | 106 | tick += (int64_t)count * system_clock_scale; |
9ee6e8bb PB |
107 | } else if (s->config == 1) { |
108 | /* 32-bit RTC. 1Hz tick. */ | |
73bcb24d | 109 | tick += NANOSECONDS_PER_SECOND; |
9ee6e8bb PB |
110 | } else if (s->mode[n] == 0xa) { |
111 | /* PWM mode. Not implemented. */ | |
112 | } else { | |
df3692e0 PM |
113 | qemu_log_mask(LOG_UNIMP, |
114 | "GPTM: 16-bit timer mode unimplemented: 0x%x\n", | |
115 | s->mode[n]); | |
116 | return; | |
9ee6e8bb PB |
117 | } |
118 | s->tick[n] = tick; | |
bc72ad67 | 119 | timer_mod(s->timer[n], tick); |
9ee6e8bb PB |
120 | } |
121 | ||
122 | static void gptm_tick(void *opaque) | |
123 | { | |
124 | gptm_state **p = (gptm_state **)opaque; | |
125 | gptm_state *s; | |
126 | int n; | |
127 | ||
128 | s = *p; | |
129 | n = p - s->opaque; | |
130 | if (s->config == 0) { | |
131 | s->state |= 1; | |
132 | if ((s->control & 0x20)) { | |
133 | /* Output trigger. */ | |
40905a6a | 134 | qemu_irq_pulse(s->trigger); |
9ee6e8bb PB |
135 | } |
136 | if (s->mode[0] & 1) { | |
137 | /* One-shot. */ | |
138 | s->control &= ~1; | |
139 | } else { | |
140 | /* Periodic. */ | |
141 | gptm_reload(s, 0, 0); | |
142 | } | |
143 | } else if (s->config == 1) { | |
144 | /* RTC. */ | |
145 | uint32_t match; | |
146 | s->rtc++; | |
147 | match = s->match[0] | (s->match[1] << 16); | |
148 | if (s->rtc > match) | |
149 | s->rtc = 0; | |
150 | if (s->rtc == 0) { | |
151 | s->state |= 8; | |
152 | } | |
153 | gptm_reload(s, 0, 0); | |
154 | } else if (s->mode[n] == 0xa) { | |
155 | /* PWM mode. Not implemented. */ | |
156 | } else { | |
df3692e0 PM |
157 | qemu_log_mask(LOG_UNIMP, |
158 | "GPTM: 16-bit timer mode unimplemented: 0x%x\n", | |
159 | s->mode[n]); | |
9ee6e8bb PB |
160 | } |
161 | gptm_update_irq(s); | |
162 | } | |
163 | ||
a8170e5e | 164 | static uint64_t gptm_read(void *opaque, hwaddr offset, |
2443fa27 | 165 | unsigned size) |
9ee6e8bb PB |
166 | { |
167 | gptm_state *s = (gptm_state *)opaque; | |
168 | ||
9ee6e8bb PB |
169 | switch (offset) { |
170 | case 0x00: /* CFG */ | |
171 | return s->config; | |
172 | case 0x04: /* TAMR */ | |
173 | return s->mode[0]; | |
174 | case 0x08: /* TBMR */ | |
175 | return s->mode[1]; | |
176 | case 0x0c: /* CTL */ | |
177 | return s->control; | |
178 | case 0x18: /* IMR */ | |
179 | return s->mask; | |
180 | case 0x1c: /* RIS */ | |
181 | return s->state; | |
182 | case 0x20: /* MIS */ | |
183 | return s->state & s->mask; | |
184 | case 0x24: /* CR */ | |
185 | return 0; | |
186 | case 0x28: /* TAILR */ | |
187 | return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0); | |
188 | case 0x2c: /* TBILR */ | |
189 | return s->load[1]; | |
190 | case 0x30: /* TAMARCHR */ | |
191 | return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0); | |
192 | case 0x34: /* TBMATCHR */ | |
193 | return s->match[1]; | |
194 | case 0x38: /* TAPR */ | |
195 | return s->prescale[0]; | |
196 | case 0x3c: /* TBPR */ | |
197 | return s->prescale[1]; | |
198 | case 0x40: /* TAPMR */ | |
199 | return s->match_prescale[0]; | |
200 | case 0x44: /* TBPMR */ | |
201 | return s->match_prescale[1]; | |
202 | case 0x48: /* TAR */ | |
1a791721 | 203 | if (s->config == 1) { |
9ee6e8bb | 204 | return s->rtc; |
1a791721 PM |
205 | } |
206 | qemu_log_mask(LOG_UNIMP, | |
9492e4b2 | 207 | "GPTM: read of TAR but timer read not supported\n"); |
1a791721 | 208 | return 0; |
9ee6e8bb | 209 | case 0x4c: /* TBR */ |
1a791721 | 210 | qemu_log_mask(LOG_UNIMP, |
9492e4b2 | 211 | "GPTM: read of TBR but timer read not supported\n"); |
1a791721 | 212 | return 0; |
9ee6e8bb | 213 | default: |
1a791721 PM |
214 | qemu_log_mask(LOG_GUEST_ERROR, |
215 | "GPTM: read at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
216 | return 0; |
217 | } | |
218 | } | |
219 | ||
a8170e5e | 220 | static void gptm_write(void *opaque, hwaddr offset, |
2443fa27 | 221 | uint64_t value, unsigned size) |
9ee6e8bb PB |
222 | { |
223 | gptm_state *s = (gptm_state *)opaque; | |
224 | uint32_t oldval; | |
225 | ||
9ee6e8bb PB |
226 | /* The timers should be disabled before changing the configuration. |
227 | We take advantage of this and defer everything until the timer | |
228 | is enabled. */ | |
229 | switch (offset) { | |
230 | case 0x00: /* CFG */ | |
231 | s->config = value; | |
232 | break; | |
233 | case 0x04: /* TAMR */ | |
234 | s->mode[0] = value; | |
235 | break; | |
236 | case 0x08: /* TBMR */ | |
237 | s->mode[1] = value; | |
238 | break; | |
239 | case 0x0c: /* CTL */ | |
240 | oldval = s->control; | |
241 | s->control = value; | |
242 | /* TODO: Implement pause. */ | |
243 | if ((oldval ^ value) & 1) { | |
244 | if (value & 1) { | |
245 | gptm_reload(s, 0, 1); | |
246 | } else { | |
247 | gptm_stop(s, 0); | |
248 | } | |
249 | } | |
250 | if (((oldval ^ value) & 0x100) && s->config >= 4) { | |
251 | if (value & 0x100) { | |
252 | gptm_reload(s, 1, 1); | |
253 | } else { | |
254 | gptm_stop(s, 1); | |
255 | } | |
256 | } | |
257 | break; | |
258 | case 0x18: /* IMR */ | |
259 | s->mask = value & 0x77; | |
260 | gptm_update_irq(s); | |
261 | break; | |
262 | case 0x24: /* CR */ | |
263 | s->state &= ~value; | |
264 | break; | |
265 | case 0x28: /* TAILR */ | |
266 | s->load[0] = value & 0xffff; | |
267 | if (s->config < 4) { | |
268 | s->load[1] = value >> 16; | |
269 | } | |
270 | break; | |
271 | case 0x2c: /* TBILR */ | |
272 | s->load[1] = value & 0xffff; | |
273 | break; | |
274 | case 0x30: /* TAMARCHR */ | |
275 | s->match[0] = value & 0xffff; | |
276 | if (s->config < 4) { | |
277 | s->match[1] = value >> 16; | |
278 | } | |
279 | break; | |
280 | case 0x34: /* TBMATCHR */ | |
281 | s->match[1] = value >> 16; | |
282 | break; | |
283 | case 0x38: /* TAPR */ | |
284 | s->prescale[0] = value; | |
285 | break; | |
286 | case 0x3c: /* TBPR */ | |
287 | s->prescale[1] = value; | |
288 | break; | |
289 | case 0x40: /* TAPMR */ | |
290 | s->match_prescale[0] = value; | |
291 | break; | |
292 | case 0x44: /* TBPMR */ | |
293 | s->match_prescale[0] = value; | |
294 | break; | |
295 | default: | |
df3692e0 | 296 | qemu_log_mask(LOG_GUEST_ERROR, |
bc281eff | 297 | "GPTM: write at bad offset 0x%x\n", (int)offset); |
9ee6e8bb PB |
298 | } |
299 | gptm_update_irq(s); | |
300 | } | |
301 | ||
2443fa27 BC |
302 | static const MemoryRegionOps gptm_ops = { |
303 | .read = gptm_read, | |
304 | .write = gptm_write, | |
305 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
306 | }; |
307 | ||
10f85a29 JQ |
308 | static const VMStateDescription vmstate_stellaris_gptm = { |
309 | .name = "stellaris_gptm", | |
310 | .version_id = 1, | |
311 | .minimum_version_id = 1, | |
8f1e884b | 312 | .fields = (VMStateField[]) { |
10f85a29 JQ |
313 | VMSTATE_UINT32(config, gptm_state), |
314 | VMSTATE_UINT32_ARRAY(mode, gptm_state, 2), | |
315 | VMSTATE_UINT32(control, gptm_state), | |
316 | VMSTATE_UINT32(state, gptm_state), | |
317 | VMSTATE_UINT32(mask, gptm_state), | |
dd8a4dcd | 318 | VMSTATE_UNUSED(8), |
10f85a29 JQ |
319 | VMSTATE_UINT32_ARRAY(load, gptm_state, 2), |
320 | VMSTATE_UINT32_ARRAY(match, gptm_state, 2), | |
321 | VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2), | |
322 | VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2), | |
323 | VMSTATE_UINT32(rtc, gptm_state), | |
324 | VMSTATE_INT64_ARRAY(tick, gptm_state, 2), | |
e720677e | 325 | VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2), |
10f85a29 JQ |
326 | VMSTATE_END_OF_LIST() |
327 | } | |
328 | }; | |
23e39294 | 329 | |
15c4fff5 | 330 | static void stellaris_gptm_init(Object *obj) |
9ee6e8bb | 331 | { |
15c4fff5 XZ |
332 | DeviceState *dev = DEVICE(obj); |
333 | gptm_state *s = STELLARIS_GPTM(obj); | |
334 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
9ee6e8bb | 335 | |
8ef1d394 AF |
336 | sysbus_init_irq(sbd, &s->irq); |
337 | qdev_init_gpio_out(dev, &s->trigger, 1); | |
9ee6e8bb | 338 | |
15c4fff5 | 339 | memory_region_init_io(&s->iomem, obj, &gptm_ops, s, |
2443fa27 | 340 | "gptm", 0x1000); |
8ef1d394 | 341 | sysbus_init_mmio(sbd, &s->iomem); |
40905a6a PB |
342 | |
343 | s->opaque[0] = s->opaque[1] = s; | |
bc72ad67 AB |
344 | s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]); |
345 | s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]); | |
9ee6e8bb PB |
346 | } |
347 | ||
348 | ||
349 | /* System controller. */ | |
350 | ||
351 | typedef struct { | |
5699301f | 352 | MemoryRegion iomem; |
9ee6e8bb PB |
353 | uint32_t pborctl; |
354 | uint32_t ldopctl; | |
355 | uint32_t int_status; | |
356 | uint32_t int_mask; | |
357 | uint32_t resc; | |
358 | uint32_t rcc; | |
dc804ab7 | 359 | uint32_t rcc2; |
9ee6e8bb PB |
360 | uint32_t rcgc[3]; |
361 | uint32_t scgc[3]; | |
362 | uint32_t dcgc[3]; | |
363 | uint32_t clkvclr; | |
364 | uint32_t ldoarst; | |
eea589cc PB |
365 | uint32_t user0; |
366 | uint32_t user1; | |
9ee6e8bb PB |
367 | qemu_irq irq; |
368 | stellaris_board_info *board; | |
369 | } ssys_state; | |
370 | ||
371 | static void ssys_update(ssys_state *s) | |
372 | { | |
373 | qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); | |
374 | } | |
375 | ||
376 | static uint32_t pllcfg_sandstorm[16] = { | |
377 | 0x31c0, /* 1 Mhz */ | |
378 | 0x1ae0, /* 1.8432 Mhz */ | |
379 | 0x18c0, /* 2 Mhz */ | |
380 | 0xd573, /* 2.4576 Mhz */ | |
381 | 0x37a6, /* 3.57954 Mhz */ | |
382 | 0x1ae2, /* 3.6864 Mhz */ | |
383 | 0x0c40, /* 4 Mhz */ | |
384 | 0x98bc, /* 4.906 Mhz */ | |
385 | 0x935b, /* 4.9152 Mhz */ | |
386 | 0x09c0, /* 5 Mhz */ | |
387 | 0x4dee, /* 5.12 Mhz */ | |
388 | 0x0c41, /* 6 Mhz */ | |
389 | 0x75db, /* 6.144 Mhz */ | |
390 | 0x1ae6, /* 7.3728 Mhz */ | |
391 | 0x0600, /* 8 Mhz */ | |
392 | 0x585b /* 8.192 Mhz */ | |
393 | }; | |
394 | ||
395 | static uint32_t pllcfg_fury[16] = { | |
396 | 0x3200, /* 1 Mhz */ | |
397 | 0x1b20, /* 1.8432 Mhz */ | |
398 | 0x1900, /* 2 Mhz */ | |
399 | 0xf42b, /* 2.4576 Mhz */ | |
400 | 0x37e3, /* 3.57954 Mhz */ | |
401 | 0x1b21, /* 3.6864 Mhz */ | |
402 | 0x0c80, /* 4 Mhz */ | |
403 | 0x98ee, /* 4.906 Mhz */ | |
404 | 0xd5b4, /* 4.9152 Mhz */ | |
405 | 0x0a00, /* 5 Mhz */ | |
406 | 0x4e27, /* 5.12 Mhz */ | |
407 | 0x1902, /* 6 Mhz */ | |
408 | 0xec1c, /* 6.144 Mhz */ | |
409 | 0x1b23, /* 7.3728 Mhz */ | |
410 | 0x0640, /* 8 Mhz */ | |
411 | 0xb11c /* 8.192 Mhz */ | |
412 | }; | |
413 | ||
dc804ab7 EA |
414 | #define DID0_VER_MASK 0x70000000 |
415 | #define DID0_VER_0 0x00000000 | |
416 | #define DID0_VER_1 0x10000000 | |
417 | ||
418 | #define DID0_CLASS_MASK 0x00FF0000 | |
419 | #define DID0_CLASS_SANDSTORM 0x00000000 | |
420 | #define DID0_CLASS_FURY 0x00010000 | |
421 | ||
422 | static int ssys_board_class(const ssys_state *s) | |
423 | { | |
424 | uint32_t did0 = s->board->did0; | |
425 | switch (did0 & DID0_VER_MASK) { | |
426 | case DID0_VER_0: | |
427 | return DID0_CLASS_SANDSTORM; | |
428 | case DID0_VER_1: | |
429 | switch (did0 & DID0_CLASS_MASK) { | |
430 | case DID0_CLASS_SANDSTORM: | |
431 | case DID0_CLASS_FURY: | |
432 | return did0 & DID0_CLASS_MASK; | |
433 | } | |
434 | /* for unknown classes, fall through */ | |
435 | default: | |
df3692e0 PM |
436 | /* This can only happen if the hardwired constant did0 value |
437 | * in this board's stellaris_board_info struct is wrong. | |
438 | */ | |
439 | g_assert_not_reached(); | |
dc804ab7 EA |
440 | } |
441 | } | |
442 | ||
a8170e5e | 443 | static uint64_t ssys_read(void *opaque, hwaddr offset, |
5699301f | 444 | unsigned size) |
9ee6e8bb PB |
445 | { |
446 | ssys_state *s = (ssys_state *)opaque; | |
447 | ||
9ee6e8bb PB |
448 | switch (offset) { |
449 | case 0x000: /* DID0 */ | |
450 | return s->board->did0; | |
451 | case 0x004: /* DID1 */ | |
452 | return s->board->did1; | |
453 | case 0x008: /* DC0 */ | |
454 | return s->board->dc0; | |
455 | case 0x010: /* DC1 */ | |
456 | return s->board->dc1; | |
457 | case 0x014: /* DC2 */ | |
458 | return s->board->dc2; | |
459 | case 0x018: /* DC3 */ | |
460 | return s->board->dc3; | |
461 | case 0x01c: /* DC4 */ | |
462 | return s->board->dc4; | |
463 | case 0x030: /* PBORCTL */ | |
464 | return s->pborctl; | |
465 | case 0x034: /* LDOPCTL */ | |
466 | return s->ldopctl; | |
467 | case 0x040: /* SRCR0 */ | |
468 | return 0; | |
469 | case 0x044: /* SRCR1 */ | |
470 | return 0; | |
471 | case 0x048: /* SRCR2 */ | |
472 | return 0; | |
473 | case 0x050: /* RIS */ | |
474 | return s->int_status; | |
475 | case 0x054: /* IMC */ | |
476 | return s->int_mask; | |
477 | case 0x058: /* MISC */ | |
478 | return s->int_status & s->int_mask; | |
479 | case 0x05c: /* RESC */ | |
480 | return s->resc; | |
481 | case 0x060: /* RCC */ | |
482 | return s->rcc; | |
483 | case 0x064: /* PLLCFG */ | |
484 | { | |
485 | int xtal; | |
486 | xtal = (s->rcc >> 6) & 0xf; | |
dc804ab7 EA |
487 | switch (ssys_board_class(s)) { |
488 | case DID0_CLASS_FURY: | |
9ee6e8bb | 489 | return pllcfg_fury[xtal]; |
dc804ab7 | 490 | case DID0_CLASS_SANDSTORM: |
9ee6e8bb | 491 | return pllcfg_sandstorm[xtal]; |
dc804ab7 | 492 | default: |
df3692e0 | 493 | g_assert_not_reached(); |
9ee6e8bb PB |
494 | } |
495 | } | |
dc804ab7 EA |
496 | case 0x070: /* RCC2 */ |
497 | return s->rcc2; | |
9ee6e8bb PB |
498 | case 0x100: /* RCGC0 */ |
499 | return s->rcgc[0]; | |
500 | case 0x104: /* RCGC1 */ | |
501 | return s->rcgc[1]; | |
502 | case 0x108: /* RCGC2 */ | |
503 | return s->rcgc[2]; | |
504 | case 0x110: /* SCGC0 */ | |
505 | return s->scgc[0]; | |
506 | case 0x114: /* SCGC1 */ | |
507 | return s->scgc[1]; | |
508 | case 0x118: /* SCGC2 */ | |
509 | return s->scgc[2]; | |
510 | case 0x120: /* DCGC0 */ | |
511 | return s->dcgc[0]; | |
512 | case 0x124: /* DCGC1 */ | |
513 | return s->dcgc[1]; | |
514 | case 0x128: /* DCGC2 */ | |
515 | return s->dcgc[2]; | |
516 | case 0x150: /* CLKVCLR */ | |
517 | return s->clkvclr; | |
518 | case 0x160: /* LDOARST */ | |
519 | return s->ldoarst; | |
eea589cc PB |
520 | case 0x1e0: /* USER0 */ |
521 | return s->user0; | |
522 | case 0x1e4: /* USER1 */ | |
523 | return s->user1; | |
9ee6e8bb | 524 | default: |
df3692e0 PM |
525 | qemu_log_mask(LOG_GUEST_ERROR, |
526 | "SSYS: read at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
527 | return 0; |
528 | } | |
529 | } | |
530 | ||
dc804ab7 EA |
531 | static bool ssys_use_rcc2(ssys_state *s) |
532 | { | |
533 | return (s->rcc2 >> 31) & 0x1; | |
534 | } | |
535 | ||
536 | /* | |
537 | * Caculate the sys. clock period in ms. | |
538 | */ | |
23e39294 PB |
539 | static void ssys_calculate_system_clock(ssys_state *s) |
540 | { | |
dc804ab7 EA |
541 | if (ssys_use_rcc2(s)) { |
542 | system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1); | |
543 | } else { | |
544 | system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1); | |
545 | } | |
23e39294 PB |
546 | } |
547 | ||
a8170e5e | 548 | static void ssys_write(void *opaque, hwaddr offset, |
5699301f | 549 | uint64_t value, unsigned size) |
9ee6e8bb PB |
550 | { |
551 | ssys_state *s = (ssys_state *)opaque; | |
552 | ||
9ee6e8bb PB |
553 | switch (offset) { |
554 | case 0x030: /* PBORCTL */ | |
555 | s->pborctl = value & 0xffff; | |
556 | break; | |
557 | case 0x034: /* LDOPCTL */ | |
558 | s->ldopctl = value & 0x1f; | |
559 | break; | |
560 | case 0x040: /* SRCR0 */ | |
561 | case 0x044: /* SRCR1 */ | |
562 | case 0x048: /* SRCR2 */ | |
9194524b | 563 | qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n"); |
9ee6e8bb PB |
564 | break; |
565 | case 0x054: /* IMC */ | |
566 | s->int_mask = value & 0x7f; | |
567 | break; | |
568 | case 0x058: /* MISC */ | |
569 | s->int_status &= ~value; | |
570 | break; | |
571 | case 0x05c: /* RESC */ | |
572 | s->resc = value & 0x3f; | |
573 | break; | |
574 | case 0x060: /* RCC */ | |
575 | if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { | |
576 | /* PLL enable. */ | |
577 | s->int_status |= (1 << 6); | |
578 | } | |
579 | s->rcc = value; | |
23e39294 | 580 | ssys_calculate_system_clock(s); |
9ee6e8bb | 581 | break; |
dc804ab7 EA |
582 | case 0x070: /* RCC2 */ |
583 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { | |
584 | break; | |
585 | } | |
586 | ||
587 | if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) { | |
588 | /* PLL enable. */ | |
589 | s->int_status |= (1 << 6); | |
590 | } | |
591 | s->rcc2 = value; | |
592 | ssys_calculate_system_clock(s); | |
593 | break; | |
9ee6e8bb PB |
594 | case 0x100: /* RCGC0 */ |
595 | s->rcgc[0] = value; | |
596 | break; | |
597 | case 0x104: /* RCGC1 */ | |
598 | s->rcgc[1] = value; | |
599 | break; | |
600 | case 0x108: /* RCGC2 */ | |
601 | s->rcgc[2] = value; | |
602 | break; | |
603 | case 0x110: /* SCGC0 */ | |
604 | s->scgc[0] = value; | |
605 | break; | |
606 | case 0x114: /* SCGC1 */ | |
607 | s->scgc[1] = value; | |
608 | break; | |
609 | case 0x118: /* SCGC2 */ | |
610 | s->scgc[2] = value; | |
611 | break; | |
612 | case 0x120: /* DCGC0 */ | |
613 | s->dcgc[0] = value; | |
614 | break; | |
615 | case 0x124: /* DCGC1 */ | |
616 | s->dcgc[1] = value; | |
617 | break; | |
618 | case 0x128: /* DCGC2 */ | |
619 | s->dcgc[2] = value; | |
620 | break; | |
621 | case 0x150: /* CLKVCLR */ | |
622 | s->clkvclr = value; | |
623 | break; | |
624 | case 0x160: /* LDOARST */ | |
625 | s->ldoarst = value; | |
626 | break; | |
627 | default: | |
df3692e0 PM |
628 | qemu_log_mask(LOG_GUEST_ERROR, |
629 | "SSYS: write at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
630 | } |
631 | ssys_update(s); | |
632 | } | |
633 | ||
5699301f BC |
634 | static const MemoryRegionOps ssys_ops = { |
635 | .read = ssys_read, | |
636 | .write = ssys_write, | |
637 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
638 | }; |
639 | ||
9596ebb7 | 640 | static void ssys_reset(void *opaque) |
9ee6e8bb PB |
641 | { |
642 | ssys_state *s = (ssys_state *)opaque; | |
643 | ||
644 | s->pborctl = 0x7ffd; | |
645 | s->rcc = 0x078e3ac0; | |
dc804ab7 EA |
646 | |
647 | if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) { | |
648 | s->rcc2 = 0; | |
649 | } else { | |
650 | s->rcc2 = 0x07802810; | |
651 | } | |
9ee6e8bb PB |
652 | s->rcgc[0] = 1; |
653 | s->scgc[0] = 1; | |
654 | s->dcgc[0] = 1; | |
bfc213af | 655 | ssys_calculate_system_clock(s); |
9ee6e8bb PB |
656 | } |
657 | ||
293c16aa | 658 | static int stellaris_sys_post_load(void *opaque, int version_id) |
23e39294 | 659 | { |
293c16aa | 660 | ssys_state *s = opaque; |
23e39294 | 661 | |
23e39294 PB |
662 | ssys_calculate_system_clock(s); |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
293c16aa JQ |
667 | static const VMStateDescription vmstate_stellaris_sys = { |
668 | .name = "stellaris_sys", | |
dc804ab7 | 669 | .version_id = 2, |
293c16aa | 670 | .minimum_version_id = 1, |
293c16aa | 671 | .post_load = stellaris_sys_post_load, |
8f1e884b | 672 | .fields = (VMStateField[]) { |
293c16aa JQ |
673 | VMSTATE_UINT32(pborctl, ssys_state), |
674 | VMSTATE_UINT32(ldopctl, ssys_state), | |
675 | VMSTATE_UINT32(int_mask, ssys_state), | |
676 | VMSTATE_UINT32(int_status, ssys_state), | |
677 | VMSTATE_UINT32(resc, ssys_state), | |
678 | VMSTATE_UINT32(rcc, ssys_state), | |
dc804ab7 | 679 | VMSTATE_UINT32_V(rcc2, ssys_state, 2), |
293c16aa JQ |
680 | VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3), |
681 | VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3), | |
682 | VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3), | |
683 | VMSTATE_UINT32(clkvclr, ssys_state), | |
684 | VMSTATE_UINT32(ldoarst, ssys_state), | |
685 | VMSTATE_END_OF_LIST() | |
686 | } | |
687 | }; | |
688 | ||
81a322d4 GH |
689 | static int stellaris_sys_init(uint32_t base, qemu_irq irq, |
690 | stellaris_board_info * board, | |
691 | uint8_t *macaddr) | |
9ee6e8bb | 692 | { |
9ee6e8bb PB |
693 | ssys_state *s; |
694 | ||
b45c03f5 | 695 | s = g_new0(ssys_state, 1); |
9ee6e8bb PB |
696 | s->irq = irq; |
697 | s->board = board; | |
eea589cc PB |
698 | /* Most devices come preprogrammed with a MAC address in the user data. */ |
699 | s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16); | |
700 | s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16); | |
9ee6e8bb | 701 | |
2c9b15ca | 702 | memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000); |
5699301f | 703 | memory_region_add_subregion(get_system_memory(), base, &s->iomem); |
9ee6e8bb | 704 | ssys_reset(s); |
293c16aa | 705 | vmstate_register(NULL, -1, &vmstate_stellaris_sys, s); |
81a322d4 | 706 | return 0; |
9ee6e8bb PB |
707 | } |
708 | ||
709 | ||
710 | /* I2C controller. */ | |
711 | ||
d94a4015 AF |
712 | #define TYPE_STELLARIS_I2C "stellaris-i2c" |
713 | #define STELLARIS_I2C(obj) \ | |
714 | OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C) | |
715 | ||
9ee6e8bb | 716 | typedef struct { |
d94a4015 AF |
717 | SysBusDevice parent_obj; |
718 | ||
a5c82852 | 719 | I2CBus *bus; |
9ee6e8bb | 720 | qemu_irq irq; |
8ea72f38 | 721 | MemoryRegion iomem; |
9ee6e8bb PB |
722 | uint32_t msa; |
723 | uint32_t mcs; | |
724 | uint32_t mdr; | |
725 | uint32_t mtpr; | |
726 | uint32_t mimr; | |
727 | uint32_t mris; | |
728 | uint32_t mcr; | |
729 | } stellaris_i2c_state; | |
730 | ||
731 | #define STELLARIS_I2C_MCS_BUSY 0x01 | |
732 | #define STELLARIS_I2C_MCS_ERROR 0x02 | |
733 | #define STELLARIS_I2C_MCS_ADRACK 0x04 | |
734 | #define STELLARIS_I2C_MCS_DATACK 0x08 | |
735 | #define STELLARIS_I2C_MCS_ARBLST 0x10 | |
736 | #define STELLARIS_I2C_MCS_IDLE 0x20 | |
737 | #define STELLARIS_I2C_MCS_BUSBSY 0x40 | |
738 | ||
a8170e5e | 739 | static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset, |
8ea72f38 | 740 | unsigned size) |
9ee6e8bb PB |
741 | { |
742 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; | |
743 | ||
9ee6e8bb PB |
744 | switch (offset) { |
745 | case 0x00: /* MSA */ | |
746 | return s->msa; | |
747 | case 0x04: /* MCS */ | |
748 | /* We don't emulate timing, so the controller is never busy. */ | |
749 | return s->mcs | STELLARIS_I2C_MCS_IDLE; | |
750 | case 0x08: /* MDR */ | |
751 | return s->mdr; | |
752 | case 0x0c: /* MTPR */ | |
753 | return s->mtpr; | |
754 | case 0x10: /* MIMR */ | |
755 | return s->mimr; | |
756 | case 0x14: /* MRIS */ | |
757 | return s->mris; | |
758 | case 0x18: /* MMIS */ | |
759 | return s->mris & s->mimr; | |
760 | case 0x20: /* MCR */ | |
761 | return s->mcr; | |
762 | default: | |
df3692e0 PM |
763 | qemu_log_mask(LOG_GUEST_ERROR, |
764 | "stellaris_i2c: read at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
765 | return 0; |
766 | } | |
767 | } | |
768 | ||
769 | static void stellaris_i2c_update(stellaris_i2c_state *s) | |
770 | { | |
771 | int level; | |
772 | ||
773 | level = (s->mris & s->mimr) != 0; | |
774 | qemu_set_irq(s->irq, level); | |
775 | } | |
776 | ||
a8170e5e | 777 | static void stellaris_i2c_write(void *opaque, hwaddr offset, |
8ea72f38 | 778 | uint64_t value, unsigned size) |
9ee6e8bb PB |
779 | { |
780 | stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; | |
781 | ||
9ee6e8bb PB |
782 | switch (offset) { |
783 | case 0x00: /* MSA */ | |
784 | s->msa = value & 0xff; | |
785 | break; | |
786 | case 0x04: /* MCS */ | |
787 | if ((s->mcr & 0x10) == 0) { | |
788 | /* Disabled. Do nothing. */ | |
789 | break; | |
790 | } | |
791 | /* Grab the bus if this is starting a transfer. */ | |
792 | if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { | |
793 | if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) { | |
794 | s->mcs |= STELLARIS_I2C_MCS_ARBLST; | |
795 | } else { | |
796 | s->mcs &= ~STELLARIS_I2C_MCS_ARBLST; | |
797 | s->mcs |= STELLARIS_I2C_MCS_BUSBSY; | |
798 | } | |
799 | } | |
800 | /* If we don't have the bus then indicate an error. */ | |
801 | if (!i2c_bus_busy(s->bus) | |
802 | || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) { | |
803 | s->mcs |= STELLARIS_I2C_MCS_ERROR; | |
804 | break; | |
805 | } | |
806 | s->mcs &= ~STELLARIS_I2C_MCS_ERROR; | |
807 | if (value & 1) { | |
808 | /* Transfer a byte. */ | |
809 | /* TODO: Handle errors. */ | |
810 | if (s->msa & 1) { | |
811 | /* Recv */ | |
812 | s->mdr = i2c_recv(s->bus) & 0xff; | |
813 | } else { | |
814 | /* Send */ | |
815 | i2c_send(s->bus, s->mdr); | |
816 | } | |
817 | /* Raise an interrupt. */ | |
818 | s->mris |= 1; | |
819 | } | |
820 | if (value & 4) { | |
821 | /* Finish transfer. */ | |
822 | i2c_end_transfer(s->bus); | |
823 | s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY; | |
824 | } | |
825 | break; | |
826 | case 0x08: /* MDR */ | |
827 | s->mdr = value & 0xff; | |
828 | break; | |
829 | case 0x0c: /* MTPR */ | |
830 | s->mtpr = value & 0xff; | |
831 | break; | |
832 | case 0x10: /* MIMR */ | |
833 | s->mimr = 1; | |
834 | break; | |
835 | case 0x1c: /* MICR */ | |
836 | s->mris &= ~value; | |
837 | break; | |
838 | case 0x20: /* MCR */ | |
df3692e0 | 839 | if (value & 1) { |
9492e4b2 PMD |
840 | qemu_log_mask(LOG_UNIMP, |
841 | "stellaris_i2c: Loopback not implemented\n"); | |
df3692e0 PM |
842 | } |
843 | if (value & 0x20) { | |
844 | qemu_log_mask(LOG_UNIMP, | |
9492e4b2 | 845 | "stellaris_i2c: Slave mode not implemented\n"); |
df3692e0 | 846 | } |
9ee6e8bb PB |
847 | s->mcr = value & 0x31; |
848 | break; | |
849 | default: | |
df3692e0 PM |
850 | qemu_log_mask(LOG_GUEST_ERROR, |
851 | "stellaris_i2c: write at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
852 | } |
853 | stellaris_i2c_update(s); | |
854 | } | |
855 | ||
856 | static void stellaris_i2c_reset(stellaris_i2c_state *s) | |
857 | { | |
858 | if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) | |
859 | i2c_end_transfer(s->bus); | |
860 | ||
861 | s->msa = 0; | |
862 | s->mcs = 0; | |
863 | s->mdr = 0; | |
864 | s->mtpr = 1; | |
865 | s->mimr = 0; | |
866 | s->mris = 0; | |
867 | s->mcr = 0; | |
868 | stellaris_i2c_update(s); | |
869 | } | |
870 | ||
8ea72f38 BC |
871 | static const MemoryRegionOps stellaris_i2c_ops = { |
872 | .read = stellaris_i2c_read, | |
873 | .write = stellaris_i2c_write, | |
874 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
875 | }; |
876 | ||
ff269cd0 JQ |
877 | static const VMStateDescription vmstate_stellaris_i2c = { |
878 | .name = "stellaris_i2c", | |
879 | .version_id = 1, | |
880 | .minimum_version_id = 1, | |
8f1e884b | 881 | .fields = (VMStateField[]) { |
ff269cd0 JQ |
882 | VMSTATE_UINT32(msa, stellaris_i2c_state), |
883 | VMSTATE_UINT32(mcs, stellaris_i2c_state), | |
884 | VMSTATE_UINT32(mdr, stellaris_i2c_state), | |
885 | VMSTATE_UINT32(mtpr, stellaris_i2c_state), | |
886 | VMSTATE_UINT32(mimr, stellaris_i2c_state), | |
887 | VMSTATE_UINT32(mris, stellaris_i2c_state), | |
888 | VMSTATE_UINT32(mcr, stellaris_i2c_state), | |
889 | VMSTATE_END_OF_LIST() | |
890 | } | |
891 | }; | |
23e39294 | 892 | |
15c4fff5 | 893 | static void stellaris_i2c_init(Object *obj) |
9ee6e8bb | 894 | { |
15c4fff5 XZ |
895 | DeviceState *dev = DEVICE(obj); |
896 | stellaris_i2c_state *s = STELLARIS_I2C(obj); | |
897 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
a5c82852 | 898 | I2CBus *bus; |
9ee6e8bb | 899 | |
d94a4015 AF |
900 | sysbus_init_irq(sbd, &s->irq); |
901 | bus = i2c_init_bus(dev, "i2c"); | |
9ee6e8bb PB |
902 | s->bus = bus; |
903 | ||
15c4fff5 | 904 | memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, |
8ea72f38 | 905 | "i2c", 0x1000); |
d94a4015 | 906 | sysbus_init_mmio(sbd, &s->iomem); |
9ee6e8bb PB |
907 | /* ??? For now we only implement the master interface. */ |
908 | stellaris_i2c_reset(s); | |
909 | } | |
910 | ||
911 | /* Analogue to Digital Converter. This is only partially implemented, | |
912 | enough for applications that use a combined ADC and timer tick. */ | |
913 | ||
914 | #define STELLARIS_ADC_EM_CONTROLLER 0 | |
915 | #define STELLARIS_ADC_EM_COMP 1 | |
916 | #define STELLARIS_ADC_EM_EXTERNAL 4 | |
917 | #define STELLARIS_ADC_EM_TIMER 5 | |
918 | #define STELLARIS_ADC_EM_PWM0 6 | |
919 | #define STELLARIS_ADC_EM_PWM1 7 | |
920 | #define STELLARIS_ADC_EM_PWM2 8 | |
921 | ||
922 | #define STELLARIS_ADC_FIFO_EMPTY 0x0100 | |
923 | #define STELLARIS_ADC_FIFO_FULL 0x1000 | |
924 | ||
7df7f67a AF |
925 | #define TYPE_STELLARIS_ADC "stellaris-adc" |
926 | #define STELLARIS_ADC(obj) \ | |
927 | OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC) | |
928 | ||
929 | typedef struct StellarisADCState { | |
930 | SysBusDevice parent_obj; | |
931 | ||
71a2df05 | 932 | MemoryRegion iomem; |
9ee6e8bb PB |
933 | uint32_t actss; |
934 | uint32_t ris; | |
935 | uint32_t im; | |
936 | uint32_t emux; | |
937 | uint32_t ostat; | |
938 | uint32_t ustat; | |
939 | uint32_t sspri; | |
940 | uint32_t sac; | |
941 | struct { | |
942 | uint32_t state; | |
943 | uint32_t data[16]; | |
944 | } fifo[4]; | |
945 | uint32_t ssmux[4]; | |
946 | uint32_t ssctl[4]; | |
23e39294 | 947 | uint32_t noise; |
2c6554bc | 948 | qemu_irq irq[4]; |
9ee6e8bb PB |
949 | } stellaris_adc_state; |
950 | ||
951 | static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) | |
952 | { | |
953 | int tail; | |
954 | ||
955 | tail = s->fifo[n].state & 0xf; | |
956 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) { | |
957 | s->ustat |= 1 << n; | |
958 | } else { | |
959 | s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf); | |
960 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL; | |
961 | if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf)) | |
962 | s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY; | |
963 | } | |
964 | return s->fifo[n].data[tail]; | |
965 | } | |
966 | ||
967 | static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, | |
968 | uint32_t value) | |
969 | { | |
970 | int head; | |
971 | ||
2c6554bc PB |
972 | /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry |
973 | FIFO fir each sequencer. */ | |
9ee6e8bb PB |
974 | head = (s->fifo[n].state >> 4) & 0xf; |
975 | if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) { | |
976 | s->ostat |= 1 << n; | |
977 | return; | |
978 | } | |
979 | s->fifo[n].data[head] = value; | |
980 | head = (head + 1) & 0xf; | |
981 | s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY; | |
982 | s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4); | |
983 | if ((s->fifo[n].state & 0xf) == head) | |
984 | s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; | |
985 | } | |
986 | ||
987 | static void stellaris_adc_update(stellaris_adc_state *s) | |
988 | { | |
989 | int level; | |
2c6554bc | 990 | int n; |
9ee6e8bb | 991 | |
2c6554bc PB |
992 | for (n = 0; n < 4; n++) { |
993 | level = (s->ris & s->im & (1 << n)) != 0; | |
994 | qemu_set_irq(s->irq[n], level); | |
995 | } | |
9ee6e8bb PB |
996 | } |
997 | ||
998 | static void stellaris_adc_trigger(void *opaque, int irq, int level) | |
999 | { | |
1000 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; | |
2c6554bc | 1001 | int n; |
9ee6e8bb | 1002 | |
2c6554bc PB |
1003 | for (n = 0; n < 4; n++) { |
1004 | if ((s->actss & (1 << n)) == 0) { | |
1005 | continue; | |
1006 | } | |
9ee6e8bb | 1007 | |
2c6554bc PB |
1008 | if (((s->emux >> (n * 4)) & 0xff) != 5) { |
1009 | continue; | |
1010 | } | |
1011 | ||
1012 | /* Some applications use the ADC as a random number source, so introduce | |
1013 | some variation into the signal. */ | |
1014 | s->noise = s->noise * 314159 + 1; | |
1015 | /* ??? actual inputs not implemented. Return an arbitrary value. */ | |
1016 | stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7)); | |
1017 | s->ris |= (1 << n); | |
1018 | stellaris_adc_update(s); | |
1019 | } | |
9ee6e8bb PB |
1020 | } |
1021 | ||
1022 | static void stellaris_adc_reset(stellaris_adc_state *s) | |
1023 | { | |
1024 | int n; | |
1025 | ||
1026 | for (n = 0; n < 4; n++) { | |
1027 | s->ssmux[n] = 0; | |
1028 | s->ssctl[n] = 0; | |
1029 | s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY; | |
1030 | } | |
1031 | } | |
1032 | ||
a8170e5e | 1033 | static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, |
71a2df05 | 1034 | unsigned size) |
9ee6e8bb PB |
1035 | { |
1036 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; | |
1037 | ||
1038 | /* TODO: Implement this. */ | |
9ee6e8bb PB |
1039 | if (offset >= 0x40 && offset < 0xc0) { |
1040 | int n; | |
1041 | n = (offset - 0x40) >> 5; | |
1042 | switch (offset & 0x1f) { | |
1043 | case 0x00: /* SSMUX */ | |
1044 | return s->ssmux[n]; | |
1045 | case 0x04: /* SSCTL */ | |
1046 | return s->ssctl[n]; | |
1047 | case 0x08: /* SSFIFO */ | |
1048 | return stellaris_adc_fifo_read(s, n); | |
1049 | case 0x0c: /* SSFSTAT */ | |
1050 | return s->fifo[n].state; | |
1051 | default: | |
1052 | break; | |
1053 | } | |
1054 | } | |
1055 | switch (offset) { | |
1056 | case 0x00: /* ACTSS */ | |
1057 | return s->actss; | |
1058 | case 0x04: /* RIS */ | |
1059 | return s->ris; | |
1060 | case 0x08: /* IM */ | |
1061 | return s->im; | |
1062 | case 0x0c: /* ISC */ | |
1063 | return s->ris & s->im; | |
1064 | case 0x10: /* OSTAT */ | |
1065 | return s->ostat; | |
1066 | case 0x14: /* EMUX */ | |
1067 | return s->emux; | |
1068 | case 0x18: /* USTAT */ | |
1069 | return s->ustat; | |
1070 | case 0x20: /* SSPRI */ | |
1071 | return s->sspri; | |
1072 | case 0x30: /* SAC */ | |
1073 | return s->sac; | |
1074 | default: | |
df3692e0 PM |
1075 | qemu_log_mask(LOG_GUEST_ERROR, |
1076 | "stellaris_adc: read at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
1077 | return 0; |
1078 | } | |
1079 | } | |
1080 | ||
a8170e5e | 1081 | static void stellaris_adc_write(void *opaque, hwaddr offset, |
71a2df05 | 1082 | uint64_t value, unsigned size) |
9ee6e8bb PB |
1083 | { |
1084 | stellaris_adc_state *s = (stellaris_adc_state *)opaque; | |
1085 | ||
1086 | /* TODO: Implement this. */ | |
9ee6e8bb PB |
1087 | if (offset >= 0x40 && offset < 0xc0) { |
1088 | int n; | |
1089 | n = (offset - 0x40) >> 5; | |
1090 | switch (offset & 0x1f) { | |
1091 | case 0x00: /* SSMUX */ | |
1092 | s->ssmux[n] = value & 0x33333333; | |
1093 | return; | |
1094 | case 0x04: /* SSCTL */ | |
1095 | if (value != 6) { | |
df3692e0 PM |
1096 | qemu_log_mask(LOG_UNIMP, |
1097 | "ADC: Unimplemented sequence %" PRIx64 "\n", | |
1098 | value); | |
9ee6e8bb PB |
1099 | } |
1100 | s->ssctl[n] = value; | |
1101 | return; | |
1102 | default: | |
1103 | break; | |
1104 | } | |
1105 | } | |
1106 | switch (offset) { | |
1107 | case 0x00: /* ACTSS */ | |
1108 | s->actss = value & 0xf; | |
9ee6e8bb PB |
1109 | break; |
1110 | case 0x08: /* IM */ | |
1111 | s->im = value; | |
1112 | break; | |
1113 | case 0x0c: /* ISC */ | |
1114 | s->ris &= ~value; | |
1115 | break; | |
1116 | case 0x10: /* OSTAT */ | |
1117 | s->ostat &= ~value; | |
1118 | break; | |
1119 | case 0x14: /* EMUX */ | |
1120 | s->emux = value; | |
1121 | break; | |
1122 | case 0x18: /* USTAT */ | |
1123 | s->ustat &= ~value; | |
1124 | break; | |
1125 | case 0x20: /* SSPRI */ | |
1126 | s->sspri = value; | |
1127 | break; | |
1128 | case 0x28: /* PSSI */ | |
9492e4b2 | 1129 | qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n"); |
9ee6e8bb PB |
1130 | break; |
1131 | case 0x30: /* SAC */ | |
1132 | s->sac = value; | |
1133 | break; | |
1134 | default: | |
df3692e0 PM |
1135 | qemu_log_mask(LOG_GUEST_ERROR, |
1136 | "stellaris_adc: write at bad offset 0x%x\n", (int)offset); | |
9ee6e8bb PB |
1137 | } |
1138 | stellaris_adc_update(s); | |
1139 | } | |
1140 | ||
71a2df05 BC |
1141 | static const MemoryRegionOps stellaris_adc_ops = { |
1142 | .read = stellaris_adc_read, | |
1143 | .write = stellaris_adc_write, | |
1144 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
1145 | }; |
1146 | ||
cf1d31dc JQ |
1147 | static const VMStateDescription vmstate_stellaris_adc = { |
1148 | .name = "stellaris_adc", | |
1149 | .version_id = 1, | |
1150 | .minimum_version_id = 1, | |
8f1e884b | 1151 | .fields = (VMStateField[]) { |
cf1d31dc JQ |
1152 | VMSTATE_UINT32(actss, stellaris_adc_state), |
1153 | VMSTATE_UINT32(ris, stellaris_adc_state), | |
1154 | VMSTATE_UINT32(im, stellaris_adc_state), | |
1155 | VMSTATE_UINT32(emux, stellaris_adc_state), | |
1156 | VMSTATE_UINT32(ostat, stellaris_adc_state), | |
1157 | VMSTATE_UINT32(ustat, stellaris_adc_state), | |
1158 | VMSTATE_UINT32(sspri, stellaris_adc_state), | |
1159 | VMSTATE_UINT32(sac, stellaris_adc_state), | |
1160 | VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), | |
1161 | VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), | |
1162 | VMSTATE_UINT32(ssmux[0], stellaris_adc_state), | |
1163 | VMSTATE_UINT32(ssctl[0], stellaris_adc_state), | |
1164 | VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), | |
1165 | VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), | |
1166 | VMSTATE_UINT32(ssmux[1], stellaris_adc_state), | |
1167 | VMSTATE_UINT32(ssctl[1], stellaris_adc_state), | |
1168 | VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), | |
1169 | VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), | |
1170 | VMSTATE_UINT32(ssmux[2], stellaris_adc_state), | |
1171 | VMSTATE_UINT32(ssctl[2], stellaris_adc_state), | |
1172 | VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), | |
1173 | VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), | |
1174 | VMSTATE_UINT32(ssmux[3], stellaris_adc_state), | |
1175 | VMSTATE_UINT32(ssctl[3], stellaris_adc_state), | |
1176 | VMSTATE_UINT32(noise, stellaris_adc_state), | |
1177 | VMSTATE_END_OF_LIST() | |
23e39294 | 1178 | } |
cf1d31dc | 1179 | }; |
23e39294 | 1180 | |
15c4fff5 | 1181 | static void stellaris_adc_init(Object *obj) |
9ee6e8bb | 1182 | { |
15c4fff5 XZ |
1183 | DeviceState *dev = DEVICE(obj); |
1184 | stellaris_adc_state *s = STELLARIS_ADC(obj); | |
1185 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
2c6554bc | 1186 | int n; |
9ee6e8bb | 1187 | |
2c6554bc | 1188 | for (n = 0; n < 4; n++) { |
7df7f67a | 1189 | sysbus_init_irq(sbd, &s->irq[n]); |
2c6554bc | 1190 | } |
9ee6e8bb | 1191 | |
15c4fff5 | 1192 | memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, |
71a2df05 | 1193 | "adc", 0x1000); |
7df7f67a | 1194 | sysbus_init_mmio(sbd, &s->iomem); |
9ee6e8bb | 1195 | stellaris_adc_reset(s); |
7df7f67a | 1196 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); |
9ee6e8bb PB |
1197 | } |
1198 | ||
d69ffb5b MD |
1199 | static |
1200 | void do_sys_reset(void *opaque, int n, int level) | |
1201 | { | |
1202 | if (level) { | |
cf83f140 | 1203 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
d69ffb5b MD |
1204 | } |
1205 | } | |
1206 | ||
9ee6e8bb PB |
1207 | /* Board init. */ |
1208 | static stellaris_board_info stellaris_boards[] = { | |
1209 | { "LM3S811EVB", | |
1210 | 0, | |
1211 | 0x0032000e, | |
1212 | 0x001f001f, /* dc0 */ | |
1213 | 0x001132bf, | |
1214 | 0x01071013, | |
1215 | 0x3f0f01ff, | |
1216 | 0x0000001f, | |
cf0dbb21 | 1217 | BP_OLED_I2C |
9ee6e8bb PB |
1218 | }, |
1219 | { "LM3S6965EVB", | |
1220 | 0x10010002, | |
1221 | 0x1073402e, | |
1222 | 0x00ff007f, /* dc0 */ | |
1223 | 0x001133ff, | |
1224 | 0x030f5317, | |
1225 | 0x0f0f87ff, | |
1226 | 0x5000007f, | |
cf0dbb21 | 1227 | BP_OLED_SSI | BP_GAMEPAD |
9ee6e8bb PB |
1228 | } |
1229 | }; | |
1230 | ||
ba1ba5cc | 1231 | static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
9ee6e8bb PB |
1232 | { |
1233 | static const int uart_irq[] = {5, 6, 33, 34}; | |
1234 | static const int timer_irq[] = {19, 21, 23, 35}; | |
1235 | static const uint32_t gpio_addr[7] = | |
1236 | { 0x40004000, 0x40005000, 0x40006000, 0x40007000, | |
1237 | 0x40024000, 0x40025000, 0x40026000}; | |
1238 | static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; | |
1239 | ||
394c8bbf PM |
1240 | /* Memory map of SoC devices, from |
1241 | * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) | |
1242 | * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf | |
1243 | * | |
1244 | * 40000000 wdtimer (unimplemented) | |
1245 | * 40002000 i2c (unimplemented) | |
1246 | * 40004000 GPIO | |
1247 | * 40005000 GPIO | |
1248 | * 40006000 GPIO | |
1249 | * 40007000 GPIO | |
1250 | * 40008000 SSI | |
1251 | * 4000c000 UART | |
1252 | * 4000d000 UART | |
1253 | * 4000e000 UART | |
1254 | * 40020000 i2c | |
1255 | * 40021000 i2c (unimplemented) | |
1256 | * 40024000 GPIO | |
1257 | * 40025000 GPIO | |
1258 | * 40026000 GPIO | |
1259 | * 40028000 PWM (unimplemented) | |
1260 | * 4002c000 QEI (unimplemented) | |
1261 | * 4002d000 QEI (unimplemented) | |
1262 | * 40030000 gptimer | |
1263 | * 40031000 gptimer | |
1264 | * 40032000 gptimer | |
1265 | * 40033000 gptimer | |
1266 | * 40038000 ADC | |
1267 | * 4003c000 analogue comparator (unimplemented) | |
1268 | * 40048000 ethernet | |
1269 | * 400fc000 hibernation module (unimplemented) | |
1270 | * 400fd000 flash memory control (unimplemented) | |
1271 | * 400fe000 system control | |
1272 | */ | |
1273 | ||
20c59c38 | 1274 | DeviceState *gpio_dev[7], *nvic; |
40905a6a PB |
1275 | qemu_irq gpio_in[7][8]; |
1276 | qemu_irq gpio_out[7][8]; | |
9ee6e8bb PB |
1277 | qemu_irq adc; |
1278 | int sram_size; | |
1279 | int flash_size; | |
a5c82852 | 1280 | I2CBus *i2c; |
40905a6a | 1281 | DeviceState *dev; |
9ee6e8bb | 1282 | int i; |
40905a6a | 1283 | int j; |
9ee6e8bb | 1284 | |
fe6ac447 AF |
1285 | MemoryRegion *sram = g_new(MemoryRegion, 1); |
1286 | MemoryRegion *flash = g_new(MemoryRegion, 1); | |
1287 | MemoryRegion *system_memory = get_system_memory(); | |
1288 | ||
1289 | flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; | |
1290 | sram_size = ((board->dc0 >> 18) + 1) * 1024; | |
1291 | ||
1292 | /* Flash programming is done via the SCU, so pretend it is ROM. */ | |
98a99ce0 | 1293 | memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, |
f8ed85ac | 1294 | &error_fatal); |
fe6ac447 AF |
1295 | memory_region_set_readonly(flash, true); |
1296 | memory_region_add_subregion(system_memory, 0, flash); | |
1297 | ||
98a99ce0 | 1298 | memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, |
f8ed85ac | 1299 | &error_fatal); |
fe6ac447 AF |
1300 | memory_region_add_subregion(system_memory, 0x20000000, sram); |
1301 | ||
f04d4465 PM |
1302 | nvic = qdev_create(NULL, TYPE_ARMV7M); |
1303 | qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); | |
1304 | qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); | |
1305 | object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), | |
1306 | "memory", &error_abort); | |
1307 | /* This will exit with an error if the user passed us a bad cpu_type */ | |
1308 | qdev_init_nofail(nvic); | |
9ee6e8bb | 1309 | |
d69ffb5b MD |
1310 | qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, |
1311 | qemu_allocate_irq(&do_sys_reset, NULL, 0)); | |
1312 | ||
9ee6e8bb | 1313 | if (board->dc1 & (1 << 16)) { |
7df7f67a | 1314 | dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000, |
20c59c38 MD |
1315 | qdev_get_gpio_in(nvic, 14), |
1316 | qdev_get_gpio_in(nvic, 15), | |
1317 | qdev_get_gpio_in(nvic, 16), | |
1318 | qdev_get_gpio_in(nvic, 17), | |
1319 | NULL); | |
40905a6a | 1320 | adc = qdev_get_gpio_in(dev, 0); |
9ee6e8bb PB |
1321 | } else { |
1322 | adc = NULL; | |
1323 | } | |
1324 | for (i = 0; i < 4; i++) { | |
1325 | if (board->dc2 & (0x10000 << i)) { | |
8ef1d394 | 1326 | dev = sysbus_create_simple(TYPE_STELLARIS_GPTM, |
40905a6a | 1327 | 0x40030000 + i * 0x1000, |
20c59c38 | 1328 | qdev_get_gpio_in(nvic, timer_irq[i])); |
40905a6a PB |
1329 | /* TODO: This is incorrect, but we get away with it because |
1330 | the ADC output is only ever pulsed. */ | |
1331 | qdev_connect_gpio_out(dev, 0, adc); | |
9ee6e8bb PB |
1332 | } |
1333 | } | |
1334 | ||
20c59c38 MD |
1335 | stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), |
1336 | board, nd_table[0].macaddr.a); | |
9ee6e8bb PB |
1337 | |
1338 | for (i = 0; i < 7; i++) { | |
1339 | if (board->dc4 & (1 << i)) { | |
7063f49f | 1340 | gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], |
20c59c38 MD |
1341 | qdev_get_gpio_in(nvic, |
1342 | gpio_irq[i])); | |
40905a6a PB |
1343 | for (j = 0; j < 8; j++) { |
1344 | gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j); | |
1345 | gpio_out[i][j] = NULL; | |
1346 | } | |
9ee6e8bb PB |
1347 | } |
1348 | } | |
1349 | ||
1350 | if (board->dc2 & (1 << 12)) { | |
20c59c38 MD |
1351 | dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000, |
1352 | qdev_get_gpio_in(nvic, 8)); | |
a5c82852 | 1353 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
cf0dbb21 | 1354 | if (board->peripherals & BP_OLED_I2C) { |
d2199005 | 1355 | i2c_create_slave(i2c, "ssd0303", 0x3d); |
9ee6e8bb PB |
1356 | } |
1357 | } | |
1358 | ||
1359 | for (i = 0; i < 4; i++) { | |
1360 | if (board->dc2 & (1 << i)) { | |
f0d1d2c1 XZ |
1361 | pl011_luminary_create(0x4000c000 + i * 0x1000, |
1362 | qdev_get_gpio_in(nvic, uart_irq[i]), | |
9bca0edb | 1363 | serial_hd(i)); |
9ee6e8bb PB |
1364 | } |
1365 | } | |
1366 | if (board->dc2 & (1 << 4)) { | |
20c59c38 MD |
1367 | dev = sysbus_create_simple("pl022", 0x40008000, |
1368 | qdev_get_gpio_in(nvic, 7)); | |
cf0dbb21 | 1369 | if (board->peripherals & BP_OLED_SSI) { |
5493e33f | 1370 | void *bus; |
8120e714 PC |
1371 | DeviceState *sddev; |
1372 | DeviceState *ssddev; | |
1373 | ||
1374 | /* Some boards have both an OLED controller and SD card connected to | |
1375 | * the same SSI port, with the SD card chip select connected to a | |
1376 | * GPIO pin. Technically the OLED chip select is connected to the | |
1377 | * SSI Fss pin. We do not bother emulating that as both devices | |
1378 | * should never be selected simultaneously, and our OLED controller | |
1379 | * ignores stray 0xff commands that occur when deselecting the SD | |
1380 | * card. | |
1381 | */ | |
5493e33f | 1382 | bus = qdev_get_child_bus(dev, "ssi"); |
5493e33f | 1383 | |
8120e714 PC |
1384 | sddev = ssi_create_slave(bus, "ssi-sd"); |
1385 | ssddev = ssi_create_slave(bus, "ssd0323"); | |
de77914e PC |
1386 | gpio_out[GPIO_D][0] = qemu_irq_split( |
1387 | qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), | |
1388 | qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); | |
1389 | gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0); | |
775616c3 | 1390 | |
775616c3 PB |
1391 | /* Make sure the select pin is high. */ |
1392 | qemu_irq_raise(gpio_out[GPIO_D][0]); | |
9ee6e8bb PB |
1393 | } |
1394 | } | |
a5580466 PB |
1395 | if (board->dc4 & (1 << 28)) { |
1396 | DeviceState *enet; | |
1397 | ||
1398 | qemu_check_nic_model(&nd_table[0], "stellaris"); | |
1399 | ||
1400 | enet = qdev_create(NULL, "stellaris_enet"); | |
540f006a | 1401 | qdev_set_nic_properties(enet, &nd_table[0]); |
e23a1b33 | 1402 | qdev_init_nofail(enet); |
1356b98d | 1403 | sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000); |
20c59c38 | 1404 | sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42)); |
a5580466 | 1405 | } |
cf0dbb21 PB |
1406 | if (board->peripherals & BP_GAMEPAD) { |
1407 | qemu_irq gpad_irq[5]; | |
1408 | static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d }; | |
1409 | ||
1410 | gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */ | |
1411 | gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */ | |
1412 | gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */ | |
1413 | gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */ | |
1414 | gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */ | |
1415 | ||
1416 | stellaris_gamepad_init(5, gpad_irq, gpad_keycode); | |
1417 | } | |
40905a6a PB |
1418 | for (i = 0; i < 7; i++) { |
1419 | if (board->dc4 & (1 << i)) { | |
1420 | for (j = 0; j < 8; j++) { | |
1421 | if (gpio_out[i][j]) { | |
1422 | qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]); | |
1423 | } | |
1424 | } | |
1425 | } | |
1426 | } | |
aecfbbc9 PM |
1427 | |
1428 | /* Add dummy regions for the devices we don't implement yet, | |
1429 | * so guest accesses don't cause unlogged crashes. | |
1430 | */ | |
1431 | create_unimplemented_device("wdtimer", 0x40000000, 0x1000); | |
1432 | create_unimplemented_device("i2c-0", 0x40002000, 0x1000); | |
1433 | create_unimplemented_device("i2c-2", 0x40021000, 0x1000); | |
1434 | create_unimplemented_device("PWM", 0x40028000, 0x1000); | |
1435 | create_unimplemented_device("QEI-0", 0x4002c000, 0x1000); | |
1436 | create_unimplemented_device("QEI-1", 0x4002d000, 0x1000); | |
1437 | create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); | |
1438 | create_unimplemented_device("hibernation", 0x400fc000, 0x1000); | |
1439 | create_unimplemented_device("flash-control", 0x400fd000, 0x1000); | |
f04d4465 PM |
1440 | |
1441 | armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); | |
9ee6e8bb PB |
1442 | } |
1443 | ||
1444 | /* FIXME: Figure out how to generate these from stellaris_boards. */ | |
3ef96221 | 1445 | static void lm3s811evb_init(MachineState *machine) |
9ee6e8bb | 1446 | { |
ba1ba5cc | 1447 | stellaris_init(machine, &stellaris_boards[0]); |
9ee6e8bb PB |
1448 | } |
1449 | ||
3ef96221 | 1450 | static void lm3s6965evb_init(MachineState *machine) |
9ee6e8bb | 1451 | { |
ba1ba5cc | 1452 | stellaris_init(machine, &stellaris_boards[1]); |
9ee6e8bb PB |
1453 | } |
1454 | ||
8a661aea | 1455 | static void lm3s811evb_class_init(ObjectClass *oc, void *data) |
e264d29d | 1456 | { |
8a661aea AF |
1457 | MachineClass *mc = MACHINE_CLASS(oc); |
1458 | ||
e264d29d EH |
1459 | mc->desc = "Stellaris LM3S811EVB"; |
1460 | mc->init = lm3s811evb_init; | |
4672cbd7 | 1461 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 1462 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
e264d29d | 1463 | } |
9ee6e8bb | 1464 | |
8a661aea AF |
1465 | static const TypeInfo lm3s811evb_type = { |
1466 | .name = MACHINE_TYPE_NAME("lm3s811evb"), | |
1467 | .parent = TYPE_MACHINE, | |
1468 | .class_init = lm3s811evb_class_init, | |
1469 | }; | |
1de9610c | 1470 | |
8a661aea | 1471 | static void lm3s6965evb_class_init(ObjectClass *oc, void *data) |
f80f9ec9 | 1472 | { |
8a661aea AF |
1473 | MachineClass *mc = MACHINE_CLASS(oc); |
1474 | ||
e264d29d EH |
1475 | mc->desc = "Stellaris LM3S6965EVB"; |
1476 | mc->init = lm3s6965evb_init; | |
4672cbd7 | 1477 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 1478 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); |
f80f9ec9 AL |
1479 | } |
1480 | ||
8a661aea AF |
1481 | static const TypeInfo lm3s6965evb_type = { |
1482 | .name = MACHINE_TYPE_NAME("lm3s6965evb"), | |
1483 | .parent = TYPE_MACHINE, | |
1484 | .class_init = lm3s6965evb_class_init, | |
1485 | }; | |
1486 | ||
1487 | static void stellaris_machine_init(void) | |
1488 | { | |
1489 | type_register_static(&lm3s811evb_type); | |
1490 | type_register_static(&lm3s6965evb_type); | |
1491 | } | |
1492 | ||
0e6aac87 | 1493 | type_init(stellaris_machine_init) |
f80f9ec9 | 1494 | |
999e12bb AL |
1495 | static void stellaris_i2c_class_init(ObjectClass *klass, void *data) |
1496 | { | |
15c4fff5 | 1497 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1498 | |
15c4fff5 | 1499 | dc->vmsd = &vmstate_stellaris_i2c; |
999e12bb AL |
1500 | } |
1501 | ||
8c43a6f0 | 1502 | static const TypeInfo stellaris_i2c_info = { |
d94a4015 | 1503 | .name = TYPE_STELLARIS_I2C, |
39bffca2 AL |
1504 | .parent = TYPE_SYS_BUS_DEVICE, |
1505 | .instance_size = sizeof(stellaris_i2c_state), | |
15c4fff5 | 1506 | .instance_init = stellaris_i2c_init, |
39bffca2 | 1507 | .class_init = stellaris_i2c_class_init, |
999e12bb AL |
1508 | }; |
1509 | ||
1510 | static void stellaris_gptm_class_init(ObjectClass *klass, void *data) | |
1511 | { | |
15c4fff5 | 1512 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1513 | |
15c4fff5 | 1514 | dc->vmsd = &vmstate_stellaris_gptm; |
999e12bb AL |
1515 | } |
1516 | ||
8c43a6f0 | 1517 | static const TypeInfo stellaris_gptm_info = { |
8ef1d394 | 1518 | .name = TYPE_STELLARIS_GPTM, |
39bffca2 AL |
1519 | .parent = TYPE_SYS_BUS_DEVICE, |
1520 | .instance_size = sizeof(gptm_state), | |
15c4fff5 | 1521 | .instance_init = stellaris_gptm_init, |
39bffca2 | 1522 | .class_init = stellaris_gptm_class_init, |
999e12bb AL |
1523 | }; |
1524 | ||
1525 | static void stellaris_adc_class_init(ObjectClass *klass, void *data) | |
1526 | { | |
15c4fff5 | 1527 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1528 | |
15c4fff5 | 1529 | dc->vmsd = &vmstate_stellaris_adc; |
999e12bb AL |
1530 | } |
1531 | ||
8c43a6f0 | 1532 | static const TypeInfo stellaris_adc_info = { |
7df7f67a | 1533 | .name = TYPE_STELLARIS_ADC, |
39bffca2 AL |
1534 | .parent = TYPE_SYS_BUS_DEVICE, |
1535 | .instance_size = sizeof(stellaris_adc_state), | |
15c4fff5 | 1536 | .instance_init = stellaris_adc_init, |
39bffca2 | 1537 | .class_init = stellaris_adc_class_init, |
999e12bb AL |
1538 | }; |
1539 | ||
83f7d43a | 1540 | static void stellaris_register_types(void) |
1de9610c | 1541 | { |
39bffca2 AL |
1542 | type_register_static(&stellaris_i2c_info); |
1543 | type_register_static(&stellaris_gptm_info); | |
1544 | type_register_static(&stellaris_adc_info); | |
1de9610c PB |
1545 | } |
1546 | ||
83f7d43a | 1547 | type_init(stellaris_register_types) |