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db635521 AF |
1 | /* |
2 | * STM32F205 SoC | |
3 | * | |
4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
12b16722 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
12ec8bd5 | 28 | #include "hw/arm/boot.h" |
db635521 AF |
29 | #include "exec/address-spaces.h" |
30 | #include "hw/arm/stm32f205_soc.h" | |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
68ba05fb | 32 | #include "hw/qdev-clock.h" |
46517dd4 | 33 | #include "sysemu/sysemu.h" |
db635521 AF |
34 | |
35 | /* At the moment only Timer 2 to 5 are modelled */ | |
36 | static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, | |
37 | 0x40000800, 0x40000C00 }; | |
38 | static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, | |
39 | 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; | |
b63041c8 AF |
40 | static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, |
41 | 0x40012200 }; | |
540a8f34 AF |
42 | static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, |
43 | 0x40003C00 }; | |
db635521 AF |
44 | |
45 | static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; | |
46 | static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; | |
b63041c8 | 47 | #define ADC_IRQ 18 |
540a8f34 | 48 | static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; |
db635521 AF |
49 | |
50 | static void stm32f205_soc_initfn(Object *obj) | |
51 | { | |
52 | STM32F205State *s = STM32F205_SOC(obj); | |
53 | int i; | |
54 | ||
db873cc5 | 55 | object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); |
b72e2f68 | 56 | |
db873cc5 | 57 | object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); |
db635521 AF |
58 | |
59 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
db873cc5 MA |
60 | object_initialize_child(obj, "usart[*]", &s->usart[i], |
61 | TYPE_STM32F2XX_USART); | |
db635521 AF |
62 | } |
63 | ||
64 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
db873cc5 MA |
65 | object_initialize_child(obj, "timer[*]", &s->timer[i], |
66 | TYPE_STM32F2XX_TIMER); | |
db635521 | 67 | } |
b63041c8 AF |
68 | |
69 | s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); | |
70 | ||
71 | for (i = 0; i < STM_NUM_ADCS; i++) { | |
db873cc5 | 72 | object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); |
b63041c8 | 73 | } |
540a8f34 AF |
74 | |
75 | for (i = 0; i < STM_NUM_SPIS; i++) { | |
db873cc5 | 76 | object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); |
540a8f34 | 77 | } |
68ba05fb PM |
78 | |
79 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); | |
80 | s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); | |
db635521 AF |
81 | } |
82 | ||
83 | static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | |
84 | { | |
85 | STM32F205State *s = STM32F205_SOC(dev_soc); | |
8a85e065 | 86 | DeviceState *dev, *armv7m; |
81fed1d0 | 87 | SysBusDevice *busdev; |
db635521 AF |
88 | int i; |
89 | ||
90 | MemoryRegion *system_memory = get_system_memory(); | |
db635521 | 91 | |
68ba05fb PM |
92 | /* |
93 | * We use s->refclk internally and only define it with qdev_init_clock_in() | |
94 | * so it is correctly parented and not leaked on an init/deinit; it is not | |
95 | * intended as an externally exposed clock. | |
96 | */ | |
97 | if (clock_has_source(s->refclk)) { | |
98 | error_setg(errp, "refclk clock must not be wired up by the board code"); | |
99 | return; | |
100 | } | |
101 | ||
102 | if (!clock_has_source(s->sysclk)) { | |
103 | error_setg(errp, "sysclk clock must be wired up by the board code"); | |
104 | return; | |
105 | } | |
106 | ||
107 | /* | |
108 | * TODO: ideally we should model the SoC RCC and its ability to | |
109 | * change the sysclk frequency and define different sysclk sources. | |
110 | */ | |
111 | ||
112 | /* The refclk always runs at frequency HCLK / 8 */ | |
113 | clock_set_mul_div(s->refclk, 8, 1); | |
114 | clock_set_source(s->refclk, s->sysclk); | |
115 | ||
cabc613f | 116 | memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash", |
32b9523a | 117 | FLASH_SIZE, &error_fatal); |
cabc613f PM |
118 | memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), |
119 | "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE); | |
db635521 | 120 | |
cabc613f PM |
121 | memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash); |
122 | memory_region_add_subregion(system_memory, 0, &s->flash_alias); | |
db635521 | 123 | |
cabc613f | 124 | memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE, |
f8ed85ac | 125 | &error_fatal); |
cabc613f | 126 | memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); |
db635521 | 127 | |
8a85e065 PM |
128 | armv7m = DEVICE(&s->armv7m); |
129 | qdev_prop_set_uint32(armv7m, "num-irq", 96); | |
4a04655c | 130 | qdev_prop_set_uint8(armv7m, "num-prio-bits", 4); |
ff6cda35 | 131 | qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); |
a1c5a062 | 132 | qdev_prop_set_bit(armv7m, "enable-bitband", true); |
68ba05fb PM |
133 | qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); |
134 | qdev_connect_clock_in(armv7m, "refclk", s->refclk); | |
5325cc34 MA |
135 | object_property_set_link(OBJECT(&s->armv7m), "memory", |
136 | OBJECT(get_system_memory()), &error_abort); | |
668f62ec | 137 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { |
b72e2f68 PM |
138 | return; |
139 | } | |
db635521 AF |
140 | |
141 | /* System configuration controller */ | |
81fed1d0 | 142 | dev = DEVICE(&s->syscfg); |
668f62ec | 143 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { |
db635521 AF |
144 | return; |
145 | } | |
81fed1d0 AF |
146 | busdev = SYS_BUS_DEVICE(dev); |
147 | sysbus_mmio_map(busdev, 0, 0x40013800); | |
db635521 AF |
148 | |
149 | /* Attach UART (uses USART registers) and USART controllers */ | |
150 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
81fed1d0 | 151 | dev = DEVICE(&(s->usart[i])); |
fc38a112 | 152 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
668f62ec | 153 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { |
db635521 AF |
154 | return; |
155 | } | |
81fed1d0 AF |
156 | busdev = SYS_BUS_DEVICE(dev); |
157 | sysbus_mmio_map(busdev, 0, usart_addr[i]); | |
8a85e065 | 158 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); |
db635521 AF |
159 | } |
160 | ||
161 | /* Timer 2 to 5 */ | |
162 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
81fed1d0 AF |
163 | dev = DEVICE(&(s->timer[i])); |
164 | qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); | |
668f62ec | 165 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { |
db635521 AF |
166 | return; |
167 | } | |
81fed1d0 AF |
168 | busdev = SYS_BUS_DEVICE(dev); |
169 | sysbus_mmio_map(busdev, 0, timer_addr[i]); | |
8a85e065 | 170 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); |
db635521 | 171 | } |
b63041c8 AF |
172 | |
173 | /* ADC 1 to 3 */ | |
5325cc34 MA |
174 | object_property_set_int(OBJECT(s->adc_irqs), "num-lines", STM_NUM_ADCS, |
175 | &error_abort); | |
668f62ec | 176 | if (!qdev_realize(DEVICE(s->adc_irqs), NULL, errp)) { |
b63041c8 AF |
177 | return; |
178 | } | |
179 | qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, | |
8a85e065 | 180 | qdev_get_gpio_in(armv7m, ADC_IRQ)); |
b63041c8 AF |
181 | |
182 | for (i = 0; i < STM_NUM_ADCS; i++) { | |
183 | dev = DEVICE(&(s->adc[i])); | |
668f62ec | 184 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) { |
b63041c8 AF |
185 | return; |
186 | } | |
187 | busdev = SYS_BUS_DEVICE(dev); | |
188 | sysbus_mmio_map(busdev, 0, adc_addr[i]); | |
189 | sysbus_connect_irq(busdev, 0, | |
190 | qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); | |
191 | } | |
540a8f34 AF |
192 | |
193 | /* SPI 1 and 2 */ | |
194 | for (i = 0; i < STM_NUM_SPIS; i++) { | |
195 | dev = DEVICE(&(s->spi[i])); | |
668f62ec | 196 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
540a8f34 AF |
197 | return; |
198 | } | |
199 | busdev = SYS_BUS_DEVICE(dev); | |
200 | sysbus_mmio_map(busdev, 0, spi_addr[i]); | |
8a85e065 | 201 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); |
540a8f34 | 202 | } |
db635521 AF |
203 | } |
204 | ||
db635521 AF |
205 | static void stm32f205_soc_class_init(ObjectClass *klass, void *data) |
206 | { | |
207 | DeviceClass *dc = DEVICE_CLASS(klass); | |
208 | ||
209 | dc->realize = stm32f205_soc_realize; | |
ff6cda35 | 210 | /* No vmstate or reset required: device has no internal state */ |
db635521 AF |
211 | } |
212 | ||
213 | static const TypeInfo stm32f205_soc_info = { | |
214 | .name = TYPE_STM32F205_SOC, | |
215 | .parent = TYPE_SYS_BUS_DEVICE, | |
216 | .instance_size = sizeof(STM32F205State), | |
217 | .instance_init = stm32f205_soc_initfn, | |
218 | .class_init = stm32f205_soc_class_init, | |
219 | }; | |
220 | ||
221 | static void stm32f205_soc_types(void) | |
222 | { | |
223 | type_register_static(&stm32f205_soc_info); | |
224 | } | |
225 | ||
226 | type_init(stm32f205_soc_types) |