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db635521 AF |
1 | /* |
2 | * STM32F205 SoC | |
3 | * | |
4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
12b16722 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
4771d756 | 27 | #include "qemu-common.h" |
db635521 AF |
28 | #include "hw/arm/arm.h" |
29 | #include "exec/address-spaces.h" | |
30 | #include "hw/arm/stm32f205_soc.h" | |
31 | ||
32 | /* At the moment only Timer 2 to 5 are modelled */ | |
33 | static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, | |
34 | 0x40000800, 0x40000C00 }; | |
35 | static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, | |
36 | 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; | |
37 | ||
38 | static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; | |
39 | static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; | |
40 | ||
41 | static void stm32f205_soc_initfn(Object *obj) | |
42 | { | |
43 | STM32F205State *s = STM32F205_SOC(obj); | |
44 | int i; | |
45 | ||
46 | object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); | |
47 | qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); | |
48 | ||
49 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
50 | object_initialize(&s->usart[i], sizeof(s->usart[i]), | |
51 | TYPE_STM32F2XX_USART); | |
52 | qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); | |
53 | } | |
54 | ||
55 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
56 | object_initialize(&s->timer[i], sizeof(s->timer[i]), | |
57 | TYPE_STM32F2XX_TIMER); | |
58 | qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); | |
59 | } | |
60 | } | |
61 | ||
62 | static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | |
63 | { | |
64 | STM32F205State *s = STM32F205_SOC(dev_soc); | |
20c59c38 | 65 | DeviceState *syscfgdev, *usartdev, *timerdev, *nvic; |
db635521 | 66 | SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev; |
db635521 AF |
67 | Error *err = NULL; |
68 | int i; | |
69 | ||
70 | MemoryRegion *system_memory = get_system_memory(); | |
71 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
72 | MemoryRegion *flash = g_new(MemoryRegion, 1); | |
73 | MemoryRegion *flash_alias = g_new(MemoryRegion, 1); | |
74 | ||
75 | memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, | |
f8ed85ac | 76 | &error_fatal); |
db635521 AF |
77 | memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", |
78 | flash, 0, FLASH_SIZE); | |
79 | ||
80 | vmstate_register_ram_global(flash); | |
81 | ||
82 | memory_region_set_readonly(flash, true); | |
83 | memory_region_set_readonly(flash_alias, true); | |
84 | ||
85 | memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); | |
86 | memory_region_add_subregion(system_memory, 0, flash_alias); | |
87 | ||
88 | memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, | |
f8ed85ac | 89 | &error_fatal); |
db635521 AF |
90 | vmstate_register_ram_global(sram); |
91 | memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); | |
92 | ||
20c59c38 MD |
93 | nvic = armv7m_init(get_system_memory(), FLASH_SIZE, 96, |
94 | s->kernel_filename, s->cpu_model); | |
db635521 AF |
95 | |
96 | /* System configuration controller */ | |
97 | syscfgdev = DEVICE(&s->syscfg); | |
98 | object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); | |
99 | if (err != NULL) { | |
100 | error_propagate(errp, err); | |
101 | return; | |
102 | } | |
103 | syscfgbusdev = SYS_BUS_DEVICE(syscfgdev); | |
104 | sysbus_mmio_map(syscfgbusdev, 0, 0x40013800); | |
20c59c38 | 105 | sysbus_connect_irq(syscfgbusdev, 0, qdev_get_gpio_in(nvic, 71)); |
db635521 AF |
106 | |
107 | /* Attach UART (uses USART registers) and USART controllers */ | |
108 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
109 | usartdev = DEVICE(&(s->usart[i])); | |
7bd43519 | 110 | qdev_prop_set_chr(usartdev, "chardev", i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL); |
db635521 AF |
111 | object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); |
112 | if (err != NULL) { | |
113 | error_propagate(errp, err); | |
114 | return; | |
115 | } | |
116 | usartbusdev = SYS_BUS_DEVICE(usartdev); | |
117 | sysbus_mmio_map(usartbusdev, 0, usart_addr[i]); | |
20c59c38 MD |
118 | sysbus_connect_irq(usartbusdev, 0, |
119 | qdev_get_gpio_in(nvic, usart_irq[i])); | |
db635521 AF |
120 | } |
121 | ||
122 | /* Timer 2 to 5 */ | |
123 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
124 | timerdev = DEVICE(&(s->timer[i])); | |
125 | qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000); | |
126 | object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); | |
127 | if (err != NULL) { | |
128 | error_propagate(errp, err); | |
129 | return; | |
130 | } | |
131 | timerbusdev = SYS_BUS_DEVICE(timerdev); | |
132 | sysbus_mmio_map(timerbusdev, 0, timer_addr[i]); | |
20c59c38 MD |
133 | sysbus_connect_irq(timerbusdev, 0, |
134 | qdev_get_gpio_in(nvic, timer_irq[i])); | |
db635521 AF |
135 | } |
136 | } | |
137 | ||
138 | static Property stm32f205_soc_properties[] = { | |
139 | DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename), | |
140 | DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model), | |
141 | DEFINE_PROP_END_OF_LIST(), | |
142 | }; | |
143 | ||
144 | static void stm32f205_soc_class_init(ObjectClass *klass, void *data) | |
145 | { | |
146 | DeviceClass *dc = DEVICE_CLASS(klass); | |
147 | ||
148 | dc->realize = stm32f205_soc_realize; | |
149 | dc->props = stm32f205_soc_properties; | |
150 | } | |
151 | ||
152 | static const TypeInfo stm32f205_soc_info = { | |
153 | .name = TYPE_STM32F205_SOC, | |
154 | .parent = TYPE_SYS_BUS_DEVICE, | |
155 | .instance_size = sizeof(STM32F205State), | |
156 | .instance_init = stm32f205_soc_initfn, | |
157 | .class_init = stm32f205_soc_class_init, | |
158 | }; | |
159 | ||
160 | static void stm32f205_soc_types(void) | |
161 | { | |
162 | type_register_static(&stm32f205_soc_info); | |
163 | } | |
164 | ||
165 | type_init(stm32f205_soc_types) |