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db635521 AF |
1 | /* |
2 | * STM32F205 SoC | |
3 | * | |
4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
12b16722 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
12ec8bd5 | 28 | #include "hw/arm/boot.h" |
db635521 AF |
29 | #include "exec/address-spaces.h" |
30 | #include "hw/arm/stm32f205_soc.h" | |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
46517dd4 | 32 | #include "sysemu/sysemu.h" |
db635521 AF |
33 | |
34 | /* At the moment only Timer 2 to 5 are modelled */ | |
35 | static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, | |
36 | 0x40000800, 0x40000C00 }; | |
37 | static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, | |
38 | 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; | |
b63041c8 AF |
39 | static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, |
40 | 0x40012200 }; | |
540a8f34 AF |
41 | static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, |
42 | 0x40003C00 }; | |
db635521 AF |
43 | |
44 | static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; | |
45 | static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; | |
b63041c8 | 46 | #define ADC_IRQ 18 |
540a8f34 | 47 | static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; |
db635521 AF |
48 | |
49 | static void stm32f205_soc_initfn(Object *obj) | |
50 | { | |
51 | STM32F205State *s = STM32F205_SOC(obj); | |
52 | int i; | |
53 | ||
db873cc5 | 54 | object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); |
b72e2f68 | 55 | |
db873cc5 | 56 | object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F2XX_SYSCFG); |
db635521 AF |
57 | |
58 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
db873cc5 MA |
59 | object_initialize_child(obj, "usart[*]", &s->usart[i], |
60 | TYPE_STM32F2XX_USART); | |
db635521 AF |
61 | } |
62 | ||
63 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
db873cc5 MA |
64 | object_initialize_child(obj, "timer[*]", &s->timer[i], |
65 | TYPE_STM32F2XX_TIMER); | |
db635521 | 66 | } |
b63041c8 AF |
67 | |
68 | s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); | |
69 | ||
70 | for (i = 0; i < STM_NUM_ADCS; i++) { | |
db873cc5 | 71 | object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC); |
b63041c8 | 72 | } |
540a8f34 AF |
73 | |
74 | for (i = 0; i < STM_NUM_SPIS; i++) { | |
db873cc5 | 75 | object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI); |
540a8f34 | 76 | } |
db635521 AF |
77 | } |
78 | ||
79 | static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | |
80 | { | |
81 | STM32F205State *s = STM32F205_SOC(dev_soc); | |
8a85e065 | 82 | DeviceState *dev, *armv7m; |
81fed1d0 | 83 | SysBusDevice *busdev; |
db635521 AF |
84 | Error *err = NULL; |
85 | int i; | |
86 | ||
87 | MemoryRegion *system_memory = get_system_memory(); | |
88 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
89 | MemoryRegion *flash = g_new(MemoryRegion, 1); | |
90 | MemoryRegion *flash_alias = g_new(MemoryRegion, 1); | |
91 | ||
32b9523a PMD |
92 | memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash", |
93 | FLASH_SIZE, &error_fatal); | |
94 | memory_region_init_alias(flash_alias, OBJECT(dev_soc), | |
95 | "STM32F205.flash.alias", flash, 0, FLASH_SIZE); | |
db635521 AF |
96 | |
97 | memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); | |
98 | memory_region_add_subregion(system_memory, 0, flash_alias); | |
99 | ||
98a99ce0 | 100 | memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, |
f8ed85ac | 101 | &error_fatal); |
db635521 AF |
102 | memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); |
103 | ||
8a85e065 PM |
104 | armv7m = DEVICE(&s->armv7m); |
105 | qdev_prop_set_uint32(armv7m, "num-irq", 96); | |
ba1ba5cc | 106 | qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); |
a1c5a062 | 107 | qdev_prop_set_bit(armv7m, "enable-bitband", true); |
b72e2f68 PM |
108 | object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), |
109 | "memory", &error_abort); | |
db873cc5 | 110 | sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &err); |
b72e2f68 PM |
111 | if (err != NULL) { |
112 | error_propagate(errp, err); | |
113 | return; | |
114 | } | |
db635521 AF |
115 | |
116 | /* System configuration controller */ | |
81fed1d0 | 117 | dev = DEVICE(&s->syscfg); |
db873cc5 | 118 | sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), &err); |
db635521 AF |
119 | if (err != NULL) { |
120 | error_propagate(errp, err); | |
121 | return; | |
122 | } | |
81fed1d0 AF |
123 | busdev = SYS_BUS_DEVICE(dev); |
124 | sysbus_mmio_map(busdev, 0, 0x40013800); | |
8a85e065 | 125 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); |
db635521 AF |
126 | |
127 | /* Attach UART (uses USART registers) and USART controllers */ | |
128 | for (i = 0; i < STM_NUM_USARTS; i++) { | |
81fed1d0 | 129 | dev = DEVICE(&(s->usart[i])); |
fc38a112 | 130 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
db873cc5 | 131 | sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), &err); |
db635521 AF |
132 | if (err != NULL) { |
133 | error_propagate(errp, err); | |
134 | return; | |
135 | } | |
81fed1d0 AF |
136 | busdev = SYS_BUS_DEVICE(dev); |
137 | sysbus_mmio_map(busdev, 0, usart_addr[i]); | |
8a85e065 | 138 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i])); |
db635521 AF |
139 | } |
140 | ||
141 | /* Timer 2 to 5 */ | |
142 | for (i = 0; i < STM_NUM_TIMERS; i++) { | |
81fed1d0 AF |
143 | dev = DEVICE(&(s->timer[i])); |
144 | qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); | |
db873cc5 | 145 | sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), &err); |
db635521 AF |
146 | if (err != NULL) { |
147 | error_propagate(errp, err); | |
148 | return; | |
149 | } | |
81fed1d0 AF |
150 | busdev = SYS_BUS_DEVICE(dev); |
151 | sysbus_mmio_map(busdev, 0, timer_addr[i]); | |
8a85e065 | 152 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i])); |
db635521 | 153 | } |
b63041c8 AF |
154 | |
155 | /* ADC 1 to 3 */ | |
156 | object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, | |
b4018194 | 157 | "num-lines", &error_abort); |
ce189ab2 | 158 | qdev_realize(DEVICE(s->adc_irqs), NULL, &err); |
b63041c8 AF |
159 | if (err != NULL) { |
160 | error_propagate(errp, err); | |
161 | return; | |
162 | } | |
163 | qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, | |
8a85e065 | 164 | qdev_get_gpio_in(armv7m, ADC_IRQ)); |
b63041c8 AF |
165 | |
166 | for (i = 0; i < STM_NUM_ADCS; i++) { | |
167 | dev = DEVICE(&(s->adc[i])); | |
db873cc5 | 168 | sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), &err); |
b63041c8 AF |
169 | if (err != NULL) { |
170 | error_propagate(errp, err); | |
171 | return; | |
172 | } | |
173 | busdev = SYS_BUS_DEVICE(dev); | |
174 | sysbus_mmio_map(busdev, 0, adc_addr[i]); | |
175 | sysbus_connect_irq(busdev, 0, | |
176 | qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); | |
177 | } | |
540a8f34 AF |
178 | |
179 | /* SPI 1 and 2 */ | |
180 | for (i = 0; i < STM_NUM_SPIS; i++) { | |
181 | dev = DEVICE(&(s->spi[i])); | |
db873cc5 | 182 | sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err); |
540a8f34 AF |
183 | if (err != NULL) { |
184 | error_propagate(errp, err); | |
185 | return; | |
186 | } | |
187 | busdev = SYS_BUS_DEVICE(dev); | |
188 | sysbus_mmio_map(busdev, 0, spi_addr[i]); | |
8a85e065 | 189 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])); |
540a8f34 | 190 | } |
db635521 AF |
191 | } |
192 | ||
193 | static Property stm32f205_soc_properties[] = { | |
ba1ba5cc | 194 | DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type), |
db635521 AF |
195 | DEFINE_PROP_END_OF_LIST(), |
196 | }; | |
197 | ||
198 | static void stm32f205_soc_class_init(ObjectClass *klass, void *data) | |
199 | { | |
200 | DeviceClass *dc = DEVICE_CLASS(klass); | |
201 | ||
202 | dc->realize = stm32f205_soc_realize; | |
4f67d30b | 203 | device_class_set_props(dc, stm32f205_soc_properties); |
db635521 AF |
204 | } |
205 | ||
206 | static const TypeInfo stm32f205_soc_info = { | |
207 | .name = TYPE_STM32F205_SOC, | |
208 | .parent = TYPE_SYS_BUS_DEVICE, | |
209 | .instance_size = sizeof(STM32F205State), | |
210 | .instance_init = stm32f205_soc_initfn, | |
211 | .class_init = stm32f205_soc_class_init, | |
212 | }; | |
213 | ||
214 | static void stm32f205_soc_types(void) | |
215 | { | |
216 | type_register_static(&stm32f205_soc_info); | |
217 | } | |
218 | ||
219 | type_init(stm32f205_soc_types) |