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Commit | Line | Data |
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5fafdf24 | 1 | /* |
16406950 | 2 | * ARM Versatile Platform/Application Baseboard System emulation. |
cdbdb648 | 3 | * |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
cdbdb648 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
12b16722 | 10 | #include "qemu/osdep.h" |
da34e65c | 11 | #include "qapi/error.h" |
4771d756 | 12 | #include "cpu.h" |
83c9f4ca | 13 | #include "hw/sysbus.h" |
12ec8bd5 | 14 | #include "hw/arm/boot.h" |
437cc27d | 15 | #include "hw/net/smc91c111.h" |
1422e32d | 16 | #include "net/net.h" |
9c17d615 | 17 | #include "sysemu/sysemu.h" |
83c9f4ca | 18 | #include "hw/pci/pci.h" |
0d09e41a | 19 | #include "hw/i2c/i2c.h" |
83c9f4ca | 20 | #include "hw/boards.h" |
022c62cb | 21 | #include "exec/address-spaces.h" |
0d09e41a | 22 | #include "hw/block/flash.h" |
223a72f1 | 23 | #include "qemu/error-report.h" |
f0d1d2c1 | 24 | #include "hw/char/pl011.h" |
964c695a EB |
25 | |
26 | #define VERSATILE_FLASH_ADDR 0x34000000 | |
27 | #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) | |
28 | #define VERSATILE_FLASH_SECT_SIZE (256 * 1024) | |
cdbdb648 | 29 | |
cdbdb648 PB |
30 | /* Primary interrupt controller. */ |
31 | ||
cfc6b245 AF |
32 | #define TYPE_VERSATILE_PB_SIC "versatilepb_sic" |
33 | #define VERSATILE_PB_SIC(obj) \ | |
34 | OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC) | |
35 | ||
36 | typedef struct vpb_sic_state { | |
37 | SysBusDevice parent_obj; | |
38 | ||
39 | MemoryRegion iomem; | |
40 | uint32_t level; | |
41 | uint32_t mask; | |
42 | uint32_t pic_enable; | |
43 | qemu_irq parent[32]; | |
44 | int irq; | |
cdbdb648 PB |
45 | } vpb_sic_state; |
46 | ||
a796d0ac PM |
47 | static const VMStateDescription vmstate_vpb_sic = { |
48 | .name = "versatilepb_sic", | |
49 | .version_id = 1, | |
50 | .minimum_version_id = 1, | |
51 | .fields = (VMStateField[]) { | |
52 | VMSTATE_UINT32(level, vpb_sic_state), | |
53 | VMSTATE_UINT32(mask, vpb_sic_state), | |
54 | VMSTATE_UINT32(pic_enable, vpb_sic_state), | |
55 | VMSTATE_END_OF_LIST() | |
56 | } | |
57 | }; | |
58 | ||
cdbdb648 PB |
59 | static void vpb_sic_update(vpb_sic_state *s) |
60 | { | |
61 | uint32_t flags; | |
62 | ||
63 | flags = s->level & s->mask; | |
d537cf6c | 64 | qemu_set_irq(s->parent[s->irq], flags != 0); |
cdbdb648 PB |
65 | } |
66 | ||
67 | static void vpb_sic_update_pic(vpb_sic_state *s) | |
68 | { | |
69 | int i; | |
70 | uint32_t mask; | |
71 | ||
72 | for (i = 21; i <= 30; i++) { | |
73 | mask = 1u << i; | |
74 | if (!(s->pic_enable & mask)) | |
75 | continue; | |
d537cf6c | 76 | qemu_set_irq(s->parent[i], (s->level & mask) != 0); |
cdbdb648 PB |
77 | } |
78 | } | |
79 | ||
80 | static void vpb_sic_set_irq(void *opaque, int irq, int level) | |
81 | { | |
82 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
83 | if (level) | |
84 | s->level |= 1u << irq; | |
85 | else | |
86 | s->level &= ~(1u << irq); | |
87 | if (s->pic_enable & (1u << irq)) | |
d537cf6c | 88 | qemu_set_irq(s->parent[irq], level); |
cdbdb648 PB |
89 | vpb_sic_update(s); |
90 | } | |
91 | ||
a8170e5e | 92 | static uint64_t vpb_sic_read(void *opaque, hwaddr offset, |
62ceeb2c | 93 | unsigned size) |
cdbdb648 PB |
94 | { |
95 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
96 | ||
cdbdb648 PB |
97 | switch (offset >> 2) { |
98 | case 0: /* STATUS */ | |
99 | return s->level & s->mask; | |
100 | case 1: /* RAWSTAT */ | |
101 | return s->level; | |
102 | case 2: /* ENABLE */ | |
103 | return s->mask; | |
104 | case 4: /* SOFTINT */ | |
105 | return s->level & 1; | |
106 | case 8: /* PICENABLE */ | |
107 | return s->pic_enable; | |
108 | default: | |
e69954b9 | 109 | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
cdbdb648 PB |
110 | return 0; |
111 | } | |
112 | } | |
113 | ||
a8170e5e | 114 | static void vpb_sic_write(void *opaque, hwaddr offset, |
62ceeb2c | 115 | uint64_t value, unsigned size) |
cdbdb648 PB |
116 | { |
117 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
cdbdb648 PB |
118 | |
119 | switch (offset >> 2) { | |
120 | case 2: /* ENSET */ | |
121 | s->mask |= value; | |
122 | break; | |
123 | case 3: /* ENCLR */ | |
124 | s->mask &= ~value; | |
125 | break; | |
126 | case 4: /* SOFTINTSET */ | |
127 | if (value) | |
128 | s->mask |= 1; | |
129 | break; | |
130 | case 5: /* SOFTINTCLR */ | |
131 | if (value) | |
132 | s->mask &= ~1u; | |
133 | break; | |
134 | case 8: /* PICENSET */ | |
135 | s->pic_enable |= (value & 0x7fe00000); | |
136 | vpb_sic_update_pic(s); | |
137 | break; | |
138 | case 9: /* PICENCLR */ | |
139 | s->pic_enable &= ~value; | |
140 | vpb_sic_update_pic(s); | |
141 | break; | |
142 | default: | |
e69954b9 | 143 | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
cdbdb648 PB |
144 | return; |
145 | } | |
146 | vpb_sic_update(s); | |
147 | } | |
148 | ||
62ceeb2c AK |
149 | static const MemoryRegionOps vpb_sic_ops = { |
150 | .read = vpb_sic_read, | |
151 | .write = vpb_sic_write, | |
152 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
153 | }; |
154 | ||
0bc91ab3 | 155 | static void vpb_sic_init(Object *obj) |
cdbdb648 | 156 | { |
0bc91ab3 XZ |
157 | DeviceState *dev = DEVICE(obj); |
158 | vpb_sic_state *s = VERSATILE_PB_SIC(obj); | |
159 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
97aff481 | 160 | int i; |
cdbdb648 | 161 | |
cfc6b245 | 162 | qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); |
97aff481 | 163 | for (i = 0; i < 32; i++) { |
cfc6b245 | 164 | sysbus_init_irq(sbd, &s->parent[i]); |
97aff481 | 165 | } |
3950f18b | 166 | s->irq = 31; |
0bc91ab3 | 167 | memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s, |
64bde0f3 | 168 | "vpb-sic", 0x1000); |
cfc6b245 | 169 | sysbus_init_mmio(sbd, &s->iomem); |
cdbdb648 PB |
170 | } |
171 | ||
172 | /* Board init. */ | |
173 | ||
16406950 | 174 | /* The AB and PB boards both use the same core, just with different |
370de023 | 175 | peripherals and expansion busses. For now we emulate a subset of the |
16406950 | 176 | PB peripherals and just change the board ID. */ |
cdbdb648 | 177 | |
f93eb9ff AZ |
178 | static struct arm_boot_info versatile_binfo; |
179 | ||
3ef96221 | 180 | static void versatile_init(MachineState *machine, int board_id) |
cdbdb648 | 181 | { |
223a72f1 | 182 | Object *cpuobj; |
20e93374 | 183 | ARMCPU *cpu; |
62ceeb2c AK |
184 | MemoryRegion *sysmem = get_system_memory(); |
185 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
97aff481 | 186 | qemu_irq pic[32]; |
3950f18b | 187 | qemu_irq sic[32]; |
242ea2c6 | 188 | DeviceState *dev, *sysctl; |
7d6e771f | 189 | SysBusDevice *busdev; |
d028d02d | 190 | DeviceState *pl041; |
502a5395 PB |
191 | PCIBus *pci_bus; |
192 | NICInfo *nd; | |
a5c82852 | 193 | I2CBus *i2c; |
502a5395 PB |
194 | int n; |
195 | int done_smc = 0; | |
964c695a | 196 | DriveInfo *dinfo; |
cdbdb648 | 197 | |
5c8c2aaf JCD |
198 | if (machine->ram_size > 0x10000000) { |
199 | /* Device starting at address 0x10000000, | |
200 | * and memory cannot overlap with devices. | |
201 | * Refuse to run rather than behaving very confusingly. | |
202 | */ | |
203 | error_report("versatilepb: memory size must not exceed 256MB"); | |
204 | exit(1); | |
205 | } | |
206 | ||
ba1ba5cc | 207 | cpuobj = object_new(machine->cpu_type); |
223a72f1 | 208 | |
61e2f352 GB |
209 | /* By default ARM1176 CPUs have EL3 enabled. This board does not |
210 | * currently support EL3 so the CPU EL3 property is disabled before | |
211 | * realization. | |
212 | */ | |
213 | if (object_property_find(cpuobj, "has_el3", NULL)) { | |
007b0657 | 214 | object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); |
61e2f352 GB |
215 | } |
216 | ||
007b0657 | 217 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
223a72f1 GB |
218 | |
219 | cpu = ARM_CPU(cpuobj); | |
220 | ||
c8623c02 DM |
221 | memory_region_allocate_system_memory(ram, NULL, "versatile.ram", |
222 | machine->ram_size); | |
1235fc06 | 223 | /* ??? RAM should repeat to fill physical memory space. */ |
cdbdb648 | 224 | /* SDRAM at address zero. */ |
62ceeb2c | 225 | memory_region_add_subregion(sysmem, 0, ram); |
cdbdb648 | 226 | |
242ea2c6 PM |
227 | sysctl = qdev_create(NULL, "realview_sysctl"); |
228 | qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); | |
242ea2c6 | 229 | qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); |
7a65c8cc | 230 | qdev_init_nofail(sysctl); |
1356b98d | 231 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); |
242ea2c6 | 232 | |
97aff481 | 233 | dev = sysbus_create_varargs("pl190", 0x10140000, |
bace999f PM |
234 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), |
235 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), | |
236 | NULL); | |
97aff481 | 237 | for (n = 0; n < 32; n++) { |
067a3ddc | 238 | pic[n] = qdev_get_gpio_in(dev, n); |
97aff481 | 239 | } |
cfc6b245 | 240 | dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL); |
3950f18b | 241 | for (n = 0; n < 32; n++) { |
1356b98d | 242 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]); |
067a3ddc | 243 | sic[n] = qdev_get_gpio_in(dev, n); |
3950f18b | 244 | } |
86394e96 PB |
245 | |
246 | sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); | |
247 | sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); | |
cdbdb648 | 248 | |
7d6e771f | 249 | dev = qdev_create(NULL, "versatile_pci"); |
1356b98d | 250 | busdev = SYS_BUS_DEVICE(dev); |
7d6e771f | 251 | qdev_init_nofail(dev); |
7468d73a PM |
252 | sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */ |
253 | sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */ | |
254 | sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */ | |
255 | sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */ | |
89a32d32 PM |
256 | sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */ |
257 | sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */ | |
258 | sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */ | |
7d6e771f PM |
259 | sysbus_connect_irq(busdev, 0, sic[27]); |
260 | sysbus_connect_irq(busdev, 1, sic[28]); | |
261 | sysbus_connect_irq(busdev, 2, sic[29]); | |
262 | sysbus_connect_irq(busdev, 3, sic[30]); | |
02e2da45 | 263 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
0027b06d | 264 | |
502a5395 PB |
265 | for(n = 0; n < nb_nics; n++) { |
266 | nd = &nd_table[n]; | |
0ae18cee | 267 | |
e6b3c8ca | 268 | if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { |
d537cf6c | 269 | smc91c111_init(nd, 0x10010000, sic[25]); |
0ae18cee | 270 | done_smc = 1; |
cdbdb648 | 271 | } else { |
29b358f9 | 272 | pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL); |
cdbdb648 PB |
273 | } |
274 | } | |
4bcbe0b6 | 275 | if (machine_usb(machine)) { |
afb9a60e | 276 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0d92ed30 | 277 | } |
9be5dafe PB |
278 | n = drive_get_max_bus(IF_SCSI); |
279 | while (n >= 0) { | |
877eb21d MCA |
280 | dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); |
281 | lsi53c8xx_handle_legacy_cmdline(dev); | |
9be5dafe | 282 | n--; |
7d8406be | 283 | } |
cdbdb648 | 284 | |
9bca0edb PM |
285 | pl011_create(0x101f1000, pic[12], serial_hd(0)); |
286 | pl011_create(0x101f2000, pic[13], serial_hd(1)); | |
287 | pl011_create(0x101f3000, pic[14], serial_hd(2)); | |
288 | pl011_create(0x10009000, sic[6], serial_hd(3)); | |
cdbdb648 | 289 | |
112a829f PM |
290 | dev = qdev_create(NULL, "pl080"); |
291 | object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", | |
292 | &error_fatal); | |
293 | qdev_init_nofail(dev); | |
294 | busdev = SYS_BUS_DEVICE(dev); | |
295 | sysbus_mmio_map(busdev, 0, 0x10130000); | |
296 | sysbus_connect_irq(busdev, 0, pic[17]); | |
297 | ||
6a824ec3 PB |
298 | sysbus_create_simple("sp804", 0x101e2000, pic[4]); |
299 | sysbus_create_simple("sp804", 0x101e3000, pic[5]); | |
cdbdb648 | 300 | |
853e65e0 JCPV |
301 | sysbus_create_simple("pl061", 0x101e4000, pic[6]); |
302 | sysbus_create_simple("pl061", 0x101e5000, pic[7]); | |
303 | sysbus_create_simple("pl061", 0x101e6000, pic[8]); | |
304 | sysbus_create_simple("pl061", 0x101e7000, pic[9]); | |
305 | ||
cdbdb648 PB |
306 | /* The versatile/PB actually has a modified Color LCD controller |
307 | that includes hardware cursor support from the PL111. */ | |
242ea2c6 PM |
308 | dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); |
309 | /* Wire up the mux control signals from the SYS_CLCD register */ | |
310 | qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); | |
cdbdb648 | 311 | |
aa9311d8 PB |
312 | sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); |
313 | sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); | |
a1bb27b1 | 314 | |
7e1543c2 | 315 | /* Add PL031 Real Time Clock. */ |
a63bdb31 | 316 | sysbus_create_simple("pl031", 0x101e8000, pic[10]); |
7e1543c2 | 317 | |
b1f05696 | 318 | dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); |
a5c82852 | 319 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); |
b1f05696 OA |
320 | i2c_create_slave(i2c, "ds1338", 0x68); |
321 | ||
d028d02d MS |
322 | /* Add PL041 AACI Interface to the LM4549 codec */ |
323 | pl041 = qdev_create(NULL, "pl041"); | |
324 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
325 | qdev_init_nofail(pl041); | |
1356b98d AF |
326 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); |
327 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]); | |
d028d02d | 328 | |
16406950 | 329 | /* Memory map for Versatile/PB: */ |
cdbdb648 PB |
330 | /* 0x10000000 System registers. */ |
331 | /* 0x10001000 PCI controller config registers. */ | |
332 | /* 0x10002000 Serial bus interface. */ | |
333 | /* 0x10003000 Secondary interrupt controller. */ | |
334 | /* 0x10004000 AACI (audio). */ | |
a1bb27b1 | 335 | /* 0x10005000 MMCI0. */ |
cdbdb648 PB |
336 | /* 0x10006000 KMI0 (keyboard). */ |
337 | /* 0x10007000 KMI1 (mouse). */ | |
338 | /* 0x10008000 Character LCD Interface. */ | |
339 | /* 0x10009000 UART3. */ | |
340 | /* 0x1000a000 Smart card 1. */ | |
a1bb27b1 | 341 | /* 0x1000b000 MMCI1. */ |
cdbdb648 PB |
342 | /* 0x10010000 Ethernet. */ |
343 | /* 0x10020000 USB. */ | |
344 | /* 0x10100000 SSMC. */ | |
345 | /* 0x10110000 MPMC. */ | |
346 | /* 0x10120000 CLCD Controller. */ | |
347 | /* 0x10130000 DMA Controller. */ | |
348 | /* 0x10140000 Vectored interrupt controller. */ | |
349 | /* 0x101d0000 AHB Monitor Interface. */ | |
350 | /* 0x101e0000 System Controller. */ | |
351 | /* 0x101e1000 Watchdog Interface. */ | |
352 | /* 0x101e2000 Timer 0/1. */ | |
353 | /* 0x101e3000 Timer 2/3. */ | |
354 | /* 0x101e4000 GPIO port 0. */ | |
355 | /* 0x101e5000 GPIO port 1. */ | |
356 | /* 0x101e6000 GPIO port 2. */ | |
357 | /* 0x101e7000 GPIO port 3. */ | |
358 | /* 0x101e8000 RTC. */ | |
359 | /* 0x101f0000 Smart card 0. */ | |
360 | /* 0x101f1000 UART0. */ | |
361 | /* 0x101f2000 UART1. */ | |
362 | /* 0x101f3000 UART2. */ | |
363 | /* 0x101f4000 SSPI. */ | |
964c695a EB |
364 | /* 0x34000000 NOR Flash */ |
365 | ||
366 | dinfo = drive_get(IF_PFLASH, 0, 0); | |
940d5b13 | 367 | if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", |
fa1d36df | 368 | VERSATILE_FLASH_SIZE, |
4be74634 | 369 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
964c695a | 370 | VERSATILE_FLASH_SECT_SIZE, |
964c695a EB |
371 | 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { |
372 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
373 | } | |
cdbdb648 | 374 | |
3ef96221 MA |
375 | versatile_binfo.ram_size = machine->ram_size; |
376 | versatile_binfo.kernel_filename = machine->kernel_filename; | |
377 | versatile_binfo.kernel_cmdline = machine->kernel_cmdline; | |
378 | versatile_binfo.initrd_filename = machine->initrd_filename; | |
f93eb9ff | 379 | versatile_binfo.board_id = board_id; |
3aaa8dfa | 380 | arm_load_kernel(cpu, &versatile_binfo); |
16406950 PB |
381 | } |
382 | ||
3ef96221 | 383 | static void vpb_init(MachineState *machine) |
16406950 | 384 | { |
3ef96221 | 385 | versatile_init(machine, 0x183); |
16406950 PB |
386 | } |
387 | ||
3ef96221 | 388 | static void vab_init(MachineState *machine) |
16406950 | 389 | { |
3ef96221 | 390 | versatile_init(machine, 0x25e); |
cdbdb648 PB |
391 | } |
392 | ||
8a661aea | 393 | static void versatilepb_class_init(ObjectClass *oc, void *data) |
e264d29d | 394 | { |
8a661aea AF |
395 | MachineClass *mc = MACHINE_CLASS(oc); |
396 | ||
e264d29d EH |
397 | mc->desc = "ARM Versatile/PB (ARM926EJ-S)"; |
398 | mc->init = vpb_init; | |
399 | mc->block_default_type = IF_SCSI; | |
4672cbd7 | 400 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 401 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
e264d29d | 402 | } |
16406950 | 403 | |
8a661aea AF |
404 | static const TypeInfo versatilepb_type = { |
405 | .name = MACHINE_TYPE_NAME("versatilepb"), | |
406 | .parent = TYPE_MACHINE, | |
407 | .class_init = versatilepb_class_init, | |
408 | }; | |
3950f18b | 409 | |
8a661aea | 410 | static void versatileab_class_init(ObjectClass *oc, void *data) |
f80f9ec9 | 411 | { |
8a661aea AF |
412 | MachineClass *mc = MACHINE_CLASS(oc); |
413 | ||
e264d29d EH |
414 | mc->desc = "ARM Versatile/AB (ARM926EJ-S)"; |
415 | mc->init = vab_init; | |
416 | mc->block_default_type = IF_SCSI; | |
4672cbd7 | 417 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 418 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); |
f80f9ec9 AL |
419 | } |
420 | ||
8a661aea AF |
421 | static const TypeInfo versatileab_type = { |
422 | .name = MACHINE_TYPE_NAME("versatileab"), | |
423 | .parent = TYPE_MACHINE, | |
424 | .class_init = versatileab_class_init, | |
425 | }; | |
426 | ||
427 | static void versatile_machine_init(void) | |
428 | { | |
429 | type_register_static(&versatilepb_type); | |
430 | type_register_static(&versatileab_type); | |
431 | } | |
432 | ||
0e6aac87 | 433 | type_init(versatile_machine_init) |
f80f9ec9 | 434 | |
999e12bb AL |
435 | static void vpb_sic_class_init(ObjectClass *klass, void *data) |
436 | { | |
39bffca2 | 437 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 438 | |
39bffca2 | 439 | dc->vmsd = &vmstate_vpb_sic; |
999e12bb AL |
440 | } |
441 | ||
8c43a6f0 | 442 | static const TypeInfo vpb_sic_info = { |
cfc6b245 | 443 | .name = TYPE_VERSATILE_PB_SIC, |
39bffca2 AL |
444 | .parent = TYPE_SYS_BUS_DEVICE, |
445 | .instance_size = sizeof(vpb_sic_state), | |
0bc91ab3 | 446 | .instance_init = vpb_sic_init, |
39bffca2 | 447 | .class_init = vpb_sic_class_init, |
a796d0ac PM |
448 | }; |
449 | ||
83f7d43a | 450 | static void versatilepb_register_types(void) |
3950f18b | 451 | { |
39bffca2 | 452 | type_register_static(&vpb_sic_info); |
3950f18b PB |
453 | } |
454 | ||
83f7d43a | 455 | type_init(versatilepb_register_types) |