[mirror_qemu.git] / hw / arm / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"
#include "hw/i2c/i2c.h"
#include "hw/boards.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "hw/block/flash.h"

#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)

/* Primary interrupt controller.  */

#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
#define VERSATILE_PB_SIC(obj) \
    OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)

typedef struct vpb_sic_state {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t level;
    uint32_t mask;
    uint32_t pic_enable;
    qemu_irq parent[32];
    int irq;
} vpb_sic_state;

static const VMStateDescription vmstate_vpb_sic = {
    .name = "versatilepb_sic",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, vpb_sic_state),
        VMSTATE_UINT32(mask, vpb_sic_state),
        VMSTATE_UINT32(pic_enable, vpb_sic_state),
        VMSTATE_END_OF_LIST()
    }
};

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static const MemoryRegionOps vpb_sic_ops = {
    .read = vpb_sic_read,
    .write = vpb_sic_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int vpb_sic_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    vpb_sic_state *s = VERSATILE_PB_SIC(dev);
    int i;

    qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(sbd, &s->parent[i]);
    }
    s->irq = 31;
    memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
                          "vpb-sic", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    return 0;
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherals and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(MachineState *machine, int board_id)
{
    ARMCPU *cpu;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    qemu_irq pic[32];
    qemu_irq sic[32];
    DeviceState *dev, *sysctl;
    SysBusDevice *busdev;
    DeviceState *pl041;
    PCIBus *pci_bus;
    NICInfo *nd;
    I2CBus *i2c;
    int n;
    int done_smc = 0;
    DriveInfo *dinfo;

    if (!machine->cpu_model) {
        machine->cpu_model = "arm926";
    }
    cpu = cpu_arm_init(machine->cpu_model);
    if (!cpu) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    memory_region_init_ram(ram, NULL, "versatile.ram", machine->ram_size,
                           &error_abort);
    vmstate_register_ram_global(ram);
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, ram);

    sysctl = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
    qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
    qdev_init_nofail(sysctl);
    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);

    dev = sysbus_create_varargs("pl190", 0x10140000,
                                qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
                                qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
                                NULL);
    for (n = 0; n < 32; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }
    dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
    for (n = 0; n < 32; n++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
        sic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
    sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);

    dev = qdev_create(NULL, "versatile_pci");
    busdev = SYS_BUS_DEVICE(dev);
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
    sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
    sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
    sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
    sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */
    sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */
    sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */
    sysbus_connect_irq(busdev, 0, sic[27]);
    sysbus_connect_irq(busdev, 1, sic[28]);
    sysbus_connect_irq(busdev, 2, sic[29]);
    sysbus_connect_irq(busdev, 3, sic[30]);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");

    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
            smc91c111_init(nd, 0x10010000, sic[25]);
            done_smc = 1;
        } else {
            pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
        }
    }
    if (usb_enabled(false)) {
        pci_create_simple(pci_bus, -1, "pci-ohci");
    }
    n = drive_get_max_bus(IF_SCSI);
    while (n >= 0) {
        pci_create_simple(pci_bus, -1, "lsi53c895a");
        n--;
    }

    sysbus_create_simple("pl011", 0x101f1000, pic[12]);
    sysbus_create_simple("pl011", 0x101f2000, pic[13]);
    sysbus_create_simple("pl011", 0x101f3000, pic[14]);
    sysbus_create_simple("pl011", 0x10009000, sic[6]);

    sysbus_create_simple("pl080", 0x10130000, pic[17]);
    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
    sysbus_create_simple("sp804", 0x101e3000, pic[5]);

    sysbus_create_simple("pl061", 0x101e4000, pic[6]);
    sysbus_create_simple("pl061", 0x101e5000, pic[7]);
    sysbus_create_simple("pl061", 0x101e6000, pic[8]);
    sysbus_create_simple("pl061", 0x101e7000, pic[9]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
    /* Wire up the mux control signals from the SYS_CLCD register */
    qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));

    sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
    sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);

    /* Add PL031 Real Time Clock. */
    sysbus_create_simple("pl031", 0x101e8000, pic[10]);

    dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
    i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
    i2c_create_slave(i2c, "ds1338", 0x68);

    /* Add PL041 AACI Interface to the LM4549 codec */
    pl041 = qdev_create(NULL, "pl041");
    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
    qdev_init_nofail(pl041);
    sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
    sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */
    /* 0x34000000 NOR Flash */

    dinfo = drive_get(IF_PFLASH, 0, 0);
    if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
                          VERSATILE_FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          VERSATILE_FLASH_SECT_SIZE,
                          VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
                          4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
        fprintf(stderr, "qemu: Error registering flash memory.\n");
    }

    versatile_binfo.ram_size = machine->ram_size;
    versatile_binfo.kernel_filename = machine->kernel_filename;
    versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
    versatile_binfo.initrd_filename = machine->initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(cpu, &versatile_binfo);
}

static void vpb_init(MachineState *machine)
{
    versatile_init(machine, 0x183);
}

static void vab_init(MachineState *machine)
{
    versatile_init(machine, 0x25e);
}

static QEMUMachine versatilepb_machine = {
    .name = "versatilepb",
    .desc = "ARM Versatile/PB (ARM926EJ-S)",
    .init = vpb_init,
    .block_default_type = IF_SCSI,
};

static QEMUMachine versatileab_machine = {
    .name = "versatileab",
    .desc = "ARM Versatile/AB (ARM926EJ-S)",
    .init = vab_init,
    .block_default_type = IF_SCSI,
};

static void versatile_machine_init(void)
{
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
}

machine_init(versatile_machine_init);

static void vpb_sic_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = vpb_sic_init;
    dc->vmsd = &vmstate_vpb_sic;
}

static const TypeInfo vpb_sic_info = {
    .name          = TYPE_VERSATILE_PB_SIC,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(vpb_sic_state),
    .class_init    = vpb_sic_class_init,
};

static void versatilepb_register_types(void)
{
    type_register_static(&vpb_sic_info);
}

type_init(versatilepb_register_types)
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
cdbdb648 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
bd2be150 PM	11	#include "hw/arm/arm.h"
bd2be150 PM	12	#include "hw/devices.h"
1422e32d	13	#include "net/net.h"
9c17d615	14	#include "sysemu/sysemu.h"
83c9f4ca	15	#include "hw/pci/pci.h"
0d09e41a	16	#include "hw/i2c/i2c.h"
83c9f4ca	17	#include "hw/boards.h"
fa1d36df	18	#include "sysemu/block-backend.h"
022c62cb	19	#include "exec/address-spaces.h"
0d09e41a	20	#include "hw/block/flash.h"
964c695a EB	21
	22	#define VERSATILE_FLASH_ADDR 0x34000000
	23	#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
	24	#define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
cdbdb648	25
cdbdb648 PB	26	/* Primary interrupt controller. */
cdbdb648 PB	27
cfc6b245 AF	28	#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
	29	#define VERSATILE_PB_SIC(obj) \
	30	OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
	31
	32	typedef struct vpb_sic_state {
	33	SysBusDevice parent_obj;
	34
	35	MemoryRegion iomem;
	36	uint32_t level;
	37	uint32_t mask;
	38	uint32_t pic_enable;
	39	qemu_irq parent[32];
	40	int irq;
cdbdb648 PB	41	} vpb_sic_state;
cdbdb648 PB	42
a796d0ac PM	43	static const VMStateDescription vmstate_vpb_sic = {
	44	.name = "versatilepb_sic",
	45	.version_id = 1,
	46	.minimum_version_id = 1,
	47	.fields = (VMStateField[]) {
	48	VMSTATE_UINT32(level, vpb_sic_state),
	49	VMSTATE_UINT32(mask, vpb_sic_state),
	50	VMSTATE_UINT32(pic_enable, vpb_sic_state),
	51	VMSTATE_END_OF_LIST()
	52	}
	53	};
	54
cdbdb648 PB	55	static void vpb_sic_update(vpb_sic_state *s)
	56	{
	57	uint32_t flags;
	58
	59	flags = s->level & s->mask;
d537cf6c	60	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	61	}
	62
	63	static void vpb_sic_update_pic(vpb_sic_state *s)
	64	{
	65	int i;
	66	uint32_t mask;
	67
	68	for (i = 21; i <= 30; i++) {
	69	mask = 1u << i;
	70	if (!(s->pic_enable & mask))
	71	continue;
d537cf6c	72	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	73	}
	74	}
	75
	76	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	77	{
	78	vpb_sic_state s = (vpb_sic_state )opaque;
	79	if (level)
	80	s->level \|= 1u << irq;
	81	else
	82	s->level &= ~(1u << irq);
	83	if (s->pic_enable & (1u << irq))
d537cf6c	84	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	85	vpb_sic_update(s);
	86	}
	87
a8170e5e	88	static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
62ceeb2c	89	unsigned size)
cdbdb648 PB	90	{
	91	vpb_sic_state s = (vpb_sic_state )opaque;
	92
cdbdb648 PB	93	switch (offset >> 2) {
	94	case 0: /* STATUS */
	95	return s->level & s->mask;
	96	case 1: /* RAWSTAT */
	97	return s->level;
	98	case 2: /* ENABLE */
	99	return s->mask;
	100	case 4: /* SOFTINT */
	101	return s->level & 1;
	102	case 8: /* PICENABLE */
	103	return s->pic_enable;
	104	default:
e69954b9	105	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	106	return 0;
	107	}
	108	}
	109
a8170e5e	110	static void vpb_sic_write(void *opaque, hwaddr offset,
62ceeb2c	111	uint64_t value, unsigned size)
cdbdb648 PB	112	{
cdbdb648 PB	113	vpb_sic_state s = (vpb_sic_state )opaque;
cdbdb648 PB	114
	115	switch (offset >> 2) {
	116	case 2: /* ENSET */
	117	s->mask \|= value;
	118	break;
	119	case 3: /* ENCLR */
	120	s->mask &= ~value;
	121	break;
	122	case 4: /* SOFTINTSET */
	123	if (value)
	124	s->mask \|= 1;
	125	break;
	126	case 5: /* SOFTINTCLR */
	127	if (value)
	128	s->mask &= ~1u;
	129	break;
	130	case 8: /* PICENSET */
	131	s->pic_enable \|= (value & 0x7fe00000);
	132	vpb_sic_update_pic(s);
	133	break;
	134	case 9: /* PICENCLR */
	135	s->pic_enable &= ~value;
	136	vpb_sic_update_pic(s);
	137	break;
	138	default:
e69954b9	139	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	140	return;
	141	}
	142	vpb_sic_update(s);
	143	}
	144
62ceeb2c AK	145	static const MemoryRegionOps vpb_sic_ops = {
	146	.read = vpb_sic_read,
	147	.write = vpb_sic_write,
	148	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	149	};
cdbdb648 PB	150
cfc6b245	151	static int vpb_sic_init(SysBusDevice *sbd)
cdbdb648	152	{
cfc6b245 AF	153	DeviceState *dev = DEVICE(sbd);
cfc6b245 AF	154	vpb_sic_state *s = VERSATILE_PB_SIC(dev);
97aff481	155	int i;
cdbdb648	156
cfc6b245	157	qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
97aff481	158	for (i = 0; i < 32; i++) {
cfc6b245	159	sysbus_init_irq(sbd, &s->parent[i]);
97aff481	160	}
3950f18b	161	s->irq = 31;
64bde0f3 PB	162	memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
64bde0f3 PB	163	"vpb-sic", 0x1000);
cfc6b245	164	sysbus_init_mmio(sbd, &s->iomem);
81a322d4	165	return 0;
cdbdb648 PB	166	}
	167
	168	/* Board init. */
	169
16406950	170	/* The AB and PB boards both use the same core, just with different
370de023	171	peripherals and expansion busses. For now we emulate a subset of the
16406950	172	PB peripherals and just change the board ID. */
cdbdb648	173
f93eb9ff AZ	174	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	175
3ef96221	176	static void versatile_init(MachineState *machine, int board_id)
cdbdb648	177	{
20e93374	178	ARMCPU *cpu;
62ceeb2c AK	179	MemoryRegion *sysmem = get_system_memory();
62ceeb2c AK	180	MemoryRegion *ram = g_new(MemoryRegion, 1);
97aff481	181	qemu_irq pic[32];
3950f18b	182	qemu_irq sic[32];
242ea2c6	183	DeviceState dev, sysctl;
7d6e771f	184	SysBusDevice *busdev;
d028d02d	185	DeviceState *pl041;
502a5395 PB	186	PCIBus *pci_bus;
502a5395 PB	187	NICInfo *nd;
a5c82852	188	I2CBus *i2c;
502a5395 PB	189	int n;
502a5395 PB	190	int done_smc = 0;
964c695a	191	DriveInfo *dinfo;
cdbdb648	192
3ef96221 MA	193	if (!machine->cpu_model) {
3ef96221 MA	194	machine->cpu_model = "arm926";
20e93374	195	}
3ef96221	196	cpu = cpu_arm_init(machine->cpu_model);
20e93374	197	if (!cpu) {
aaed909a FB	198	fprintf(stderr, "Unable to find CPU definition\n");
	199	exit(1);
	200	}
49946538 HT	201	memory_region_init_ram(ram, NULL, "versatile.ram", machine->ram_size,
49946538 HT	202	&error_abort);
c5705a77	203	vmstate_register_ram_global(ram);
1235fc06	204	/* ??? RAM should repeat to fill physical memory space. */
cdbdb648	205	/* SDRAM at address zero. */
62ceeb2c	206	memory_region_add_subregion(sysmem, 0, ram);
cdbdb648	207
242ea2c6 PM	208	sysctl = qdev_create(NULL, "realview_sysctl");
242ea2c6 PM	209	qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
242ea2c6	210	qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
7a65c8cc	211	qdev_init_nofail(sysctl);
1356b98d	212	sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
242ea2c6	213
97aff481	214	dev = sysbus_create_varargs("pl190", 0x10140000,
bace999f PM	215	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
	216	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
	217	NULL);
97aff481	218	for (n = 0; n < 32; n++) {
067a3ddc	219	pic[n] = qdev_get_gpio_in(dev, n);
97aff481	220	}
cfc6b245	221	dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
3950f18b	222	for (n = 0; n < 32; n++) {
1356b98d	223	sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
067a3ddc	224	sic[n] = qdev_get_gpio_in(dev, n);
3950f18b	225	}
86394e96 PB	226
	227	sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
	228	sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
cdbdb648	229
7d6e771f	230	dev = qdev_create(NULL, "versatile_pci");
1356b98d	231	busdev = SYS_BUS_DEVICE(dev);
7d6e771f	232	qdev_init_nofail(dev);
7468d73a PM	233	sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
	234	sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
	235	sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
	236	sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
89a32d32 PM	237	sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */
	238	sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */
	239	sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */
7d6e771f PM	240	sysbus_connect_irq(busdev, 0, sic[27]);
	241	sysbus_connect_irq(busdev, 1, sic[28]);
	242	sysbus_connect_irq(busdev, 2, sic[29]);
	243	sysbus_connect_irq(busdev, 3, sic[30]);
02e2da45	244	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0027b06d	245
502a5395 PB	246	for(n = 0; n < nb_nics; n++) {
502a5395 PB	247	nd = &nd_table[n];
0ae18cee	248
e6b3c8ca	249	if (!done_smc && (!nd->model \|\| strcmp(nd->model, "smc91c111") == 0)) {
d537cf6c	250	smc91c111_init(nd, 0x10010000, sic[25]);
0ae18cee	251	done_smc = 1;
cdbdb648	252	} else {
29b358f9	253	pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
cdbdb648 PB	254	}
cdbdb648 PB	255	}
094b287f	256	if (usb_enabled(false)) {
afb9a60e	257	pci_create_simple(pci_bus, -1, "pci-ohci");
0d92ed30	258	}
9be5dafe PB	259	n = drive_get_max_bus(IF_SCSI);
	260	while (n >= 0) {
	261	pci_create_simple(pci_bus, -1, "lsi53c895a");
	262	n--;
7d8406be	263	}
cdbdb648	264
a7d518a6 PB	265	sysbus_create_simple("pl011", 0x101f1000, pic[12]);
	266	sysbus_create_simple("pl011", 0x101f2000, pic[13]);
	267	sysbus_create_simple("pl011", 0x101f3000, pic[14]);
	268	sysbus_create_simple("pl011", 0x10009000, sic[6]);
cdbdb648	269
b4496b13	270	sysbus_create_simple("pl080", 0x10130000, pic[17]);
6a824ec3 PB	271	sysbus_create_simple("sp804", 0x101e2000, pic[4]);
6a824ec3 PB	272	sysbus_create_simple("sp804", 0x101e3000, pic[5]);
cdbdb648	273
853e65e0 JCPV	274	sysbus_create_simple("pl061", 0x101e4000, pic[6]);
	275	sysbus_create_simple("pl061", 0x101e5000, pic[7]);
	276	sysbus_create_simple("pl061", 0x101e6000, pic[8]);
	277	sysbus_create_simple("pl061", 0x101e7000, pic[9]);
	278
cdbdb648 PB	279	/* The versatile/PB actually has a modified Color LCD controller
cdbdb648 PB	280	that includes hardware cursor support from the PL111. */
242ea2c6 PM	281	dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
	282	/* Wire up the mux control signals from the SYS_CLCD register */
	283	qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
cdbdb648	284
aa9311d8 PB	285	sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
aa9311d8 PB	286	sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
a1bb27b1	287
7e1543c2	288	/* Add PL031 Real Time Clock. */
a63bdb31	289	sysbus_create_simple("pl031", 0x101e8000, pic[10]);
7e1543c2	290
b1f05696	291	dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
a5c82852	292	i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
b1f05696 OA	293	i2c_create_slave(i2c, "ds1338", 0x68);
b1f05696 OA	294
d028d02d MS	295	/* Add PL041 AACI Interface to the LM4549 codec */
	296	pl041 = qdev_create(NULL, "pl041");
	297	qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
	298	qdev_init_nofail(pl041);
1356b98d AF	299	sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
1356b98d AF	300	sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
d028d02d	301
16406950	302	/* Memory map for Versatile/PB: */
cdbdb648 PB	303	/* 0x10000000 System registers. */
	304	/* 0x10001000 PCI controller config registers. */
	305	/* 0x10002000 Serial bus interface. */
	306	/* 0x10003000 Secondary interrupt controller. */
	307	/* 0x10004000 AACI (audio). */
a1bb27b1	308	/* 0x10005000 MMCI0. */
cdbdb648 PB	309	/* 0x10006000 KMI0 (keyboard). */
	310	/* 0x10007000 KMI1 (mouse). */
	311	/* 0x10008000 Character LCD Interface. */
	312	/* 0x10009000 UART3. */
	313	/* 0x1000a000 Smart card 1. */
a1bb27b1	314	/* 0x1000b000 MMCI1. */
cdbdb648 PB	315	/* 0x10010000 Ethernet. */
	316	/* 0x10020000 USB. */
	317	/* 0x10100000 SSMC. */
	318	/* 0x10110000 MPMC. */
	319	/* 0x10120000 CLCD Controller. */
	320	/* 0x10130000 DMA Controller. */
	321	/* 0x10140000 Vectored interrupt controller. */
	322	/* 0x101d0000 AHB Monitor Interface. */
	323	/* 0x101e0000 System Controller. */
	324	/* 0x101e1000 Watchdog Interface. */
	325	/* 0x101e2000 Timer 0/1. */
	326	/* 0x101e3000 Timer 2/3. */
	327	/* 0x101e4000 GPIO port 0. */
	328	/* 0x101e5000 GPIO port 1. */
	329	/* 0x101e6000 GPIO port 2. */
	330	/* 0x101e7000 GPIO port 3. */
	331	/* 0x101e8000 RTC. */
	332	/* 0x101f0000 Smart card 0. */
	333	/* 0x101f1000 UART0. */
	334	/* 0x101f2000 UART1. */
	335	/* 0x101f3000 UART2. */
	336	/* 0x101f4000 SSPI. */
964c695a EB	337	/* 0x34000000 NOR Flash */
	338
	339	dinfo = drive_get(IF_PFLASH, 0, 0);
	340	if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
fa1d36df	341	VERSATILE_FLASH_SIZE,
4be74634	342	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
964c695a EB	343	VERSATILE_FLASH_SECT_SIZE,
	344	VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
	345	4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
	346	fprintf(stderr, "qemu: Error registering flash memory.\n");
	347	}
cdbdb648	348
3ef96221 MA	349	versatile_binfo.ram_size = machine->ram_size;
	350	versatile_binfo.kernel_filename = machine->kernel_filename;
	351	versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
	352	versatile_binfo.initrd_filename = machine->initrd_filename;
f93eb9ff	353	versatile_binfo.board_id = board_id;
3aaa8dfa	354	arm_load_kernel(cpu, &versatile_binfo);
16406950 PB	355	}
16406950 PB	356
3ef96221	357	static void vpb_init(MachineState *machine)
16406950	358	{
3ef96221	359	versatile_init(machine, 0x183);
16406950 PB	360	}
16406950 PB	361
3ef96221	362	static void vab_init(MachineState *machine)
16406950	363	{
3ef96221	364	versatile_init(machine, 0x25e);
cdbdb648 PB	365	}
cdbdb648 PB	366
f80f9ec9	367	static QEMUMachine versatilepb_machine = {
c9b1ae2c BS	368	.name = "versatilepb",
	369	.desc = "ARM Versatile/PB (ARM926EJ-S)",
	370	.init = vpb_init,
2d0d2837	371	.block_default_type = IF_SCSI,
cdbdb648	372	};
16406950	373
f80f9ec9	374	static QEMUMachine versatileab_machine = {
c9b1ae2c BS	375	.name = "versatileab",
	376	.desc = "ARM Versatile/AB (ARM926EJ-S)",
	377	.init = vab_init,
2d0d2837	378	.block_default_type = IF_SCSI,
16406950	379	};
3950f18b	380
f80f9ec9 AL	381	static void versatile_machine_init(void)
	382	{
	383	qemu_register_machine(&versatilepb_machine);
	384	qemu_register_machine(&versatileab_machine);
	385	}
	386
	387	machine_init(versatile_machine_init);
	388
999e12bb AL	389	static void vpb_sic_class_init(ObjectClass klass, void data)
999e12bb AL	390	{
39bffca2	391	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	392	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	393
	394	k->init = vpb_sic_init;
39bffca2	395	dc->vmsd = &vmstate_vpb_sic;
999e12bb AL	396	}
999e12bb AL	397
8c43a6f0	398	static const TypeInfo vpb_sic_info = {
cfc6b245	399	.name = TYPE_VERSATILE_PB_SIC,
39bffca2 AL	400	.parent = TYPE_SYS_BUS_DEVICE,
	401	.instance_size = sizeof(vpb_sic_state),
	402	.class_init = vpb_sic_class_init,
a796d0ac PM	403	};
a796d0ac PM	404
83f7d43a	405	static void versatilepb_register_types(void)
3950f18b	406	{
39bffca2	407	type_register_static(&vpb_sic_info);
3950f18b PB	408	}
3950f18b PB	409
83f7d43a	410	type_init(versatilepb_register_types)