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f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
12b16722 | 31 | #include "qemu/osdep.h" |
da34e65c | 32 | #include "qapi/error.h" |
f5fdcd6e PM |
33 | #include "hw/sysbus.h" |
34 | #include "hw/arm/arm.h" | |
35 | #include "hw/arm/primecell.h" | |
afe0b380 | 36 | #include "hw/arm/virt.h" |
f5fdcd6e PM |
37 | #include "hw/devices.h" |
38 | #include "net/net.h" | |
fa1d36df | 39 | #include "sysemu/block-backend.h" |
f5fdcd6e | 40 | #include "sysemu/device_tree.h" |
9695200a | 41 | #include "sysemu/numa.h" |
f5fdcd6e PM |
42 | #include "sysemu/sysemu.h" |
43 | #include "sysemu/kvm.h" | |
44 | #include "hw/boards.h" | |
acf82361 | 45 | #include "hw/loader.h" |
f5fdcd6e PM |
46 | #include "exec/address-spaces.h" |
47 | #include "qemu/bitops.h" | |
48 | #include "qemu/error-report.h" | |
4ab29b82 | 49 | #include "hw/pci-host/gpex.h" |
d7c2e2db | 50 | #include "hw/arm/virt-acpi-build.h" |
5f7a5a0e EA |
51 | #include "hw/arm/sysbus-fdt.h" |
52 | #include "hw/platform-bus.h" | |
decf4f80 | 53 | #include "hw/arm/fdt.h" |
0e3e858f | 54 | #include "hw/intc/arm_gic_common.h" |
e6fbcbc4 | 55 | #include "kvm_arm.h" |
c30e1565 | 56 | #include "hw/smbios/smbios.h" |
b92ad394 | 57 | #include "qapi/visitor.h" |
3e6ebb64 | 58 | #include "standard-headers/linux/input.h" |
f5fdcd6e | 59 | |
f5fdcd6e | 60 | /* Number of external interrupt lines to configure the GIC with */ |
5f7a5a0e | 61 | #define NUM_IRQS 256 |
f5fdcd6e | 62 | |
5f7a5a0e EA |
63 | #define PLATFORM_BUS_NUM_IRQS 64 |
64 | ||
65 | static ARMPlatformBusSystemParams platform_bus_params; | |
66 | ||
f5fdcd6e PM |
67 | typedef struct VirtBoardInfo { |
68 | struct arm_boot_info bootinfo; | |
69 | const char *cpu_model; | |
f5fdcd6e PM |
70 | const MemMapEntry *memmap; |
71 | const int *irqmap; | |
72 | int smp_cpus; | |
73 | void *fdt; | |
74 | int fdt_size; | |
75 | uint32_t clock_phandle; | |
747d009d | 76 | uint32_t gic_phandle; |
bd204e63 | 77 | uint32_t v2m_phandle; |
4824a61a | 78 | bool using_psci; |
f5fdcd6e PM |
79 | } VirtBoardInfo; |
80 | ||
c2919690 GB |
81 | typedef struct { |
82 | MachineClass parent; | |
83 | VirtBoardInfo *daughterboard; | |
84 | } VirtMachineClass; | |
85 | ||
86 | typedef struct { | |
87 | MachineState parent; | |
083a5890 | 88 | bool secure; |
5125f9cd | 89 | bool highmem; |
b92ad394 | 90 | int32_t gic_version; |
c2919690 GB |
91 | } VirtMachineState; |
92 | ||
98cec76a | 93 | #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") |
c2919690 GB |
94 | #define VIRT_MACHINE(obj) \ |
95 | OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) | |
96 | #define VIRT_MACHINE_GET_CLASS(obj) \ | |
97 | OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) | |
98 | #define VIRT_MACHINE_CLASS(klass) \ | |
99 | OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) | |
100 | ||
71c27684 PM |
101 | /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means |
102 | * RAM can go up to the 256GB mark, leaving 256GB of the physical | |
103 | * address space unallocated and free for future use between 256G and 512G. | |
104 | * If we need to provide more RAM to VMs in the future then we need to: | |
105 | * * allocate a second bank of RAM starting at 2TB and working up | |
106 | * * fix the DT and ACPI table generation code in QEMU to correctly | |
107 | * report two split lumps of RAM to the guest | |
108 | * * fix KVM in the host kernel to allow guests with >40 bit address spaces | |
109 | * (We don't want to fill all the way up to 512GB with RAM because | |
110 | * we might want it for non-RAM purposes later. Conversely it seems | |
111 | * reasonable to assume that anybody configuring a VM with a quarter | |
112 | * of a terabyte of RAM will be doing it on a host with more than a | |
113 | * terabyte of physical address space.) | |
114 | */ | |
115 | #define RAMLIMIT_GB 255 | |
116 | #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) | |
117 | ||
f5fdcd6e PM |
118 | /* Addresses and sizes of our components. |
119 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
120 | * 128MB..256MB is used for miscellaneous device I/O. | |
121 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
122 | * PCI memory window will go if we add a PCI host controller). | |
123 | * 1GB and up is RAM (which may happily spill over into the | |
124 | * high memory region beyond 4GB). | |
125 | * This represents a compromise between how much RAM can be given to | |
126 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
127 | * Note that devices should generally be placed at multiples of 0x10000, |
128 | * to accommodate guests using 64K pages. | |
f5fdcd6e PM |
129 | */ |
130 | static const MemMapEntry a15memmap[] = { | |
131 | /* Space up to 0x8000000 is reserved for a boot ROM */ | |
94edf02c EA |
132 | [VIRT_FLASH] = { 0, 0x08000000 }, |
133 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 134 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
135 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
136 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
137 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
b92ad394 PF |
138 | /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ |
139 | [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, | |
140 | /* This redistributor space allows up to 2*64kB*123 CPUs */ | |
141 | [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, | |
94edf02c EA |
142 | [VIRT_UART] = { 0x09000000, 0x00001000 }, |
143 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
0b341a85 | 144 | [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, |
b0a3721e | 145 | [VIRT_GPIO] = { 0x09030000, 0x00001000 }, |
3df708eb | 146 | [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, |
94edf02c | 147 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, |
f5fdcd6e | 148 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c | 149 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
83ec1923 | 150 | [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, |
94edf02c EA |
151 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, |
152 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
153 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
71c27684 | 154 | [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, |
5125f9cd PF |
155 | /* Second PCIe window, 512GB wide at the 512GB boundary */ |
156 | [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, | |
f5fdcd6e PM |
157 | }; |
158 | ||
159 | static const int a15irqmap[] = { | |
160 | [VIRT_UART] = 1, | |
6e411af9 | 161 | [VIRT_RTC] = 2, |
4ab29b82 | 162 | [VIRT_PCIE] = 3, /* ... to 6 */ |
b0a3721e | 163 | [VIRT_GPIO] = 7, |
3df708eb | 164 | [VIRT_SECURE_UART] = 8, |
f5fdcd6e | 165 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 166 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
5f7a5a0e | 167 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
168 | }; |
169 | ||
170 | static VirtBoardInfo machines[] = { | |
171 | { | |
172 | .cpu_model = "cortex-a15", | |
f5fdcd6e PM |
173 | .memmap = a15memmap, |
174 | .irqmap = a15irqmap, | |
175 | }, | |
8772de2c SZ |
176 | { |
177 | .cpu_model = "cortex-a53", | |
178 | .memmap = a15memmap, | |
179 | .irqmap = a15irqmap, | |
180 | }, | |
f42c5c8e PM |
181 | { |
182 | .cpu_model = "cortex-a57", | |
183 | .memmap = a15memmap, | |
184 | .irqmap = a15irqmap, | |
185 | }, | |
198aa064 PM |
186 | { |
187 | .cpu_model = "host", | |
198aa064 PM |
188 | .memmap = a15memmap, |
189 | .irqmap = a15irqmap, | |
190 | }, | |
f5fdcd6e PM |
191 | }; |
192 | ||
193 | static VirtBoardInfo *find_machine_info(const char *cpu) | |
194 | { | |
195 | int i; | |
196 | ||
197 | for (i = 0; i < ARRAY_SIZE(machines); i++) { | |
198 | if (strcmp(cpu, machines[i].cpu_model) == 0) { | |
199 | return &machines[i]; | |
200 | } | |
201 | } | |
202 | return NULL; | |
203 | } | |
204 | ||
205 | static void create_fdt(VirtBoardInfo *vbi) | |
206 | { | |
207 | void *fdt = create_device_tree(&vbi->fdt_size); | |
208 | ||
209 | if (!fdt) { | |
210 | error_report("create_device_tree() failed"); | |
211 | exit(1); | |
212 | } | |
213 | ||
214 | vbi->fdt = fdt; | |
215 | ||
216 | /* Header */ | |
5a4348d1 PC |
217 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
218 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
219 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
f5fdcd6e PM |
220 | |
221 | /* | |
222 | * /chosen and /memory nodes must exist for load_dtb | |
223 | * to fill in necessary properties later | |
224 | */ | |
5a4348d1 PC |
225 | qemu_fdt_add_subnode(fdt, "/chosen"); |
226 | qemu_fdt_add_subnode(fdt, "/memory"); | |
227 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
f5fdcd6e PM |
228 | |
229 | /* Clock node, for the benefit of the UART. The kernel device tree | |
230 | * binding documentation claims the PL011 node clock properties are | |
231 | * optional but in practice if you omit them the kernel refuses to | |
232 | * probe for the device. | |
233 | */ | |
5a4348d1 PC |
234 | vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
235 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); | |
236 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
237 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
238 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
239 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 240 | "clk24mhz"); |
5a4348d1 | 241 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); |
f5fdcd6e | 242 | |
06955739 PS |
243 | } |
244 | ||
245 | static void fdt_add_psci_node(const VirtBoardInfo *vbi) | |
246 | { | |
211b0169 RH |
247 | uint32_t cpu_suspend_fn; |
248 | uint32_t cpu_off_fn; | |
249 | uint32_t cpu_on_fn; | |
250 | uint32_t migrate_fn; | |
06955739 PS |
251 | void *fdt = vbi->fdt; |
252 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); | |
253 | ||
4824a61a PM |
254 | if (!vbi->using_psci) { |
255 | return; | |
256 | } | |
257 | ||
211b0169 RH |
258 | qemu_fdt_add_subnode(fdt, "/psci"); |
259 | if (armcpu->psci_version == 2) { | |
260 | const char comp[] = "arm,psci-0.2\0arm,psci"; | |
261 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | |
863714ba | 262 | |
211b0169 RH |
263 | cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; |
264 | if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { | |
265 | cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; | |
266 | cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; | |
267 | migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; | |
268 | } else { | |
269 | cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; | |
270 | cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; | |
271 | migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; | |
06955739 | 272 | } |
211b0169 RH |
273 | } else { |
274 | qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); | |
06955739 | 275 | |
211b0169 RH |
276 | cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; |
277 | cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; | |
278 | cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; | |
279 | migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; | |
f5fdcd6e | 280 | } |
211b0169 RH |
281 | |
282 | /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer | |
283 | * to the instruction that should be used to invoke PSCI functions. | |
284 | * However, the device tree binding uses 'method' instead, so that is | |
285 | * what we should use here. | |
286 | */ | |
287 | qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); | |
288 | ||
289 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); | |
290 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); | |
291 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); | |
292 | qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); | |
f5fdcd6e PM |
293 | } |
294 | ||
b92ad394 | 295 | static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, int gictype) |
f5fdcd6e PM |
296 | { |
297 | /* Note that on A15 h/w these interrupts are level-triggered, | |
298 | * but for the GIC implementation provided by both QEMU and KVM | |
299 | * they are edge-triggered. | |
300 | */ | |
b32a9509 | 301 | ARMCPU *armcpu; |
f5fdcd6e PM |
302 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; |
303 | ||
b92ad394 PF |
304 | if (gictype == 2) { |
305 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | |
306 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
307 | (1 << vbi->smp_cpus) - 1); | |
308 | } | |
f5fdcd6e | 309 | |
5a4348d1 | 310 | qemu_fdt_add_subnode(vbi->fdt, "/timer"); |
b32a9509 CF |
311 | |
312 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
313 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
314 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
315 | qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", | |
316 | compat, sizeof(compat)); | |
317 | } else { | |
318 | qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", | |
319 | "arm,armv7-timer"); | |
320 | } | |
caa49adb | 321 | qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); |
5a4348d1 | 322 | qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", |
ee246400 SZ |
323 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
324 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
325 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
326 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
327 | } |
328 | ||
329 | static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) | |
330 | { | |
331 | int cpu; | |
8d45c54d | 332 | int addr_cells = 1; |
9695200a | 333 | unsigned int i; |
8d45c54d PF |
334 | |
335 | /* | |
336 | * From Documentation/devicetree/bindings/arm/cpus.txt | |
337 | * On ARM v8 64-bit systems value should be set to 2, | |
338 | * that corresponds to the MPIDR_EL1 register size. | |
339 | * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
340 | * in the system, #address-cells can be set to 1, since | |
341 | * MPIDR_EL1[63:32] bits are not used for CPUs | |
342 | * identification. | |
343 | * | |
344 | * Here we actually don't know whether our system is 32- or 64-bit one. | |
345 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | |
346 | * at least one of them has Aff3 populated, we set #address-cells to 2. | |
347 | */ | |
348 | for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { | |
349 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
350 | ||
351 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | |
352 | addr_cells = 2; | |
353 | break; | |
354 | } | |
355 | } | |
f5fdcd6e | 356 | |
5a4348d1 | 357 | qemu_fdt_add_subnode(vbi->fdt, "/cpus"); |
8d45c54d | 358 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); |
5a4348d1 | 359 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); |
f5fdcd6e PM |
360 | |
361 | for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { | |
362 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | |
363 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
364 | ||
5a4348d1 PC |
365 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
366 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); | |
367 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", | |
f5fdcd6e PM |
368 | armcpu->dtb_compatible); |
369 | ||
4824a61a | 370 | if (vbi->using_psci && vbi->smp_cpus > 1) { |
5a4348d1 | 371 | qemu_fdt_setprop_string(vbi->fdt, nodename, |
f5fdcd6e PM |
372 | "enable-method", "psci"); |
373 | } | |
374 | ||
8d45c54d PF |
375 | if (addr_cells == 2) { |
376 | qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", | |
377 | armcpu->mp_affinity); | |
378 | } else { | |
379 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", | |
380 | armcpu->mp_affinity); | |
381 | } | |
382 | ||
9695200a SZ |
383 | for (i = 0; i < nb_numa_nodes; i++) { |
384 | if (test_bit(cpu, numa_info[i].node_cpu)) { | |
385 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); | |
386 | } | |
387 | } | |
388 | ||
f5fdcd6e PM |
389 | g_free(nodename); |
390 | } | |
391 | } | |
392 | ||
bd204e63 | 393 | static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) |
f5fdcd6e | 394 | { |
bd204e63 CD |
395 | vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
396 | qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); | |
397 | qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", | |
398 | "arm,gic-v2m-frame"); | |
399 | qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); | |
400 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", | |
401 | 2, vbi->memmap[VIRT_GIC_V2M].base, | |
402 | 2, vbi->memmap[VIRT_GIC_V2M].size); | |
403 | qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); | |
404 | } | |
f5fdcd6e | 405 | |
b92ad394 | 406 | static void fdt_add_gic_node(VirtBoardInfo *vbi, int type) |
bd204e63 | 407 | { |
747d009d CD |
408 | vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
409 | qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); | |
f5fdcd6e | 410 | |
5a4348d1 | 411 | qemu_fdt_add_subnode(vbi->fdt, "/intc"); |
5a4348d1 PC |
412 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); |
413 | qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); | |
dfd90a87 CD |
414 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); |
415 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); | |
416 | qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); | |
b92ad394 PF |
417 | if (type == 3) { |
418 | qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", | |
419 | "arm,gic-v3"); | |
420 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", | |
421 | 2, vbi->memmap[VIRT_GIC_DIST].base, | |
422 | 2, vbi->memmap[VIRT_GIC_DIST].size, | |
423 | 2, vbi->memmap[VIRT_GIC_REDIST].base, | |
424 | 2, vbi->memmap[VIRT_GIC_REDIST].size); | |
425 | } else { | |
426 | /* 'cortex-a15-gic' means 'GIC v2' */ | |
427 | qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", | |
428 | "arm,cortex-a15-gic"); | |
429 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", | |
430 | 2, vbi->memmap[VIRT_GIC_DIST].base, | |
431 | 2, vbi->memmap[VIRT_GIC_DIST].size, | |
432 | 2, vbi->memmap[VIRT_GIC_CPU].base, | |
433 | 2, vbi->memmap[VIRT_GIC_CPU].size); | |
434 | } | |
435 | ||
747d009d | 436 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); |
f5fdcd6e PM |
437 | } |
438 | ||
01fe6b60 SZ |
439 | static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype) |
440 | { | |
441 | CPUState *cpu; | |
442 | ARMCPU *armcpu; | |
443 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
444 | ||
445 | CPU_FOREACH(cpu) { | |
446 | armcpu = ARM_CPU(cpu); | |
447 | if (!armcpu->has_pmu || | |
448 | !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { | |
449 | return; | |
450 | } | |
451 | } | |
452 | ||
453 | if (gictype == 2) { | |
454 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | |
455 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
456 | (1 << vbi->smp_cpus) - 1); | |
457 | } | |
458 | ||
459 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
460 | qemu_fdt_add_subnode(vbi->fdt, "/pmu"); | |
461 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
462 | const char compat[] = "arm,armv8-pmuv3"; | |
463 | qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", | |
464 | compat, sizeof(compat)); | |
465 | qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", | |
466 | GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); | |
467 | } | |
468 | } | |
469 | ||
bd204e63 CD |
470 | static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) |
471 | { | |
472 | int i; | |
473 | int irq = vbi->irqmap[VIRT_GIC_V2M]; | |
474 | DeviceState *dev; | |
475 | ||
476 | dev = qdev_create(NULL, "arm-gicv2m"); | |
477 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); | |
478 | qdev_prop_set_uint32(dev, "base-spi", irq); | |
479 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
480 | qdev_init_nofail(dev); | |
481 | ||
482 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
483 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
484 | } | |
485 | ||
486 | fdt_add_v2m_gic_node(vbi); | |
487 | } | |
488 | ||
b92ad394 | 489 | static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, int type, bool secure) |
64204743 | 490 | { |
b92ad394 | 491 | /* We create a standalone GIC */ |
64204743 PM |
492 | DeviceState *gicdev; |
493 | SysBusDevice *gicbusdev; | |
e6fbcbc4 | 494 | const char *gictype; |
64204743 PM |
495 | int i; |
496 | ||
b92ad394 | 497 | gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); |
64204743 PM |
498 | |
499 | gicdev = qdev_create(NULL, gictype); | |
b92ad394 | 500 | qdev_prop_set_uint32(gicdev, "revision", type); |
64204743 PM |
501 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); |
502 | /* Note that the num-irq property counts both internal and external | |
503 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
504 | */ | |
505 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
0e21f183 PM |
506 | if (!kvm_irqchip_in_kernel()) { |
507 | qdev_prop_set_bit(gicdev, "has-security-extensions", secure); | |
508 | } | |
64204743 PM |
509 | qdev_init_nofail(gicdev); |
510 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
511 | sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); | |
b92ad394 PF |
512 | if (type == 3) { |
513 | sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); | |
514 | } else { | |
515 | sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); | |
516 | } | |
64204743 PM |
517 | |
518 | /* Wire the outputs from each CPU's generic timer to the | |
519 | * appropriate GIC PPI inputs, and the GIC's IRQ output to | |
520 | * the CPU's IRQ input. | |
521 | */ | |
522 | for (i = 0; i < smp_cpus; i++) { | |
523 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 524 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
525 | int irq; |
526 | /* Mapping from the output timer irq lines from the CPU to the | |
527 | * GIC PPI inputs we use for the virt board. | |
64204743 | 528 | */ |
a007b1f8 PM |
529 | const int timer_irq[] = { |
530 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
531 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
532 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
533 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
534 | }; | |
535 | ||
536 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
537 | qdev_connect_gpio_out(cpudev, irq, | |
538 | qdev_get_gpio_in(gicdev, | |
539 | ppibase + timer_irq[irq])); | |
540 | } | |
64204743 PM |
541 | |
542 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
8e7b4ca0 GB |
543 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
544 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
64204743 PM |
545 | } |
546 | ||
547 | for (i = 0; i < NUM_IRQS; i++) { | |
548 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
549 | } | |
550 | ||
b92ad394 | 551 | fdt_add_gic_node(vbi, type); |
bd204e63 | 552 | |
b92ad394 PF |
553 | if (type == 2) { |
554 | create_v2m(vbi, pic); | |
555 | } | |
64204743 PM |
556 | } |
557 | ||
3df708eb | 558 | static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic, int uart, |
9bbbf649 | 559 | MemoryRegion *mem, CharDriverState *chr) |
f5fdcd6e PM |
560 | { |
561 | char *nodename; | |
3df708eb PM |
562 | hwaddr base = vbi->memmap[uart].base; |
563 | hwaddr size = vbi->memmap[uart].size; | |
564 | int irq = vbi->irqmap[uart]; | |
f5fdcd6e PM |
565 | const char compat[] = "arm,pl011\0arm,primecell"; |
566 | const char clocknames[] = "uartclk\0apb_pclk"; | |
3df708eb PM |
567 | DeviceState *dev = qdev_create(NULL, "pl011"); |
568 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
f5fdcd6e | 569 | |
9bbbf649 | 570 | qdev_prop_set_chr(dev, "chardev", chr); |
3df708eb PM |
571 | qdev_init_nofail(dev); |
572 | memory_region_add_subregion(mem, base, | |
573 | sysbus_mmio_get_region(s, 0)); | |
574 | sysbus_connect_irq(s, 0, pic[irq]); | |
f5fdcd6e PM |
575 | |
576 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
5a4348d1 | 577 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
f5fdcd6e | 578 | /* Note that we can't use setprop_string because of the embedded NUL */ |
5a4348d1 | 579 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", |
f5fdcd6e | 580 | compat, sizeof(compat)); |
5a4348d1 | 581 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
f5fdcd6e | 582 | 2, base, 2, size); |
5a4348d1 | 583 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", |
f5fdcd6e | 584 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 585 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
5a4348d1 | 586 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", |
f5fdcd6e | 587 | vbi->clock_phandle, vbi->clock_phandle); |
5a4348d1 | 588 | qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", |
f5fdcd6e | 589 | clocknames, sizeof(clocknames)); |
f022b8e9 | 590 | |
3df708eb PM |
591 | if (uart == VIRT_UART) { |
592 | qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); | |
593 | } else { | |
594 | /* Mark as not usable by the normal world */ | |
595 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
596 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
597 | } | |
598 | ||
f5fdcd6e PM |
599 | g_free(nodename); |
600 | } | |
601 | ||
6e411af9 PM |
602 | static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) |
603 | { | |
604 | char *nodename; | |
605 | hwaddr base = vbi->memmap[VIRT_RTC].base; | |
606 | hwaddr size = vbi->memmap[VIRT_RTC].size; | |
607 | int irq = vbi->irqmap[VIRT_RTC]; | |
608 | const char compat[] = "arm,pl031\0arm,primecell"; | |
609 | ||
610 | sysbus_create_simple("pl031", base, pic[irq]); | |
611 | ||
612 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
613 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
614 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); | |
615 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
616 | 2, base, 2, size); | |
617 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
618 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
0be969a2 | 619 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
6e411af9 PM |
620 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); |
621 | qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); | |
622 | g_free(nodename); | |
623 | } | |
624 | ||
94f02c5e | 625 | static DeviceState *gpio_key_dev; |
4bedd849 SZ |
626 | static void virt_powerdown_req(Notifier *n, void *opaque) |
627 | { | |
628 | /* use gpio Pin 3 for power button event */ | |
94f02c5e | 629 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
4bedd849 SZ |
630 | } |
631 | ||
632 | static Notifier virt_system_powerdown_notifier = { | |
633 | .notify = virt_powerdown_req | |
634 | }; | |
635 | ||
b0a3721e SZ |
636 | static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic) |
637 | { | |
638 | char *nodename; | |
94f02c5e | 639 | DeviceState *pl061_dev; |
b0a3721e SZ |
640 | hwaddr base = vbi->memmap[VIRT_GPIO].base; |
641 | hwaddr size = vbi->memmap[VIRT_GPIO].size; | |
642 | int irq = vbi->irqmap[VIRT_GPIO]; | |
643 | const char compat[] = "arm,pl061\0arm,primecell"; | |
644 | ||
4bedd849 | 645 | pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); |
b0a3721e | 646 | |
3e6ebb64 | 647 | uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
b0a3721e SZ |
648 | nodename = g_strdup_printf("/pl061@%" PRIx64, base); |
649 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
650 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
651 | 2, base, 2, size); | |
652 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); | |
653 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); | |
654 | qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); | |
655 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
656 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
657 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
658 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); | |
659 | qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); | |
3e6ebb64 SZ |
660 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); |
661 | ||
94f02c5e SZ |
662 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
663 | qdev_get_gpio_in(pl061_dev, 3)); | |
3e6ebb64 SZ |
664 | qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); |
665 | qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); | |
666 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); | |
667 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); | |
668 | ||
669 | qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); | |
670 | qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", | |
671 | "label", "GPIO Key Poweroff"); | |
672 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", | |
673 | KEY_POWER); | |
674 | qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", | |
675 | "gpios", phandle, 3, 0); | |
b0a3721e | 676 | |
4bedd849 SZ |
677 | /* connect powerdown request */ |
678 | qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); | |
679 | ||
b0a3721e SZ |
680 | g_free(nodename); |
681 | } | |
682 | ||
f5fdcd6e PM |
683 | static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) |
684 | { | |
685 | int i; | |
686 | hwaddr size = vbi->memmap[VIRT_MMIO].size; | |
687 | ||
587078f0 LE |
688 | /* We create the transports in forwards order. Since qbus_realize() |
689 | * prepends (not appends) new child buses, the incrementing loop below will | |
690 | * create a list of virtio-mmio buses with decreasing base addresses. | |
691 | * | |
692 | * When a -device option is processed from the command line, | |
693 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
694 | * order. The upshot is that -device options in increasing command line | |
695 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
696 | * | |
697 | * When this code was originally written, that arrangement ensured that the | |
698 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
699 | * the first -device on the command line. (The end-to-end order is a | |
700 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
701 | * guest kernel's name-to-address assignment strategy.) | |
702 | * | |
703 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
704 | * the message, if not necessarily the code, of commit 70161ff336. | |
705 | * Therefore the loop now establishes the inverse of the original intent. | |
706 | * | |
707 | * Unfortunately, we can't counteract the kernel change by reversing the | |
708 | * loop; it would break existing command lines. | |
709 | * | |
710 | * In any case, the kernel makes no guarantee about the stability of | |
711 | * enumeration order of virtio devices (as demonstrated by it changing | |
712 | * between kernel versions). For reliable and stable identification | |
713 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
714 | */ |
715 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
716 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
717 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
718 | ||
719 | sysbus_create_simple("virtio-mmio", base, pic[irq]); | |
720 | } | |
721 | ||
587078f0 LE |
722 | /* We add dtb nodes in reverse order so that they appear in the finished |
723 | * device tree lowest address first. | |
724 | * | |
725 | * Note that this mapping is independent of the loop above. The previous | |
726 | * loop influences virtio device to virtio transport assignment, whereas | |
727 | * this loop controls how virtio transports are laid out in the dtb. | |
728 | */ | |
f5fdcd6e PM |
729 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
730 | char *nodename; | |
731 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
732 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
733 | ||
734 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
5a4348d1 PC |
735 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
736 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
737 | "compatible", "virtio,mmio"); | |
738 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
739 | 2, base, 2, size); | |
740 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
741 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
742 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
f5fdcd6e PM |
743 | g_free(nodename); |
744 | } | |
745 | } | |
746 | ||
acf82361 | 747 | static void create_one_flash(const char *name, hwaddr flashbase, |
738a5d9f PM |
748 | hwaddr flashsize, const char *file, |
749 | MemoryRegion *sysmem) | |
acf82361 PM |
750 | { |
751 | /* Create and map a single flash device. We use the same | |
752 | * parameters as the flash devices on the Versatile Express board. | |
753 | */ | |
754 | DriveInfo *dinfo = drive_get_next(IF_PFLASH); | |
755 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
16f4a8dc | 756 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
acf82361 PM |
757 | const uint64_t sectorlength = 256 * 1024; |
758 | ||
9b3d111a MA |
759 | if (dinfo) { |
760 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
761 | &error_abort); | |
acf82361 PM |
762 | } |
763 | ||
764 | qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); | |
765 | qdev_prop_set_uint64(dev, "sector-length", sectorlength); | |
766 | qdev_prop_set_uint8(dev, "width", 4); | |
767 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 768 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
769 | qdev_prop_set_uint16(dev, "id0", 0x89); |
770 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
771 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
772 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
773 | qdev_prop_set_string(dev, "name", name); | |
774 | qdev_init_nofail(dev); | |
775 | ||
738a5d9f PM |
776 | memory_region_add_subregion(sysmem, flashbase, |
777 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); | |
acf82361 | 778 | |
16f4a8dc | 779 | if (file) { |
6e05a12f | 780 | char *fn; |
4de9a883 | 781 | int image_size; |
acf82361 PM |
782 | |
783 | if (drive_get(IF_PFLASH, 0, 0)) { | |
784 | error_report("The contents of the first flash device may be " | |
785 | "specified with -bios or with -drive if=pflash... " | |
786 | "but you cannot use both options at once"); | |
787 | exit(1); | |
788 | } | |
16f4a8dc | 789 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); |
4de9a883 | 790 | if (!fn) { |
16f4a8dc | 791 | error_report("Could not find ROM image '%s'", file); |
4de9a883 SW |
792 | exit(1); |
793 | } | |
16f4a8dc | 794 | image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); |
4de9a883 SW |
795 | g_free(fn); |
796 | if (image_size < 0) { | |
16f4a8dc | 797 | error_report("Could not load ROM image '%s'", file); |
acf82361 PM |
798 | exit(1); |
799 | } | |
800 | } | |
16f4a8dc PM |
801 | } |
802 | ||
738a5d9f PM |
803 | static void create_flash(const VirtBoardInfo *vbi, |
804 | MemoryRegion *sysmem, | |
805 | MemoryRegion *secure_sysmem) | |
16f4a8dc PM |
806 | { |
807 | /* Create two flash devices to fill the VIRT_FLASH space in the memmap. | |
808 | * Any file passed via -bios goes in the first of these. | |
738a5d9f PM |
809 | * sysmem is the system memory space. secure_sysmem is the secure view |
810 | * of the system, and the first flash device should be made visible only | |
811 | * there. The second flash device is visible to both secure and nonsecure. | |
812 | * If sysmem == secure_sysmem this means there is no separate Secure | |
813 | * address space and both flash devices are generally visible. | |
16f4a8dc PM |
814 | */ |
815 | hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; | |
816 | hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; | |
817 | char *nodename; | |
acf82361 | 818 | |
738a5d9f PM |
819 | create_one_flash("virt.flash0", flashbase, flashsize, |
820 | bios_name, secure_sysmem); | |
821 | create_one_flash("virt.flash1", flashbase + flashsize, flashsize, | |
822 | NULL, sysmem); | |
acf82361 | 823 | |
738a5d9f PM |
824 | if (sysmem == secure_sysmem) { |
825 | /* Report both flash devices as a single node in the DT */ | |
826 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
827 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
828 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
829 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
830 | 2, flashbase, 2, flashsize, | |
831 | 2, flashbase + flashsize, 2, flashsize); | |
832 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
833 | g_free(nodename); | |
834 | } else { | |
835 | /* Report the devices as separate nodes so we can mark one as | |
836 | * only visible to the secure world. | |
837 | */ | |
838 | nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); | |
839 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
840 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
841 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
842 | 2, flashbase, 2, flashsize); | |
843 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
844 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
845 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
846 | g_free(nodename); | |
847 | ||
848 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
849 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
850 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
851 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
852 | 2, flashbase + flashsize, 2, flashsize); | |
853 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
854 | g_free(nodename); | |
855 | } | |
acf82361 PM |
856 | } |
857 | ||
0b341a85 | 858 | static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as) |
578f3c7b LE |
859 | { |
860 | hwaddr base = vbi->memmap[VIRT_FW_CFG].base; | |
861 | hwaddr size = vbi->memmap[VIRT_FW_CFG].size; | |
862 | char *nodename; | |
863 | ||
0b341a85 | 864 | fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); |
578f3c7b LE |
865 | |
866 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
867 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
868 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
869 | "compatible", "qemu,fw-cfg-mmio"); | |
870 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
871 | 2, base, 2, size); | |
872 | g_free(nodename); | |
873 | } | |
874 | ||
4ab29b82 AG |
875 | static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, |
876 | int first_irq, const char *nodename) | |
877 | { | |
878 | int devfn, pin; | |
dfd90a87 | 879 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
880 | uint32_t *irq_map = full_irq_map; |
881 | ||
882 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
883 | for (pin = 0; pin < 4; pin++) { | |
884 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
885 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
886 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
887 | int i; | |
888 | ||
889 | uint32_t map[] = { | |
890 | devfn << 8, 0, 0, /* devfn */ | |
891 | pin + 1, /* PCI pin */ | |
dfd90a87 | 892 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
893 | |
894 | /* Convert map to big endian */ | |
dfd90a87 | 895 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
896 | irq_map[i] = cpu_to_be32(map[i]); |
897 | } | |
dfd90a87 | 898 | irq_map += 10; |
4ab29b82 AG |
899 | } |
900 | } | |
901 | ||
902 | qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", | |
903 | full_irq_map, sizeof(full_irq_map)); | |
904 | ||
905 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", | |
906 | 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ | |
907 | 0x7 /* PCI irq */); | |
908 | } | |
909 | ||
5125f9cd PF |
910 | static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, |
911 | bool use_highmem) | |
4ab29b82 | 912 | { |
6a1f001b SZ |
913 | hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; |
914 | hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; | |
5125f9cd PF |
915 | hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; |
916 | hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; | |
6a1f001b SZ |
917 | hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; |
918 | hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; | |
919 | hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; | |
920 | hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; | |
921 | hwaddr base = base_mmio; | |
922 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
4ab29b82 AG |
923 | int irq = vbi->irqmap[VIRT_PCIE]; |
924 | MemoryRegion *mmio_alias; | |
925 | MemoryRegion *mmio_reg; | |
926 | MemoryRegion *ecam_alias; | |
927 | MemoryRegion *ecam_reg; | |
928 | DeviceState *dev; | |
929 | char *nodename; | |
930 | int i; | |
fea9b3ca | 931 | PCIHostState *pci; |
4ab29b82 | 932 | |
4ab29b82 AG |
933 | dev = qdev_create(NULL, TYPE_GPEX_HOST); |
934 | qdev_init_nofail(dev); | |
935 | ||
936 | /* Map only the first size_ecam bytes of ECAM space */ | |
937 | ecam_alias = g_new0(MemoryRegion, 1); | |
938 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
939 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
940 | ecam_reg, 0, size_ecam); | |
941 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
942 | ||
943 | /* Map the MMIO window into system address space so as to expose | |
944 | * the section of PCI MMIO space which starts at the same base address | |
945 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
946 | * the window). | |
947 | */ | |
948 | mmio_alias = g_new0(MemoryRegion, 1); | |
949 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
950 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
951 | mmio_reg, base_mmio, size_mmio); | |
952 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
953 | ||
5125f9cd PF |
954 | if (use_highmem) { |
955 | /* Map high MMIO space */ | |
956 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
957 | ||
958 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
959 | mmio_reg, base_mmio_high, size_mmio_high); | |
960 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
961 | high_mmio_alias); | |
962 | } | |
963 | ||
4ab29b82 | 964 | /* Map IO port space */ |
6a1f001b | 965 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
966 | |
967 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
968 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
969 | } | |
970 | ||
fea9b3ca AK |
971 | pci = PCI_HOST_BRIDGE(dev); |
972 | if (pci->bus) { | |
973 | for (i = 0; i < nb_nics; i++) { | |
974 | NICInfo *nd = &nd_table[i]; | |
975 | ||
976 | if (!nd->model) { | |
977 | nd->model = g_strdup("virtio"); | |
978 | } | |
979 | ||
980 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
981 | } | |
982 | } | |
983 | ||
4ab29b82 AG |
984 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
985 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
986 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
987 | "compatible", "pci-host-ecam-generic"); | |
988 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); | |
989 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); | |
990 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); | |
991 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, | |
992 | nr_pcie_buses - 1); | |
993 | ||
b92ad394 PF |
994 | if (vbi->v2m_phandle) { |
995 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", | |
996 | vbi->v2m_phandle); | |
997 | } | |
bd204e63 | 998 | |
4ab29b82 AG |
999 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
1000 | 2, base_ecam, 2, size_ecam); | |
5125f9cd PF |
1001 | |
1002 | if (use_highmem) { | |
1003 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
1004 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
1005 | 2, base_pio, 2, size_pio, | |
1006 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1007 | 2, base_mmio, 2, size_mmio, | |
1008 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
1009 | 2, base_mmio_high, | |
1010 | 2, base_mmio_high, 2, size_mmio_high); | |
1011 | } else { | |
1012 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
1013 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
1014 | 2, base_pio, 2, size_pio, | |
1015 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1016 | 2, base_mmio, 2, size_mmio); | |
1017 | } | |
4ab29b82 AG |
1018 | |
1019 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); | |
747d009d | 1020 | create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); |
4ab29b82 AG |
1021 | |
1022 | g_free(nodename); | |
1023 | } | |
1024 | ||
5f7a5a0e EA |
1025 | static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) |
1026 | { | |
1027 | DeviceState *dev; | |
1028 | SysBusDevice *s; | |
1029 | int i; | |
1030 | ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); | |
1031 | MemoryRegion *sysmem = get_system_memory(); | |
1032 | ||
1033 | platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; | |
1034 | platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; | |
1035 | platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; | |
1036 | platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; | |
1037 | ||
1038 | fdt_params->system_params = &platform_bus_params; | |
1039 | fdt_params->binfo = &vbi->bootinfo; | |
1040 | fdt_params->intc = "/intc"; | |
1041 | /* | |
1042 | * register a machine init done notifier that creates the device tree | |
1043 | * nodes of the platform bus and its children dynamic sysbus devices | |
1044 | */ | |
1045 | arm_register_platform_bus_fdt_creator(fdt_params); | |
1046 | ||
1047 | dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); | |
1048 | dev->id = TYPE_PLATFORM_BUS_DEVICE; | |
1049 | qdev_prop_set_uint32(dev, "num_irqs", | |
1050 | platform_bus_params.platform_bus_num_irqs); | |
1051 | qdev_prop_set_uint32(dev, "mmio_size", | |
1052 | platform_bus_params.platform_bus_size); | |
1053 | qdev_init_nofail(dev); | |
1054 | s = SYS_BUS_DEVICE(dev); | |
1055 | ||
1056 | for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { | |
1057 | int irqn = platform_bus_params.platform_bus_first_irq + i; | |
1058 | sysbus_connect_irq(s, i, pic[irqn]); | |
1059 | } | |
1060 | ||
1061 | memory_region_add_subregion(sysmem, | |
1062 | platform_bus_params.platform_bus_base, | |
1063 | sysbus_mmio_get_region(s, 0)); | |
1064 | } | |
1065 | ||
83ec1923 PM |
1066 | static void create_secure_ram(VirtBoardInfo *vbi, MemoryRegion *secure_sysmem) |
1067 | { | |
1068 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
1069 | char *nodename; | |
1070 | hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; | |
1071 | hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; | |
1072 | ||
1073 | memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); | |
1074 | vmstate_register_ram_global(secram); | |
1075 | memory_region_add_subregion(secure_sysmem, base, secram); | |
1076 | ||
1077 | nodename = g_strdup_printf("/secram@%" PRIx64, base); | |
1078 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
1079 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); | |
1080 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); | |
1081 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
1082 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
1083 | ||
1084 | g_free(nodename); | |
1085 | } | |
1086 | ||
f5fdcd6e PM |
1087 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
1088 | { | |
1089 | const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; | |
1090 | ||
1091 | *fdt_size = board->fdt_size; | |
1092 | return board->fdt; | |
1093 | } | |
1094 | ||
c30e1565 WH |
1095 | static void virt_build_smbios(VirtGuestInfo *guest_info) |
1096 | { | |
1097 | FWCfgState *fw_cfg = guest_info->fw_cfg; | |
1098 | uint8_t *smbios_tables, *smbios_anchor; | |
1099 | size_t smbios_tables_len, smbios_anchor_len; | |
bab27ea2 | 1100 | const char *product = "QEMU Virtual Machine"; |
c30e1565 WH |
1101 | |
1102 | if (!fw_cfg) { | |
1103 | return; | |
1104 | } | |
1105 | ||
bab27ea2 AJ |
1106 | if (kvm_enabled()) { |
1107 | product = "KVM Virtual Machine"; | |
1108 | } | |
1109 | ||
1110 | smbios_set_defaults("QEMU", product, | |
c30e1565 WH |
1111 | "1.0", false, true, SMBIOS_ENTRY_POINT_30); |
1112 | ||
1113 | smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, | |
1114 | &smbios_anchor, &smbios_anchor_len); | |
1115 | ||
1116 | if (smbios_anchor) { | |
1117 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
1118 | smbios_tables, smbios_tables_len); | |
1119 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
1120 | smbios_anchor, smbios_anchor_len); | |
1121 | } | |
1122 | } | |
1123 | ||
d7c2e2db SZ |
1124 | static |
1125 | void virt_guest_info_machine_done(Notifier *notifier, void *data) | |
1126 | { | |
1127 | VirtGuestInfoState *guest_info_state = container_of(notifier, | |
1128 | VirtGuestInfoState, machine_done); | |
1129 | virt_acpi_setup(&guest_info_state->info); | |
c30e1565 | 1130 | virt_build_smbios(&guest_info_state->info); |
d7c2e2db SZ |
1131 | } |
1132 | ||
3ef96221 | 1133 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 1134 | { |
e5a5604f | 1135 | VirtMachineState *vms = VIRT_MACHINE(machine); |
f5fdcd6e PM |
1136 | qemu_irq pic[NUM_IRQS]; |
1137 | MemoryRegion *sysmem = get_system_memory(); | |
3df708eb | 1138 | MemoryRegion *secure_sysmem = NULL; |
b92ad394 | 1139 | int gic_version = vms->gic_version; |
7ea686f5 | 1140 | int n, virt_max_cpus; |
f5fdcd6e | 1141 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
3ef96221 | 1142 | const char *cpu_model = machine->cpu_model; |
f5fdcd6e | 1143 | VirtBoardInfo *vbi; |
d7c2e2db SZ |
1144 | VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); |
1145 | VirtGuestInfo *guest_info = &guest_info_state->info; | |
f313369f | 1146 | char **cpustr; |
4824a61a | 1147 | bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); |
f5fdcd6e PM |
1148 | |
1149 | if (!cpu_model) { | |
1150 | cpu_model = "cortex-a15"; | |
1151 | } | |
1152 | ||
b92ad394 PF |
1153 | /* We can probe only here because during property set |
1154 | * KVM is not available yet | |
1155 | */ | |
1156 | if (!gic_version) { | |
0bf8039d CR |
1157 | if (!kvm_enabled()) { |
1158 | error_report("gic-version=host requires KVM"); | |
1159 | exit(1); | |
1160 | } | |
1161 | ||
b92ad394 PF |
1162 | gic_version = kvm_arm_vgic_probe(); |
1163 | if (!gic_version) { | |
faa811f6 | 1164 | error_report("Unable to determine GIC version supported by host"); |
b92ad394 PF |
1165 | exit(1); |
1166 | } | |
1167 | } | |
1168 | ||
f313369f GB |
1169 | /* Separate the actual CPU model name from any appended features */ |
1170 | cpustr = g_strsplit(cpu_model, ",", 2); | |
1171 | ||
1172 | vbi = find_machine_info(cpustr[0]); | |
f5fdcd6e PM |
1173 | |
1174 | if (!vbi) { | |
f313369f | 1175 | error_report("mach-virt: CPU %s not supported", cpustr[0]); |
f5fdcd6e PM |
1176 | exit(1); |
1177 | } | |
1178 | ||
4824a61a PM |
1179 | /* If we have an EL3 boot ROM then the assumption is that it will |
1180 | * implement PSCI itself, so disable QEMU's internal implementation | |
1181 | * so it doesn't get in the way. Instead of starting secondary | |
1182 | * CPUs in PSCI powerdown state we will start them all running and | |
1183 | * let the boot ROM sort them out. | |
1184 | * The usual case is that we do use QEMU's PSCI implementation. | |
1185 | */ | |
1186 | vbi->using_psci = !(vms->secure && firmware_loaded); | |
1187 | ||
4b280b72 AJ |
1188 | /* The maximum number of CPUs depends on the GIC version, or on how |
1189 | * many redistributors we can fit into the memory map. | |
1190 | */ | |
1191 | if (gic_version == 3) { | |
7ea686f5 | 1192 | virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; |
4b280b72 | 1193 | } else { |
7ea686f5 | 1194 | virt_max_cpus = GIC_NCPU; |
4b280b72 AJ |
1195 | } |
1196 | ||
7ea686f5 | 1197 | if (max_cpus > virt_max_cpus) { |
4b280b72 AJ |
1198 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
1199 | "supported by machine 'mach-virt' (%d)", | |
7ea686f5 | 1200 | max_cpus, virt_max_cpus); |
4b280b72 AJ |
1201 | exit(1); |
1202 | } | |
1203 | ||
f5fdcd6e PM |
1204 | vbi->smp_cpus = smp_cpus; |
1205 | ||
3ef96221 | 1206 | if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { |
71c27684 | 1207 | error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); |
f5fdcd6e PM |
1208 | exit(1); |
1209 | } | |
1210 | ||
3df708eb PM |
1211 | if (vms->secure) { |
1212 | if (kvm_enabled()) { | |
1213 | error_report("mach-virt: KVM does not support Security extensions"); | |
1214 | exit(1); | |
1215 | } | |
1216 | ||
1217 | /* The Secure view of the world is the same as the NonSecure, | |
1218 | * but with a few extra devices. Create it as a container region | |
1219 | * containing the system memory at low priority; any secure-only | |
1220 | * devices go in at higher priority and take precedence. | |
1221 | */ | |
1222 | secure_sysmem = g_new(MemoryRegion, 1); | |
1223 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", | |
1224 | UINT64_MAX); | |
1225 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
1226 | } | |
1227 | ||
f5fdcd6e | 1228 | create_fdt(vbi); |
f5fdcd6e PM |
1229 | |
1230 | for (n = 0; n < smp_cpus; n++) { | |
f313369f GB |
1231 | ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); |
1232 | CPUClass *cc = CPU_CLASS(oc); | |
f5fdcd6e | 1233 | Object *cpuobj; |
f313369f | 1234 | Error *err = NULL; |
886bc7a0 | 1235 | char *cpuopts = g_strdup(cpustr[1]); |
f5fdcd6e PM |
1236 | |
1237 | if (!oc) { | |
faa811f6 | 1238 | error_report("Unable to find CPU definition"); |
f5fdcd6e PM |
1239 | exit(1); |
1240 | } | |
1241 | cpuobj = object_new(object_class_get_name(oc)); | |
1242 | ||
f313369f | 1243 | /* Handle any CPU options specified by the user */ |
886bc7a0 AB |
1244 | cc->parse_features(CPU(cpuobj), cpuopts, &err); |
1245 | g_free(cpuopts); | |
f313369f | 1246 | if (err) { |
19867549 | 1247 | error_report_err(err); |
f313369f GB |
1248 | exit(1); |
1249 | } | |
1250 | ||
e5a5604f GB |
1251 | if (!vms->secure) { |
1252 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
1253 | } | |
1254 | ||
4824a61a PM |
1255 | if (vbi->using_psci) { |
1256 | object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, | |
1257 | "psci-conduit", NULL); | |
211b0169 | 1258 | |
4824a61a PM |
1259 | /* Secondary CPUs start in PSCI powered-down state */ |
1260 | if (n > 0) { | |
1261 | object_property_set_bool(cpuobj, true, | |
1262 | "start-powered-off", NULL); | |
1263 | } | |
f5fdcd6e | 1264 | } |
ba750085 PM |
1265 | |
1266 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { | |
1267 | object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, | |
1268 | "reset-cbar", &error_abort); | |
1269 | } | |
1270 | ||
1d939a68 PM |
1271 | object_property_set_link(cpuobj, OBJECT(sysmem), "memory", |
1272 | &error_abort); | |
3df708eb PM |
1273 | if (vms->secure) { |
1274 | object_property_set_link(cpuobj, OBJECT(secure_sysmem), | |
1275 | "secure-memory", &error_abort); | |
1276 | } | |
1d939a68 | 1277 | |
f5fdcd6e PM |
1278 | object_property_set_bool(cpuobj, true, "realized", NULL); |
1279 | } | |
f313369f | 1280 | g_strfreev(cpustr); |
b92ad394 | 1281 | fdt_add_timer_nodes(vbi, gic_version); |
f5fdcd6e | 1282 | fdt_add_cpu_nodes(vbi); |
06955739 | 1283 | fdt_add_psci_node(vbi); |
f5fdcd6e | 1284 | |
c8623c02 DM |
1285 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", |
1286 | machine->ram_size); | |
f5fdcd6e PM |
1287 | memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); |
1288 | ||
738a5d9f | 1289 | create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); |
acf82361 | 1290 | |
b92ad394 | 1291 | create_gic(vbi, pic, gic_version, vms->secure); |
f5fdcd6e | 1292 | |
01fe6b60 SZ |
1293 | fdt_add_pmu_nodes(vbi, gic_version); |
1294 | ||
9bbbf649 | 1295 | create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); |
3df708eb PM |
1296 | |
1297 | if (vms->secure) { | |
83ec1923 | 1298 | create_secure_ram(vbi, secure_sysmem); |
9bbbf649 | 1299 | create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); |
3df708eb | 1300 | } |
f5fdcd6e | 1301 | |
6e411af9 PM |
1302 | create_rtc(vbi, pic); |
1303 | ||
5125f9cd | 1304 | create_pcie(vbi, pic, vms->highmem); |
4ab29b82 | 1305 | |
b0a3721e SZ |
1306 | create_gpio(vbi, pic); |
1307 | ||
f5fdcd6e PM |
1308 | /* Create mmio transports, so the user can create virtio backends |
1309 | * (which will be automatically plugged in to the transports). If | |
1310 | * no backend is created the transport will just sit harmlessly idle. | |
1311 | */ | |
1312 | create_virtio_devices(vbi, pic); | |
1313 | ||
0b341a85 | 1314 | create_fw_cfg(vbi, &address_space_memory); |
d7c2e2db SZ |
1315 | rom_set_fw(fw_cfg_find()); |
1316 | ||
1317 | guest_info->smp_cpus = smp_cpus; | |
1318 | guest_info->fw_cfg = fw_cfg_find(); | |
1319 | guest_info->memmap = vbi->memmap; | |
1320 | guest_info->irqmap = vbi->irqmap; | |
5125f9cd | 1321 | guest_info->use_highmem = vms->highmem; |
b92ad394 | 1322 | guest_info->gic_version = gic_version; |
d7c2e2db SZ |
1323 | guest_info_state->machine_done.notify = virt_guest_info_machine_done; |
1324 | qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); | |
578f3c7b | 1325 | |
3ef96221 MA |
1326 | vbi->bootinfo.ram_size = machine->ram_size; |
1327 | vbi->bootinfo.kernel_filename = machine->kernel_filename; | |
1328 | vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
1329 | vbi->bootinfo.initrd_filename = machine->initrd_filename; | |
f5fdcd6e PM |
1330 | vbi->bootinfo.nb_cpus = smp_cpus; |
1331 | vbi->bootinfo.board_id = -1; | |
1332 | vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; | |
1333 | vbi->bootinfo.get_dtb = machvirt_dtb; | |
4824a61a | 1334 | vbi->bootinfo.firmware_loaded = firmware_loaded; |
f5fdcd6e | 1335 | arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); |
5f7a5a0e EA |
1336 | |
1337 | /* | |
1338 | * arm_load_kernel machine init done notifier registration must | |
1339 | * happen before the platform_bus_create call. In this latter, | |
1340 | * another notifier is registered which adds platform bus nodes. | |
1341 | * Notifiers are executed in registration reverse order. | |
1342 | */ | |
1343 | create_platform_bus(vbi, pic); | |
f5fdcd6e PM |
1344 | } |
1345 | ||
083a5890 GB |
1346 | static bool virt_get_secure(Object *obj, Error **errp) |
1347 | { | |
1348 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1349 | ||
1350 | return vms->secure; | |
1351 | } | |
1352 | ||
1353 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
1354 | { | |
1355 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1356 | ||
1357 | vms->secure = value; | |
1358 | } | |
1359 | ||
5125f9cd PF |
1360 | static bool virt_get_highmem(Object *obj, Error **errp) |
1361 | { | |
1362 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1363 | ||
1364 | return vms->highmem; | |
1365 | } | |
1366 | ||
1367 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
1368 | { | |
1369 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1370 | ||
1371 | vms->highmem = value; | |
1372 | } | |
1373 | ||
b92ad394 PF |
1374 | static char *virt_get_gic_version(Object *obj, Error **errp) |
1375 | { | |
1376 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1377 | const char *val = vms->gic_version == 3 ? "3" : "2"; | |
1378 | ||
1379 | return g_strdup(val); | |
1380 | } | |
1381 | ||
1382 | static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | |
1383 | { | |
1384 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1385 | ||
1386 | if (!strcmp(value, "3")) { | |
1387 | vms->gic_version = 3; | |
1388 | } else if (!strcmp(value, "2")) { | |
1389 | vms->gic_version = 2; | |
1390 | } else if (!strcmp(value, "host")) { | |
1391 | vms->gic_version = 0; /* Will probe later */ | |
1392 | } else { | |
7b55044f MA |
1393 | error_setg(errp, "Invalid gic-version value"); |
1394 | error_append_hint(errp, "Valid values are 3, 2, host.\n"); | |
b92ad394 PF |
1395 | } |
1396 | } | |
1397 | ||
ed796373 WH |
1398 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
1399 | { | |
9c94d8e6 WH |
1400 | MachineClass *mc = MACHINE_CLASS(oc); |
1401 | ||
1402 | mc->init = machvirt_init; | |
1403 | /* Start max_cpus at the maximum QEMU supports. We'll further restrict | |
1404 | * it later in machvirt_init, where we have more information about the | |
1405 | * configuration of the particular instance. | |
1406 | */ | |
1407 | mc->max_cpus = MAX_CPUMASK_BITS; | |
1408 | mc->has_dynamic_sysbus = true; | |
1409 | mc->block_default_type = IF_VIRTIO; | |
1410 | mc->no_cdrom = 1; | |
1411 | mc->pci_allow_0_address = true; | |
ed796373 WH |
1412 | } |
1413 | ||
1414 | static const TypeInfo virt_machine_info = { | |
1415 | .name = TYPE_VIRT_MACHINE, | |
1416 | .parent = TYPE_MACHINE, | |
1417 | .abstract = true, | |
1418 | .instance_size = sizeof(VirtMachineState), | |
1419 | .class_size = sizeof(VirtMachineClass), | |
1420 | .class_init = virt_machine_class_init, | |
1421 | }; | |
1422 | ||
7a2ecd95 AJ |
1423 | static void machvirt_machine_init(void) |
1424 | { | |
1425 | type_register_static(&virt_machine_info); | |
1426 | } | |
1427 | type_init(machvirt_machine_init); | |
1428 | ||
9c94d8e6 | 1429 | static void virt_2_6_instance_init(Object *obj) |
083a5890 GB |
1430 | { |
1431 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1432 | ||
2d710006 PM |
1433 | /* EL3 is disabled by default on virt: this makes us consistent |
1434 | * between KVM and TCG for this board, and it also allows us to | |
1435 | * boot UEFI blobs which assume no TrustZone support. | |
1436 | */ | |
1437 | vms->secure = false; | |
083a5890 GB |
1438 | object_property_add_bool(obj, "secure", virt_get_secure, |
1439 | virt_set_secure, NULL); | |
1440 | object_property_set_description(obj, "secure", | |
1441 | "Set on/off to enable/disable the ARM " | |
1442 | "Security Extensions (TrustZone)", | |
1443 | NULL); | |
5125f9cd PF |
1444 | |
1445 | /* High memory is enabled by default */ | |
1446 | vms->highmem = true; | |
1447 | object_property_add_bool(obj, "highmem", virt_get_highmem, | |
1448 | virt_set_highmem, NULL); | |
1449 | object_property_set_description(obj, "highmem", | |
1450 | "Set on/off to enable/disable using " | |
1451 | "physical address space above 32 bits", | |
1452 | NULL); | |
b92ad394 PF |
1453 | /* Default GIC type is v2 */ |
1454 | vms->gic_version = 2; | |
1455 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | |
1456 | virt_set_gic_version, NULL); | |
1457 | object_property_set_description(obj, "gic-version", | |
1458 | "Set GIC version. " | |
1459 | "Valid values are 2, 3 and host", NULL); | |
083a5890 GB |
1460 | } |
1461 | ||
9c94d8e6 | 1462 | static void virt_2_6_class_init(ObjectClass *oc, void *data) |
c2919690 GB |
1463 | { |
1464 | MachineClass *mc = MACHINE_CLASS(oc); | |
1465 | ||
ed796373 WH |
1466 | mc->desc = "QEMU 2.6 ARM Virtual Machine"; |
1467 | mc->alias = "virt"; | |
c2919690 GB |
1468 | } |
1469 | ||
7a2ecd95 | 1470 | static const TypeInfo machvirt_2_6_info = { |
ed796373 WH |
1471 | .name = MACHINE_TYPE_NAME("virt-2.6"), |
1472 | .parent = TYPE_VIRT_MACHINE, | |
9c94d8e6 WH |
1473 | .instance_init = virt_2_6_instance_init, |
1474 | .class_init = virt_2_6_class_init, | |
f5fdcd6e PM |
1475 | }; |
1476 | ||
7a2ecd95 | 1477 | static void machvirt_machine_2_6_init(void) |
f5fdcd6e | 1478 | { |
7a2ecd95 | 1479 | type_register_static(&machvirt_2_6_info); |
f5fdcd6e | 1480 | } |
7a2ecd95 | 1481 | type_init(machvirt_machine_2_6_init); |