]>
Commit | Line | Data |
---|---|---|
f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
31 | #include "hw/sysbus.h" | |
32 | #include "hw/arm/arm.h" | |
33 | #include "hw/arm/primecell.h" | |
afe0b380 | 34 | #include "hw/arm/virt.h" |
f5fdcd6e PM |
35 | #include "hw/devices.h" |
36 | #include "net/net.h" | |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
f5fdcd6e PM |
38 | #include "sysemu/device_tree.h" |
39 | #include "sysemu/sysemu.h" | |
40 | #include "sysemu/kvm.h" | |
41 | #include "hw/boards.h" | |
acf82361 | 42 | #include "hw/loader.h" |
f5fdcd6e PM |
43 | #include "exec/address-spaces.h" |
44 | #include "qemu/bitops.h" | |
45 | #include "qemu/error-report.h" | |
4ab29b82 | 46 | #include "hw/pci-host/gpex.h" |
d7c2e2db | 47 | #include "hw/arm/virt-acpi-build.h" |
5f7a5a0e EA |
48 | #include "hw/arm/sysbus-fdt.h" |
49 | #include "hw/platform-bus.h" | |
decf4f80 | 50 | #include "hw/arm/fdt.h" |
0e3e858f | 51 | #include "hw/intc/arm_gic_common.h" |
e6fbcbc4 | 52 | #include "kvm_arm.h" |
c30e1565 | 53 | #include "hw/smbios/smbios.h" |
f5fdcd6e | 54 | |
f5fdcd6e | 55 | /* Number of external interrupt lines to configure the GIC with */ |
5f7a5a0e | 56 | #define NUM_IRQS 256 |
f5fdcd6e | 57 | |
5f7a5a0e EA |
58 | #define PLATFORM_BUS_NUM_IRQS 64 |
59 | ||
60 | static ARMPlatformBusSystemParams platform_bus_params; | |
61 | ||
f5fdcd6e PM |
62 | typedef struct VirtBoardInfo { |
63 | struct arm_boot_info bootinfo; | |
64 | const char *cpu_model; | |
f5fdcd6e PM |
65 | const MemMapEntry *memmap; |
66 | const int *irqmap; | |
67 | int smp_cpus; | |
68 | void *fdt; | |
69 | int fdt_size; | |
70 | uint32_t clock_phandle; | |
747d009d | 71 | uint32_t gic_phandle; |
bd204e63 | 72 | uint32_t v2m_phandle; |
f5fdcd6e PM |
73 | } VirtBoardInfo; |
74 | ||
c2919690 GB |
75 | typedef struct { |
76 | MachineClass parent; | |
77 | VirtBoardInfo *daughterboard; | |
78 | } VirtMachineClass; | |
79 | ||
80 | typedef struct { | |
81 | MachineState parent; | |
083a5890 | 82 | bool secure; |
5125f9cd | 83 | bool highmem; |
c2919690 GB |
84 | } VirtMachineState; |
85 | ||
86 | #define TYPE_VIRT_MACHINE "virt" | |
87 | #define VIRT_MACHINE(obj) \ | |
88 | OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) | |
89 | #define VIRT_MACHINE_GET_CLASS(obj) \ | |
90 | OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) | |
91 | #define VIRT_MACHINE_CLASS(klass) \ | |
92 | OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) | |
93 | ||
f5fdcd6e PM |
94 | /* Addresses and sizes of our components. |
95 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
96 | * 128MB..256MB is used for miscellaneous device I/O. | |
97 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
98 | * PCI memory window will go if we add a PCI host controller). | |
99 | * 1GB and up is RAM (which may happily spill over into the | |
100 | * high memory region beyond 4GB). | |
101 | * This represents a compromise between how much RAM can be given to | |
102 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
103 | * Note that devices should generally be placed at multiples of 0x10000, |
104 | * to accommodate guests using 64K pages. | |
f5fdcd6e PM |
105 | */ |
106 | static const MemMapEntry a15memmap[] = { | |
107 | /* Space up to 0x8000000 is reserved for a boot ROM */ | |
94edf02c EA |
108 | [VIRT_FLASH] = { 0, 0x08000000 }, |
109 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 110 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
111 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
112 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
113 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
114 | [VIRT_UART] = { 0x09000000, 0x00001000 }, | |
115 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
116 | [VIRT_FW_CFG] = { 0x09020000, 0x0000000a }, | |
117 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, | |
f5fdcd6e | 118 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c EA |
119 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
120 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, | |
121 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
122 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
123 | [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 }, | |
5125f9cd PF |
124 | /* Second PCIe window, 512GB wide at the 512GB boundary */ |
125 | [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, | |
f5fdcd6e PM |
126 | }; |
127 | ||
128 | static const int a15irqmap[] = { | |
129 | [VIRT_UART] = 1, | |
6e411af9 | 130 | [VIRT_RTC] = 2, |
4ab29b82 | 131 | [VIRT_PCIE] = 3, /* ... to 6 */ |
f5fdcd6e | 132 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 133 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
5f7a5a0e | 134 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
135 | }; |
136 | ||
137 | static VirtBoardInfo machines[] = { | |
138 | { | |
139 | .cpu_model = "cortex-a15", | |
f5fdcd6e PM |
140 | .memmap = a15memmap, |
141 | .irqmap = a15irqmap, | |
142 | }, | |
8772de2c SZ |
143 | { |
144 | .cpu_model = "cortex-a53", | |
145 | .memmap = a15memmap, | |
146 | .irqmap = a15irqmap, | |
147 | }, | |
f42c5c8e PM |
148 | { |
149 | .cpu_model = "cortex-a57", | |
150 | .memmap = a15memmap, | |
151 | .irqmap = a15irqmap, | |
152 | }, | |
198aa064 PM |
153 | { |
154 | .cpu_model = "host", | |
198aa064 PM |
155 | .memmap = a15memmap, |
156 | .irqmap = a15irqmap, | |
157 | }, | |
f5fdcd6e PM |
158 | }; |
159 | ||
160 | static VirtBoardInfo *find_machine_info(const char *cpu) | |
161 | { | |
162 | int i; | |
163 | ||
164 | for (i = 0; i < ARRAY_SIZE(machines); i++) { | |
165 | if (strcmp(cpu, machines[i].cpu_model) == 0) { | |
166 | return &machines[i]; | |
167 | } | |
168 | } | |
169 | return NULL; | |
170 | } | |
171 | ||
172 | static void create_fdt(VirtBoardInfo *vbi) | |
173 | { | |
174 | void *fdt = create_device_tree(&vbi->fdt_size); | |
175 | ||
176 | if (!fdt) { | |
177 | error_report("create_device_tree() failed"); | |
178 | exit(1); | |
179 | } | |
180 | ||
181 | vbi->fdt = fdt; | |
182 | ||
183 | /* Header */ | |
5a4348d1 PC |
184 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
185 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
186 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
f5fdcd6e PM |
187 | |
188 | /* | |
189 | * /chosen and /memory nodes must exist for load_dtb | |
190 | * to fill in necessary properties later | |
191 | */ | |
5a4348d1 PC |
192 | qemu_fdt_add_subnode(fdt, "/chosen"); |
193 | qemu_fdt_add_subnode(fdt, "/memory"); | |
194 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
f5fdcd6e PM |
195 | |
196 | /* Clock node, for the benefit of the UART. The kernel device tree | |
197 | * binding documentation claims the PL011 node clock properties are | |
198 | * optional but in practice if you omit them the kernel refuses to | |
199 | * probe for the device. | |
200 | */ | |
5a4348d1 PC |
201 | vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
202 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); | |
203 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
204 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
205 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
206 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 207 | "clk24mhz"); |
5a4348d1 | 208 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); |
f5fdcd6e | 209 | |
06955739 PS |
210 | } |
211 | ||
212 | static void fdt_add_psci_node(const VirtBoardInfo *vbi) | |
213 | { | |
211b0169 RH |
214 | uint32_t cpu_suspend_fn; |
215 | uint32_t cpu_off_fn; | |
216 | uint32_t cpu_on_fn; | |
217 | uint32_t migrate_fn; | |
06955739 PS |
218 | void *fdt = vbi->fdt; |
219 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); | |
220 | ||
211b0169 RH |
221 | qemu_fdt_add_subnode(fdt, "/psci"); |
222 | if (armcpu->psci_version == 2) { | |
223 | const char comp[] = "arm,psci-0.2\0arm,psci"; | |
224 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | |
863714ba | 225 | |
211b0169 RH |
226 | cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; |
227 | if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { | |
228 | cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; | |
229 | cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; | |
230 | migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; | |
231 | } else { | |
232 | cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; | |
233 | cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; | |
234 | migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; | |
06955739 | 235 | } |
211b0169 RH |
236 | } else { |
237 | qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); | |
06955739 | 238 | |
211b0169 RH |
239 | cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; |
240 | cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; | |
241 | cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; | |
242 | migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; | |
f5fdcd6e | 243 | } |
211b0169 RH |
244 | |
245 | /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer | |
246 | * to the instruction that should be used to invoke PSCI functions. | |
247 | * However, the device tree binding uses 'method' instead, so that is | |
248 | * what we should use here. | |
249 | */ | |
250 | qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); | |
251 | ||
252 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); | |
253 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); | |
254 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); | |
255 | qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); | |
f5fdcd6e PM |
256 | } |
257 | ||
258 | static void fdt_add_timer_nodes(const VirtBoardInfo *vbi) | |
259 | { | |
260 | /* Note that on A15 h/w these interrupts are level-triggered, | |
261 | * but for the GIC implementation provided by both QEMU and KVM | |
262 | * they are edge-triggered. | |
263 | */ | |
b32a9509 | 264 | ARMCPU *armcpu; |
f5fdcd6e PM |
265 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; |
266 | ||
267 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | |
268 | GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1); | |
269 | ||
5a4348d1 | 270 | qemu_fdt_add_subnode(vbi->fdt, "/timer"); |
b32a9509 CF |
271 | |
272 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
273 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
274 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
275 | qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", | |
276 | compat, sizeof(compat)); | |
277 | } else { | |
278 | qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", | |
279 | "arm,armv7-timer"); | |
280 | } | |
5a4348d1 | 281 | qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", |
ee246400 SZ |
282 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
283 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
284 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
285 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
286 | } |
287 | ||
288 | static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi) | |
289 | { | |
290 | int cpu; | |
291 | ||
5a4348d1 PC |
292 | qemu_fdt_add_subnode(vbi->fdt, "/cpus"); |
293 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1); | |
294 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); | |
f5fdcd6e PM |
295 | |
296 | for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { | |
297 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | |
298 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
299 | ||
5a4348d1 PC |
300 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
301 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); | |
302 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", | |
f5fdcd6e PM |
303 | armcpu->dtb_compatible); |
304 | ||
305 | if (vbi->smp_cpus > 1) { | |
5a4348d1 | 306 | qemu_fdt_setprop_string(vbi->fdt, nodename, |
f5fdcd6e PM |
307 | "enable-method", "psci"); |
308 | } | |
309 | ||
eb5e1d3c | 310 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity); |
f5fdcd6e PM |
311 | g_free(nodename); |
312 | } | |
313 | } | |
314 | ||
bd204e63 | 315 | static void fdt_add_v2m_gic_node(VirtBoardInfo *vbi) |
f5fdcd6e | 316 | { |
bd204e63 CD |
317 | vbi->v2m_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
318 | qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); | |
319 | qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", | |
320 | "arm,gic-v2m-frame"); | |
321 | qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); | |
322 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", | |
323 | 2, vbi->memmap[VIRT_GIC_V2M].base, | |
324 | 2, vbi->memmap[VIRT_GIC_V2M].size); | |
325 | qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->v2m_phandle); | |
326 | } | |
f5fdcd6e | 327 | |
bd204e63 CD |
328 | static void fdt_add_gic_node(VirtBoardInfo *vbi) |
329 | { | |
747d009d CD |
330 | vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
331 | qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); | |
f5fdcd6e | 332 | |
5a4348d1 | 333 | qemu_fdt_add_subnode(vbi->fdt, "/intc"); |
64204743 | 334 | /* 'cortex-a15-gic' means 'GIC v2' */ |
5a4348d1 | 335 | qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", |
64204743 | 336 | "arm,cortex-a15-gic"); |
5a4348d1 PC |
337 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); |
338 | qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); | |
339 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", | |
f5fdcd6e PM |
340 | 2, vbi->memmap[VIRT_GIC_DIST].base, |
341 | 2, vbi->memmap[VIRT_GIC_DIST].size, | |
342 | 2, vbi->memmap[VIRT_GIC_CPU].base, | |
343 | 2, vbi->memmap[VIRT_GIC_CPU].size); | |
dfd90a87 CD |
344 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); |
345 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); | |
346 | qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); | |
747d009d | 347 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); |
f5fdcd6e PM |
348 | } |
349 | ||
bd204e63 CD |
350 | static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic) |
351 | { | |
352 | int i; | |
353 | int irq = vbi->irqmap[VIRT_GIC_V2M]; | |
354 | DeviceState *dev; | |
355 | ||
356 | dev = qdev_create(NULL, "arm-gicv2m"); | |
357 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); | |
358 | qdev_prop_set_uint32(dev, "base-spi", irq); | |
359 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
360 | qdev_init_nofail(dev); | |
361 | ||
362 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
363 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
364 | } | |
365 | ||
366 | fdt_add_v2m_gic_node(vbi); | |
367 | } | |
368 | ||
747d009d | 369 | static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic) |
64204743 PM |
370 | { |
371 | /* We create a standalone GIC v2 */ | |
372 | DeviceState *gicdev; | |
373 | SysBusDevice *gicbusdev; | |
e6fbcbc4 | 374 | const char *gictype; |
64204743 PM |
375 | int i; |
376 | ||
e6fbcbc4 | 377 | gictype = gic_class_name(); |
64204743 PM |
378 | |
379 | gicdev = qdev_create(NULL, gictype); | |
380 | qdev_prop_set_uint32(gicdev, "revision", 2); | |
381 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); | |
382 | /* Note that the num-irq property counts both internal and external | |
383 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
384 | */ | |
385 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
386 | qdev_init_nofail(gicdev); | |
387 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
388 | sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); | |
389 | sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); | |
390 | ||
391 | /* Wire the outputs from each CPU's generic timer to the | |
392 | * appropriate GIC PPI inputs, and the GIC's IRQ output to | |
393 | * the CPU's IRQ input. | |
394 | */ | |
395 | for (i = 0; i < smp_cpus; i++) { | |
396 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 397 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
398 | int irq; |
399 | /* Mapping from the output timer irq lines from the CPU to the | |
400 | * GIC PPI inputs we use for the virt board. | |
64204743 | 401 | */ |
a007b1f8 PM |
402 | const int timer_irq[] = { |
403 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
404 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
405 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
406 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
407 | }; | |
408 | ||
409 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
410 | qdev_connect_gpio_out(cpudev, irq, | |
411 | qdev_get_gpio_in(gicdev, | |
412 | ppibase + timer_irq[irq])); | |
413 | } | |
64204743 PM |
414 | |
415 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
8e7b4ca0 GB |
416 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
417 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
64204743 PM |
418 | } |
419 | ||
420 | for (i = 0; i < NUM_IRQS; i++) { | |
421 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
422 | } | |
423 | ||
747d009d | 424 | fdt_add_gic_node(vbi); |
bd204e63 CD |
425 | |
426 | create_v2m(vbi, pic); | |
64204743 PM |
427 | } |
428 | ||
f5fdcd6e PM |
429 | static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic) |
430 | { | |
431 | char *nodename; | |
432 | hwaddr base = vbi->memmap[VIRT_UART].base; | |
433 | hwaddr size = vbi->memmap[VIRT_UART].size; | |
434 | int irq = vbi->irqmap[VIRT_UART]; | |
435 | const char compat[] = "arm,pl011\0arm,primecell"; | |
436 | const char clocknames[] = "uartclk\0apb_pclk"; | |
437 | ||
438 | sysbus_create_simple("pl011", base, pic[irq]); | |
439 | ||
440 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
5a4348d1 | 441 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
f5fdcd6e | 442 | /* Note that we can't use setprop_string because of the embedded NUL */ |
5a4348d1 | 443 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", |
f5fdcd6e | 444 | compat, sizeof(compat)); |
5a4348d1 | 445 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
f5fdcd6e | 446 | 2, base, 2, size); |
5a4348d1 | 447 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", |
f5fdcd6e | 448 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 449 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
5a4348d1 | 450 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", |
f5fdcd6e | 451 | vbi->clock_phandle, vbi->clock_phandle); |
5a4348d1 | 452 | qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", |
f5fdcd6e | 453 | clocknames, sizeof(clocknames)); |
f022b8e9 | 454 | |
9c7074da | 455 | qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); |
f5fdcd6e PM |
456 | g_free(nodename); |
457 | } | |
458 | ||
6e411af9 PM |
459 | static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic) |
460 | { | |
461 | char *nodename; | |
462 | hwaddr base = vbi->memmap[VIRT_RTC].base; | |
463 | hwaddr size = vbi->memmap[VIRT_RTC].size; | |
464 | int irq = vbi->irqmap[VIRT_RTC]; | |
465 | const char compat[] = "arm,pl031\0arm,primecell"; | |
466 | ||
467 | sysbus_create_simple("pl031", base, pic[irq]); | |
468 | ||
469 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
470 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
471 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); | |
472 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
473 | 2, base, 2, size); | |
474 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
475 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
0be969a2 | 476 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
6e411af9 PM |
477 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); |
478 | qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); | |
479 | g_free(nodename); | |
480 | } | |
481 | ||
f5fdcd6e PM |
482 | static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic) |
483 | { | |
484 | int i; | |
485 | hwaddr size = vbi->memmap[VIRT_MMIO].size; | |
486 | ||
587078f0 LE |
487 | /* We create the transports in forwards order. Since qbus_realize() |
488 | * prepends (not appends) new child buses, the incrementing loop below will | |
489 | * create a list of virtio-mmio buses with decreasing base addresses. | |
490 | * | |
491 | * When a -device option is processed from the command line, | |
492 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
493 | * order. The upshot is that -device options in increasing command line | |
494 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
495 | * | |
496 | * When this code was originally written, that arrangement ensured that the | |
497 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
498 | * the first -device on the command line. (The end-to-end order is a | |
499 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
500 | * guest kernel's name-to-address assignment strategy.) | |
501 | * | |
502 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
503 | * the message, if not necessarily the code, of commit 70161ff336. | |
504 | * Therefore the loop now establishes the inverse of the original intent. | |
505 | * | |
506 | * Unfortunately, we can't counteract the kernel change by reversing the | |
507 | * loop; it would break existing command lines. | |
508 | * | |
509 | * In any case, the kernel makes no guarantee about the stability of | |
510 | * enumeration order of virtio devices (as demonstrated by it changing | |
511 | * between kernel versions). For reliable and stable identification | |
512 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
513 | */ |
514 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
515 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
516 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
517 | ||
518 | sysbus_create_simple("virtio-mmio", base, pic[irq]); | |
519 | } | |
520 | ||
587078f0 LE |
521 | /* We add dtb nodes in reverse order so that they appear in the finished |
522 | * device tree lowest address first. | |
523 | * | |
524 | * Note that this mapping is independent of the loop above. The previous | |
525 | * loop influences virtio device to virtio transport assignment, whereas | |
526 | * this loop controls how virtio transports are laid out in the dtb. | |
527 | */ | |
f5fdcd6e PM |
528 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
529 | char *nodename; | |
530 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
531 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
532 | ||
533 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
5a4348d1 PC |
534 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
535 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
536 | "compatible", "virtio,mmio"); | |
537 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
538 | 2, base, 2, size); | |
539 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
540 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
541 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
f5fdcd6e PM |
542 | g_free(nodename); |
543 | } | |
544 | } | |
545 | ||
acf82361 PM |
546 | static void create_one_flash(const char *name, hwaddr flashbase, |
547 | hwaddr flashsize) | |
548 | { | |
549 | /* Create and map a single flash device. We use the same | |
550 | * parameters as the flash devices on the Versatile Express board. | |
551 | */ | |
552 | DriveInfo *dinfo = drive_get_next(IF_PFLASH); | |
553 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
554 | const uint64_t sectorlength = 256 * 1024; | |
555 | ||
9b3d111a MA |
556 | if (dinfo) { |
557 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
558 | &error_abort); | |
acf82361 PM |
559 | } |
560 | ||
561 | qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); | |
562 | qdev_prop_set_uint64(dev, "sector-length", sectorlength); | |
563 | qdev_prop_set_uint8(dev, "width", 4); | |
564 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 565 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
566 | qdev_prop_set_uint16(dev, "id0", 0x89); |
567 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
568 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
569 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
570 | qdev_prop_set_string(dev, "name", name); | |
571 | qdev_init_nofail(dev); | |
572 | ||
573 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, flashbase); | |
574 | } | |
575 | ||
576 | static void create_flash(const VirtBoardInfo *vbi) | |
577 | { | |
578 | /* Create two flash devices to fill the VIRT_FLASH space in the memmap. | |
579 | * Any file passed via -bios goes in the first of these. | |
580 | */ | |
581 | hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; | |
582 | hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; | |
583 | char *nodename; | |
584 | ||
585 | if (bios_name) { | |
6e05a12f | 586 | char *fn; |
4de9a883 | 587 | int image_size; |
acf82361 PM |
588 | |
589 | if (drive_get(IF_PFLASH, 0, 0)) { | |
590 | error_report("The contents of the first flash device may be " | |
591 | "specified with -bios or with -drive if=pflash... " | |
592 | "but you cannot use both options at once"); | |
593 | exit(1); | |
594 | } | |
595 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
4de9a883 SW |
596 | if (!fn) { |
597 | error_report("Could not find ROM image '%s'", bios_name); | |
598 | exit(1); | |
599 | } | |
600 | image_size = load_image_targphys(fn, flashbase, flashsize); | |
601 | g_free(fn); | |
602 | if (image_size < 0) { | |
acf82361 PM |
603 | error_report("Could not load ROM image '%s'", bios_name); |
604 | exit(1); | |
605 | } | |
606 | } | |
607 | ||
608 | create_one_flash("virt.flash0", flashbase, flashsize); | |
609 | create_one_flash("virt.flash1", flashbase + flashsize, flashsize); | |
610 | ||
611 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
612 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
613 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
614 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
615 | 2, flashbase, 2, flashsize, | |
616 | 2, flashbase + flashsize, 2, flashsize); | |
617 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
618 | g_free(nodename); | |
619 | } | |
620 | ||
578f3c7b LE |
621 | static void create_fw_cfg(const VirtBoardInfo *vbi) |
622 | { | |
623 | hwaddr base = vbi->memmap[VIRT_FW_CFG].base; | |
624 | hwaddr size = vbi->memmap[VIRT_FW_CFG].size; | |
625 | char *nodename; | |
626 | ||
627 | fw_cfg_init_mem_wide(base + 8, base, 8); | |
628 | ||
629 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
630 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
631 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
632 | "compatible", "qemu,fw-cfg-mmio"); | |
633 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
634 | 2, base, 2, size); | |
635 | g_free(nodename); | |
636 | } | |
637 | ||
4ab29b82 AG |
638 | static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle, |
639 | int first_irq, const char *nodename) | |
640 | { | |
641 | int devfn, pin; | |
dfd90a87 | 642 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
643 | uint32_t *irq_map = full_irq_map; |
644 | ||
645 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
646 | for (pin = 0; pin < 4; pin++) { | |
647 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
648 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
649 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
650 | int i; | |
651 | ||
652 | uint32_t map[] = { | |
653 | devfn << 8, 0, 0, /* devfn */ | |
654 | pin + 1, /* PCI pin */ | |
dfd90a87 | 655 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
656 | |
657 | /* Convert map to big endian */ | |
dfd90a87 | 658 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
659 | irq_map[i] = cpu_to_be32(map[i]); |
660 | } | |
dfd90a87 | 661 | irq_map += 10; |
4ab29b82 AG |
662 | } |
663 | } | |
664 | ||
665 | qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", | |
666 | full_irq_map, sizeof(full_irq_map)); | |
667 | ||
668 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", | |
669 | 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ | |
670 | 0x7 /* PCI irq */); | |
671 | } | |
672 | ||
5125f9cd PF |
673 | static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic, |
674 | bool use_highmem) | |
4ab29b82 | 675 | { |
6a1f001b SZ |
676 | hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; |
677 | hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; | |
5125f9cd PF |
678 | hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; |
679 | hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; | |
6a1f001b SZ |
680 | hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; |
681 | hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; | |
682 | hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; | |
683 | hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; | |
684 | hwaddr base = base_mmio; | |
685 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
4ab29b82 AG |
686 | int irq = vbi->irqmap[VIRT_PCIE]; |
687 | MemoryRegion *mmio_alias; | |
688 | MemoryRegion *mmio_reg; | |
689 | MemoryRegion *ecam_alias; | |
690 | MemoryRegion *ecam_reg; | |
691 | DeviceState *dev; | |
692 | char *nodename; | |
693 | int i; | |
694 | ||
4ab29b82 AG |
695 | dev = qdev_create(NULL, TYPE_GPEX_HOST); |
696 | qdev_init_nofail(dev); | |
697 | ||
698 | /* Map only the first size_ecam bytes of ECAM space */ | |
699 | ecam_alias = g_new0(MemoryRegion, 1); | |
700 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
701 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
702 | ecam_reg, 0, size_ecam); | |
703 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
704 | ||
705 | /* Map the MMIO window into system address space so as to expose | |
706 | * the section of PCI MMIO space which starts at the same base address | |
707 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
708 | * the window). | |
709 | */ | |
710 | mmio_alias = g_new0(MemoryRegion, 1); | |
711 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
712 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
713 | mmio_reg, base_mmio, size_mmio); | |
714 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
715 | ||
5125f9cd PF |
716 | if (use_highmem) { |
717 | /* Map high MMIO space */ | |
718 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
719 | ||
720 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
721 | mmio_reg, base_mmio_high, size_mmio_high); | |
722 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
723 | high_mmio_alias); | |
724 | } | |
725 | ||
4ab29b82 | 726 | /* Map IO port space */ |
6a1f001b | 727 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
728 | |
729 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
730 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
731 | } | |
732 | ||
733 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); | |
734 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
735 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
736 | "compatible", "pci-host-ecam-generic"); | |
737 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); | |
738 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); | |
739 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); | |
740 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, | |
741 | nr_pcie_buses - 1); | |
742 | ||
bd204e63 CD |
743 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", vbi->v2m_phandle); |
744 | ||
4ab29b82 AG |
745 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
746 | 2, base_ecam, 2, size_ecam); | |
5125f9cd PF |
747 | |
748 | if (use_highmem) { | |
749 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
750 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
751 | 2, base_pio, 2, size_pio, | |
752 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
753 | 2, base_mmio, 2, size_mmio, | |
754 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
755 | 2, base_mmio_high, | |
756 | 2, base_mmio_high, 2, size_mmio_high); | |
757 | } else { | |
758 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
759 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
760 | 2, base_pio, 2, size_pio, | |
761 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
762 | 2, base_mmio, 2, size_mmio); | |
763 | } | |
4ab29b82 AG |
764 | |
765 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); | |
747d009d | 766 | create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); |
4ab29b82 AG |
767 | |
768 | g_free(nodename); | |
769 | } | |
770 | ||
5f7a5a0e EA |
771 | static void create_platform_bus(VirtBoardInfo *vbi, qemu_irq *pic) |
772 | { | |
773 | DeviceState *dev; | |
774 | SysBusDevice *s; | |
775 | int i; | |
776 | ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); | |
777 | MemoryRegion *sysmem = get_system_memory(); | |
778 | ||
779 | platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; | |
780 | platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; | |
781 | platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; | |
782 | platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; | |
783 | ||
784 | fdt_params->system_params = &platform_bus_params; | |
785 | fdt_params->binfo = &vbi->bootinfo; | |
786 | fdt_params->intc = "/intc"; | |
787 | /* | |
788 | * register a machine init done notifier that creates the device tree | |
789 | * nodes of the platform bus and its children dynamic sysbus devices | |
790 | */ | |
791 | arm_register_platform_bus_fdt_creator(fdt_params); | |
792 | ||
793 | dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); | |
794 | dev->id = TYPE_PLATFORM_BUS_DEVICE; | |
795 | qdev_prop_set_uint32(dev, "num_irqs", | |
796 | platform_bus_params.platform_bus_num_irqs); | |
797 | qdev_prop_set_uint32(dev, "mmio_size", | |
798 | platform_bus_params.platform_bus_size); | |
799 | qdev_init_nofail(dev); | |
800 | s = SYS_BUS_DEVICE(dev); | |
801 | ||
802 | for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { | |
803 | int irqn = platform_bus_params.platform_bus_first_irq + i; | |
804 | sysbus_connect_irq(s, i, pic[irqn]); | |
805 | } | |
806 | ||
807 | memory_region_add_subregion(sysmem, | |
808 | platform_bus_params.platform_bus_base, | |
809 | sysbus_mmio_get_region(s, 0)); | |
810 | } | |
811 | ||
f5fdcd6e PM |
812 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
813 | { | |
814 | const VirtBoardInfo *board = (const VirtBoardInfo *)binfo; | |
815 | ||
816 | *fdt_size = board->fdt_size; | |
817 | return board->fdt; | |
818 | } | |
819 | ||
c30e1565 WH |
820 | static void virt_build_smbios(VirtGuestInfo *guest_info) |
821 | { | |
822 | FWCfgState *fw_cfg = guest_info->fw_cfg; | |
823 | uint8_t *smbios_tables, *smbios_anchor; | |
824 | size_t smbios_tables_len, smbios_anchor_len; | |
825 | ||
826 | if (!fw_cfg) { | |
827 | return; | |
828 | } | |
829 | ||
830 | smbios_set_defaults("QEMU", "QEMU Virtual Machine", | |
831 | "1.0", false, true, SMBIOS_ENTRY_POINT_30); | |
832 | ||
833 | smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, | |
834 | &smbios_anchor, &smbios_anchor_len); | |
835 | ||
836 | if (smbios_anchor) { | |
837 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
838 | smbios_tables, smbios_tables_len); | |
839 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
840 | smbios_anchor, smbios_anchor_len); | |
841 | } | |
842 | } | |
843 | ||
d7c2e2db SZ |
844 | static |
845 | void virt_guest_info_machine_done(Notifier *notifier, void *data) | |
846 | { | |
847 | VirtGuestInfoState *guest_info_state = container_of(notifier, | |
848 | VirtGuestInfoState, machine_done); | |
849 | virt_acpi_setup(&guest_info_state->info); | |
c30e1565 | 850 | virt_build_smbios(&guest_info_state->info); |
d7c2e2db SZ |
851 | } |
852 | ||
3ef96221 | 853 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 854 | { |
e5a5604f | 855 | VirtMachineState *vms = VIRT_MACHINE(machine); |
f5fdcd6e PM |
856 | qemu_irq pic[NUM_IRQS]; |
857 | MemoryRegion *sysmem = get_system_memory(); | |
858 | int n; | |
859 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
3ef96221 | 860 | const char *cpu_model = machine->cpu_model; |
f5fdcd6e | 861 | VirtBoardInfo *vbi; |
d7c2e2db SZ |
862 | VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); |
863 | VirtGuestInfo *guest_info = &guest_info_state->info; | |
f313369f | 864 | char **cpustr; |
f5fdcd6e PM |
865 | |
866 | if (!cpu_model) { | |
867 | cpu_model = "cortex-a15"; | |
868 | } | |
869 | ||
f313369f GB |
870 | /* Separate the actual CPU model name from any appended features */ |
871 | cpustr = g_strsplit(cpu_model, ",", 2); | |
872 | ||
873 | vbi = find_machine_info(cpustr[0]); | |
f5fdcd6e PM |
874 | |
875 | if (!vbi) { | |
f313369f | 876 | error_report("mach-virt: CPU %s not supported", cpustr[0]); |
f5fdcd6e PM |
877 | exit(1); |
878 | } | |
879 | ||
880 | vbi->smp_cpus = smp_cpus; | |
881 | ||
3ef96221 | 882 | if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { |
f5fdcd6e PM |
883 | error_report("mach-virt: cannot model more than 30GB RAM"); |
884 | exit(1); | |
885 | } | |
886 | ||
887 | create_fdt(vbi); | |
f5fdcd6e PM |
888 | |
889 | for (n = 0; n < smp_cpus; n++) { | |
f313369f GB |
890 | ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); |
891 | CPUClass *cc = CPU_CLASS(oc); | |
f5fdcd6e | 892 | Object *cpuobj; |
f313369f | 893 | Error *err = NULL; |
886bc7a0 | 894 | char *cpuopts = g_strdup(cpustr[1]); |
f5fdcd6e PM |
895 | |
896 | if (!oc) { | |
897 | fprintf(stderr, "Unable to find CPU definition\n"); | |
898 | exit(1); | |
899 | } | |
900 | cpuobj = object_new(object_class_get_name(oc)); | |
901 | ||
f313369f | 902 | /* Handle any CPU options specified by the user */ |
886bc7a0 AB |
903 | cc->parse_features(CPU(cpuobj), cpuopts, &err); |
904 | g_free(cpuopts); | |
f313369f | 905 | if (err) { |
19867549 | 906 | error_report_err(err); |
f313369f GB |
907 | exit(1); |
908 | } | |
909 | ||
e5a5604f GB |
910 | if (!vms->secure) { |
911 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
912 | } | |
913 | ||
211b0169 RH |
914 | object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, "psci-conduit", |
915 | NULL); | |
916 | ||
f5fdcd6e PM |
917 | /* Secondary CPUs start in PSCI powered-down state */ |
918 | if (n > 0) { | |
919 | object_property_set_bool(cpuobj, true, "start-powered-off", NULL); | |
920 | } | |
ba750085 PM |
921 | |
922 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { | |
923 | object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, | |
924 | "reset-cbar", &error_abort); | |
925 | } | |
926 | ||
f5fdcd6e PM |
927 | object_property_set_bool(cpuobj, true, "realized", NULL); |
928 | } | |
f313369f | 929 | g_strfreev(cpustr); |
b32a9509 | 930 | fdt_add_timer_nodes(vbi); |
f5fdcd6e | 931 | fdt_add_cpu_nodes(vbi); |
06955739 | 932 | fdt_add_psci_node(vbi); |
f5fdcd6e | 933 | |
c8623c02 DM |
934 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", |
935 | machine->ram_size); | |
f5fdcd6e PM |
936 | memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); |
937 | ||
acf82361 PM |
938 | create_flash(vbi); |
939 | ||
747d009d | 940 | create_gic(vbi, pic); |
f5fdcd6e PM |
941 | |
942 | create_uart(vbi, pic); | |
943 | ||
6e411af9 PM |
944 | create_rtc(vbi, pic); |
945 | ||
5125f9cd | 946 | create_pcie(vbi, pic, vms->highmem); |
4ab29b82 | 947 | |
f5fdcd6e PM |
948 | /* Create mmio transports, so the user can create virtio backends |
949 | * (which will be automatically plugged in to the transports). If | |
950 | * no backend is created the transport will just sit harmlessly idle. | |
951 | */ | |
952 | create_virtio_devices(vbi, pic); | |
953 | ||
578f3c7b | 954 | create_fw_cfg(vbi); |
d7c2e2db SZ |
955 | rom_set_fw(fw_cfg_find()); |
956 | ||
957 | guest_info->smp_cpus = smp_cpus; | |
958 | guest_info->fw_cfg = fw_cfg_find(); | |
959 | guest_info->memmap = vbi->memmap; | |
960 | guest_info->irqmap = vbi->irqmap; | |
5125f9cd | 961 | guest_info->use_highmem = vms->highmem; |
d7c2e2db SZ |
962 | guest_info_state->machine_done.notify = virt_guest_info_machine_done; |
963 | qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); | |
578f3c7b | 964 | |
3ef96221 MA |
965 | vbi->bootinfo.ram_size = machine->ram_size; |
966 | vbi->bootinfo.kernel_filename = machine->kernel_filename; | |
967 | vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
968 | vbi->bootinfo.initrd_filename = machine->initrd_filename; | |
f5fdcd6e PM |
969 | vbi->bootinfo.nb_cpus = smp_cpus; |
970 | vbi->bootinfo.board_id = -1; | |
971 | vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; | |
972 | vbi->bootinfo.get_dtb = machvirt_dtb; | |
aa351061 | 973 | vbi->bootinfo.firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); |
f5fdcd6e | 974 | arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); |
5f7a5a0e EA |
975 | |
976 | /* | |
977 | * arm_load_kernel machine init done notifier registration must | |
978 | * happen before the platform_bus_create call. In this latter, | |
979 | * another notifier is registered which adds platform bus nodes. | |
980 | * Notifiers are executed in registration reverse order. | |
981 | */ | |
982 | create_platform_bus(vbi, pic); | |
f5fdcd6e PM |
983 | } |
984 | ||
083a5890 GB |
985 | static bool virt_get_secure(Object *obj, Error **errp) |
986 | { | |
987 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
988 | ||
989 | return vms->secure; | |
990 | } | |
991 | ||
992 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
993 | { | |
994 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
995 | ||
996 | vms->secure = value; | |
997 | } | |
998 | ||
5125f9cd PF |
999 | static bool virt_get_highmem(Object *obj, Error **errp) |
1000 | { | |
1001 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1002 | ||
1003 | return vms->highmem; | |
1004 | } | |
1005 | ||
1006 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
1007 | { | |
1008 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1009 | ||
1010 | vms->highmem = value; | |
1011 | } | |
1012 | ||
083a5890 GB |
1013 | static void virt_instance_init(Object *obj) |
1014 | { | |
1015 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1016 | ||
1017 | /* EL3 is enabled by default on virt */ | |
1018 | vms->secure = true; | |
1019 | object_property_add_bool(obj, "secure", virt_get_secure, | |
1020 | virt_set_secure, NULL); | |
1021 | object_property_set_description(obj, "secure", | |
1022 | "Set on/off to enable/disable the ARM " | |
1023 | "Security Extensions (TrustZone)", | |
1024 | NULL); | |
5125f9cd PF |
1025 | |
1026 | /* High memory is enabled by default */ | |
1027 | vms->highmem = true; | |
1028 | object_property_add_bool(obj, "highmem", virt_get_highmem, | |
1029 | virt_set_highmem, NULL); | |
1030 | object_property_set_description(obj, "highmem", | |
1031 | "Set on/off to enable/disable using " | |
1032 | "physical address space above 32 bits", | |
1033 | NULL); | |
083a5890 GB |
1034 | } |
1035 | ||
c2919690 GB |
1036 | static void virt_class_init(ObjectClass *oc, void *data) |
1037 | { | |
1038 | MachineClass *mc = MACHINE_CLASS(oc); | |
1039 | ||
1040 | mc->name = TYPE_VIRT_MACHINE; | |
1041 | mc->desc = "ARM Virtual Machine", | |
1042 | mc->init = machvirt_init; | |
1043 | mc->max_cpus = 8; | |
5f7a5a0e | 1044 | mc->has_dynamic_sysbus = true; |
4e2c0b2a PM |
1045 | mc->block_default_type = IF_VIRTIO; |
1046 | mc->no_cdrom = 1; | |
c2919690 GB |
1047 | } |
1048 | ||
1049 | static const TypeInfo machvirt_info = { | |
1050 | .name = TYPE_VIRT_MACHINE, | |
1051 | .parent = TYPE_MACHINE, | |
1052 | .instance_size = sizeof(VirtMachineState), | |
083a5890 | 1053 | .instance_init = virt_instance_init, |
c2919690 GB |
1054 | .class_size = sizeof(VirtMachineClass), |
1055 | .class_init = virt_class_init, | |
f5fdcd6e PM |
1056 | }; |
1057 | ||
1058 | static void machvirt_machine_init(void) | |
1059 | { | |
c2919690 | 1060 | type_register_static(&machvirt_info); |
f5fdcd6e PM |
1061 | } |
1062 | ||
1063 | machine_init(machvirt_machine_init); |