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f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
12b16722 | 31 | #include "qemu/osdep.h" |
da34e65c | 32 | #include "qapi/error.h" |
f5fdcd6e PM |
33 | #include "hw/sysbus.h" |
34 | #include "hw/arm/arm.h" | |
35 | #include "hw/arm/primecell.h" | |
afe0b380 | 36 | #include "hw/arm/virt.h" |
6f2062b9 EH |
37 | #include "hw/vfio/vfio-calxeda-xgmac.h" |
38 | #include "hw/vfio/vfio-amd-xgbe.h" | |
f5fdcd6e PM |
39 | #include "hw/devices.h" |
40 | #include "net/net.h" | |
fa1d36df | 41 | #include "sysemu/block-backend.h" |
f5fdcd6e | 42 | #include "sysemu/device_tree.h" |
9695200a | 43 | #include "sysemu/numa.h" |
f5fdcd6e PM |
44 | #include "sysemu/sysemu.h" |
45 | #include "sysemu/kvm.h" | |
1287f2b3 | 46 | #include "hw/compat.h" |
acf82361 | 47 | #include "hw/loader.h" |
f5fdcd6e PM |
48 | #include "exec/address-spaces.h" |
49 | #include "qemu/bitops.h" | |
50 | #include "qemu/error-report.h" | |
4ab29b82 | 51 | #include "hw/pci-host/gpex.h" |
5f7a5a0e EA |
52 | #include "hw/arm/sysbus-fdt.h" |
53 | #include "hw/platform-bus.h" | |
decf4f80 | 54 | #include "hw/arm/fdt.h" |
95eb49c8 AJ |
55 | #include "hw/intc/arm_gic.h" |
56 | #include "hw/intc/arm_gicv3_common.h" | |
e6fbcbc4 | 57 | #include "kvm_arm.h" |
c30e1565 | 58 | #include "hw/smbios/smbios.h" |
b92ad394 | 59 | #include "qapi/visitor.h" |
3e6ebb64 | 60 | #include "standard-headers/linux/input.h" |
584105ea | 61 | #include "hw/arm/smmuv3.h" |
f5fdcd6e | 62 | |
3356ebce | 63 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ |
ab093c3c AJ |
64 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ |
65 | void *data) \ | |
66 | { \ | |
67 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
68 | virt_machine_##major##_##minor##_options(mc); \ | |
69 | mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ | |
3356ebce AJ |
70 | if (latest) { \ |
71 | mc->alias = "virt"; \ | |
72 | } \ | |
ab093c3c AJ |
73 | } \ |
74 | static const TypeInfo machvirt_##major##_##minor##_info = { \ | |
75 | .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ | |
76 | .parent = TYPE_VIRT_MACHINE, \ | |
77 | .instance_init = virt_##major##_##minor##_instance_init, \ | |
78 | .class_init = virt_##major##_##minor##_class_init, \ | |
79 | }; \ | |
80 | static void machvirt_machine_##major##_##minor##_init(void) \ | |
81 | { \ | |
82 | type_register_static(&machvirt_##major##_##minor##_info); \ | |
83 | } \ | |
84 | type_init(machvirt_machine_##major##_##minor##_init); | |
85 | ||
3356ebce AJ |
86 | #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ |
87 | DEFINE_VIRT_MACHINE_LATEST(major, minor, true) | |
88 | #define DEFINE_VIRT_MACHINE(major, minor) \ | |
89 | DEFINE_VIRT_MACHINE_LATEST(major, minor, false) | |
90 | ||
ab093c3c | 91 | |
a72d4363 AJ |
92 | /* Number of external interrupt lines to configure the GIC with */ |
93 | #define NUM_IRQS 256 | |
94 | ||
95 | #define PLATFORM_BUS_NUM_IRQS 64 | |
96 | ||
97 | static ARMPlatformBusSystemParams platform_bus_params; | |
98 | ||
71c27684 PM |
99 | /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means |
100 | * RAM can go up to the 256GB mark, leaving 256GB of the physical | |
101 | * address space unallocated and free for future use between 256G and 512G. | |
102 | * If we need to provide more RAM to VMs in the future then we need to: | |
103 | * * allocate a second bank of RAM starting at 2TB and working up | |
104 | * * fix the DT and ACPI table generation code in QEMU to correctly | |
105 | * report two split lumps of RAM to the guest | |
106 | * * fix KVM in the host kernel to allow guests with >40 bit address spaces | |
107 | * (We don't want to fill all the way up to 512GB with RAM because | |
108 | * we might want it for non-RAM purposes later. Conversely it seems | |
109 | * reasonable to assume that anybody configuring a VM with a quarter | |
110 | * of a terabyte of RAM will be doing it on a host with more than a | |
111 | * terabyte of physical address space.) | |
112 | */ | |
113 | #define RAMLIMIT_GB 255 | |
114 | #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) | |
115 | ||
f5fdcd6e PM |
116 | /* Addresses and sizes of our components. |
117 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
118 | * 128MB..256MB is used for miscellaneous device I/O. | |
119 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
120 | * PCI memory window will go if we add a PCI host controller). | |
121 | * 1GB and up is RAM (which may happily spill over into the | |
122 | * high memory region beyond 4GB). | |
123 | * This represents a compromise between how much RAM can be given to | |
124 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
125 | * Note that devices should generally be placed at multiples of 0x10000, |
126 | * to accommodate guests using 64K pages. | |
f5fdcd6e PM |
127 | */ |
128 | static const MemMapEntry a15memmap[] = { | |
129 | /* Space up to 0x8000000 is reserved for a boot ROM */ | |
94edf02c EA |
130 | [VIRT_FLASH] = { 0, 0x08000000 }, |
131 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 132 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
133 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
134 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
135 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
b92ad394 PF |
136 | /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ |
137 | [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, | |
138 | /* This redistributor space allows up to 2*64kB*123 CPUs */ | |
139 | [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, | |
94edf02c EA |
140 | [VIRT_UART] = { 0x09000000, 0x00001000 }, |
141 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
0b341a85 | 142 | [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, |
b0a3721e | 143 | [VIRT_GPIO] = { 0x09030000, 0x00001000 }, |
3df708eb | 144 | [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, |
584105ea | 145 | [VIRT_SMMU] = { 0x09050000, 0x00020000 }, |
94edf02c | 146 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, |
f5fdcd6e | 147 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c | 148 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
83ec1923 | 149 | [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, |
94edf02c EA |
150 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, |
151 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
152 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
71c27684 | 153 | [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, |
5125f9cd PF |
154 | /* Second PCIe window, 512GB wide at the 512GB boundary */ |
155 | [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, | |
f5fdcd6e PM |
156 | }; |
157 | ||
158 | static const int a15irqmap[] = { | |
159 | [VIRT_UART] = 1, | |
6e411af9 | 160 | [VIRT_RTC] = 2, |
4ab29b82 | 161 | [VIRT_PCIE] = 3, /* ... to 6 */ |
b0a3721e | 162 | [VIRT_GPIO] = 7, |
3df708eb | 163 | [VIRT_SECURE_UART] = 8, |
f5fdcd6e | 164 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 165 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
584105ea | 166 | [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ |
5f7a5a0e | 167 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
168 | }; |
169 | ||
9ac4ef77 | 170 | static const char *valid_cpus[] = { |
ba1ba5cc IM |
171 | ARM_CPU_TYPE_NAME("cortex-a15"), |
172 | ARM_CPU_TYPE_NAME("cortex-a53"), | |
173 | ARM_CPU_TYPE_NAME("cortex-a57"), | |
174 | ARM_CPU_TYPE_NAME("host"), | |
9076ddb3 | 175 | ARM_CPU_TYPE_NAME("max"), |
f5fdcd6e PM |
176 | }; |
177 | ||
ba1ba5cc | 178 | static bool cpu_type_valid(const char *cpu) |
f5fdcd6e PM |
179 | { |
180 | int i; | |
181 | ||
9ac4ef77 PM |
182 | for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { |
183 | if (strcmp(cpu, valid_cpus[i]) == 0) { | |
184 | return true; | |
f5fdcd6e PM |
185 | } |
186 | } | |
9ac4ef77 | 187 | return false; |
f5fdcd6e PM |
188 | } |
189 | ||
c8ef2bda | 190 | static void create_fdt(VirtMachineState *vms) |
f5fdcd6e | 191 | { |
c8ef2bda | 192 | void *fdt = create_device_tree(&vms->fdt_size); |
f5fdcd6e PM |
193 | |
194 | if (!fdt) { | |
195 | error_report("create_device_tree() failed"); | |
196 | exit(1); | |
197 | } | |
198 | ||
c8ef2bda | 199 | vms->fdt = fdt; |
f5fdcd6e PM |
200 | |
201 | /* Header */ | |
5a4348d1 PC |
202 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
203 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
204 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
f5fdcd6e PM |
205 | |
206 | /* | |
207 | * /chosen and /memory nodes must exist for load_dtb | |
208 | * to fill in necessary properties later | |
209 | */ | |
5a4348d1 PC |
210 | qemu_fdt_add_subnode(fdt, "/chosen"); |
211 | qemu_fdt_add_subnode(fdt, "/memory"); | |
212 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
f5fdcd6e PM |
213 | |
214 | /* Clock node, for the benefit of the UART. The kernel device tree | |
215 | * binding documentation claims the PL011 node clock properties are | |
216 | * optional but in practice if you omit them the kernel refuses to | |
217 | * probe for the device. | |
218 | */ | |
c8ef2bda | 219 | vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
5a4348d1 PC |
220 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); |
221 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
222 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
223 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
224 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 225 | "clk24mhz"); |
c8ef2bda | 226 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); |
f5fdcd6e | 227 | |
c7637c04 AJ |
228 | if (have_numa_distance) { |
229 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); | |
230 | uint32_t *matrix = g_malloc0(size); | |
231 | int idx, i, j; | |
232 | ||
233 | for (i = 0; i < nb_numa_nodes; i++) { | |
234 | for (j = 0; j < nb_numa_nodes; j++) { | |
235 | idx = (i * nb_numa_nodes + j) * 3; | |
236 | matrix[idx + 0] = cpu_to_be32(i); | |
237 | matrix[idx + 1] = cpu_to_be32(j); | |
238 | matrix[idx + 2] = cpu_to_be32(numa_info[i].distance[j]); | |
239 | } | |
240 | } | |
241 | ||
242 | qemu_fdt_add_subnode(fdt, "/distance-map"); | |
243 | qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", | |
244 | "numa-distance-map-v1"); | |
245 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | |
246 | matrix, size); | |
247 | g_free(matrix); | |
248 | } | |
06955739 PS |
249 | } |
250 | ||
055a7f2b | 251 | static void fdt_add_timer_nodes(const VirtMachineState *vms) |
f5fdcd6e | 252 | { |
156bc9a5 PM |
253 | /* On real hardware these interrupts are level-triggered. |
254 | * On KVM they were edge-triggered before host kernel version 4.4, | |
255 | * and level-triggered afterwards. | |
256 | * On emulated QEMU they are level-triggered. | |
257 | * | |
258 | * Getting the DTB info about them wrong is awkward for some | |
259 | * guest kernels: | |
260 | * pre-4.8 ignore the DT and leave the interrupt configured | |
261 | * with whatever the GIC reset value (or the bootloader) left it at | |
262 | * 4.8 before rc6 honour the incorrect data by programming it back | |
263 | * into the GIC, causing problems | |
264 | * 4.8rc6 and later ignore the DT and always write "level triggered" | |
265 | * into the GIC | |
266 | * | |
267 | * For backwards-compatibility, virt-2.8 and earlier will continue | |
268 | * to say these are edge-triggered, but later machines will report | |
269 | * the correct information. | |
f5fdcd6e | 270 | */ |
b32a9509 | 271 | ARMCPU *armcpu; |
156bc9a5 PM |
272 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
273 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
274 | ||
275 | if (vmc->claim_edge_triggered_timers) { | |
276 | irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; | |
277 | } | |
f5fdcd6e | 278 | |
055a7f2b | 279 | if (vms->gic_version == 2) { |
b92ad394 PF |
280 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
281 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
c8ef2bda | 282 | (1 << vms->smp_cpus) - 1); |
b92ad394 | 283 | } |
f5fdcd6e | 284 | |
c8ef2bda | 285 | qemu_fdt_add_subnode(vms->fdt, "/timer"); |
b32a9509 CF |
286 | |
287 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
288 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
289 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
c8ef2bda | 290 | qemu_fdt_setprop(vms->fdt, "/timer", "compatible", |
b32a9509 CF |
291 | compat, sizeof(compat)); |
292 | } else { | |
c8ef2bda | 293 | qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", |
b32a9509 CF |
294 | "arm,armv7-timer"); |
295 | } | |
c8ef2bda PM |
296 | qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); |
297 | qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", | |
ee246400 SZ |
298 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
299 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
300 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
301 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
302 | } |
303 | ||
c8ef2bda | 304 | static void fdt_add_cpu_nodes(const VirtMachineState *vms) |
f5fdcd6e PM |
305 | { |
306 | int cpu; | |
8d45c54d | 307 | int addr_cells = 1; |
4ccf5826 | 308 | const MachineState *ms = MACHINE(vms); |
8d45c54d PF |
309 | |
310 | /* | |
311 | * From Documentation/devicetree/bindings/arm/cpus.txt | |
312 | * On ARM v8 64-bit systems value should be set to 2, | |
313 | * that corresponds to the MPIDR_EL1 register size. | |
314 | * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
315 | * in the system, #address-cells can be set to 1, since | |
316 | * MPIDR_EL1[63:32] bits are not used for CPUs | |
317 | * identification. | |
318 | * | |
319 | * Here we actually don't know whether our system is 32- or 64-bit one. | |
320 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | |
321 | * at least one of them has Aff3 populated, we set #address-cells to 2. | |
322 | */ | |
c8ef2bda | 323 | for (cpu = 0; cpu < vms->smp_cpus; cpu++) { |
8d45c54d PF |
324 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); |
325 | ||
326 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | |
327 | addr_cells = 2; | |
328 | break; | |
329 | } | |
330 | } | |
f5fdcd6e | 331 | |
c8ef2bda PM |
332 | qemu_fdt_add_subnode(vms->fdt, "/cpus"); |
333 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); | |
334 | qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); | |
f5fdcd6e | 335 | |
c8ef2bda | 336 | for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) { |
f5fdcd6e PM |
337 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
338 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
4ccf5826 | 339 | CPUState *cs = CPU(armcpu); |
f5fdcd6e | 340 | |
c8ef2bda PM |
341 | qemu_fdt_add_subnode(vms->fdt, nodename); |
342 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); | |
343 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", | |
f5fdcd6e PM |
344 | armcpu->dtb_compatible); |
345 | ||
2013c566 PM |
346 | if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED |
347 | && vms->smp_cpus > 1) { | |
c8ef2bda | 348 | qemu_fdt_setprop_string(vms->fdt, nodename, |
f5fdcd6e PM |
349 | "enable-method", "psci"); |
350 | } | |
351 | ||
8d45c54d | 352 | if (addr_cells == 2) { |
c8ef2bda | 353 | qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", |
8d45c54d PF |
354 | armcpu->mp_affinity); |
355 | } else { | |
c8ef2bda | 356 | qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", |
8d45c54d PF |
357 | armcpu->mp_affinity); |
358 | } | |
359 | ||
4ccf5826 IM |
360 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { |
361 | qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", | |
362 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); | |
9695200a SZ |
363 | } |
364 | ||
f5fdcd6e PM |
365 | g_free(nodename); |
366 | } | |
367 | } | |
368 | ||
c8ef2bda | 369 | static void fdt_add_its_gic_node(VirtMachineState *vms) |
02f98731 | 370 | { |
c8ef2bda PM |
371 | vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
372 | qemu_fdt_add_subnode(vms->fdt, "/intc/its"); | |
373 | qemu_fdt_setprop_string(vms->fdt, "/intc/its", "compatible", | |
02f98731 | 374 | "arm,gic-v3-its"); |
c8ef2bda PM |
375 | qemu_fdt_setprop(vms->fdt, "/intc/its", "msi-controller", NULL, 0); |
376 | qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/its", "reg", | |
377 | 2, vms->memmap[VIRT_GIC_ITS].base, | |
378 | 2, vms->memmap[VIRT_GIC_ITS].size); | |
379 | qemu_fdt_setprop_cell(vms->fdt, "/intc/its", "phandle", vms->msi_phandle); | |
02f98731 PF |
380 | } |
381 | ||
c8ef2bda | 382 | static void fdt_add_v2m_gic_node(VirtMachineState *vms) |
f5fdcd6e | 383 | { |
c8ef2bda PM |
384 | vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
385 | qemu_fdt_add_subnode(vms->fdt, "/intc/v2m"); | |
386 | qemu_fdt_setprop_string(vms->fdt, "/intc/v2m", "compatible", | |
bd204e63 | 387 | "arm,gic-v2m-frame"); |
c8ef2bda PM |
388 | qemu_fdt_setprop(vms->fdt, "/intc/v2m", "msi-controller", NULL, 0); |
389 | qemu_fdt_setprop_sized_cells(vms->fdt, "/intc/v2m", "reg", | |
390 | 2, vms->memmap[VIRT_GIC_V2M].base, | |
391 | 2, vms->memmap[VIRT_GIC_V2M].size); | |
392 | qemu_fdt_setprop_cell(vms->fdt, "/intc/v2m", "phandle", vms->msi_phandle); | |
bd204e63 | 393 | } |
f5fdcd6e | 394 | |
055a7f2b | 395 | static void fdt_add_gic_node(VirtMachineState *vms) |
bd204e63 | 396 | { |
c8ef2bda PM |
397 | vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt); |
398 | qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle); | |
399 | ||
400 | qemu_fdt_add_subnode(vms->fdt, "/intc"); | |
401 | qemu_fdt_setprop_cell(vms->fdt, "/intc", "#interrupt-cells", 3); | |
402 | qemu_fdt_setprop(vms->fdt, "/intc", "interrupt-controller", NULL, 0); | |
403 | qemu_fdt_setprop_cell(vms->fdt, "/intc", "#address-cells", 0x2); | |
404 | qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2); | |
405 | qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0); | |
055a7f2b | 406 | if (vms->gic_version == 3) { |
c8ef2bda | 407 | qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", |
b92ad394 | 408 | "arm,gic-v3"); |
c8ef2bda PM |
409 | qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", |
410 | 2, vms->memmap[VIRT_GIC_DIST].base, | |
411 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
412 | 2, vms->memmap[VIRT_GIC_REDIST].base, | |
413 | 2, vms->memmap[VIRT_GIC_REDIST].size); | |
f29cacfb PM |
414 | if (vms->virt) { |
415 | qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts", | |
416 | GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ, | |
417 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
418 | } | |
b92ad394 PF |
419 | } else { |
420 | /* 'cortex-a15-gic' means 'GIC v2' */ | |
c8ef2bda | 421 | qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible", |
b92ad394 | 422 | "arm,cortex-a15-gic"); |
c8ef2bda PM |
423 | qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg", |
424 | 2, vms->memmap[VIRT_GIC_DIST].base, | |
425 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
426 | 2, vms->memmap[VIRT_GIC_CPU].base, | |
427 | 2, vms->memmap[VIRT_GIC_CPU].size); | |
b92ad394 PF |
428 | } |
429 | ||
c8ef2bda | 430 | qemu_fdt_setprop_cell(vms->fdt, "/intc", "phandle", vms->gic_phandle); |
f5fdcd6e PM |
431 | } |
432 | ||
055a7f2b | 433 | static void fdt_add_pmu_nodes(const VirtMachineState *vms) |
01fe6b60 SZ |
434 | { |
435 | CPUState *cpu; | |
436 | ARMCPU *armcpu; | |
437 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
438 | ||
439 | CPU_FOREACH(cpu) { | |
440 | armcpu = ARM_CPU(cpu); | |
3f07cb2a | 441 | if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { |
01fe6b60 SZ |
442 | return; |
443 | } | |
3f07cb2a | 444 | if (kvm_enabled()) { |
b2bfe9f7 AJ |
445 | if (kvm_irqchip_in_kernel()) { |
446 | kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); | |
3f07cb2a | 447 | } |
b2bfe9f7 | 448 | kvm_arm_pmu_init(cpu); |
3f07cb2a | 449 | } |
01fe6b60 SZ |
450 | } |
451 | ||
055a7f2b | 452 | if (vms->gic_version == 2) { |
01fe6b60 SZ |
453 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
454 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
c8ef2bda | 455 | (1 << vms->smp_cpus) - 1); |
01fe6b60 SZ |
456 | } |
457 | ||
458 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
c8ef2bda | 459 | qemu_fdt_add_subnode(vms->fdt, "/pmu"); |
01fe6b60 SZ |
460 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { |
461 | const char compat[] = "arm,armv8-pmuv3"; | |
c8ef2bda | 462 | qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", |
01fe6b60 | 463 | compat, sizeof(compat)); |
c8ef2bda | 464 | qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", |
01fe6b60 SZ |
465 | GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); |
466 | } | |
467 | } | |
468 | ||
c8ef2bda | 469 | static void create_its(VirtMachineState *vms, DeviceState *gicdev) |
02f98731 PF |
470 | { |
471 | const char *itsclass = its_class_name(); | |
472 | DeviceState *dev; | |
473 | ||
474 | if (!itsclass) { | |
475 | /* Do nothing if not supported */ | |
476 | return; | |
477 | } | |
478 | ||
479 | dev = qdev_create(NULL, itsclass); | |
480 | ||
481 | object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", | |
482 | &error_abort); | |
483 | qdev_init_nofail(dev); | |
c8ef2bda | 484 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); |
02f98731 | 485 | |
c8ef2bda | 486 | fdt_add_its_gic_node(vms); |
02f98731 PF |
487 | } |
488 | ||
c8ef2bda | 489 | static void create_v2m(VirtMachineState *vms, qemu_irq *pic) |
bd204e63 CD |
490 | { |
491 | int i; | |
c8ef2bda | 492 | int irq = vms->irqmap[VIRT_GIC_V2M]; |
bd204e63 CD |
493 | DeviceState *dev; |
494 | ||
495 | dev = qdev_create(NULL, "arm-gicv2m"); | |
c8ef2bda | 496 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); |
bd204e63 CD |
497 | qdev_prop_set_uint32(dev, "base-spi", irq); |
498 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
499 | qdev_init_nofail(dev); | |
500 | ||
501 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
502 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
503 | } | |
504 | ||
c8ef2bda | 505 | fdt_add_v2m_gic_node(vms); |
bd204e63 CD |
506 | } |
507 | ||
055a7f2b | 508 | static void create_gic(VirtMachineState *vms, qemu_irq *pic) |
64204743 | 509 | { |
b92ad394 | 510 | /* We create a standalone GIC */ |
64204743 PM |
511 | DeviceState *gicdev; |
512 | SysBusDevice *gicbusdev; | |
e6fbcbc4 | 513 | const char *gictype; |
055a7f2b | 514 | int type = vms->gic_version, i; |
64204743 | 515 | |
b92ad394 | 516 | gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); |
64204743 PM |
517 | |
518 | gicdev = qdev_create(NULL, gictype); | |
b92ad394 | 519 | qdev_prop_set_uint32(gicdev, "revision", type); |
64204743 PM |
520 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); |
521 | /* Note that the num-irq property counts both internal and external | |
522 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
523 | */ | |
524 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
0e21f183 | 525 | if (!kvm_irqchip_in_kernel()) { |
0127937b | 526 | qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure); |
0e21f183 | 527 | } |
64204743 PM |
528 | qdev_init_nofail(gicdev); |
529 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
c8ef2bda | 530 | sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); |
b92ad394 | 531 | if (type == 3) { |
c8ef2bda | 532 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); |
b92ad394 | 533 | } else { |
c8ef2bda | 534 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); |
b92ad394 | 535 | } |
64204743 | 536 | |
5454006a PM |
537 | /* Wire the outputs from each CPU's generic timer and the GICv3 |
538 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | |
539 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | |
64204743 PM |
540 | */ |
541 | for (i = 0; i < smp_cpus; i++) { | |
542 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 543 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
544 | int irq; |
545 | /* Mapping from the output timer irq lines from the CPU to the | |
546 | * GIC PPI inputs we use for the virt board. | |
64204743 | 547 | */ |
a007b1f8 PM |
548 | const int timer_irq[] = { |
549 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
550 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
551 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
552 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
553 | }; | |
554 | ||
555 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
556 | qdev_connect_gpio_out(cpudev, irq, | |
557 | qdev_get_gpio_in(gicdev, | |
558 | ppibase + timer_irq[irq])); | |
559 | } | |
64204743 | 560 | |
5454006a PM |
561 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, |
562 | qdev_get_gpio_in(gicdev, ppibase | |
563 | + ARCH_GICV3_MAINT_IRQ)); | |
07f48730 AJ |
564 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, |
565 | qdev_get_gpio_in(gicdev, ppibase | |
566 | + VIRTUAL_PMU_IRQ)); | |
5454006a | 567 | |
64204743 | 568 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
8e7b4ca0 GB |
569 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
570 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
5454006a PM |
571 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, |
572 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
573 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | |
574 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
64204743 PM |
575 | } |
576 | ||
577 | for (i = 0; i < NUM_IRQS; i++) { | |
578 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
579 | } | |
580 | ||
055a7f2b | 581 | fdt_add_gic_node(vms); |
bd204e63 | 582 | |
ccc11b02 | 583 | if (type == 3 && vms->its) { |
c8ef2bda | 584 | create_its(vms, gicdev); |
2231f69b | 585 | } else if (type == 2) { |
c8ef2bda | 586 | create_v2m(vms, pic); |
b92ad394 | 587 | } |
64204743 PM |
588 | } |
589 | ||
c8ef2bda | 590 | static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, |
0ec7b3e7 | 591 | MemoryRegion *mem, Chardev *chr) |
f5fdcd6e PM |
592 | { |
593 | char *nodename; | |
c8ef2bda PM |
594 | hwaddr base = vms->memmap[uart].base; |
595 | hwaddr size = vms->memmap[uart].size; | |
596 | int irq = vms->irqmap[uart]; | |
f5fdcd6e PM |
597 | const char compat[] = "arm,pl011\0arm,primecell"; |
598 | const char clocknames[] = "uartclk\0apb_pclk"; | |
3df708eb PM |
599 | DeviceState *dev = qdev_create(NULL, "pl011"); |
600 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
f5fdcd6e | 601 | |
9bbbf649 | 602 | qdev_prop_set_chr(dev, "chardev", chr); |
3df708eb PM |
603 | qdev_init_nofail(dev); |
604 | memory_region_add_subregion(mem, base, | |
605 | sysbus_mmio_get_region(s, 0)); | |
606 | sysbus_connect_irq(s, 0, pic[irq]); | |
f5fdcd6e PM |
607 | |
608 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
c8ef2bda | 609 | qemu_fdt_add_subnode(vms->fdt, nodename); |
f5fdcd6e | 610 | /* Note that we can't use setprop_string because of the embedded NUL */ |
c8ef2bda | 611 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", |
f5fdcd6e | 612 | compat, sizeof(compat)); |
c8ef2bda | 613 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
f5fdcd6e | 614 | 2, base, 2, size); |
c8ef2bda | 615 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
f5fdcd6e | 616 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 617 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
c8ef2bda PM |
618 | qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", |
619 | vms->clock_phandle, vms->clock_phandle); | |
620 | qemu_fdt_setprop(vms->fdt, nodename, "clock-names", | |
f5fdcd6e | 621 | clocknames, sizeof(clocknames)); |
f022b8e9 | 622 | |
3df708eb | 623 | if (uart == VIRT_UART) { |
c8ef2bda | 624 | qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename); |
3df708eb PM |
625 | } else { |
626 | /* Mark as not usable by the normal world */ | |
c8ef2bda PM |
627 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); |
628 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
3df708eb PM |
629 | } |
630 | ||
f5fdcd6e PM |
631 | g_free(nodename); |
632 | } | |
633 | ||
c8ef2bda | 634 | static void create_rtc(const VirtMachineState *vms, qemu_irq *pic) |
6e411af9 PM |
635 | { |
636 | char *nodename; | |
c8ef2bda PM |
637 | hwaddr base = vms->memmap[VIRT_RTC].base; |
638 | hwaddr size = vms->memmap[VIRT_RTC].size; | |
639 | int irq = vms->irqmap[VIRT_RTC]; | |
6e411af9 PM |
640 | const char compat[] = "arm,pl031\0arm,primecell"; |
641 | ||
642 | sysbus_create_simple("pl031", base, pic[irq]); | |
643 | ||
644 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
c8ef2bda PM |
645 | qemu_fdt_add_subnode(vms->fdt, nodename); |
646 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); | |
647 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
6e411af9 | 648 | 2, base, 2, size); |
c8ef2bda | 649 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
6e411af9 | 650 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 651 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
c8ef2bda PM |
652 | qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); |
653 | qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); | |
6e411af9 PM |
654 | g_free(nodename); |
655 | } | |
656 | ||
94f02c5e | 657 | static DeviceState *gpio_key_dev; |
4bedd849 SZ |
658 | static void virt_powerdown_req(Notifier *n, void *opaque) |
659 | { | |
660 | /* use gpio Pin 3 for power button event */ | |
94f02c5e | 661 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
4bedd849 SZ |
662 | } |
663 | ||
664 | static Notifier virt_system_powerdown_notifier = { | |
665 | .notify = virt_powerdown_req | |
666 | }; | |
667 | ||
c8ef2bda | 668 | static void create_gpio(const VirtMachineState *vms, qemu_irq *pic) |
b0a3721e SZ |
669 | { |
670 | char *nodename; | |
94f02c5e | 671 | DeviceState *pl061_dev; |
c8ef2bda PM |
672 | hwaddr base = vms->memmap[VIRT_GPIO].base; |
673 | hwaddr size = vms->memmap[VIRT_GPIO].size; | |
674 | int irq = vms->irqmap[VIRT_GPIO]; | |
b0a3721e SZ |
675 | const char compat[] = "arm,pl061\0arm,primecell"; |
676 | ||
4bedd849 | 677 | pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); |
b0a3721e | 678 | |
c8ef2bda | 679 | uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt); |
b0a3721e | 680 | nodename = g_strdup_printf("/pl061@%" PRIx64, base); |
c8ef2bda PM |
681 | qemu_fdt_add_subnode(vms->fdt, nodename); |
682 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
b0a3721e | 683 | 2, base, 2, size); |
c8ef2bda PM |
684 | qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat)); |
685 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); | |
686 | qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); | |
687 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", | |
b0a3721e SZ |
688 | GIC_FDT_IRQ_TYPE_SPI, irq, |
689 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
c8ef2bda PM |
690 | qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle); |
691 | qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); | |
692 | qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); | |
3e6ebb64 | 693 | |
94f02c5e SZ |
694 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
695 | qdev_get_gpio_in(pl061_dev, 3)); | |
c8ef2bda PM |
696 | qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); |
697 | qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys"); | |
698 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); | |
699 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); | |
3e6ebb64 | 700 | |
c8ef2bda PM |
701 | qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); |
702 | qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", | |
3e6ebb64 | 703 | "label", "GPIO Key Poweroff"); |
c8ef2bda | 704 | qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", |
3e6ebb64 | 705 | KEY_POWER); |
c8ef2bda | 706 | qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", |
3e6ebb64 | 707 | "gpios", phandle, 3, 0); |
b0a3721e | 708 | |
4bedd849 SZ |
709 | /* connect powerdown request */ |
710 | qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); | |
711 | ||
b0a3721e SZ |
712 | g_free(nodename); |
713 | } | |
714 | ||
c8ef2bda | 715 | static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic) |
f5fdcd6e PM |
716 | { |
717 | int i; | |
c8ef2bda | 718 | hwaddr size = vms->memmap[VIRT_MMIO].size; |
f5fdcd6e | 719 | |
587078f0 LE |
720 | /* We create the transports in forwards order. Since qbus_realize() |
721 | * prepends (not appends) new child buses, the incrementing loop below will | |
722 | * create a list of virtio-mmio buses with decreasing base addresses. | |
723 | * | |
724 | * When a -device option is processed from the command line, | |
725 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
726 | * order. The upshot is that -device options in increasing command line | |
727 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
728 | * | |
729 | * When this code was originally written, that arrangement ensured that the | |
730 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
731 | * the first -device on the command line. (The end-to-end order is a | |
732 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
733 | * guest kernel's name-to-address assignment strategy.) | |
734 | * | |
735 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
736 | * the message, if not necessarily the code, of commit 70161ff336. | |
737 | * Therefore the loop now establishes the inverse of the original intent. | |
738 | * | |
739 | * Unfortunately, we can't counteract the kernel change by reversing the | |
740 | * loop; it would break existing command lines. | |
741 | * | |
742 | * In any case, the kernel makes no guarantee about the stability of | |
743 | * enumeration order of virtio devices (as demonstrated by it changing | |
744 | * between kernel versions). For reliable and stable identification | |
745 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
746 | */ |
747 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
c8ef2bda PM |
748 | int irq = vms->irqmap[VIRT_MMIO] + i; |
749 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e PM |
750 | |
751 | sysbus_create_simple("virtio-mmio", base, pic[irq]); | |
752 | } | |
753 | ||
587078f0 LE |
754 | /* We add dtb nodes in reverse order so that they appear in the finished |
755 | * device tree lowest address first. | |
756 | * | |
757 | * Note that this mapping is independent of the loop above. The previous | |
758 | * loop influences virtio device to virtio transport assignment, whereas | |
759 | * this loop controls how virtio transports are laid out in the dtb. | |
760 | */ | |
f5fdcd6e PM |
761 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
762 | char *nodename; | |
c8ef2bda PM |
763 | int irq = vms->irqmap[VIRT_MMIO] + i; |
764 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e PM |
765 | |
766 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
c8ef2bda PM |
767 | qemu_fdt_add_subnode(vms->fdt, nodename); |
768 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
5a4348d1 | 769 | "compatible", "virtio,mmio"); |
c8ef2bda | 770 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
5a4348d1 | 771 | 2, base, 2, size); |
c8ef2bda | 772 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", |
5a4348d1 PC |
773 | GIC_FDT_IRQ_TYPE_SPI, irq, |
774 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
054bb7b2 | 775 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
f5fdcd6e PM |
776 | g_free(nodename); |
777 | } | |
778 | } | |
779 | ||
acf82361 | 780 | static void create_one_flash(const char *name, hwaddr flashbase, |
738a5d9f PM |
781 | hwaddr flashsize, const char *file, |
782 | MemoryRegion *sysmem) | |
acf82361 PM |
783 | { |
784 | /* Create and map a single flash device. We use the same | |
785 | * parameters as the flash devices on the Versatile Express board. | |
786 | */ | |
787 | DriveInfo *dinfo = drive_get_next(IF_PFLASH); | |
788 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
16f4a8dc | 789 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
acf82361 PM |
790 | const uint64_t sectorlength = 256 * 1024; |
791 | ||
9b3d111a MA |
792 | if (dinfo) { |
793 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
794 | &error_abort); | |
acf82361 PM |
795 | } |
796 | ||
797 | qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); | |
798 | qdev_prop_set_uint64(dev, "sector-length", sectorlength); | |
799 | qdev_prop_set_uint8(dev, "width", 4); | |
800 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 801 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
802 | qdev_prop_set_uint16(dev, "id0", 0x89); |
803 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
804 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
805 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
806 | qdev_prop_set_string(dev, "name", name); | |
807 | qdev_init_nofail(dev); | |
808 | ||
738a5d9f PM |
809 | memory_region_add_subregion(sysmem, flashbase, |
810 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); | |
acf82361 | 811 | |
16f4a8dc | 812 | if (file) { |
6e05a12f | 813 | char *fn; |
4de9a883 | 814 | int image_size; |
acf82361 PM |
815 | |
816 | if (drive_get(IF_PFLASH, 0, 0)) { | |
817 | error_report("The contents of the first flash device may be " | |
818 | "specified with -bios or with -drive if=pflash... " | |
819 | "but you cannot use both options at once"); | |
820 | exit(1); | |
821 | } | |
16f4a8dc | 822 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); |
4de9a883 | 823 | if (!fn) { |
16f4a8dc | 824 | error_report("Could not find ROM image '%s'", file); |
4de9a883 SW |
825 | exit(1); |
826 | } | |
16f4a8dc | 827 | image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); |
4de9a883 SW |
828 | g_free(fn); |
829 | if (image_size < 0) { | |
16f4a8dc | 830 | error_report("Could not load ROM image '%s'", file); |
acf82361 PM |
831 | exit(1); |
832 | } | |
833 | } | |
16f4a8dc PM |
834 | } |
835 | ||
c8ef2bda | 836 | static void create_flash(const VirtMachineState *vms, |
738a5d9f PM |
837 | MemoryRegion *sysmem, |
838 | MemoryRegion *secure_sysmem) | |
16f4a8dc PM |
839 | { |
840 | /* Create two flash devices to fill the VIRT_FLASH space in the memmap. | |
841 | * Any file passed via -bios goes in the first of these. | |
738a5d9f PM |
842 | * sysmem is the system memory space. secure_sysmem is the secure view |
843 | * of the system, and the first flash device should be made visible only | |
844 | * there. The second flash device is visible to both secure and nonsecure. | |
845 | * If sysmem == secure_sysmem this means there is no separate Secure | |
846 | * address space and both flash devices are generally visible. | |
16f4a8dc | 847 | */ |
c8ef2bda PM |
848 | hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; |
849 | hwaddr flashbase = vms->memmap[VIRT_FLASH].base; | |
16f4a8dc | 850 | char *nodename; |
acf82361 | 851 | |
738a5d9f PM |
852 | create_one_flash("virt.flash0", flashbase, flashsize, |
853 | bios_name, secure_sysmem); | |
854 | create_one_flash("virt.flash1", flashbase + flashsize, flashsize, | |
855 | NULL, sysmem); | |
acf82361 | 856 | |
738a5d9f PM |
857 | if (sysmem == secure_sysmem) { |
858 | /* Report both flash devices as a single node in the DT */ | |
859 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
c8ef2bda PM |
860 | qemu_fdt_add_subnode(vms->fdt, nodename); |
861 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
862 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f PM |
863 | 2, flashbase, 2, flashsize, |
864 | 2, flashbase + flashsize, 2, flashsize); | |
c8ef2bda | 865 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
866 | g_free(nodename); |
867 | } else { | |
868 | /* Report the devices as separate nodes so we can mark one as | |
869 | * only visible to the secure world. | |
870 | */ | |
871 | nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); | |
c8ef2bda PM |
872 | qemu_fdt_add_subnode(vms->fdt, nodename); |
873 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
874 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f | 875 | 2, flashbase, 2, flashsize); |
c8ef2bda PM |
876 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
877 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | |
878 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
738a5d9f PM |
879 | g_free(nodename); |
880 | ||
881 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
c8ef2bda PM |
882 | qemu_fdt_add_subnode(vms->fdt, nodename); |
883 | qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash"); | |
884 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | |
738a5d9f | 885 | 2, flashbase + flashsize, 2, flashsize); |
c8ef2bda | 886 | qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
887 | g_free(nodename); |
888 | } | |
acf82361 PM |
889 | } |
890 | ||
af1f60a4 | 891 | static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) |
578f3c7b | 892 | { |
c8ef2bda PM |
893 | hwaddr base = vms->memmap[VIRT_FW_CFG].base; |
894 | hwaddr size = vms->memmap[VIRT_FW_CFG].size; | |
5836d168 | 895 | FWCfgState *fw_cfg; |
578f3c7b LE |
896 | char *nodename; |
897 | ||
5836d168 IM |
898 | fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); |
899 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); | |
578f3c7b LE |
900 | |
901 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
c8ef2bda PM |
902 | qemu_fdt_add_subnode(vms->fdt, nodename); |
903 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
578f3c7b | 904 | "compatible", "qemu,fw-cfg-mmio"); |
c8ef2bda | 905 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
578f3c7b | 906 | 2, base, 2, size); |
14efdb5c | 907 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
578f3c7b | 908 | g_free(nodename); |
af1f60a4 | 909 | return fw_cfg; |
578f3c7b LE |
910 | } |
911 | ||
c8ef2bda | 912 | static void create_pcie_irq_map(const VirtMachineState *vms, |
9ac4ef77 | 913 | uint32_t gic_phandle, |
4ab29b82 AG |
914 | int first_irq, const char *nodename) |
915 | { | |
916 | int devfn, pin; | |
dfd90a87 | 917 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
918 | uint32_t *irq_map = full_irq_map; |
919 | ||
920 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
921 | for (pin = 0; pin < 4; pin++) { | |
922 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
923 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
924 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
925 | int i; | |
926 | ||
927 | uint32_t map[] = { | |
928 | devfn << 8, 0, 0, /* devfn */ | |
929 | pin + 1, /* PCI pin */ | |
dfd90a87 | 930 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
931 | |
932 | /* Convert map to big endian */ | |
dfd90a87 | 933 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
934 | irq_map[i] = cpu_to_be32(map[i]); |
935 | } | |
dfd90a87 | 936 | irq_map += 10; |
4ab29b82 AG |
937 | } |
938 | } | |
939 | ||
c8ef2bda | 940 | qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", |
4ab29b82 AG |
941 | full_irq_map, sizeof(full_irq_map)); |
942 | ||
c8ef2bda | 943 | qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", |
4ab29b82 AG |
944 | 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ |
945 | 0x7 /* PCI irq */); | |
946 | } | |
947 | ||
584105ea PM |
948 | static void create_smmu(const VirtMachineState *vms, qemu_irq *pic, |
949 | PCIBus *bus) | |
950 | { | |
951 | char *node; | |
952 | const char compat[] = "arm,smmu-v3"; | |
953 | int irq = vms->irqmap[VIRT_SMMU]; | |
954 | int i; | |
955 | hwaddr base = vms->memmap[VIRT_SMMU].base; | |
956 | hwaddr size = vms->memmap[VIRT_SMMU].size; | |
957 | const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; | |
958 | DeviceState *dev; | |
959 | ||
960 | if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { | |
961 | return; | |
962 | } | |
963 | ||
964 | dev = qdev_create(NULL, "arm-smmuv3"); | |
965 | ||
966 | object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus", | |
967 | &error_abort); | |
968 | qdev_init_nofail(dev); | |
969 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); | |
970 | for (i = 0; i < NUM_SMMU_IRQS; i++) { | |
971 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
972 | } | |
973 | ||
974 | node = g_strdup_printf("/smmuv3@%" PRIx64, base); | |
975 | qemu_fdt_add_subnode(vms->fdt, node); | |
976 | qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); | |
977 | qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); | |
978 | ||
979 | qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", | |
980 | GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
981 | GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
982 | GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
983 | GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
984 | ||
985 | qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, | |
986 | sizeof(irq_names)); | |
987 | ||
988 | qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); | |
989 | qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); | |
990 | qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); | |
991 | ||
992 | qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); | |
993 | ||
994 | qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); | |
995 | g_free(node); | |
996 | } | |
997 | ||
998 | static void create_pcie(VirtMachineState *vms, qemu_irq *pic) | |
4ab29b82 | 999 | { |
c8ef2bda PM |
1000 | hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; |
1001 | hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; | |
1002 | hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; | |
1003 | hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; | |
1004 | hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; | |
1005 | hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; | |
1006 | hwaddr base_ecam = vms->memmap[VIRT_PCIE_ECAM].base; | |
1007 | hwaddr size_ecam = vms->memmap[VIRT_PCIE_ECAM].size; | |
6a1f001b SZ |
1008 | hwaddr base = base_mmio; |
1009 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
c8ef2bda | 1010 | int irq = vms->irqmap[VIRT_PCIE]; |
4ab29b82 AG |
1011 | MemoryRegion *mmio_alias; |
1012 | MemoryRegion *mmio_reg; | |
1013 | MemoryRegion *ecam_alias; | |
1014 | MemoryRegion *ecam_reg; | |
1015 | DeviceState *dev; | |
1016 | char *nodename; | |
1017 | int i; | |
fea9b3ca | 1018 | PCIHostState *pci; |
4ab29b82 | 1019 | |
4ab29b82 AG |
1020 | dev = qdev_create(NULL, TYPE_GPEX_HOST); |
1021 | qdev_init_nofail(dev); | |
1022 | ||
1023 | /* Map only the first size_ecam bytes of ECAM space */ | |
1024 | ecam_alias = g_new0(MemoryRegion, 1); | |
1025 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
1026 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
1027 | ecam_reg, 0, size_ecam); | |
1028 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
1029 | ||
1030 | /* Map the MMIO window into system address space so as to expose | |
1031 | * the section of PCI MMIO space which starts at the same base address | |
1032 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
1033 | * the window). | |
1034 | */ | |
1035 | mmio_alias = g_new0(MemoryRegion, 1); | |
1036 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
1037 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
1038 | mmio_reg, base_mmio, size_mmio); | |
1039 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
1040 | ||
0127937b | 1041 | if (vms->highmem) { |
5125f9cd PF |
1042 | /* Map high MMIO space */ |
1043 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
1044 | ||
1045 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
1046 | mmio_reg, base_mmio_high, size_mmio_high); | |
1047 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
1048 | high_mmio_alias); | |
1049 | } | |
1050 | ||
4ab29b82 | 1051 | /* Map IO port space */ |
6a1f001b | 1052 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
1053 | |
1054 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
1055 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
c9bb8e16 | 1056 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
4ab29b82 AG |
1057 | } |
1058 | ||
fea9b3ca AK |
1059 | pci = PCI_HOST_BRIDGE(dev); |
1060 | if (pci->bus) { | |
1061 | for (i = 0; i < nb_nics; i++) { | |
1062 | NICInfo *nd = &nd_table[i]; | |
1063 | ||
1064 | if (!nd->model) { | |
1065 | nd->model = g_strdup("virtio"); | |
1066 | } | |
1067 | ||
1068 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
1069 | } | |
1070 | } | |
1071 | ||
4ab29b82 | 1072 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
c8ef2bda PM |
1073 | qemu_fdt_add_subnode(vms->fdt, nodename); |
1074 | qemu_fdt_setprop_string(vms->fdt, nodename, | |
4ab29b82 | 1075 | "compatible", "pci-host-ecam-generic"); |
c8ef2bda PM |
1076 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); |
1077 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); | |
1078 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); | |
6d9c1b8d | 1079 | qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); |
c8ef2bda | 1080 | qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, |
4ab29b82 | 1081 | nr_pcie_buses - 1); |
c8ef2bda | 1082 | qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); |
4ab29b82 | 1083 | |
c8ef2bda PM |
1084 | if (vms->msi_phandle) { |
1085 | qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", | |
1086 | vms->msi_phandle); | |
b92ad394 | 1087 | } |
bd204e63 | 1088 | |
c8ef2bda | 1089 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", |
4ab29b82 | 1090 | 2, base_ecam, 2, size_ecam); |
5125f9cd | 1091 | |
0127937b | 1092 | if (vms->highmem) { |
c8ef2bda | 1093 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", |
5125f9cd PF |
1094 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1095 | 2, base_pio, 2, size_pio, | |
1096 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1097 | 2, base_mmio, 2, size_mmio, | |
1098 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
1099 | 2, base_mmio_high, | |
1100 | 2, base_mmio_high, 2, size_mmio_high); | |
1101 | } else { | |
c8ef2bda | 1102 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", |
5125f9cd PF |
1103 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1104 | 2, base_pio, 2, size_pio, | |
1105 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1106 | 2, base_mmio, 2, size_mmio); | |
1107 | } | |
4ab29b82 | 1108 | |
c8ef2bda PM |
1109 | qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); |
1110 | create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); | |
4ab29b82 | 1111 | |
584105ea PM |
1112 | if (vms->iommu) { |
1113 | vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt); | |
1114 | ||
1115 | create_smmu(vms, pic, pci->bus); | |
1116 | ||
1117 | qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", | |
1118 | 0x0, vms->iommu_phandle, 0x0, 0x10000); | |
1119 | } | |
1120 | ||
4ab29b82 AG |
1121 | g_free(nodename); |
1122 | } | |
1123 | ||
c8ef2bda | 1124 | static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic) |
5f7a5a0e EA |
1125 | { |
1126 | DeviceState *dev; | |
1127 | SysBusDevice *s; | |
1128 | int i; | |
1129 | ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); | |
1130 | MemoryRegion *sysmem = get_system_memory(); | |
1131 | ||
c8ef2bda PM |
1132 | platform_bus_params.platform_bus_base = vms->memmap[VIRT_PLATFORM_BUS].base; |
1133 | platform_bus_params.platform_bus_size = vms->memmap[VIRT_PLATFORM_BUS].size; | |
1134 | platform_bus_params.platform_bus_first_irq = vms->irqmap[VIRT_PLATFORM_BUS]; | |
5f7a5a0e EA |
1135 | platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; |
1136 | ||
1137 | fdt_params->system_params = &platform_bus_params; | |
c8ef2bda | 1138 | fdt_params->binfo = &vms->bootinfo; |
5f7a5a0e EA |
1139 | fdt_params->intc = "/intc"; |
1140 | /* | |
1141 | * register a machine init done notifier that creates the device tree | |
1142 | * nodes of the platform bus and its children dynamic sysbus devices | |
1143 | */ | |
1144 | arm_register_platform_bus_fdt_creator(fdt_params); | |
1145 | ||
1146 | dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); | |
1147 | dev->id = TYPE_PLATFORM_BUS_DEVICE; | |
1148 | qdev_prop_set_uint32(dev, "num_irqs", | |
1149 | platform_bus_params.platform_bus_num_irqs); | |
1150 | qdev_prop_set_uint32(dev, "mmio_size", | |
1151 | platform_bus_params.platform_bus_size); | |
1152 | qdev_init_nofail(dev); | |
1153 | s = SYS_BUS_DEVICE(dev); | |
1154 | ||
1155 | for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { | |
1156 | int irqn = platform_bus_params.platform_bus_first_irq + i; | |
1157 | sysbus_connect_irq(s, i, pic[irqn]); | |
1158 | } | |
1159 | ||
1160 | memory_region_add_subregion(sysmem, | |
1161 | platform_bus_params.platform_bus_base, | |
1162 | sysbus_mmio_get_region(s, 0)); | |
1163 | } | |
1164 | ||
c8ef2bda | 1165 | static void create_secure_ram(VirtMachineState *vms, |
9ac4ef77 | 1166 | MemoryRegion *secure_sysmem) |
83ec1923 PM |
1167 | { |
1168 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
1169 | char *nodename; | |
c8ef2bda PM |
1170 | hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; |
1171 | hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; | |
83ec1923 | 1172 | |
98a99ce0 PM |
1173 | memory_region_init_ram(secram, NULL, "virt.secure-ram", size, |
1174 | &error_fatal); | |
83ec1923 PM |
1175 | memory_region_add_subregion(secure_sysmem, base, secram); |
1176 | ||
1177 | nodename = g_strdup_printf("/secram@%" PRIx64, base); | |
c8ef2bda PM |
1178 | qemu_fdt_add_subnode(vms->fdt, nodename); |
1179 | qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); | |
1180 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size); | |
1181 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | |
1182 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | |
83ec1923 PM |
1183 | |
1184 | g_free(nodename); | |
1185 | } | |
1186 | ||
f5fdcd6e PM |
1187 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
1188 | { | |
9ac4ef77 PM |
1189 | const VirtMachineState *board = container_of(binfo, VirtMachineState, |
1190 | bootinfo); | |
f5fdcd6e PM |
1191 | |
1192 | *fdt_size = board->fdt_size; | |
1193 | return board->fdt; | |
1194 | } | |
1195 | ||
e9a8e474 | 1196 | static void virt_build_smbios(VirtMachineState *vms) |
c30e1565 | 1197 | { |
dfadc3bf WH |
1198 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
1199 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
c30e1565 WH |
1200 | uint8_t *smbios_tables, *smbios_anchor; |
1201 | size_t smbios_tables_len, smbios_anchor_len; | |
bab27ea2 | 1202 | const char *product = "QEMU Virtual Machine"; |
c30e1565 | 1203 | |
af1f60a4 | 1204 | if (!vms->fw_cfg) { |
c30e1565 WH |
1205 | return; |
1206 | } | |
1207 | ||
bab27ea2 AJ |
1208 | if (kvm_enabled()) { |
1209 | product = "KVM Virtual Machine"; | |
1210 | } | |
1211 | ||
1212 | smbios_set_defaults("QEMU", product, | |
dfadc3bf WH |
1213 | vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, |
1214 | true, SMBIOS_ENTRY_POINT_30); | |
c30e1565 WH |
1215 | |
1216 | smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, | |
1217 | &smbios_anchor, &smbios_anchor_len); | |
1218 | ||
1219 | if (smbios_anchor) { | |
af1f60a4 | 1220 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", |
c30e1565 | 1221 | smbios_tables, smbios_tables_len); |
af1f60a4 | 1222 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", |
c30e1565 WH |
1223 | smbios_anchor, smbios_anchor_len); |
1224 | } | |
1225 | } | |
1226 | ||
d7c2e2db | 1227 | static |
054f4dc9 | 1228 | void virt_machine_done(Notifier *notifier, void *data) |
d7c2e2db | 1229 | { |
054f4dc9 AJ |
1230 | VirtMachineState *vms = container_of(notifier, VirtMachineState, |
1231 | machine_done); | |
1232 | ||
e9a8e474 AJ |
1233 | virt_acpi_setup(vms); |
1234 | virt_build_smbios(vms); | |
d7c2e2db SZ |
1235 | } |
1236 | ||
46de5913 IM |
1237 | static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) |
1238 | { | |
1239 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | |
1240 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
1241 | ||
1242 | if (!vmc->disallow_affinity_adjustment) { | |
1243 | /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the | |
1244 | * GIC's target-list limitations. 32-bit KVM hosts currently | |
1245 | * always create clusters of 4 CPUs, but that is expected to | |
1246 | * change when they gain support for gicv3. When KVM is enabled | |
1247 | * it will override the changes we make here, therefore our | |
1248 | * purposes are to make TCG consistent (with 64-bit KVM hosts) | |
1249 | * and to improve SGI efficiency. | |
1250 | */ | |
1251 | if (vms->gic_version == 3) { | |
1252 | clustersz = GICV3_TARGETLIST_BITS; | |
1253 | } else { | |
1254 | clustersz = GIC_TARGETLIST_BITS; | |
1255 | } | |
1256 | } | |
1257 | return arm_cpu_mp_affinity(idx, clustersz); | |
1258 | } | |
1259 | ||
3ef96221 | 1260 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 1261 | { |
e5a5604f | 1262 | VirtMachineState *vms = VIRT_MACHINE(machine); |
95eb49c8 | 1263 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); |
17d3d0e2 IM |
1264 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
1265 | const CPUArchIdList *possible_cpus; | |
f5fdcd6e PM |
1266 | qemu_irq pic[NUM_IRQS]; |
1267 | MemoryRegion *sysmem = get_system_memory(); | |
3df708eb | 1268 | MemoryRegion *secure_sysmem = NULL; |
7ea686f5 | 1269 | int n, virt_max_cpus; |
f5fdcd6e | 1270 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
4824a61a | 1271 | bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); |
f5fdcd6e | 1272 | |
b92ad394 PF |
1273 | /* We can probe only here because during property set |
1274 | * KVM is not available yet | |
1275 | */ | |
dc16538a PM |
1276 | if (vms->gic_version <= 0) { |
1277 | /* "host" or "max" */ | |
0bf8039d | 1278 | if (!kvm_enabled()) { |
dc16538a PM |
1279 | if (vms->gic_version == 0) { |
1280 | error_report("gic-version=host requires KVM"); | |
1281 | exit(1); | |
1282 | } else { | |
1283 | /* "max": currently means 3 for TCG */ | |
1284 | vms->gic_version = 3; | |
1285 | } | |
1286 | } else { | |
1287 | vms->gic_version = kvm_arm_vgic_probe(); | |
1288 | if (!vms->gic_version) { | |
1289 | error_report( | |
1290 | "Unable to determine GIC version supported by host"); | |
1291 | exit(1); | |
1292 | } | |
b92ad394 PF |
1293 | } |
1294 | } | |
1295 | ||
ba1ba5cc IM |
1296 | if (!cpu_type_valid(machine->cpu_type)) { |
1297 | error_report("mach-virt: CPU type %s not supported", machine->cpu_type); | |
f5fdcd6e PM |
1298 | exit(1); |
1299 | } | |
1300 | ||
4824a61a PM |
1301 | /* If we have an EL3 boot ROM then the assumption is that it will |
1302 | * implement PSCI itself, so disable QEMU's internal implementation | |
1303 | * so it doesn't get in the way. Instead of starting secondary | |
1304 | * CPUs in PSCI powerdown state we will start them all running and | |
1305 | * let the boot ROM sort them out. | |
f29cacfb PM |
1306 | * The usual case is that we do use QEMU's PSCI implementation; |
1307 | * if the guest has EL2 then we will use SMC as the conduit, | |
1308 | * and otherwise we will use HVC (for backwards compatibility and | |
1309 | * because if we're using KVM then we must use HVC). | |
4824a61a | 1310 | */ |
2013c566 PM |
1311 | if (vms->secure && firmware_loaded) { |
1312 | vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
f29cacfb PM |
1313 | } else if (vms->virt) { |
1314 | vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; | |
2013c566 PM |
1315 | } else { |
1316 | vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; | |
1317 | } | |
4824a61a | 1318 | |
4b280b72 AJ |
1319 | /* The maximum number of CPUs depends on the GIC version, or on how |
1320 | * many redistributors we can fit into the memory map. | |
1321 | */ | |
055a7f2b | 1322 | if (vms->gic_version == 3) { |
c8ef2bda | 1323 | virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / 0x20000; |
4b280b72 | 1324 | } else { |
7ea686f5 | 1325 | virt_max_cpus = GIC_NCPU; |
4b280b72 AJ |
1326 | } |
1327 | ||
7ea686f5 | 1328 | if (max_cpus > virt_max_cpus) { |
4b280b72 AJ |
1329 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
1330 | "supported by machine 'mach-virt' (%d)", | |
7ea686f5 | 1331 | max_cpus, virt_max_cpus); |
4b280b72 AJ |
1332 | exit(1); |
1333 | } | |
1334 | ||
c8ef2bda | 1335 | vms->smp_cpus = smp_cpus; |
f5fdcd6e | 1336 | |
c8ef2bda | 1337 | if (machine->ram_size > vms->memmap[VIRT_MEM].size) { |
71c27684 | 1338 | error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); |
f5fdcd6e PM |
1339 | exit(1); |
1340 | } | |
1341 | ||
f29cacfb PM |
1342 | if (vms->virt && kvm_enabled()) { |
1343 | error_report("mach-virt: KVM does not support providing " | |
1344 | "Virtualization extensions to the guest CPU"); | |
1345 | exit(1); | |
1346 | } | |
1347 | ||
3df708eb PM |
1348 | if (vms->secure) { |
1349 | if (kvm_enabled()) { | |
1350 | error_report("mach-virt: KVM does not support Security extensions"); | |
1351 | exit(1); | |
1352 | } | |
1353 | ||
1354 | /* The Secure view of the world is the same as the NonSecure, | |
1355 | * but with a few extra devices. Create it as a container region | |
1356 | * containing the system memory at low priority; any secure-only | |
1357 | * devices go in at higher priority and take precedence. | |
1358 | */ | |
1359 | secure_sysmem = g_new(MemoryRegion, 1); | |
1360 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", | |
1361 | UINT64_MAX); | |
1362 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
1363 | } | |
1364 | ||
c8ef2bda | 1365 | create_fdt(vms); |
f5fdcd6e | 1366 | |
17d3d0e2 IM |
1367 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
1368 | for (n = 0; n < possible_cpus->len; n++) { | |
1369 | Object *cpuobj; | |
d9c34f9c | 1370 | CPUState *cs; |
46de5913 | 1371 | |
17d3d0e2 IM |
1372 | if (n >= smp_cpus) { |
1373 | break; | |
1374 | } | |
1375 | ||
d342eb76 | 1376 | cpuobj = object_new(possible_cpus->cpus[n].type); |
17d3d0e2 | 1377 | object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, |
46de5913 | 1378 | "mp-affinity", NULL); |
f313369f | 1379 | |
d9c34f9c IM |
1380 | cs = CPU(cpuobj); |
1381 | cs->cpu_index = n; | |
1382 | ||
a0ceb640 IM |
1383 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), |
1384 | &error_fatal); | |
bd4c1bfe | 1385 | |
e5a5604f GB |
1386 | if (!vms->secure) { |
1387 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
1388 | } | |
1389 | ||
f29cacfb | 1390 | if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) { |
c25bd18a PM |
1391 | object_property_set_bool(cpuobj, false, "has_el2", NULL); |
1392 | } | |
1393 | ||
2013c566 PM |
1394 | if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { |
1395 | object_property_set_int(cpuobj, vms->psci_conduit, | |
4824a61a | 1396 | "psci-conduit", NULL); |
211b0169 | 1397 | |
4824a61a PM |
1398 | /* Secondary CPUs start in PSCI powered-down state */ |
1399 | if (n > 0) { | |
1400 | object_property_set_bool(cpuobj, true, | |
1401 | "start-powered-off", NULL); | |
1402 | } | |
f5fdcd6e | 1403 | } |
ba750085 | 1404 | |
1141d1eb WH |
1405 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { |
1406 | object_property_set_bool(cpuobj, false, "pmu", NULL); | |
1407 | } | |
1408 | ||
ba750085 | 1409 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { |
c8ef2bda | 1410 | object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base, |
ba750085 PM |
1411 | "reset-cbar", &error_abort); |
1412 | } | |
1413 | ||
1d939a68 PM |
1414 | object_property_set_link(cpuobj, OBJECT(sysmem), "memory", |
1415 | &error_abort); | |
3df708eb PM |
1416 | if (vms->secure) { |
1417 | object_property_set_link(cpuobj, OBJECT(secure_sysmem), | |
1418 | "secure-memory", &error_abort); | |
1419 | } | |
1d939a68 | 1420 | |
c88bc3e0 | 1421 | object_property_set_bool(cpuobj, true, "realized", &error_fatal); |
dbb74759 | 1422 | object_unref(cpuobj); |
f5fdcd6e | 1423 | } |
055a7f2b | 1424 | fdt_add_timer_nodes(vms); |
c8ef2bda | 1425 | fdt_add_cpu_nodes(vms); |
f5fdcd6e | 1426 | |
c8623c02 DM |
1427 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", |
1428 | machine->ram_size); | |
c8ef2bda | 1429 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); |
f5fdcd6e | 1430 | |
c8ef2bda | 1431 | create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); |
acf82361 | 1432 | |
055a7f2b | 1433 | create_gic(vms, pic); |
f5fdcd6e | 1434 | |
055a7f2b | 1435 | fdt_add_pmu_nodes(vms); |
01fe6b60 | 1436 | |
9bca0edb | 1437 | create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); |
3df708eb PM |
1438 | |
1439 | if (vms->secure) { | |
c8ef2bda | 1440 | create_secure_ram(vms, secure_sysmem); |
9bca0edb | 1441 | create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); |
3df708eb | 1442 | } |
f5fdcd6e | 1443 | |
c8ef2bda | 1444 | create_rtc(vms, pic); |
6e411af9 | 1445 | |
0127937b | 1446 | create_pcie(vms, pic); |
4ab29b82 | 1447 | |
c8ef2bda | 1448 | create_gpio(vms, pic); |
b0a3721e | 1449 | |
f5fdcd6e PM |
1450 | /* Create mmio transports, so the user can create virtio backends |
1451 | * (which will be automatically plugged in to the transports). If | |
1452 | * no backend is created the transport will just sit harmlessly idle. | |
1453 | */ | |
c8ef2bda | 1454 | create_virtio_devices(vms, pic); |
f5fdcd6e | 1455 | |
af1f60a4 AJ |
1456 | vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); |
1457 | rom_set_fw(vms->fw_cfg); | |
d7c2e2db | 1458 | |
054f4dc9 AJ |
1459 | vms->machine_done.notify = virt_machine_done; |
1460 | qemu_add_machine_init_done_notifier(&vms->machine_done); | |
578f3c7b | 1461 | |
c8ef2bda PM |
1462 | vms->bootinfo.ram_size = machine->ram_size; |
1463 | vms->bootinfo.kernel_filename = machine->kernel_filename; | |
1464 | vms->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
1465 | vms->bootinfo.initrd_filename = machine->initrd_filename; | |
1466 | vms->bootinfo.nb_cpus = smp_cpus; | |
1467 | vms->bootinfo.board_id = -1; | |
1468 | vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; | |
1469 | vms->bootinfo.get_dtb = machvirt_dtb; | |
1470 | vms->bootinfo.firmware_loaded = firmware_loaded; | |
1471 | arm_load_kernel(ARM_CPU(first_cpu), &vms->bootinfo); | |
5f7a5a0e EA |
1472 | |
1473 | /* | |
1474 | * arm_load_kernel machine init done notifier registration must | |
1475 | * happen before the platform_bus_create call. In this latter, | |
1476 | * another notifier is registered which adds platform bus nodes. | |
1477 | * Notifiers are executed in registration reverse order. | |
1478 | */ | |
c8ef2bda | 1479 | create_platform_bus(vms, pic); |
f5fdcd6e PM |
1480 | } |
1481 | ||
083a5890 GB |
1482 | static bool virt_get_secure(Object *obj, Error **errp) |
1483 | { | |
1484 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1485 | ||
1486 | return vms->secure; | |
1487 | } | |
1488 | ||
1489 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
1490 | { | |
1491 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1492 | ||
1493 | vms->secure = value; | |
1494 | } | |
1495 | ||
f29cacfb PM |
1496 | static bool virt_get_virt(Object *obj, Error **errp) |
1497 | { | |
1498 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1499 | ||
1500 | return vms->virt; | |
1501 | } | |
1502 | ||
1503 | static void virt_set_virt(Object *obj, bool value, Error **errp) | |
1504 | { | |
1505 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1506 | ||
1507 | vms->virt = value; | |
1508 | } | |
1509 | ||
5125f9cd PF |
1510 | static bool virt_get_highmem(Object *obj, Error **errp) |
1511 | { | |
1512 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1513 | ||
1514 | return vms->highmem; | |
1515 | } | |
1516 | ||
1517 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
1518 | { | |
1519 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1520 | ||
1521 | vms->highmem = value; | |
1522 | } | |
1523 | ||
ccc11b02 EA |
1524 | static bool virt_get_its(Object *obj, Error **errp) |
1525 | { | |
1526 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1527 | ||
1528 | return vms->its; | |
1529 | } | |
1530 | ||
1531 | static void virt_set_its(Object *obj, bool value, Error **errp) | |
1532 | { | |
1533 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1534 | ||
1535 | vms->its = value; | |
1536 | } | |
1537 | ||
b92ad394 PF |
1538 | static char *virt_get_gic_version(Object *obj, Error **errp) |
1539 | { | |
1540 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1541 | const char *val = vms->gic_version == 3 ? "3" : "2"; | |
1542 | ||
1543 | return g_strdup(val); | |
1544 | } | |
1545 | ||
1546 | static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | |
1547 | { | |
1548 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1549 | ||
1550 | if (!strcmp(value, "3")) { | |
1551 | vms->gic_version = 3; | |
1552 | } else if (!strcmp(value, "2")) { | |
1553 | vms->gic_version = 2; | |
1554 | } else if (!strcmp(value, "host")) { | |
1555 | vms->gic_version = 0; /* Will probe later */ | |
dc16538a PM |
1556 | } else if (!strcmp(value, "max")) { |
1557 | vms->gic_version = -1; /* Will probe later */ | |
b92ad394 | 1558 | } else { |
7b55044f | 1559 | error_setg(errp, "Invalid gic-version value"); |
dc16538a | 1560 | error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); |
b92ad394 PF |
1561 | } |
1562 | } | |
1563 | ||
e24e3454 EA |
1564 | static char *virt_get_iommu(Object *obj, Error **errp) |
1565 | { | |
1566 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1567 | ||
1568 | switch (vms->iommu) { | |
1569 | case VIRT_IOMMU_NONE: | |
1570 | return g_strdup("none"); | |
1571 | case VIRT_IOMMU_SMMUV3: | |
1572 | return g_strdup("smmuv3"); | |
1573 | default: | |
1574 | g_assert_not_reached(); | |
1575 | } | |
1576 | } | |
1577 | ||
1578 | static void virt_set_iommu(Object *obj, const char *value, Error **errp) | |
1579 | { | |
1580 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1581 | ||
1582 | if (!strcmp(value, "smmuv3")) { | |
1583 | vms->iommu = VIRT_IOMMU_SMMUV3; | |
1584 | } else if (!strcmp(value, "none")) { | |
1585 | vms->iommu = VIRT_IOMMU_NONE; | |
1586 | } else { | |
1587 | error_setg(errp, "Invalid iommu value"); | |
1588 | error_append_hint(errp, "Valid values are none, smmuv3.\n"); | |
1589 | } | |
1590 | } | |
1591 | ||
ea089eeb IM |
1592 | static CpuInstanceProperties |
1593 | virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
1594 | { | |
1595 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1596 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
1597 | ||
1598 | assert(cpu_index < possible_cpus->len); | |
1599 | return possible_cpus->cpus[cpu_index].props; | |
1600 | } | |
1601 | ||
79e07936 IM |
1602 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) |
1603 | { | |
1604 | return idx % nb_numa_nodes; | |
1605 | } | |
1606 | ||
17d3d0e2 IM |
1607 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
1608 | { | |
1609 | int n; | |
1610 | VirtMachineState *vms = VIRT_MACHINE(ms); | |
1611 | ||
1612 | if (ms->possible_cpus) { | |
1613 | assert(ms->possible_cpus->len == max_cpus); | |
1614 | return ms->possible_cpus; | |
1615 | } | |
1616 | ||
1617 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
1618 | sizeof(CPUArchId) * max_cpus); | |
1619 | ms->possible_cpus->len = max_cpus; | |
1620 | for (n = 0; n < ms->possible_cpus->len; n++) { | |
d342eb76 | 1621 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
17d3d0e2 IM |
1622 | ms->possible_cpus->cpus[n].arch_id = |
1623 | virt_cpu_mp_affinity(vms, n); | |
1624 | ms->possible_cpus->cpus[n].props.has_thread_id = true; | |
1625 | ms->possible_cpus->cpus[n].props.thread_id = n; | |
17d3d0e2 IM |
1626 | } |
1627 | return ms->possible_cpus; | |
1628 | } | |
1629 | ||
ed796373 WH |
1630 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
1631 | { | |
9c94d8e6 WH |
1632 | MachineClass *mc = MACHINE_CLASS(oc); |
1633 | ||
1634 | mc->init = machvirt_init; | |
1635 | /* Start max_cpus at the maximum QEMU supports. We'll further restrict | |
1636 | * it later in machvirt_init, where we have more information about the | |
1637 | * configuration of the particular instance. | |
1638 | */ | |
079019f2 | 1639 | mc->max_cpus = 255; |
6f2062b9 EH |
1640 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); |
1641 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); | |
9c94d8e6 WH |
1642 | mc->block_default_type = IF_VIRTIO; |
1643 | mc->no_cdrom = 1; | |
1644 | mc->pci_allow_0_address = true; | |
a2519ad1 PM |
1645 | /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ |
1646 | mc->minimum_page_bits = 12; | |
17d3d0e2 | 1647 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
ea089eeb | 1648 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; |
ba1ba5cc | 1649 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
79e07936 | 1650 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
ed796373 WH |
1651 | } |
1652 | ||
1653 | static const TypeInfo virt_machine_info = { | |
1654 | .name = TYPE_VIRT_MACHINE, | |
1655 | .parent = TYPE_MACHINE, | |
1656 | .abstract = true, | |
1657 | .instance_size = sizeof(VirtMachineState), | |
1658 | .class_size = sizeof(VirtMachineClass), | |
1659 | .class_init = virt_machine_class_init, | |
1660 | }; | |
1661 | ||
7a2ecd95 AJ |
1662 | static void machvirt_machine_init(void) |
1663 | { | |
1664 | type_register_static(&virt_machine_info); | |
1665 | } | |
1666 | type_init(machvirt_machine_init); | |
1667 | ||
a2a05159 | 1668 | static void virt_2_12_instance_init(Object *obj) |
083a5890 GB |
1669 | { |
1670 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
ccc11b02 | 1671 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
083a5890 | 1672 | |
2d710006 PM |
1673 | /* EL3 is disabled by default on virt: this makes us consistent |
1674 | * between KVM and TCG for this board, and it also allows us to | |
1675 | * boot UEFI blobs which assume no TrustZone support. | |
1676 | */ | |
1677 | vms->secure = false; | |
083a5890 GB |
1678 | object_property_add_bool(obj, "secure", virt_get_secure, |
1679 | virt_set_secure, NULL); | |
1680 | object_property_set_description(obj, "secure", | |
1681 | "Set on/off to enable/disable the ARM " | |
1682 | "Security Extensions (TrustZone)", | |
1683 | NULL); | |
5125f9cd | 1684 | |
f29cacfb PM |
1685 | /* EL2 is also disabled by default, for similar reasons */ |
1686 | vms->virt = false; | |
1687 | object_property_add_bool(obj, "virtualization", virt_get_virt, | |
1688 | virt_set_virt, NULL); | |
1689 | object_property_set_description(obj, "virtualization", | |
1690 | "Set on/off to enable/disable emulating a " | |
1691 | "guest CPU which implements the ARM " | |
1692 | "Virtualization Extensions", | |
1693 | NULL); | |
1694 | ||
5125f9cd PF |
1695 | /* High memory is enabled by default */ |
1696 | vms->highmem = true; | |
1697 | object_property_add_bool(obj, "highmem", virt_get_highmem, | |
1698 | virt_set_highmem, NULL); | |
1699 | object_property_set_description(obj, "highmem", | |
1700 | "Set on/off to enable/disable using " | |
1701 | "physical address space above 32 bits", | |
1702 | NULL); | |
b92ad394 PF |
1703 | /* Default GIC type is v2 */ |
1704 | vms->gic_version = 2; | |
1705 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | |
1706 | virt_set_gic_version, NULL); | |
1707 | object_property_set_description(obj, "gic-version", | |
1708 | "Set GIC version. " | |
1709 | "Valid values are 2, 3 and host", NULL); | |
9ac4ef77 | 1710 | |
ccc11b02 EA |
1711 | if (vmc->no_its) { |
1712 | vms->its = false; | |
1713 | } else { | |
1714 | /* Default allows ITS instantiation */ | |
1715 | vms->its = true; | |
1716 | object_property_add_bool(obj, "its", virt_get_its, | |
1717 | virt_set_its, NULL); | |
1718 | object_property_set_description(obj, "its", | |
1719 | "Set on/off to enable/disable " | |
1720 | "ITS instantiation", | |
1721 | NULL); | |
1722 | } | |
1723 | ||
e24e3454 EA |
1724 | /* Default disallows iommu instantiation */ |
1725 | vms->iommu = VIRT_IOMMU_NONE; | |
1726 | object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL); | |
1727 | object_property_set_description(obj, "iommu", | |
1728 | "Set the IOMMU type. " | |
1729 | "Valid values are none and smmuv3", | |
1730 | NULL); | |
1731 | ||
9ac4ef77 PM |
1732 | vms->memmap = a15memmap; |
1733 | vms->irqmap = a15irqmap; | |
083a5890 GB |
1734 | } |
1735 | ||
a2a05159 PM |
1736 | static void virt_machine_2_12_options(MachineClass *mc) |
1737 | { | |
1738 | } | |
1739 | DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) | |
1740 | ||
1741 | #define VIRT_COMPAT_2_11 \ | |
1742 | HW_COMPAT_2_11 | |
1743 | ||
1744 | static void virt_2_11_instance_init(Object *obj) | |
1745 | { | |
1746 | virt_2_12_instance_init(obj); | |
1747 | } | |
1748 | ||
79283dda EA |
1749 | static void virt_machine_2_11_options(MachineClass *mc) |
1750 | { | |
dfadc3bf WH |
1751 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1752 | ||
a2a05159 PM |
1753 | virt_machine_2_12_options(mc); |
1754 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); | |
dfadc3bf | 1755 | vmc->smbios_old_sys_ver = true; |
79283dda | 1756 | } |
a2a05159 | 1757 | DEFINE_VIRT_MACHINE(2, 11) |
79283dda EA |
1758 | |
1759 | #define VIRT_COMPAT_2_10 \ | |
1760 | HW_COMPAT_2_10 | |
1761 | ||
1762 | static void virt_2_10_instance_init(Object *obj) | |
1763 | { | |
1764 | virt_2_11_instance_init(obj); | |
1765 | } | |
1766 | ||
f22ab6cb EA |
1767 | static void virt_machine_2_10_options(MachineClass *mc) |
1768 | { | |
79283dda EA |
1769 | virt_machine_2_11_options(mc); |
1770 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_10); | |
f22ab6cb | 1771 | } |
79283dda | 1772 | DEFINE_VIRT_MACHINE(2, 10) |
f22ab6cb EA |
1773 | |
1774 | #define VIRT_COMPAT_2_9 \ | |
1775 | HW_COMPAT_2_9 | |
1776 | ||
1777 | static void virt_2_9_instance_init(Object *obj) | |
1778 | { | |
1779 | virt_2_10_instance_init(obj); | |
1780 | } | |
1781 | ||
e353aac5 PM |
1782 | static void virt_machine_2_9_options(MachineClass *mc) |
1783 | { | |
f22ab6cb EA |
1784 | virt_machine_2_10_options(mc); |
1785 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9); | |
e353aac5 | 1786 | } |
f22ab6cb | 1787 | DEFINE_VIRT_MACHINE(2, 9) |
e353aac5 PM |
1788 | |
1789 | #define VIRT_COMPAT_2_8 \ | |
1790 | HW_COMPAT_2_8 | |
1791 | ||
1792 | static void virt_2_8_instance_init(Object *obj) | |
1793 | { | |
1794 | virt_2_9_instance_init(obj); | |
1795 | } | |
1796 | ||
96b0439b AJ |
1797 | static void virt_machine_2_8_options(MachineClass *mc) |
1798 | { | |
156bc9a5 PM |
1799 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1800 | ||
e353aac5 PM |
1801 | virt_machine_2_9_options(mc); |
1802 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); | |
156bc9a5 PM |
1803 | /* For 2.8 and earlier we falsely claimed in the DT that |
1804 | * our timers were edge-triggered, not level-triggered. | |
1805 | */ | |
1806 | vmc->claim_edge_triggered_timers = true; | |
96b0439b | 1807 | } |
e353aac5 | 1808 | DEFINE_VIRT_MACHINE(2, 8) |
96b0439b AJ |
1809 | |
1810 | #define VIRT_COMPAT_2_7 \ | |
1811 | HW_COMPAT_2_7 | |
1812 | ||
1813 | static void virt_2_7_instance_init(Object *obj) | |
1814 | { | |
1815 | virt_2_8_instance_init(obj); | |
1816 | } | |
1817 | ||
1287f2b3 AJ |
1818 | static void virt_machine_2_7_options(MachineClass *mc) |
1819 | { | |
2231f69b AJ |
1820 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1821 | ||
96b0439b AJ |
1822 | virt_machine_2_8_options(mc); |
1823 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); | |
2231f69b AJ |
1824 | /* ITS was introduced with 2.8 */ |
1825 | vmc->no_its = true; | |
a2519ad1 PM |
1826 | /* Stick with 1K pages for migration compatibility */ |
1827 | mc->minimum_page_bits = 0; | |
1287f2b3 | 1828 | } |
96b0439b | 1829 | DEFINE_VIRT_MACHINE(2, 7) |
1287f2b3 AJ |
1830 | |
1831 | #define VIRT_COMPAT_2_6 \ | |
1832 | HW_COMPAT_2_6 | |
1833 | ||
1834 | static void virt_2_6_instance_init(Object *obj) | |
1835 | { | |
1836 | virt_2_7_instance_init(obj); | |
1837 | } | |
1838 | ||
ab093c3c | 1839 | static void virt_machine_2_6_options(MachineClass *mc) |
c2919690 | 1840 | { |
95eb49c8 AJ |
1841 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1842 | ||
1287f2b3 AJ |
1843 | virt_machine_2_7_options(mc); |
1844 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); | |
95eb49c8 | 1845 | vmc->disallow_affinity_adjustment = true; |
1141d1eb WH |
1846 | /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ |
1847 | vmc->no_pmu = true; | |
c2919690 | 1848 | } |
1287f2b3 | 1849 | DEFINE_VIRT_MACHINE(2, 6) |