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f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
12b16722 | 31 | #include "qemu/osdep.h" |
2c65db5e | 32 | #include "qemu/datadir.h" |
350a9c9e | 33 | #include "qemu/units.h" |
e0561e60 | 34 | #include "qemu/option.h" |
70e89132 | 35 | #include "monitor/qdev.h" |
f5fdcd6e | 36 | #include "hw/sysbus.h" |
12ec8bd5 | 37 | #include "hw/arm/boot.h" |
f5fdcd6e | 38 | #include "hw/arm/primecell.h" |
afe0b380 | 39 | #include "hw/arm/virt.h" |
81c7db72 | 40 | #include "hw/block/flash.h" |
6f2062b9 EH |
41 | #include "hw/vfio/vfio-calxeda-xgmac.h" |
42 | #include "hw/vfio/vfio-amd-xgbe.h" | |
94692dcd | 43 | #include "hw/display/ramfb.h" |
f5fdcd6e PM |
44 | #include "net/net.h" |
45 | #include "sysemu/device_tree.h" | |
9695200a | 46 | #include "sysemu/numa.h" |
54d31236 | 47 | #include "sysemu/runstate.h" |
c294ac32 | 48 | #include "sysemu/tpm.h" |
5e91b9e0 | 49 | #include "sysemu/tcg.h" |
f5fdcd6e | 50 | #include "sysemu/kvm.h" |
bede0117 | 51 | #include "sysemu/hvf.h" |
5e91b9e0 | 52 | #include "sysemu/qtest.h" |
acf82361 | 53 | #include "hw/loader.h" |
05dfb447 | 54 | #include "qapi/error.h" |
f5fdcd6e PM |
55 | #include "qemu/bitops.h" |
56 | #include "qemu/error-report.h" | |
0b8fa32f | 57 | #include "qemu/module.h" |
4ab29b82 | 58 | #include "hw/pci-host/gpex.h" |
70e89132 | 59 | #include "hw/virtio/virtio-pci.h" |
d24a7bc2 | 60 | #include "hw/core/sysbus-fdt.h" |
5f7a5a0e | 61 | #include "hw/platform-bus.h" |
a27bd6c7 | 62 | #include "hw/qdev-properties.h" |
decf4f80 | 63 | #include "hw/arm/fdt.h" |
95eb49c8 AJ |
64 | #include "hw/intc/arm_gic.h" |
65 | #include "hw/intc/arm_gicv3_common.h" | |
0c40daf0 | 66 | #include "hw/intc/arm_gicv3_its_common.h" |
64552b6b | 67 | #include "hw/irq.h" |
e6fbcbc4 | 68 | #include "kvm_arm.h" |
a2eb5c0c | 69 | #include "hw/firmware/smbios.h" |
b92ad394 | 70 | #include "qapi/visitor.h" |
17e89077 | 71 | #include "qapi/qapi-visit-common.h" |
3e6ebb64 | 72 | #include "standard-headers/linux/input.h" |
584105ea | 73 | #include "hw/arm/smmuv3.h" |
957e32cf | 74 | #include "hw/acpi/acpi.h" |
2ba956cc | 75 | #include "target/arm/internals.h" |
1f283ae1 EA |
76 | #include "hw/mem/pc-dimm.h" |
77 | #include "hw/mem/nvdimm.h" | |
cff51ac9 | 78 | #include "hw/acpi/generic_event_device.h" |
30ec5ccd | 79 | #include "hw/virtio/virtio-md-pci.h" |
70e89132 | 80 | #include "hw/virtio/virtio-iommu.h" |
d8f6d15f | 81 | #include "hw/char/pl011.h" |
60592cfe | 82 | #include "qemu/guest-random.h" |
f5fdcd6e | 83 | |
3356ebce | 84 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ |
ab093c3c AJ |
85 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ |
86 | void *data) \ | |
87 | { \ | |
88 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
89 | virt_machine_##major##_##minor##_options(mc); \ | |
90 | mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ | |
3356ebce AJ |
91 | if (latest) { \ |
92 | mc->alias = "virt"; \ | |
93 | } \ | |
ab093c3c AJ |
94 | } \ |
95 | static const TypeInfo machvirt_##major##_##minor##_info = { \ | |
96 | .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ | |
97 | .parent = TYPE_VIRT_MACHINE, \ | |
ab093c3c AJ |
98 | .class_init = virt_##major##_##minor##_class_init, \ |
99 | }; \ | |
100 | static void machvirt_machine_##major##_##minor##_init(void) \ | |
101 | { \ | |
102 | type_register_static(&machvirt_##major##_##minor##_info); \ | |
103 | } \ | |
104 | type_init(machvirt_machine_##major##_##minor##_init); | |
105 | ||
3356ebce AJ |
106 | #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ |
107 | DEFINE_VIRT_MACHINE_LATEST(major, minor, true) | |
108 | #define DEFINE_VIRT_MACHINE(major, minor) \ | |
109 | DEFINE_VIRT_MACHINE_LATEST(major, minor, false) | |
110 | ||
ab093c3c | 111 | |
a72d4363 AJ |
112 | /* Number of external interrupt lines to configure the GIC with */ |
113 | #define NUM_IRQS 256 | |
114 | ||
115 | #define PLATFORM_BUS_NUM_IRQS 64 | |
116 | ||
50a17297 | 117 | /* Legacy RAM limit in GB (< version 4.0) */ |
957e32cf EA |
118 | #define LEGACY_RAMLIMIT_GB 255 |
119 | #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) | |
71c27684 | 120 | |
f5fdcd6e PM |
121 | /* Addresses and sizes of our components. |
122 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
123 | * 128MB..256MB is used for miscellaneous device I/O. | |
124 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
125 | * PCI memory window will go if we add a PCI host controller). | |
126 | * 1GB and up is RAM (which may happily spill over into the | |
127 | * high memory region beyond 4GB). | |
128 | * This represents a compromise between how much RAM can be given to | |
129 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
130 | * Note that devices should generally be placed at multiples of 0x10000, |
131 | * to accommodate guests using 64K pages. | |
f5fdcd6e | 132 | */ |
350a9c9e | 133 | static const MemMapEntry base_memmap[] = { |
f5fdcd6e | 134 | /* Space up to 0x8000000 is reserved for a boot ROM */ |
94edf02c EA |
135 | [VIRT_FLASH] = { 0, 0x08000000 }, |
136 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 137 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
138 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
139 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
140 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
55ef3233 LM |
141 | [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 }, |
142 | [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 }, | |
b92ad394 PF |
143 | /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ |
144 | [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, | |
145 | /* This redistributor space allows up to 2*64kB*123 CPUs */ | |
146 | [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, | |
94edf02c EA |
147 | [VIRT_UART] = { 0x09000000, 0x00001000 }, |
148 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
0b341a85 | 149 | [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, |
b0a3721e | 150 | [VIRT_GPIO] = { 0x09030000, 0x00001000 }, |
3df708eb | 151 | [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, |
584105ea | 152 | [VIRT_SMMU] = { 0x09050000, 0x00020000 }, |
cff51ac9 SK |
153 | [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN }, |
154 | [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN }, | |
b5a60bee | 155 | [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN}, |
68970d1e | 156 | [VIRT_PVTIME] = { 0x090a0000, 0x00010000 }, |
daa726d9 | 157 | [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 }, |
94edf02c | 158 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, |
f5fdcd6e | 159 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c | 160 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
83ec1923 | 161 | [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, |
94edf02c EA |
162 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, |
163 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
164 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
957e32cf EA |
165 | /* Actual RAM size depends on initial RAM and device memory settings */ |
166 | [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, | |
350a9c9e EA |
167 | }; |
168 | ||
169 | /* | |
170 | * Highmem IO Regions: This memory map is floating, located after the RAM. | |
171 | * Each MemMapEntry base (GPA) will be dynamically computed, depending on the | |
172 | * top of the RAM, so that its base get the same alignment as the size, | |
173 | * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is | |
174 | * less than 256GiB of RAM, the floating area starts at the 256GiB mark. | |
175 | * Note the extended_memmap is sized so that it eventually also includes the | |
176 | * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last | |
177 | * index of base_memmap). | |
f40408a9 GS |
178 | * |
179 | * The memory map for these Highmem IO Regions can be in legacy or compact | |
180 | * layout, depending on 'compact-highmem' property. With legacy layout, the | |
181 | * PA space for one specific region is always reserved, even if the region | |
182 | * has been disabled or doesn't fit into the PA space. However, the PA space | |
183 | * for the region won't be reserved in these circumstances with compact layout. | |
350a9c9e EA |
184 | */ |
185 | static MemMapEntry extended_memmap[] = { | |
f90747c4 | 186 | /* Additional 64 MB redist region (can contain up to 512 redistributors) */ |
350a9c9e EA |
187 | [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, |
188 | [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, | |
189 | /* Second PCIe window */ | |
190 | [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, | |
f5fdcd6e PM |
191 | }; |
192 | ||
193 | static const int a15irqmap[] = { | |
194 | [VIRT_UART] = 1, | |
6e411af9 | 195 | [VIRT_RTC] = 2, |
4ab29b82 | 196 | [VIRT_PCIE] = 3, /* ... to 6 */ |
b0a3721e | 197 | [VIRT_GPIO] = 7, |
3df708eb | 198 | [VIRT_SECURE_UART] = 8, |
cff51ac9 | 199 | [VIRT_ACPI_GED] = 9, |
f5fdcd6e | 200 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 201 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
584105ea | 202 | [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */ |
5f7a5a0e | 203 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
204 | }; |
205 | ||
9ac4ef77 | 206 | static const char *valid_cpus[] = { |
7a98c837 | 207 | #ifdef CONFIG_TCG |
4414942e | 208 | ARM_CPU_TYPE_NAME("cortex-a7"), |
ba1ba5cc | 209 | ARM_CPU_TYPE_NAME("cortex-a15"), |
3b16766b | 210 | ARM_CPU_TYPE_NAME("cortex-a35"), |
94bc3b06 | 211 | ARM_CPU_TYPE_NAME("cortex-a55"), |
2264faa5 | 212 | ARM_CPU_TYPE_NAME("cortex-a72"), |
2f6283fc | 213 | ARM_CPU_TYPE_NAME("cortex-a76"), |
4d39fcd8 | 214 | ARM_CPU_TYPE_NAME("a64fx"), |
5db6de80 | 215 | ARM_CPU_TYPE_NAME("neoverse-n1"), |
c74138c6 | 216 | ARM_CPU_TYPE_NAME("neoverse-v1"), |
39920a04 FR |
217 | #endif |
218 | ARM_CPU_TYPE_NAME("cortex-a53"), | |
219 | ARM_CPU_TYPE_NAME("cortex-a57"), | |
ba1ba5cc | 220 | ARM_CPU_TYPE_NAME("host"), |
9076ddb3 | 221 | ARM_CPU_TYPE_NAME("max"), |
f5fdcd6e PM |
222 | }; |
223 | ||
ba1ba5cc | 224 | static bool cpu_type_valid(const char *cpu) |
f5fdcd6e PM |
225 | { |
226 | int i; | |
227 | ||
9ac4ef77 PM |
228 | for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { |
229 | if (strcmp(cpu, valid_cpus[i]) == 0) { | |
230 | return true; | |
f5fdcd6e PM |
231 | } |
232 | } | |
9ac4ef77 | 233 | return false; |
f5fdcd6e PM |
234 | } |
235 | ||
5242876f | 236 | static void create_randomness(MachineState *ms, const char *node) |
60592cfe | 237 | { |
5242876f JD |
238 | struct { |
239 | uint64_t kaslr; | |
240 | uint8_t rng[32]; | |
241 | } seed; | |
60592cfe | 242 | |
9261ef5e | 243 | if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { |
60592cfe JF |
244 | return; |
245 | } | |
5242876f JD |
246 | qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); |
247 | qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); | |
60592cfe JF |
248 | } |
249 | ||
c8ef2bda | 250 | static void create_fdt(VirtMachineState *vms) |
f5fdcd6e | 251 | { |
aa570207 TX |
252 | MachineState *ms = MACHINE(vms); |
253 | int nb_numa_nodes = ms->numa_state->num_nodes; | |
c8ef2bda | 254 | void *fdt = create_device_tree(&vms->fdt_size); |
f5fdcd6e PM |
255 | |
256 | if (!fdt) { | |
257 | error_report("create_device_tree() failed"); | |
258 | exit(1); | |
259 | } | |
260 | ||
a6487d37 | 261 | ms->fdt = fdt; |
f5fdcd6e PM |
262 | |
263 | /* Header */ | |
5a4348d1 PC |
264 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
265 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
266 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
5f1d731c | 267 | qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt"); |
f5fdcd6e | 268 | |
e2eb3d29 | 269 | /* /chosen must exist for load_dtb to fill in necessary properties later */ |
5a4348d1 | 270 | qemu_fdt_add_subnode(fdt, "/chosen"); |
5242876f JD |
271 | if (vms->dtb_randomness) { |
272 | create_randomness(ms, "/chosen"); | |
33973e1e | 273 | } |
f5fdcd6e | 274 | |
ef6a5c71 JF |
275 | if (vms->secure) { |
276 | qemu_fdt_add_subnode(fdt, "/secure-chosen"); | |
5242876f JD |
277 | if (vms->dtb_randomness) { |
278 | create_randomness(ms, "/secure-chosen"); | |
33973e1e | 279 | } |
ef6a5c71 JF |
280 | } |
281 | ||
f5fdcd6e PM |
282 | /* Clock node, for the benefit of the UART. The kernel device tree |
283 | * binding documentation claims the PL011 node clock properties are | |
284 | * optional but in practice if you omit them the kernel refuses to | |
285 | * probe for the device. | |
286 | */ | |
c8ef2bda | 287 | vms->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
5a4348d1 PC |
288 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); |
289 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
290 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
291 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
292 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 293 | "clk24mhz"); |
c8ef2bda | 294 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); |
f5fdcd6e | 295 | |
118154b7 | 296 | if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { |
c7637c04 AJ |
297 | int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); |
298 | uint32_t *matrix = g_malloc0(size); | |
299 | int idx, i, j; | |
300 | ||
301 | for (i = 0; i < nb_numa_nodes; i++) { | |
302 | for (j = 0; j < nb_numa_nodes; j++) { | |
303 | idx = (i * nb_numa_nodes + j) * 3; | |
304 | matrix[idx + 0] = cpu_to_be32(i); | |
305 | matrix[idx + 1] = cpu_to_be32(j); | |
7e721e7b TX |
306 | matrix[idx + 2] = |
307 | cpu_to_be32(ms->numa_state->nodes[i].distance[j]); | |
c7637c04 AJ |
308 | } |
309 | } | |
310 | ||
311 | qemu_fdt_add_subnode(fdt, "/distance-map"); | |
312 | qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", | |
313 | "numa-distance-map-v1"); | |
314 | qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", | |
315 | matrix, size); | |
316 | g_free(matrix); | |
317 | } | |
06955739 PS |
318 | } |
319 | ||
055a7f2b | 320 | static void fdt_add_timer_nodes(const VirtMachineState *vms) |
f5fdcd6e | 321 | { |
156bc9a5 PM |
322 | /* On real hardware these interrupts are level-triggered. |
323 | * On KVM they were edge-triggered before host kernel version 4.4, | |
324 | * and level-triggered afterwards. | |
325 | * On emulated QEMU they are level-triggered. | |
326 | * | |
327 | * Getting the DTB info about them wrong is awkward for some | |
328 | * guest kernels: | |
329 | * pre-4.8 ignore the DT and leave the interrupt configured | |
330 | * with whatever the GIC reset value (or the bootloader) left it at | |
331 | * 4.8 before rc6 honour the incorrect data by programming it back | |
332 | * into the GIC, causing problems | |
333 | * 4.8rc6 and later ignore the DT and always write "level triggered" | |
334 | * into the GIC | |
335 | * | |
336 | * For backwards-compatibility, virt-2.8 and earlier will continue | |
337 | * to say these are edge-triggered, but later machines will report | |
338 | * the correct information. | |
f5fdcd6e | 339 | */ |
b32a9509 | 340 | ARMCPU *armcpu; |
156bc9a5 PM |
341 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
342 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
a6487d37 | 343 | MachineState *ms = MACHINE(vms); |
156bc9a5 PM |
344 | |
345 | if (vmc->claim_edge_triggered_timers) { | |
346 | irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; | |
347 | } | |
f5fdcd6e | 348 | |
d04460e5 | 349 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
b92ad394 PF |
350 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
351 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
9cd07db9 | 352 | (1 << MACHINE(vms)->smp.cpus) - 1); |
b92ad394 | 353 | } |
f5fdcd6e | 354 | |
a6487d37 | 355 | qemu_fdt_add_subnode(ms->fdt, "/timer"); |
b32a9509 CF |
356 | |
357 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
358 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
359 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
a6487d37 | 360 | qemu_fdt_setprop(ms->fdt, "/timer", "compatible", |
b32a9509 CF |
361 | compat, sizeof(compat)); |
362 | } else { | |
a6487d37 | 363 | qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", |
b32a9509 CF |
364 | "arm,armv7-timer"); |
365 | } | |
a6487d37 AB |
366 | qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); |
367 | qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | |
ee246400 SZ |
368 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
369 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
370 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
371 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
372 | } |
373 | ||
c8ef2bda | 374 | static void fdt_add_cpu_nodes(const VirtMachineState *vms) |
f5fdcd6e PM |
375 | { |
376 | int cpu; | |
8d45c54d | 377 | int addr_cells = 1; |
4ccf5826 | 378 | const MachineState *ms = MACHINE(vms); |
72b0527f | 379 | const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
9cd07db9 | 380 | int smp_cpus = ms->smp.cpus; |
8d45c54d PF |
381 | |
382 | /* | |
72b0527f AJ |
383 | * See Linux Documentation/devicetree/bindings/arm/cpus.yaml |
384 | * On ARM v8 64-bit systems value should be set to 2, | |
385 | * that corresponds to the MPIDR_EL1 register size. | |
386 | * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
387 | * in the system, #address-cells can be set to 1, since | |
388 | * MPIDR_EL1[63:32] bits are not used for CPUs | |
389 | * identification. | |
8d45c54d | 390 | * |
72b0527f AJ |
391 | * Here we actually don't know whether our system is 32- or 64-bit one. |
392 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | |
393 | * at least one of them has Aff3 populated, we set #address-cells to 2. | |
8d45c54d | 394 | */ |
9cd07db9 | 395 | for (cpu = 0; cpu < smp_cpus; cpu++) { |
8d45c54d PF |
396 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); |
397 | ||
398 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | |
399 | addr_cells = 2; | |
400 | break; | |
401 | } | |
402 | } | |
f5fdcd6e | 403 | |
a6487d37 AB |
404 | qemu_fdt_add_subnode(ms->fdt, "/cpus"); |
405 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); | |
406 | qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); | |
f5fdcd6e | 407 | |
9cd07db9 | 408 | for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { |
f5fdcd6e PM |
409 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
410 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
4ccf5826 | 411 | CPUState *cs = CPU(armcpu); |
f5fdcd6e | 412 | |
a6487d37 AB |
413 | qemu_fdt_add_subnode(ms->fdt, nodename); |
414 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); | |
415 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
f5fdcd6e PM |
416 | armcpu->dtb_compatible); |
417 | ||
9cd07db9 | 418 | if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { |
a6487d37 | 419 | qemu_fdt_setprop_string(ms->fdt, nodename, |
f5fdcd6e PM |
420 | "enable-method", "psci"); |
421 | } | |
422 | ||
8d45c54d | 423 | if (addr_cells == 2) { |
a6487d37 | 424 | qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", |
8d45c54d PF |
425 | armcpu->mp_affinity); |
426 | } else { | |
a6487d37 | 427 | qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", |
8d45c54d PF |
428 | armcpu->mp_affinity); |
429 | } | |
430 | ||
4ccf5826 | 431 | if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { |
a6487d37 | 432 | qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", |
4ccf5826 | 433 | ms->possible_cpus->cpus[cs->cpu_index].props.node_id); |
9695200a SZ |
434 | } |
435 | ||
72b0527f AJ |
436 | if (!vmc->no_cpu_topology) { |
437 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", | |
438 | qemu_fdt_alloc_phandle(ms->fdt)); | |
439 | } | |
440 | ||
f5fdcd6e PM |
441 | g_free(nodename); |
442 | } | |
72b0527f AJ |
443 | |
444 | if (!vmc->no_cpu_topology) { | |
445 | /* | |
446 | * Add vCPU topology description through fdt node cpu-map. | |
447 | * | |
448 | * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt | |
449 | * In a SMP system, the hierarchy of CPUs can be defined through | |
450 | * four entities that are used to describe the layout of CPUs in | |
451 | * the system: socket/cluster/core/thread. | |
452 | * | |
453 | * A socket node represents the boundary of system physical package | |
454 | * and its child nodes must be one or more cluster nodes. A system | |
455 | * can contain several layers of clustering within a single physical | |
456 | * package and cluster nodes can be contained in parent cluster nodes. | |
457 | * | |
28a60a59 YW |
458 | * Note: currently we only support one layer of clustering within |
459 | * each physical package. | |
72b0527f AJ |
460 | */ |
461 | qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); | |
462 | ||
463 | for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { | |
464 | char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu); | |
465 | char *map_path; | |
466 | ||
467 | if (ms->smp.threads > 1) { | |
468 | map_path = g_strdup_printf( | |
28a60a59 YW |
469 | "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d", |
470 | cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), | |
471 | (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, | |
72b0527f AJ |
472 | (cpu / ms->smp.threads) % ms->smp.cores, |
473 | cpu % ms->smp.threads); | |
474 | } else { | |
475 | map_path = g_strdup_printf( | |
28a60a59 YW |
476 | "/cpus/cpu-map/socket%d/cluster%d/core%d", |
477 | cpu / (ms->smp.clusters * ms->smp.cores), | |
478 | (cpu / ms->smp.cores) % ms->smp.clusters, | |
72b0527f AJ |
479 | cpu % ms->smp.cores); |
480 | } | |
481 | qemu_fdt_add_path(ms->fdt, map_path); | |
482 | qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); | |
483 | ||
484 | g_free(map_path); | |
485 | g_free(cpu_path); | |
486 | } | |
487 | } | |
f5fdcd6e PM |
488 | } |
489 | ||
c8ef2bda | 490 | static void fdt_add_its_gic_node(VirtMachineState *vms) |
02f98731 | 491 | { |
bb2a3348 | 492 | char *nodename; |
a6487d37 | 493 | MachineState *ms = MACHINE(vms); |
bb2a3348 | 494 | |
a6487d37 | 495 | vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); |
bb2a3348 EA |
496 | nodename = g_strdup_printf("/intc/its@%" PRIx64, |
497 | vms->memmap[VIRT_GIC_ITS].base); | |
a6487d37 AB |
498 | qemu_fdt_add_subnode(ms->fdt, nodename); |
499 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
02f98731 | 500 | "arm,gic-v3-its"); |
a6487d37 | 501 | qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); |
a312a530 | 502 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); |
a6487d37 | 503 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
c8ef2bda PM |
504 | 2, vms->memmap[VIRT_GIC_ITS].base, |
505 | 2, vms->memmap[VIRT_GIC_ITS].size); | |
a6487d37 | 506 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); |
bb2a3348 | 507 | g_free(nodename); |
02f98731 PF |
508 | } |
509 | ||
c8ef2bda | 510 | static void fdt_add_v2m_gic_node(VirtMachineState *vms) |
f5fdcd6e | 511 | { |
a6487d37 | 512 | MachineState *ms = MACHINE(vms); |
bb2a3348 EA |
513 | char *nodename; |
514 | ||
515 | nodename = g_strdup_printf("/intc/v2m@%" PRIx64, | |
516 | vms->memmap[VIRT_GIC_V2M].base); | |
a6487d37 AB |
517 | vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); |
518 | qemu_fdt_add_subnode(ms->fdt, nodename); | |
519 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", | |
bd204e63 | 520 | "arm,gic-v2m-frame"); |
a6487d37 AB |
521 | qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); |
522 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
c8ef2bda PM |
523 | 2, vms->memmap[VIRT_GIC_V2M].base, |
524 | 2, vms->memmap[VIRT_GIC_V2M].size); | |
a6487d37 | 525 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); |
bb2a3348 | 526 | g_free(nodename); |
bd204e63 | 527 | } |
f5fdcd6e | 528 | |
055a7f2b | 529 | static void fdt_add_gic_node(VirtMachineState *vms) |
bd204e63 | 530 | { |
a6487d37 | 531 | MachineState *ms = MACHINE(vms); |
bb2a3348 EA |
532 | char *nodename; |
533 | ||
a6487d37 AB |
534 | vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); |
535 | qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); | |
c8ef2bda | 536 | |
bb2a3348 EA |
537 | nodename = g_strdup_printf("/intc@%" PRIx64, |
538 | vms->memmap[VIRT_GIC_DIST].base); | |
a6487d37 AB |
539 | qemu_fdt_add_subnode(ms->fdt, nodename); |
540 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); | |
541 | qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); | |
542 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); | |
543 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); | |
544 | qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); | |
7cf3f8d2 | 545 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
f90747c4 EA |
546 | int nb_redist_regions = virt_gicv3_redist_region_count(vms); |
547 | ||
a6487d37 | 548 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", |
b92ad394 | 549 | "arm,gic-v3"); |
f90747c4 | 550 | |
a6487d37 | 551 | qemu_fdt_setprop_cell(ms->fdt, nodename, |
f90747c4 EA |
552 | "#redistributor-regions", nb_redist_regions); |
553 | ||
554 | if (nb_redist_regions == 1) { | |
a6487d37 | 555 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
f90747c4 EA |
556 | 2, vms->memmap[VIRT_GIC_DIST].base, |
557 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
558 | 2, vms->memmap[VIRT_GIC_REDIST].base, | |
559 | 2, vms->memmap[VIRT_GIC_REDIST].size); | |
560 | } else { | |
a6487d37 | 561 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
bf424a12 EA |
562 | 2, vms->memmap[VIRT_GIC_DIST].base, |
563 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
564 | 2, vms->memmap[VIRT_GIC_REDIST].base, | |
565 | 2, vms->memmap[VIRT_GIC_REDIST].size, | |
566 | 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, | |
567 | 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); | |
f90747c4 EA |
568 | } |
569 | ||
f29cacfb | 570 | if (vms->virt) { |
a6487d37 | 571 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", |
55ef3233 | 572 | GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, |
f29cacfb PM |
573 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
574 | } | |
b92ad394 PF |
575 | } else { |
576 | /* 'cortex-a15-gic' means 'GIC v2' */ | |
a6487d37 | 577 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", |
b92ad394 | 578 | "arm,cortex-a15-gic"); |
55ef3233 | 579 | if (!vms->virt) { |
a6487d37 | 580 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
55ef3233 LM |
581 | 2, vms->memmap[VIRT_GIC_DIST].base, |
582 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
583 | 2, vms->memmap[VIRT_GIC_CPU].base, | |
584 | 2, vms->memmap[VIRT_GIC_CPU].size); | |
585 | } else { | |
a6487d37 | 586 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
55ef3233 LM |
587 | 2, vms->memmap[VIRT_GIC_DIST].base, |
588 | 2, vms->memmap[VIRT_GIC_DIST].size, | |
589 | 2, vms->memmap[VIRT_GIC_CPU].base, | |
590 | 2, vms->memmap[VIRT_GIC_CPU].size, | |
591 | 2, vms->memmap[VIRT_GIC_HYP].base, | |
592 | 2, vms->memmap[VIRT_GIC_HYP].size, | |
593 | 2, vms->memmap[VIRT_GIC_VCPU].base, | |
594 | 2, vms->memmap[VIRT_GIC_VCPU].size); | |
a6487d37 | 595 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", |
55ef3233 LM |
596 | GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, |
597 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
598 | } | |
b92ad394 PF |
599 | } |
600 | ||
a6487d37 | 601 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); |
bb2a3348 | 602 | g_free(nodename); |
f5fdcd6e PM |
603 | } |
604 | ||
055a7f2b | 605 | static void fdt_add_pmu_nodes(const VirtMachineState *vms) |
01fe6b60 | 606 | { |
946f1bb1 | 607 | ARMCPU *armcpu = ARM_CPU(first_cpu); |
01fe6b60 | 608 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; |
a6487d37 | 609 | MachineState *ms = MACHINE(vms); |
01fe6b60 | 610 | |
946f1bb1 AJ |
611 | if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { |
612 | assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL)); | |
613 | return; | |
01fe6b60 SZ |
614 | } |
615 | ||
d04460e5 | 616 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
01fe6b60 SZ |
617 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, |
618 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
9cd07db9 | 619 | (1 << MACHINE(vms)->smp.cpus) - 1); |
01fe6b60 SZ |
620 | } |
621 | ||
a6487d37 | 622 | qemu_fdt_add_subnode(ms->fdt, "/pmu"); |
01fe6b60 SZ |
623 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { |
624 | const char compat[] = "arm,armv8-pmuv3"; | |
a6487d37 | 625 | qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", |
01fe6b60 | 626 | compat, sizeof(compat)); |
a6487d37 | 627 | qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", |
01fe6b60 SZ |
628 | GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); |
629 | } | |
630 | } | |
631 | ||
b8b69f4c | 632 | static inline DeviceState *create_acpi_ged(VirtMachineState *vms) |
cff51ac9 SK |
633 | { |
634 | DeviceState *dev; | |
635 | MachineState *ms = MACHINE(vms); | |
636 | int irq = vms->irqmap[VIRT_ACPI_GED]; | |
1962f31b | 637 | uint32_t event = ACPI_GED_PWR_DOWN_EVT; |
cff51ac9 SK |
638 | |
639 | if (ms->ram_slots) { | |
1962f31b | 640 | event |= ACPI_GED_MEM_HOTPLUG_EVT; |
cff51ac9 SK |
641 | } |
642 | ||
c2505d1c SK |
643 | if (ms->nvdimms_state->is_enabled) { |
644 | event |= ACPI_GED_NVDIMM_HOTPLUG_EVT; | |
645 | } | |
646 | ||
3e80f690 | 647 | dev = qdev_new(TYPE_ACPI_GED); |
cff51ac9 SK |
648 | qdev_prop_set_uint32(dev, "ged-event", event); |
649 | ||
650 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base); | |
651 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); | |
b8b69f4c | 652 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); |
cff51ac9 | 653 | |
3c6ef471 | 654 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
cff51ac9 SK |
655 | |
656 | return dev; | |
657 | } | |
658 | ||
b8b69f4c | 659 | static void create_its(VirtMachineState *vms) |
02f98731 PF |
660 | { |
661 | const char *itsclass = its_class_name(); | |
662 | DeviceState *dev; | |
663 | ||
0e5c1c9a SM |
664 | if (!strcmp(itsclass, "arm-gicv3-its")) { |
665 | if (!vms->tcg_its) { | |
666 | itsclass = NULL; | |
667 | } | |
668 | } | |
669 | ||
02f98731 PF |
670 | if (!itsclass) { |
671 | /* Do nothing if not supported */ | |
672 | return; | |
673 | } | |
674 | ||
3e80f690 | 675 | dev = qdev_new(itsclass); |
02f98731 | 676 | |
5325cc34 | 677 | object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), |
02f98731 | 678 | &error_abort); |
3c6ef471 | 679 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
c8ef2bda | 680 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); |
02f98731 | 681 | |
c8ef2bda | 682 | fdt_add_its_gic_node(vms); |
1b6f99d8 | 683 | vms->msi_controller = VIRT_MSI_CTRL_ITS; |
02f98731 PF |
684 | } |
685 | ||
b8b69f4c | 686 | static void create_v2m(VirtMachineState *vms) |
bd204e63 CD |
687 | { |
688 | int i; | |
c8ef2bda | 689 | int irq = vms->irqmap[VIRT_GIC_V2M]; |
bd204e63 CD |
690 | DeviceState *dev; |
691 | ||
3e80f690 | 692 | dev = qdev_new("arm-gicv2m"); |
c8ef2bda | 693 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base); |
bd204e63 CD |
694 | qdev_prop_set_uint32(dev, "base-spi", irq); |
695 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
3c6ef471 | 696 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
bd204e63 CD |
697 | |
698 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
b8b69f4c PMD |
699 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
700 | qdev_get_gpio_in(vms->gic, irq + i)); | |
bd204e63 CD |
701 | } |
702 | ||
c8ef2bda | 703 | fdt_add_v2m_gic_node(vms); |
1b6f99d8 | 704 | vms->msi_controller = VIRT_MSI_CTRL_GICV2M; |
bd204e63 CD |
705 | } |
706 | ||
0e5c1c9a | 707 | static void create_gic(VirtMachineState *vms, MemoryRegion *mem) |
64204743 | 708 | { |
cc7d44c2 | 709 | MachineState *ms = MACHINE(vms); |
b92ad394 | 710 | /* We create a standalone GIC */ |
64204743 | 711 | SysBusDevice *gicbusdev; |
e6fbcbc4 | 712 | const char *gictype; |
5a389a9a | 713 | int i; |
cc7d44c2 | 714 | unsigned int smp_cpus = ms->smp.cpus; |
03d72fa1 | 715 | uint32_t nb_redist_regions = 0; |
5a389a9a | 716 | int revision; |
64204743 | 717 | |
5a389a9a PM |
718 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
719 | gictype = gic_class_name(); | |
720 | } else { | |
721 | gictype = gicv3_class_name(); | |
722 | } | |
64204743 | 723 | |
5a389a9a PM |
724 | switch (vms->gic_version) { |
725 | case VIRT_GIC_VERSION_2: | |
726 | revision = 2; | |
727 | break; | |
728 | case VIRT_GIC_VERSION_3: | |
729 | revision = 3; | |
730 | break; | |
7cf3f8d2 PM |
731 | case VIRT_GIC_VERSION_4: |
732 | revision = 4; | |
733 | break; | |
5a389a9a PM |
734 | default: |
735 | g_assert_not_reached(); | |
736 | } | |
3e80f690 | 737 | vms->gic = qdev_new(gictype); |
5a389a9a | 738 | qdev_prop_set_uint32(vms->gic, "revision", revision); |
b8b69f4c | 739 | qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); |
64204743 PM |
740 | /* Note that the num-irq property counts both internal and external |
741 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
742 | */ | |
b8b69f4c | 743 | qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); |
0e21f183 | 744 | if (!kvm_irqchip_in_kernel()) { |
b8b69f4c | 745 | qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); |
0e21f183 | 746 | } |
1e575b66 | 747 | |
7cf3f8d2 | 748 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
f31985a7 | 749 | uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); |
1e575b66 EA |
750 | uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); |
751 | ||
03d72fa1 EA |
752 | nb_redist_regions = virt_gicv3_redist_region_count(vms); |
753 | ||
b8b69f4c | 754 | qdev_prop_set_uint32(vms->gic, "len-redist-region-count", |
03d72fa1 | 755 | nb_redist_regions); |
b8b69f4c | 756 | qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count); |
03d72fa1 | 757 | |
0e5c1c9a SM |
758 | if (!kvm_irqchip_in_kernel()) { |
759 | if (vms->tcg_its) { | |
760 | object_property_set_link(OBJECT(vms->gic), "sysmem", | |
761 | OBJECT(mem), &error_fatal); | |
762 | qdev_prop_set_bit(vms->gic, "has-lpi", true); | |
763 | } | |
764 | } | |
765 | ||
03d72fa1 EA |
766 | if (nb_redist_regions == 2) { |
767 | uint32_t redist1_capacity = | |
f31985a7 | 768 | virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); |
03d72fa1 | 769 | |
b8b69f4c | 770 | qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", |
03d72fa1 EA |
771 | MIN(smp_cpus - redist0_count, redist1_capacity)); |
772 | } | |
55ef3233 LM |
773 | } else { |
774 | if (!kvm_irqchip_in_kernel()) { | |
b8b69f4c | 775 | qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", |
55ef3233 LM |
776 | vms->virt); |
777 | } | |
1e575b66 | 778 | } |
b8b69f4c | 779 | gicbusdev = SYS_BUS_DEVICE(vms->gic); |
3c6ef471 | 780 | sysbus_realize_and_unref(gicbusdev, &error_fatal); |
c8ef2bda | 781 | sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); |
7cf3f8d2 | 782 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
c8ef2bda | 783 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); |
03d72fa1 | 784 | if (nb_redist_regions == 2) { |
bf424a12 EA |
785 | sysbus_mmio_map(gicbusdev, 2, |
786 | vms->memmap[VIRT_HIGH_GIC_REDIST2].base); | |
03d72fa1 | 787 | } |
b92ad394 | 788 | } else { |
c8ef2bda | 789 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); |
55ef3233 LM |
790 | if (vms->virt) { |
791 | sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); | |
792 | sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); | |
793 | } | |
b92ad394 | 794 | } |
64204743 | 795 | |
5454006a PM |
796 | /* Wire the outputs from each CPU's generic timer and the GICv3 |
797 | * maintenance interrupt signal to the appropriate GIC PPI inputs, | |
798 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | |
64204743 PM |
799 | */ |
800 | for (i = 0; i < smp_cpus; i++) { | |
801 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 802 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
803 | int irq; |
804 | /* Mapping from the output timer irq lines from the CPU to the | |
805 | * GIC PPI inputs we use for the virt board. | |
64204743 | 806 | */ |
a007b1f8 PM |
807 | const int timer_irq[] = { |
808 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
809 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
810 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
811 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
812 | }; | |
813 | ||
814 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
815 | qdev_connect_gpio_out(cpudev, irq, | |
b8b69f4c | 816 | qdev_get_gpio_in(vms->gic, |
a007b1f8 PM |
817 | ppibase + timer_irq[irq])); |
818 | } | |
64204743 | 819 | |
7cf3f8d2 | 820 | if (vms->gic_version != VIRT_GIC_VERSION_2) { |
b8b69f4c | 821 | qemu_irq irq = qdev_get_gpio_in(vms->gic, |
55ef3233 LM |
822 | ppibase + ARCH_GIC_MAINT_IRQ); |
823 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", | |
824 | 0, irq); | |
825 | } else if (vms->virt) { | |
b8b69f4c | 826 | qemu_irq irq = qdev_get_gpio_in(vms->gic, |
55ef3233 LM |
827 | ppibase + ARCH_GIC_MAINT_IRQ); |
828 | sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); | |
829 | } | |
830 | ||
07f48730 | 831 | qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, |
b8b69f4c | 832 | qdev_get_gpio_in(vms->gic, ppibase |
07f48730 | 833 | + VIRTUAL_PMU_IRQ)); |
5454006a | 834 | |
64204743 | 835 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
8e7b4ca0 GB |
836 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
837 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
5454006a PM |
838 | sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, |
839 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
840 | sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, | |
841 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
64204743 PM |
842 | } |
843 | ||
055a7f2b | 844 | fdt_add_gic_node(vms); |
bd204e63 | 845 | |
7cf3f8d2 | 846 | if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) { |
b8b69f4c | 847 | create_its(vms); |
5a389a9a | 848 | } else if (vms->gic_version == VIRT_GIC_VERSION_2) { |
b8b69f4c | 849 | create_v2m(vms); |
b92ad394 | 850 | } |
64204743 PM |
851 | } |
852 | ||
b8b69f4c | 853 | static void create_uart(const VirtMachineState *vms, int uart, |
0ec7b3e7 | 854 | MemoryRegion *mem, Chardev *chr) |
f5fdcd6e PM |
855 | { |
856 | char *nodename; | |
c8ef2bda PM |
857 | hwaddr base = vms->memmap[uart].base; |
858 | hwaddr size = vms->memmap[uart].size; | |
859 | int irq = vms->irqmap[uart]; | |
f5fdcd6e PM |
860 | const char compat[] = "arm,pl011\0arm,primecell"; |
861 | const char clocknames[] = "uartclk\0apb_pclk"; | |
3e80f690 | 862 | DeviceState *dev = qdev_new(TYPE_PL011); |
3df708eb | 863 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
a6487d37 | 864 | MachineState *ms = MACHINE(vms); |
f5fdcd6e | 865 | |
9bbbf649 | 866 | qdev_prop_set_chr(dev, "chardev", chr); |
3c6ef471 | 867 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
3df708eb PM |
868 | memory_region_add_subregion(mem, base, |
869 | sysbus_mmio_get_region(s, 0)); | |
b8b69f4c | 870 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); |
f5fdcd6e PM |
871 | |
872 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
a6487d37 | 873 | qemu_fdt_add_subnode(ms->fdt, nodename); |
f5fdcd6e | 874 | /* Note that we can't use setprop_string because of the embedded NUL */ |
a6487d37 | 875 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", |
f5fdcd6e | 876 | compat, sizeof(compat)); |
a6487d37 | 877 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
f5fdcd6e | 878 | 2, base, 2, size); |
a6487d37 | 879 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", |
f5fdcd6e | 880 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 881 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
a6487d37 | 882 | qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", |
c8ef2bda | 883 | vms->clock_phandle, vms->clock_phandle); |
a6487d37 | 884 | qemu_fdt_setprop(ms->fdt, nodename, "clock-names", |
f5fdcd6e | 885 | clocknames, sizeof(clocknames)); |
f022b8e9 | 886 | |
3df708eb | 887 | if (uart == VIRT_UART) { |
a6487d37 | 888 | qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); |
3df708eb PM |
889 | } else { |
890 | /* Mark as not usable by the normal world */ | |
a6487d37 AB |
891 | qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); |
892 | qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); | |
fb23d693 | 893 | |
a6487d37 | 894 | qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", |
fb23d693 | 895 | nodename); |
3df708eb PM |
896 | } |
897 | ||
f5fdcd6e PM |
898 | g_free(nodename); |
899 | } | |
900 | ||
b8b69f4c | 901 | static void create_rtc(const VirtMachineState *vms) |
6e411af9 PM |
902 | { |
903 | char *nodename; | |
c8ef2bda PM |
904 | hwaddr base = vms->memmap[VIRT_RTC].base; |
905 | hwaddr size = vms->memmap[VIRT_RTC].size; | |
906 | int irq = vms->irqmap[VIRT_RTC]; | |
6e411af9 | 907 | const char compat[] = "arm,pl031\0arm,primecell"; |
a6487d37 | 908 | MachineState *ms = MACHINE(vms); |
6e411af9 | 909 | |
b8b69f4c | 910 | sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); |
6e411af9 PM |
911 | |
912 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
a6487d37 AB |
913 | qemu_fdt_add_subnode(ms->fdt, nodename); |
914 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); | |
915 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
6e411af9 | 916 | 2, base, 2, size); |
a6487d37 | 917 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", |
6e411af9 | 918 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 919 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
a6487d37 AB |
920 | qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); |
921 | qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); | |
6e411af9 PM |
922 | g_free(nodename); |
923 | } | |
924 | ||
94f02c5e | 925 | static DeviceState *gpio_key_dev; |
4bedd849 SZ |
926 | static void virt_powerdown_req(Notifier *n, void *opaque) |
927 | { | |
1962f31b SK |
928 | VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier); |
929 | ||
930 | if (s->acpi_dev) { | |
931 | acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS); | |
932 | } else { | |
933 | /* use gpio Pin 3 for power button event */ | |
934 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); | |
935 | } | |
4bedd849 SZ |
936 | } |
937 | ||
a6487d37 | 938 | static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, |
e61bde40 MU |
939 | uint32_t phandle) |
940 | { | |
941 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, | |
942 | qdev_get_gpio_in(pl061_dev, 3)); | |
943 | ||
a6487d37 AB |
944 | qemu_fdt_add_subnode(fdt, "/gpio-keys"); |
945 | qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys"); | |
e61bde40 | 946 | |
a6487d37 AB |
947 | qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff"); |
948 | qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff", | |
e61bde40 | 949 | "label", "GPIO Key Poweroff"); |
a6487d37 | 950 | qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code", |
e61bde40 | 951 | KEY_POWER); |
a6487d37 | 952 | qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff", |
e61bde40 MU |
953 | "gpios", phandle, 3, 0); |
954 | } | |
955 | ||
daa726d9 MU |
956 | #define SECURE_GPIO_POWEROFF 0 |
957 | #define SECURE_GPIO_RESET 1 | |
958 | ||
a6487d37 | 959 | static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev, |
daa726d9 MU |
960 | uint32_t phandle) |
961 | { | |
962 | DeviceState *gpio_pwr_dev; | |
963 | ||
964 | /* gpio-pwr */ | |
965 | gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); | |
966 | ||
967 | /* connect secure pl061 to gpio-pwr */ | |
968 | qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET, | |
969 | qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0)); | |
970 | qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF, | |
971 | qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0)); | |
972 | ||
a6487d37 AB |
973 | qemu_fdt_add_subnode(fdt, "/gpio-poweroff"); |
974 | qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible", | |
daa726d9 | 975 | "gpio-poweroff"); |
a6487d37 | 976 | qemu_fdt_setprop_cells(fdt, "/gpio-poweroff", |
daa726d9 | 977 | "gpios", phandle, SECURE_GPIO_POWEROFF, 0); |
a6487d37 AB |
978 | qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled"); |
979 | qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status", | |
daa726d9 MU |
980 | "okay"); |
981 | ||
a6487d37 AB |
982 | qemu_fdt_add_subnode(fdt, "/gpio-restart"); |
983 | qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible", | |
daa726d9 | 984 | "gpio-restart"); |
a6487d37 | 985 | qemu_fdt_setprop_cells(fdt, "/gpio-restart", |
daa726d9 | 986 | "gpios", phandle, SECURE_GPIO_RESET, 0); |
a6487d37 AB |
987 | qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled"); |
988 | qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status", | |
daa726d9 MU |
989 | "okay"); |
990 | } | |
991 | ||
e61bde40 MU |
992 | static void create_gpio_devices(const VirtMachineState *vms, int gpio, |
993 | MemoryRegion *mem) | |
b0a3721e SZ |
994 | { |
995 | char *nodename; | |
94f02c5e | 996 | DeviceState *pl061_dev; |
e61bde40 MU |
997 | hwaddr base = vms->memmap[gpio].base; |
998 | hwaddr size = vms->memmap[gpio].size; | |
999 | int irq = vms->irqmap[gpio]; | |
b0a3721e | 1000 | const char compat[] = "arm,pl061\0arm,primecell"; |
e61bde40 | 1001 | SysBusDevice *s; |
a6487d37 | 1002 | MachineState *ms = MACHINE(vms); |
b0a3721e | 1003 | |
e61bde40 | 1004 | pl061_dev = qdev_new("pl061"); |
d6773a1f PM |
1005 | /* Pull lines down to 0 if not driven by the PL061 */ |
1006 | qdev_prop_set_uint32(pl061_dev, "pullups", 0); | |
1007 | qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); | |
e61bde40 MU |
1008 | s = SYS_BUS_DEVICE(pl061_dev); |
1009 | sysbus_realize_and_unref(s, &error_fatal); | |
1010 | memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); | |
1011 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); | |
b0a3721e | 1012 | |
a6487d37 | 1013 | uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); |
b0a3721e | 1014 | nodename = g_strdup_printf("/pl061@%" PRIx64, base); |
a6487d37 AB |
1015 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1016 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
b0a3721e | 1017 | 2, base, 2, size); |
a6487d37 AB |
1018 | qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); |
1019 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); | |
1020 | qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); | |
1021 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", | |
b0a3721e SZ |
1022 | GIC_FDT_IRQ_TYPE_SPI, irq, |
1023 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
a6487d37 AB |
1024 | qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); |
1025 | qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); | |
1026 | qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); | |
3e6ebb64 | 1027 | |
daa726d9 MU |
1028 | if (gpio != VIRT_GPIO) { |
1029 | /* Mark as not usable by the normal world */ | |
a6487d37 AB |
1030 | qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); |
1031 | qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); | |
daa726d9 | 1032 | } |
b0a3721e | 1033 | g_free(nodename); |
e61bde40 MU |
1034 | |
1035 | /* Child gpio devices */ | |
daa726d9 | 1036 | if (gpio == VIRT_GPIO) { |
a6487d37 | 1037 | create_gpio_keys(ms->fdt, pl061_dev, phandle); |
daa726d9 | 1038 | } else { |
a6487d37 | 1039 | create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); |
daa726d9 | 1040 | } |
b0a3721e SZ |
1041 | } |
1042 | ||
b8b69f4c | 1043 | static void create_virtio_devices(const VirtMachineState *vms) |
f5fdcd6e PM |
1044 | { |
1045 | int i; | |
c8ef2bda | 1046 | hwaddr size = vms->memmap[VIRT_MMIO].size; |
a6487d37 | 1047 | MachineState *ms = MACHINE(vms); |
f5fdcd6e | 1048 | |
587078f0 LE |
1049 | /* We create the transports in forwards order. Since qbus_realize() |
1050 | * prepends (not appends) new child buses, the incrementing loop below will | |
1051 | * create a list of virtio-mmio buses with decreasing base addresses. | |
1052 | * | |
1053 | * When a -device option is processed from the command line, | |
1054 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
1055 | * order. The upshot is that -device options in increasing command line | |
1056 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
1057 | * | |
1058 | * When this code was originally written, that arrangement ensured that the | |
1059 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
1060 | * the first -device on the command line. (The end-to-end order is a | |
1061 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
1062 | * guest kernel's name-to-address assignment strategy.) | |
1063 | * | |
1064 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
1065 | * the message, if not necessarily the code, of commit 70161ff336. | |
1066 | * Therefore the loop now establishes the inverse of the original intent. | |
1067 | * | |
1068 | * Unfortunately, we can't counteract the kernel change by reversing the | |
1069 | * loop; it would break existing command lines. | |
1070 | * | |
1071 | * In any case, the kernel makes no guarantee about the stability of | |
1072 | * enumeration order of virtio devices (as demonstrated by it changing | |
1073 | * between kernel versions). For reliable and stable identification | |
1074 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
1075 | */ |
1076 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
c8ef2bda PM |
1077 | int irq = vms->irqmap[VIRT_MMIO] + i; |
1078 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e | 1079 | |
b8b69f4c PMD |
1080 | sysbus_create_simple("virtio-mmio", base, |
1081 | qdev_get_gpio_in(vms->gic, irq)); | |
f5fdcd6e PM |
1082 | } |
1083 | ||
587078f0 LE |
1084 | /* We add dtb nodes in reverse order so that they appear in the finished |
1085 | * device tree lowest address first. | |
1086 | * | |
1087 | * Note that this mapping is independent of the loop above. The previous | |
1088 | * loop influences virtio device to virtio transport assignment, whereas | |
1089 | * this loop controls how virtio transports are laid out in the dtb. | |
1090 | */ | |
f5fdcd6e PM |
1091 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
1092 | char *nodename; | |
c8ef2bda PM |
1093 | int irq = vms->irqmap[VIRT_MMIO] + i; |
1094 | hwaddr base = vms->memmap[VIRT_MMIO].base + i * size; | |
f5fdcd6e PM |
1095 | |
1096 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
a6487d37 AB |
1097 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1098 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
5a4348d1 | 1099 | "compatible", "virtio,mmio"); |
a6487d37 | 1100 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
5a4348d1 | 1101 | 2, base, 2, size); |
a6487d37 | 1102 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", |
5a4348d1 PC |
1103 | GIC_FDT_IRQ_TYPE_SPI, irq, |
1104 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
a6487d37 | 1105 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
f5fdcd6e PM |
1106 | g_free(nodename); |
1107 | } | |
1108 | } | |
1109 | ||
e0561e60 MA |
1110 | #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) |
1111 | ||
1112 | static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, | |
1113 | const char *name, | |
1114 | const char *alias_prop_name) | |
acf82361 | 1115 | { |
e0561e60 MA |
1116 | /* |
1117 | * Create a single flash device. We use the same parameters as | |
1118 | * the flash devices on the Versatile Express board. | |
acf82361 | 1119 | */ |
df707969 | 1120 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
acf82361 | 1121 | |
e0561e60 | 1122 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); |
acf82361 PM |
1123 | qdev_prop_set_uint8(dev, "width", 4); |
1124 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 1125 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
1126 | qdev_prop_set_uint16(dev, "id0", 0x89); |
1127 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
1128 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
1129 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
1130 | qdev_prop_set_string(dev, "name", name); | |
d2623129 | 1131 | object_property_add_child(OBJECT(vms), name, OBJECT(dev)); |
e0561e60 | 1132 | object_property_add_alias(OBJECT(vms), alias_prop_name, |
d2623129 | 1133 | OBJECT(dev), "drive"); |
e0561e60 MA |
1134 | return PFLASH_CFI01(dev); |
1135 | } | |
acf82361 | 1136 | |
e0561e60 MA |
1137 | static void virt_flash_create(VirtMachineState *vms) |
1138 | { | |
1139 | vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0"); | |
1140 | vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); | |
1141 | } | |
acf82361 | 1142 | |
e0561e60 MA |
1143 | static void virt_flash_map1(PFlashCFI01 *flash, |
1144 | hwaddr base, hwaddr size, | |
1145 | MemoryRegion *sysmem) | |
1146 | { | |
1147 | DeviceState *dev = DEVICE(flash); | |
acf82361 | 1148 | |
4cdd0a77 | 1149 | assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); |
e0561e60 MA |
1150 | assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); |
1151 | qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); | |
3c6ef471 | 1152 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
e0561e60 MA |
1153 | |
1154 | memory_region_add_subregion(sysmem, base, | |
1155 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), | |
1156 | 0)); | |
16f4a8dc PM |
1157 | } |
1158 | ||
e0561e60 MA |
1159 | static void virt_flash_map(VirtMachineState *vms, |
1160 | MemoryRegion *sysmem, | |
1161 | MemoryRegion *secure_sysmem) | |
16f4a8dc | 1162 | { |
e0561e60 MA |
1163 | /* |
1164 | * Map two flash devices to fill the VIRT_FLASH space in the memmap. | |
738a5d9f PM |
1165 | * sysmem is the system memory space. secure_sysmem is the secure view |
1166 | * of the system, and the first flash device should be made visible only | |
1167 | * there. The second flash device is visible to both secure and nonsecure. | |
1168 | * If sysmem == secure_sysmem this means there is no separate Secure | |
1169 | * address space and both flash devices are generally visible. | |
16f4a8dc | 1170 | */ |
c8ef2bda PM |
1171 | hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; |
1172 | hwaddr flashbase = vms->memmap[VIRT_FLASH].base; | |
acf82361 | 1173 | |
e0561e60 MA |
1174 | virt_flash_map1(vms->flash[0], flashbase, flashsize, |
1175 | secure_sysmem); | |
1176 | virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, | |
1177 | sysmem); | |
1178 | } | |
1179 | ||
1180 | static void virt_flash_fdt(VirtMachineState *vms, | |
1181 | MemoryRegion *sysmem, | |
1182 | MemoryRegion *secure_sysmem) | |
1183 | { | |
1184 | hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2; | |
1185 | hwaddr flashbase = vms->memmap[VIRT_FLASH].base; | |
a6487d37 | 1186 | MachineState *ms = MACHINE(vms); |
e0561e60 | 1187 | char *nodename; |
acf82361 | 1188 | |
738a5d9f PM |
1189 | if (sysmem == secure_sysmem) { |
1190 | /* Report both flash devices as a single node in the DT */ | |
1191 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
a6487d37 AB |
1192 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1193 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); | |
1194 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
738a5d9f PM |
1195 | 2, flashbase, 2, flashsize, |
1196 | 2, flashbase + flashsize, 2, flashsize); | |
a6487d37 | 1197 | qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
1198 | g_free(nodename); |
1199 | } else { | |
e0561e60 MA |
1200 | /* |
1201 | * Report the devices as separate nodes so we can mark one as | |
738a5d9f PM |
1202 | * only visible to the secure world. |
1203 | */ | |
1204 | nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); | |
a6487d37 AB |
1205 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1206 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); | |
1207 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
738a5d9f | 1208 | 2, flashbase, 2, flashsize); |
a6487d37 AB |
1209 | qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); |
1210 | qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); | |
1211 | qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); | |
738a5d9f PM |
1212 | g_free(nodename); |
1213 | ||
e8ca920f | 1214 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize); |
a6487d37 AB |
1215 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1216 | qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); | |
1217 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", | |
738a5d9f | 1218 | 2, flashbase + flashsize, 2, flashsize); |
a6487d37 | 1219 | qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); |
738a5d9f PM |
1220 | g_free(nodename); |
1221 | } | |
acf82361 PM |
1222 | } |
1223 | ||
e0561e60 MA |
1224 | static bool virt_firmware_init(VirtMachineState *vms, |
1225 | MemoryRegion *sysmem, | |
1226 | MemoryRegion *secure_sysmem) | |
1227 | { | |
1228 | int i; | |
0ad3b5d3 | 1229 | const char *bios_name; |
e0561e60 MA |
1230 | BlockBackend *pflash_blk0; |
1231 | ||
1232 | /* Map legacy -drive if=pflash to machine properties */ | |
1233 | for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { | |
1234 | pflash_cfi01_legacy_drive(vms->flash[i], | |
1235 | drive_get(IF_PFLASH, 0, i)); | |
1236 | } | |
1237 | ||
1238 | virt_flash_map(vms, sysmem, secure_sysmem); | |
1239 | ||
1240 | pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); | |
1241 | ||
0ad3b5d3 | 1242 | bios_name = MACHINE(vms)->firmware; |
e0561e60 MA |
1243 | if (bios_name) { |
1244 | char *fname; | |
1245 | MemoryRegion *mr; | |
1246 | int image_size; | |
1247 | ||
1248 | if (pflash_blk0) { | |
1249 | error_report("The contents of the first flash device may be " | |
1250 | "specified with -bios or with -drive if=pflash... " | |
1251 | "but you cannot use both options at once"); | |
1252 | exit(1); | |
1253 | } | |
1254 | ||
1255 | /* Fall back to -bios */ | |
1256 | ||
1257 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
1258 | if (!fname) { | |
1259 | error_report("Could not find ROM image '%s'", bios_name); | |
1260 | exit(1); | |
1261 | } | |
1262 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0); | |
1263 | image_size = load_image_mr(fname, mr); | |
1264 | g_free(fname); | |
1265 | if (image_size < 0) { | |
1266 | error_report("Could not load ROM image '%s'", bios_name); | |
1267 | exit(1); | |
1268 | } | |
1269 | } | |
1270 | ||
1271 | return pflash_blk0 || bios_name; | |
1272 | } | |
1273 | ||
af1f60a4 | 1274 | static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as) |
578f3c7b | 1275 | { |
cc7d44c2 | 1276 | MachineState *ms = MACHINE(vms); |
c8ef2bda PM |
1277 | hwaddr base = vms->memmap[VIRT_FW_CFG].base; |
1278 | hwaddr size = vms->memmap[VIRT_FW_CFG].size; | |
5836d168 | 1279 | FWCfgState *fw_cfg; |
578f3c7b LE |
1280 | char *nodename; |
1281 | ||
5836d168 | 1282 | fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); |
cc7d44c2 | 1283 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); |
578f3c7b LE |
1284 | |
1285 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
a6487d37 AB |
1286 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1287 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
578f3c7b | 1288 | "compatible", "qemu,fw-cfg-mmio"); |
a6487d37 | 1289 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
578f3c7b | 1290 | 2, base, 2, size); |
a6487d37 | 1291 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
578f3c7b | 1292 | g_free(nodename); |
af1f60a4 | 1293 | return fw_cfg; |
578f3c7b LE |
1294 | } |
1295 | ||
a6487d37 | 1296 | static void create_pcie_irq_map(const MachineState *ms, |
9ac4ef77 | 1297 | uint32_t gic_phandle, |
4ab29b82 AG |
1298 | int first_irq, const char *nodename) |
1299 | { | |
1300 | int devfn, pin; | |
dfd90a87 | 1301 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
1302 | uint32_t *irq_map = full_irq_map; |
1303 | ||
1304 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
1305 | for (pin = 0; pin < 4; pin++) { | |
1306 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
1307 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
1308 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
1309 | int i; | |
1310 | ||
1311 | uint32_t map[] = { | |
1312 | devfn << 8, 0, 0, /* devfn */ | |
1313 | pin + 1, /* PCI pin */ | |
dfd90a87 | 1314 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
1315 | |
1316 | /* Convert map to big endian */ | |
dfd90a87 | 1317 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
1318 | irq_map[i] = cpu_to_be32(map[i]); |
1319 | } | |
dfd90a87 | 1320 | irq_map += 10; |
4ab29b82 AG |
1321 | } |
1322 | } | |
1323 | ||
a6487d37 | 1324 | qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", |
4ab29b82 AG |
1325 | full_irq_map, sizeof(full_irq_map)); |
1326 | ||
a6487d37 | 1327 | qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", |
4934e479 PMD |
1328 | cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */ |
1329 | 0, 0, | |
4ab29b82 AG |
1330 | 0x7 /* PCI irq */); |
1331 | } | |
1332 | ||
b8b69f4c | 1333 | static void create_smmu(const VirtMachineState *vms, |
584105ea PM |
1334 | PCIBus *bus) |
1335 | { | |
1336 | char *node; | |
1337 | const char compat[] = "arm,smmu-v3"; | |
1338 | int irq = vms->irqmap[VIRT_SMMU]; | |
1339 | int i; | |
1340 | hwaddr base = vms->memmap[VIRT_SMMU].base; | |
1341 | hwaddr size = vms->memmap[VIRT_SMMU].size; | |
1342 | const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror"; | |
1343 | DeviceState *dev; | |
a6487d37 | 1344 | MachineState *ms = MACHINE(vms); |
584105ea PM |
1345 | |
1346 | if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) { | |
1347 | return; | |
1348 | } | |
1349 | ||
a431ab0e | 1350 | dev = qdev_new(TYPE_ARM_SMMUV3); |
584105ea | 1351 | |
5325cc34 | 1352 | object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), |
584105ea | 1353 | &error_abort); |
3c6ef471 | 1354 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
584105ea PM |
1355 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
1356 | for (i = 0; i < NUM_SMMU_IRQS; i++) { | |
b8b69f4c PMD |
1357 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
1358 | qdev_get_gpio_in(vms->gic, irq + i)); | |
584105ea PM |
1359 | } |
1360 | ||
1361 | node = g_strdup_printf("/smmuv3@%" PRIx64, base); | |
a6487d37 AB |
1362 | qemu_fdt_add_subnode(ms->fdt, node); |
1363 | qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); | |
1364 | qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); | |
584105ea | 1365 | |
a6487d37 | 1366 | qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", |
584105ea PM |
1367 | GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, |
1368 | GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
1369 | GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, | |
1370 | GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
1371 | ||
a6487d37 | 1372 | qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, |
584105ea PM |
1373 | sizeof(irq_names)); |
1374 | ||
a6487d37 | 1375 | qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); |
584105ea | 1376 | |
a6487d37 | 1377 | qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); |
584105ea | 1378 | |
a6487d37 | 1379 | qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); |
584105ea PM |
1380 | g_free(node); |
1381 | } | |
1382 | ||
0fbddcec | 1383 | static void create_virtio_iommu_dt_bindings(VirtMachineState *vms) |
70e89132 | 1384 | { |
7cd5d384 | 1385 | const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; |
70e89132 | 1386 | uint16_t bdf = vms->virtio_iommu_bdf; |
a6487d37 | 1387 | MachineState *ms = MACHINE(vms); |
70e89132 EA |
1388 | char *node; |
1389 | ||
a6487d37 | 1390 | vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); |
70e89132 | 1391 | |
7cd5d384 JPB |
1392 | node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename, |
1393 | PCI_SLOT(bdf), PCI_FUNC(bdf)); | |
a6487d37 AB |
1394 | qemu_fdt_add_subnode(ms->fdt, node); |
1395 | qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); | |
1396 | qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", | |
70e89132 EA |
1397 | 1, bdf << 8, 1, 0, 1, 0, |
1398 | 1, 0, 1, 0); | |
1399 | ||
a6487d37 AB |
1400 | qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); |
1401 | qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); | |
70e89132 EA |
1402 | g_free(node); |
1403 | ||
a6487d37 | 1404 | qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", |
70e89132 EA |
1405 | 0x0, vms->iommu_phandle, 0x0, bdf, |
1406 | bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); | |
1407 | } | |
1408 | ||
b8b69f4c | 1409 | static void create_pcie(VirtMachineState *vms) |
4ab29b82 | 1410 | { |
c8ef2bda PM |
1411 | hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; |
1412 | hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; | |
bf424a12 EA |
1413 | hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; |
1414 | hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; | |
c8ef2bda PM |
1415 | hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; |
1416 | hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; | |
601d626d | 1417 | hwaddr base_ecam, size_ecam; |
6a1f001b | 1418 | hwaddr base = base_mmio; |
601d626d | 1419 | int nr_pcie_buses; |
c8ef2bda | 1420 | int irq = vms->irqmap[VIRT_PCIE]; |
4ab29b82 AG |
1421 | MemoryRegion *mmio_alias; |
1422 | MemoryRegion *mmio_reg; | |
1423 | MemoryRegion *ecam_alias; | |
1424 | MemoryRegion *ecam_reg; | |
1425 | DeviceState *dev; | |
1426 | char *nodename; | |
601d626d | 1427 | int i, ecam_id; |
fea9b3ca | 1428 | PCIHostState *pci; |
a6487d37 | 1429 | MachineState *ms = MACHINE(vms); |
50989d04 | 1430 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
4ab29b82 | 1431 | |
3e80f690 | 1432 | dev = qdev_new(TYPE_GPEX_HOST); |
3c6ef471 | 1433 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
4ab29b82 | 1434 | |
601d626d EA |
1435 | ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); |
1436 | base_ecam = vms->memmap[ecam_id].base; | |
1437 | size_ecam = vms->memmap[ecam_id].size; | |
1438 | nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
4ab29b82 AG |
1439 | /* Map only the first size_ecam bytes of ECAM space */ |
1440 | ecam_alias = g_new0(MemoryRegion, 1); | |
1441 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
1442 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
1443 | ecam_reg, 0, size_ecam); | |
1444 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
1445 | ||
1446 | /* Map the MMIO window into system address space so as to expose | |
1447 | * the section of PCI MMIO space which starts at the same base address | |
1448 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
1449 | * the window). | |
1450 | */ | |
1451 | mmio_alias = g_new0(MemoryRegion, 1); | |
1452 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
1453 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
1454 | mmio_reg, base_mmio, size_mmio); | |
1455 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
1456 | ||
c8f008c4 | 1457 | if (vms->highmem_mmio) { |
5125f9cd PF |
1458 | /* Map high MMIO space */ |
1459 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
1460 | ||
1461 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
1462 | mmio_reg, base_mmio_high, size_mmio_high); | |
1463 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
1464 | high_mmio_alias); | |
1465 | } | |
1466 | ||
4ab29b82 | 1467 | /* Map IO port space */ |
6a1f001b | 1468 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
1469 | |
1470 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
b8b69f4c PMD |
1471 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
1472 | qdev_get_gpio_in(vms->gic, irq + i)); | |
c9bb8e16 | 1473 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
4ab29b82 AG |
1474 | } |
1475 | ||
fea9b3ca | 1476 | pci = PCI_HOST_BRIDGE(dev); |
6d7a8548 | 1477 | pci->bypass_iommu = vms->default_bus_bypass_iommu; |
09fad167 JC |
1478 | vms->bus = pci->bus; |
1479 | if (vms->bus) { | |
fea9b3ca | 1480 | for (i = 0; i < nb_nics; i++) { |
b697a489 | 1481 | pci_nic_init_nofail(&nd_table[i], pci->bus, mc->default_nic, NULL); |
fea9b3ca AK |
1482 | } |
1483 | } | |
1484 | ||
70e89132 | 1485 | nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
a6487d37 AB |
1486 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1487 | qemu_fdt_setprop_string(ms->fdt, nodename, | |
4ab29b82 | 1488 | "compatible", "pci-host-ecam-generic"); |
a6487d37 AB |
1489 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); |
1490 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); | |
1491 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); | |
1492 | qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); | |
1493 | qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, | |
4ab29b82 | 1494 | nr_pcie_buses - 1); |
a6487d37 | 1495 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
4ab29b82 | 1496 | |
c8ef2bda | 1497 | if (vms->msi_phandle) { |
6b2f3ac9 JPB |
1498 | qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", |
1499 | 0, vms->msi_phandle, 0, 0x10000); | |
b92ad394 | 1500 | } |
bd204e63 | 1501 | |
a6487d37 | 1502 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
4ab29b82 | 1503 | 2, base_ecam, 2, size_ecam); |
5125f9cd | 1504 | |
c8f008c4 | 1505 | if (vms->highmem_mmio) { |
a6487d37 | 1506 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", |
5125f9cd PF |
1507 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1508 | 2, base_pio, 2, size_pio, | |
1509 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1510 | 2, base_mmio, 2, size_mmio, | |
1511 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
1512 | 2, base_mmio_high, | |
1513 | 2, base_mmio_high, 2, size_mmio_high); | |
1514 | } else { | |
a6487d37 | 1515 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", |
5125f9cd PF |
1516 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
1517 | 2, base_pio, 2, size_pio, | |
1518 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1519 | 2, base_mmio, 2, size_mmio); | |
1520 | } | |
4ab29b82 | 1521 | |
a6487d37 AB |
1522 | qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); |
1523 | create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); | |
4ab29b82 | 1524 | |
584105ea | 1525 | if (vms->iommu) { |
a6487d37 | 1526 | vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); |
584105ea | 1527 | |
70e89132 EA |
1528 | switch (vms->iommu) { |
1529 | case VIRT_IOMMU_SMMUV3: | |
09fad167 | 1530 | create_smmu(vms, vms->bus); |
a6487d37 | 1531 | qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", |
70e89132 EA |
1532 | 0x0, vms->iommu_phandle, 0x0, 0x10000); |
1533 | break; | |
1534 | default: | |
1535 | g_assert_not_reached(); | |
1536 | } | |
584105ea | 1537 | } |
4ab29b82 AG |
1538 | } |
1539 | ||
b8b69f4c | 1540 | static void create_platform_bus(VirtMachineState *vms) |
5f7a5a0e EA |
1541 | { |
1542 | DeviceState *dev; | |
1543 | SysBusDevice *s; | |
1544 | int i; | |
5f7a5a0e EA |
1545 | MemoryRegion *sysmem = get_system_memory(); |
1546 | ||
3e80f690 | 1547 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
163f3847 | 1548 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); |
3b77f6c3 IM |
1549 | qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); |
1550 | qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size); | |
3c6ef471 | 1551 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
a3fc8396 | 1552 | vms->platform_bus_dev = dev; |
5f7a5a0e | 1553 | |
3b77f6c3 IM |
1554 | s = SYS_BUS_DEVICE(dev); |
1555 | for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) { | |
b8b69f4c PMD |
1556 | int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i; |
1557 | sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); | |
5f7a5a0e EA |
1558 | } |
1559 | ||
1560 | memory_region_add_subregion(sysmem, | |
3b77f6c3 | 1561 | vms->memmap[VIRT_PLATFORM_BUS].base, |
5f7a5a0e EA |
1562 | sysbus_mmio_get_region(s, 0)); |
1563 | } | |
1564 | ||
8bce44a2 RH |
1565 | static void create_tag_ram(MemoryRegion *tag_sysmem, |
1566 | hwaddr base, hwaddr size, | |
1567 | const char *name) | |
1568 | { | |
1569 | MemoryRegion *tagram = g_new(MemoryRegion, 1); | |
1570 | ||
1571 | memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal); | |
1572 | memory_region_add_subregion(tag_sysmem, base / 32, tagram); | |
1573 | } | |
1574 | ||
c8ef2bda | 1575 | static void create_secure_ram(VirtMachineState *vms, |
8bce44a2 RH |
1576 | MemoryRegion *secure_sysmem, |
1577 | MemoryRegion *secure_tag_sysmem) | |
83ec1923 PM |
1578 | { |
1579 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
1580 | char *nodename; | |
c8ef2bda PM |
1581 | hwaddr base = vms->memmap[VIRT_SECURE_MEM].base; |
1582 | hwaddr size = vms->memmap[VIRT_SECURE_MEM].size; | |
a6487d37 | 1583 | MachineState *ms = MACHINE(vms); |
83ec1923 | 1584 | |
98a99ce0 PM |
1585 | memory_region_init_ram(secram, NULL, "virt.secure-ram", size, |
1586 | &error_fatal); | |
83ec1923 PM |
1587 | memory_region_add_subregion(secure_sysmem, base, secram); |
1588 | ||
1589 | nodename = g_strdup_printf("/secram@%" PRIx64, base); | |
a6487d37 AB |
1590 | qemu_fdt_add_subnode(ms->fdt, nodename); |
1591 | qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); | |
1592 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); | |
1593 | qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); | |
1594 | qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); | |
83ec1923 | 1595 | |
8bce44a2 RH |
1596 | if (secure_tag_sysmem) { |
1597 | create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag"); | |
1598 | } | |
1599 | ||
83ec1923 PM |
1600 | g_free(nodename); |
1601 | } | |
1602 | ||
f5fdcd6e PM |
1603 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
1604 | { | |
9ac4ef77 PM |
1605 | const VirtMachineState *board = container_of(binfo, VirtMachineState, |
1606 | bootinfo); | |
a6487d37 AB |
1607 | MachineState *ms = MACHINE(board); |
1608 | ||
f5fdcd6e PM |
1609 | |
1610 | *fdt_size = board->fdt_size; | |
a6487d37 | 1611 | return ms->fdt; |
f5fdcd6e PM |
1612 | } |
1613 | ||
e9a8e474 | 1614 | static void virt_build_smbios(VirtMachineState *vms) |
c30e1565 | 1615 | { |
dfadc3bf | 1616 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
0a0044b1 | 1617 | MachineState *ms = MACHINE(vms); |
dfadc3bf | 1618 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
c30e1565 WH |
1619 | uint8_t *smbios_tables, *smbios_anchor; |
1620 | size_t smbios_tables_len, smbios_anchor_len; | |
0a0044b1 | 1621 | struct smbios_phys_mem_area mem_array; |
bab27ea2 | 1622 | const char *product = "QEMU Virtual Machine"; |
c30e1565 | 1623 | |
bab27ea2 AJ |
1624 | if (kvm_enabled()) { |
1625 | product = "KVM Virtual Machine"; | |
1626 | } | |
1627 | ||
1628 | smbios_set_defaults("QEMU", product, | |
dfadc3bf | 1629 | vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, |
10be11d0 | 1630 | true, SMBIOS_ENTRY_POINT_TYPE_64); |
c30e1565 | 1631 | |
0a0044b1 MC |
1632 | /* build the array of physical mem area from base_memmap */ |
1633 | mem_array.address = vms->memmap[VIRT_MEM].base; | |
1634 | mem_array.length = ms->ram_size; | |
1635 | ||
1636 | smbios_get_tables(ms, &mem_array, 1, | |
05dfb447 VB |
1637 | &smbios_tables, &smbios_tables_len, |
1638 | &smbios_anchor, &smbios_anchor_len, | |
1639 | &error_fatal); | |
c30e1565 WH |
1640 | |
1641 | if (smbios_anchor) { | |
af1f60a4 | 1642 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables", |
c30e1565 | 1643 | smbios_tables, smbios_tables_len); |
af1f60a4 | 1644 | fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor", |
c30e1565 WH |
1645 | smbios_anchor, smbios_anchor_len); |
1646 | } | |
1647 | } | |
1648 | ||
d7c2e2db | 1649 | static |
054f4dc9 | 1650 | void virt_machine_done(Notifier *notifier, void *data) |
d7c2e2db | 1651 | { |
054f4dc9 AJ |
1652 | VirtMachineState *vms = container_of(notifier, VirtMachineState, |
1653 | machine_done); | |
2744ece8 | 1654 | MachineState *ms = MACHINE(vms); |
3b77f6c3 IM |
1655 | ARMCPU *cpu = ARM_CPU(first_cpu); |
1656 | struct arm_boot_info *info = &vms->bootinfo; | |
1657 | AddressSpace *as = arm_boot_address_space(cpu, info); | |
1658 | ||
1659 | /* | |
1660 | * If the user provided a dtb, we assume the dynamic sysbus nodes | |
1661 | * already are integrated there. This corresponds to a use case where | |
1662 | * the dynamic sysbus nodes are complex and their generation is not yet | |
1663 | * supported. In that case the user can take charge of the guest dt | |
1664 | * while qemu takes charge of the qom stuff. | |
1665 | */ | |
1666 | if (info->dtb_filename == NULL) { | |
a6487d37 | 1667 | platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", |
3b77f6c3 IM |
1668 | vms->memmap[VIRT_PLATFORM_BUS].base, |
1669 | vms->memmap[VIRT_PLATFORM_BUS].size, | |
1670 | vms->irqmap[VIRT_PLATFORM_BUS]); | |
1671 | } | |
2744ece8 | 1672 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { |
3b77f6c3 IM |
1673 | exit(1); |
1674 | } | |
054f4dc9 | 1675 | |
09fad167 JC |
1676 | fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); |
1677 | ||
e9a8e474 AJ |
1678 | virt_acpi_setup(vms); |
1679 | virt_build_smbios(vms); | |
d7c2e2db SZ |
1680 | } |
1681 | ||
46de5913 IM |
1682 | static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) |
1683 | { | |
1684 | uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; | |
1685 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | |
1686 | ||
1687 | if (!vmc->disallow_affinity_adjustment) { | |
1688 | /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the | |
1689 | * GIC's target-list limitations. 32-bit KVM hosts currently | |
1690 | * always create clusters of 4 CPUs, but that is expected to | |
1691 | * change when they gain support for gicv3. When KVM is enabled | |
1692 | * it will override the changes we make here, therefore our | |
1693 | * purposes are to make TCG consistent (with 64-bit KVM hosts) | |
1694 | * and to improve SGI efficiency. | |
1695 | */ | |
7cf3f8d2 | 1696 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
46de5913 | 1697 | clustersz = GIC_TARGETLIST_BITS; |
7cf3f8d2 PM |
1698 | } else { |
1699 | clustersz = GICV3_TARGETLIST_BITS; | |
46de5913 IM |
1700 | } |
1701 | } | |
1702 | return arm_cpu_mp_affinity(idx, clustersz); | |
1703 | } | |
1704 | ||
a5cb1350 GS |
1705 | static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, |
1706 | int index) | |
1707 | { | |
1708 | bool *enabled_array[] = { | |
1709 | &vms->highmem_redists, | |
1710 | &vms->highmem_ecam, | |
1711 | &vms->highmem_mmio, | |
1712 | }; | |
1713 | ||
1714 | assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == | |
1715 | ARRAY_SIZE(enabled_array)); | |
1716 | assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); | |
1717 | ||
1718 | return enabled_array[index - VIRT_LOWMEMMAP_LAST]; | |
1719 | } | |
1720 | ||
4af6b6ed GS |
1721 | static void virt_set_high_memmap(VirtMachineState *vms, |
1722 | hwaddr base, int pa_bits) | |
1723 | { | |
fa245799 | 1724 | hwaddr region_base, region_size; |
a5cb1350 | 1725 | bool *region_enabled, fits; |
4af6b6ed GS |
1726 | int i; |
1727 | ||
1728 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | |
a5cb1350 | 1729 | region_enabled = virt_get_high_memmap_enabled(vms, i); |
fa245799 | 1730 | region_base = ROUND_UP(base, extended_memmap[i].size); |
370bea9d | 1731 | region_size = extended_memmap[i].size; |
4af6b6ed | 1732 | |
fa245799 | 1733 | vms->memmap[i].base = region_base; |
370bea9d | 1734 | vms->memmap[i].size = region_size; |
4af6b6ed GS |
1735 | |
1736 | /* | |
4a4ff9ed GS |
1737 | * Check each device to see if it fits in the PA space, |
1738 | * moving highest_gpa as we go. For compatibility, move | |
1739 | * highest_gpa for disabled fitting devices as well, if | |
1740 | * the compact layout has been disabled. | |
4af6b6ed GS |
1741 | * |
1742 | * For each device that doesn't fit, disable it. | |
1743 | */ | |
fa245799 | 1744 | fits = (region_base + region_size) <= BIT_ULL(pa_bits); |
4a4ff9ed GS |
1745 | *region_enabled &= fits; |
1746 | if (vms->highmem_compact && !*region_enabled) { | |
1747 | continue; | |
4af6b6ed GS |
1748 | } |
1749 | ||
fa245799 | 1750 | base = region_base + region_size; |
4a4ff9ed GS |
1751 | if (fits) { |
1752 | vms->highest_gpa = base - 1; | |
1753 | } | |
4af6b6ed GS |
1754 | } |
1755 | } | |
1756 | ||
3715c251 | 1757 | static void virt_set_memmap(VirtMachineState *vms, int pa_bits) |
350a9c9e | 1758 | { |
957e32cf | 1759 | MachineState *ms = MACHINE(vms); |
0152b169 | 1760 | hwaddr base, device_memory_base, device_memory_size, memtop; |
350a9c9e EA |
1761 | int i; |
1762 | ||
1763 | vms->memmap = extended_memmap; | |
1764 | ||
1765 | for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { | |
1766 | vms->memmap[i] = base_memmap[i]; | |
1767 | } | |
1768 | ||
957e32cf EA |
1769 | if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { |
1770 | error_report("unsupported number of memory slots: %"PRIu64, | |
1771 | ms->ram_slots); | |
1772 | exit(EXIT_FAILURE); | |
1773 | } | |
1774 | ||
3715c251 MZ |
1775 | /* |
1776 | * !highmem is exactly the same as limiting the PA space to 32bit, | |
1777 | * irrespective of the underlying capabilities of the HW. | |
1778 | */ | |
1779 | if (!vms->highmem) { | |
1780 | pa_bits = 32; | |
1781 | } | |
1782 | ||
957e32cf EA |
1783 | /* |
1784 | * We compute the base of the high IO region depending on the | |
1785 | * amount of initial and device memory. The device memory start/size | |
1786 | * is aligned on 1GiB. We never put the high IO region below 256GiB | |
1787 | * so that if maxram_size is < 255GiB we keep the legacy memory map. | |
1788 | * The device region size assumes 1GiB page max alignment per slot. | |
1789 | */ | |
1790 | device_memory_base = | |
1791 | ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); | |
1792 | device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; | |
1793 | ||
1794 | /* Base address of the high IO region */ | |
0152b169 | 1795 | memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); |
3715c251 MZ |
1796 | if (memtop > BIT_ULL(pa_bits)) { |
1797 | error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", | |
1798 | pa_bits, memtop - BIT_ULL(pa_bits)); | |
0152b169 MZ |
1799 | exit(EXIT_FAILURE); |
1800 | } | |
957e32cf EA |
1801 | if (base < device_memory_base) { |
1802 | error_report("maxmem/slots too huge"); | |
1803 | exit(EXIT_FAILURE); | |
1804 | } | |
1805 | if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { | |
1806 | base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; | |
1807 | } | |
350a9c9e | 1808 | |
d9afe24c MZ |
1809 | /* We know for sure that at least the memory fits in the PA space */ |
1810 | vms->highest_gpa = memtop - 1; | |
1811 | ||
4af6b6ed | 1812 | virt_set_high_memmap(vms, base, pa_bits); |
3715c251 | 1813 | |
957e32cf | 1814 | if (device_memory_size > 0) { |
176d0730 | 1815 | machine_memory_devices_init(ms, device_memory_base, device_memory_size); |
957e32cf | 1816 | } |
350a9c9e EA |
1817 | } |
1818 | ||
a3495d11 AG |
1819 | static VirtGICType finalize_gic_version_do(const char *accel_name, |
1820 | VirtGICType gic_version, | |
1821 | int gics_supported, | |
1822 | unsigned int max_cpus) | |
1823 | { | |
1824 | /* Convert host/max/nosel to GIC version number */ | |
1825 | switch (gic_version) { | |
1826 | case VIRT_GIC_VERSION_HOST: | |
1827 | if (!kvm_enabled()) { | |
1828 | error_report("gic-version=host requires KVM"); | |
1829 | exit(1); | |
1830 | } | |
1831 | ||
1832 | /* For KVM, gic-version=host means gic-version=max */ | |
1833 | return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, | |
1834 | gics_supported, max_cpus); | |
1835 | case VIRT_GIC_VERSION_MAX: | |
1836 | if (gics_supported & VIRT_GIC_VERSION_4_MASK) { | |
1837 | gic_version = VIRT_GIC_VERSION_4; | |
1838 | } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { | |
1839 | gic_version = VIRT_GIC_VERSION_3; | |
1840 | } else { | |
1841 | gic_version = VIRT_GIC_VERSION_2; | |
1842 | } | |
1843 | break; | |
1844 | case VIRT_GIC_VERSION_NOSEL: | |
1845 | if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && | |
1846 | max_cpus <= GIC_NCPU) { | |
1847 | gic_version = VIRT_GIC_VERSION_2; | |
1848 | } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { | |
1849 | /* | |
1850 | * in case the host does not support v2 emulation or | |
1851 | * the end-user requested more than 8 VCPUs we now default | |
1852 | * to v3. In any case defaulting to v2 would be broken. | |
1853 | */ | |
1854 | gic_version = VIRT_GIC_VERSION_3; | |
1855 | } else if (max_cpus > GIC_NCPU) { | |
1856 | error_report("%s only supports GICv2 emulation but more than 8 " | |
1857 | "vcpus are requested", accel_name); | |
1858 | exit(1); | |
1859 | } | |
1860 | break; | |
1861 | case VIRT_GIC_VERSION_2: | |
1862 | case VIRT_GIC_VERSION_3: | |
1863 | case VIRT_GIC_VERSION_4: | |
1864 | break; | |
1865 | } | |
1866 | ||
1867 | /* Check chosen version is effectively supported */ | |
1868 | switch (gic_version) { | |
1869 | case VIRT_GIC_VERSION_2: | |
1870 | if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { | |
1871 | error_report("%s does not support GICv2 emulation", accel_name); | |
1872 | exit(1); | |
1873 | } | |
1874 | break; | |
1875 | case VIRT_GIC_VERSION_3: | |
1876 | if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { | |
1877 | error_report("%s does not support GICv3 emulation", accel_name); | |
1878 | exit(1); | |
1879 | } | |
1880 | break; | |
1881 | case VIRT_GIC_VERSION_4: | |
1882 | if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { | |
1883 | error_report("%s does not support GICv4 emulation, is virtualization=on?", | |
1884 | accel_name); | |
1885 | exit(1); | |
1886 | } | |
1887 | break; | |
1888 | default: | |
1889 | error_report("logic error in finalize_gic_version"); | |
1890 | exit(1); | |
1891 | break; | |
1892 | } | |
1893 | ||
1894 | return gic_version; | |
1895 | } | |
1896 | ||
36bf4ec8 EA |
1897 | /* |
1898 | * finalize_gic_version - Determines the final gic_version | |
1899 | * according to the gic-version property | |
1900 | * | |
1901 | * Default GIC type is v2 | |
1902 | */ | |
1903 | static void finalize_gic_version(VirtMachineState *vms) | |
1904 | { | |
a3495d11 | 1905 | const char *accel_name = current_accel_name(); |
6785aee0 | 1906 | unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; |
a3495d11 | 1907 | int gics_supported = 0; |
6785aee0 | 1908 | |
a3495d11 AG |
1909 | /* Determine which GIC versions the current environment supports */ |
1910 | if (kvm_enabled() && kvm_irqchip_in_kernel()) { | |
1911 | int probe_bitmap = kvm_arm_vgic_probe(); | |
97b4c918 | 1912 | |
97b4c918 EA |
1913 | if (!probe_bitmap) { |
1914 | error_report("Unable to determine GIC version supported by host"); | |
1915 | exit(1); | |
1916 | } | |
1917 | ||
a3495d11 AG |
1918 | if (probe_bitmap & KVM_ARM_VGIC_V2) { |
1919 | gics_supported |= VIRT_GIC_VERSION_2_MASK; | |
97b4c918 | 1920 | } |
a3495d11 AG |
1921 | if (probe_bitmap & KVM_ARM_VGIC_V3) { |
1922 | gics_supported |= VIRT_GIC_VERSION_3_MASK; | |
36bf4ec8 | 1923 | } |
a3495d11 AG |
1924 | } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { |
1925 | /* KVM w/o kernel irqchip can only deal with GICv2 */ | |
1926 | gics_supported |= VIRT_GIC_VERSION_2_MASK; | |
1927 | accel_name = "KVM with kernel-irqchip=off"; | |
5e91b9e0 | 1928 | } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { |
a3495d11 | 1929 | gics_supported |= VIRT_GIC_VERSION_2_MASK; |
299b4a3e | 1930 | if (module_object_class_by_name("arm-gicv3")) { |
a3495d11 | 1931 | gics_supported |= VIRT_GIC_VERSION_3_MASK; |
7cf3f8d2 PM |
1932 | if (vms->virt) { |
1933 | /* GICv4 only makes sense if CPU has EL2 */ | |
a3495d11 | 1934 | gics_supported |= VIRT_GIC_VERSION_4_MASK; |
7cf3f8d2 | 1935 | } |
299b4a3e | 1936 | } |
5e91b9e0 AG |
1937 | } else { |
1938 | error_report("Unsupported accelerator, can not determine GIC support"); | |
1939 | exit(1); | |
36bf4ec8 | 1940 | } |
a3495d11 AG |
1941 | |
1942 | /* | |
1943 | * Then convert helpers like host/max to concrete GIC versions and ensure | |
1944 | * the desired version is supported | |
1945 | */ | |
1946 | vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, | |
1947 | gics_supported, max_cpus); | |
36bf4ec8 EA |
1948 | } |
1949 | ||
fe11f058 AJ |
1950 | /* |
1951 | * virt_cpu_post_init() must be called after the CPUs have | |
1952 | * been realized and the GIC has been created. | |
1953 | */ | |
9cd07db9 | 1954 | static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) |
fe11f058 | 1955 | { |
9cd07db9 | 1956 | int max_cpus = MACHINE(vms)->smp.max_cpus; |
68970d1e | 1957 | bool aarch64, pmu, steal_time; |
946f1bb1 | 1958 | CPUState *cpu; |
fe11f058 AJ |
1959 | |
1960 | aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL); | |
946f1bb1 | 1961 | pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL); |
68970d1e AJ |
1962 | steal_time = object_property_get_bool(OBJECT(first_cpu), |
1963 | "kvm-steal-time", NULL); | |
fe11f058 | 1964 | |
946f1bb1 | 1965 | if (kvm_enabled()) { |
68970d1e AJ |
1966 | hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base; |
1967 | hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size; | |
1968 | ||
1969 | if (steal_time) { | |
1970 | MemoryRegion *pvtime = g_new(MemoryRegion, 1); | |
1971 | hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU; | |
1972 | ||
1973 | /* The memory region size must be a multiple of host page size. */ | |
1974 | pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size); | |
1975 | ||
1976 | if (pvtime_size > pvtime_reg_size) { | |
1977 | error_report("pvtime requires a %" HWADDR_PRId | |
1978 | " byte memory region for %d CPUs," | |
1979 | " but only %" HWADDR_PRId " has been reserved", | |
1980 | pvtime_size, max_cpus, pvtime_reg_size); | |
1981 | exit(1); | |
1982 | } | |
1983 | ||
1984 | memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL); | |
1985 | memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); | |
1986 | } | |
1987 | ||
946f1bb1 AJ |
1988 | CPU_FOREACH(cpu) { |
1989 | if (pmu) { | |
1990 | assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); | |
1991 | if (kvm_irqchip_in_kernel()) { | |
1992 | kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ)); | |
1993 | } | |
1994 | kvm_arm_pmu_init(cpu); | |
1995 | } | |
68970d1e AJ |
1996 | if (steal_time) { |
1997 | kvm_arm_pvtime_init(cpu, pvtime_reg_base + | |
1998 | cpu->cpu_index * PVTIME_SIZE_PER_CPU); | |
1999 | } | |
946f1bb1 AJ |
2000 | } |
2001 | } else { | |
fe11f058 AJ |
2002 | if (aarch64 && vms->highmem) { |
2003 | int requested_pa_size = 64 - clz64(vms->highest_gpa); | |
2004 | int pamax = arm_pamax(ARM_CPU(first_cpu)); | |
2005 | ||
2006 | if (pamax < requested_pa_size) { | |
2007 | error_report("VCPU supports less PA bits (%d) than " | |
2008 | "requested by the memory map (%d)", | |
2009 | pamax, requested_pa_size); | |
2010 | exit(1); | |
2011 | } | |
2012 | } | |
2013 | } | |
2014 | } | |
2015 | ||
3ef96221 | 2016 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 2017 | { |
e5a5604f | 2018 | VirtMachineState *vms = VIRT_MACHINE(machine); |
95eb49c8 | 2019 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); |
17d3d0e2 IM |
2020 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
2021 | const CPUArchIdList *possible_cpus; | |
f5fdcd6e | 2022 | MemoryRegion *sysmem = get_system_memory(); |
3df708eb | 2023 | MemoryRegion *secure_sysmem = NULL; |
8bce44a2 RH |
2024 | MemoryRegion *tag_sysmem = NULL; |
2025 | MemoryRegion *secure_tag_sysmem = NULL; | |
7ea686f5 | 2026 | int n, virt_max_cpus; |
e0561e60 | 2027 | bool firmware_loaded; |
17ec075a | 2028 | bool aarch64 = true; |
cff51ac9 | 2029 | bool has_ged = !vmc->no_ged; |
cc7d44c2 LX |
2030 | unsigned int smp_cpus = machine->smp.cpus; |
2031 | unsigned int max_cpus = machine->smp.max_cpus; | |
f5fdcd6e | 2032 | |
3715c251 MZ |
2033 | if (!cpu_type_valid(machine->cpu_type)) { |
2034 | error_report("mach-virt: CPU type %s not supported", machine->cpu_type); | |
2035 | exit(1); | |
2036 | } | |
2037 | ||
2038 | possible_cpus = mc->possible_cpu_arch_ids(machine); | |
2039 | ||
c9650222 EA |
2040 | /* |
2041 | * In accelerated mode, the memory map is computed earlier in kvm_type() | |
2042 | * to create a VM with the right number of IPA bits. | |
2043 | */ | |
2044 | if (!vms->memmap) { | |
3715c251 MZ |
2045 | Object *cpuobj; |
2046 | ARMCPU *armcpu; | |
2047 | int pa_bits; | |
2048 | ||
2049 | /* | |
b3db996f | 2050 | * Instantiate a temporary CPU object to find out about what |
3715c251 MZ |
2051 | * we are about to deal with. Once this is done, get rid of |
2052 | * the object. | |
2053 | */ | |
2054 | cpuobj = object_new(possible_cpus->cpus[0].type); | |
2055 | armcpu = ARM_CPU(cpuobj); | |
2056 | ||
22536b13 | 2057 | pa_bits = arm_pamax(armcpu); |
3715c251 MZ |
2058 | |
2059 | object_unref(cpuobj); | |
2060 | ||
2061 | virt_set_memmap(vms, pa_bits); | |
c9650222 | 2062 | } |
350a9c9e | 2063 | |
b92ad394 PF |
2064 | /* We can probe only here because during property set |
2065 | * KVM is not available yet | |
2066 | */ | |
36bf4ec8 | 2067 | finalize_gic_version(vms); |
b92ad394 | 2068 | |
e0561e60 | 2069 | if (vms->secure) { |
e0561e60 MA |
2070 | /* |
2071 | * The Secure view of the world is the same as the NonSecure, | |
2072 | * but with a few extra devices. Create it as a container region | |
2073 | * containing the system memory at low priority; any secure-only | |
2074 | * devices go in at higher priority and take precedence. | |
2075 | */ | |
2076 | secure_sysmem = g_new(MemoryRegion, 1); | |
2077 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", | |
2078 | UINT64_MAX); | |
2079 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
2080 | } | |
2081 | ||
2082 | firmware_loaded = virt_firmware_init(vms, sysmem, | |
2083 | secure_sysmem ?: sysmem); | |
2084 | ||
4824a61a PM |
2085 | /* If we have an EL3 boot ROM then the assumption is that it will |
2086 | * implement PSCI itself, so disable QEMU's internal implementation | |
2087 | * so it doesn't get in the way. Instead of starting secondary | |
2088 | * CPUs in PSCI powerdown state we will start them all running and | |
2089 | * let the boot ROM sort them out. | |
f29cacfb PM |
2090 | * The usual case is that we do use QEMU's PSCI implementation; |
2091 | * if the guest has EL2 then we will use SMC as the conduit, | |
2092 | * and otherwise we will use HVC (for backwards compatibility and | |
2093 | * because if we're using KVM then we must use HVC). | |
4824a61a | 2094 | */ |
2013c566 PM |
2095 | if (vms->secure && firmware_loaded) { |
2096 | vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | |
f29cacfb PM |
2097 | } else if (vms->virt) { |
2098 | vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC; | |
2013c566 PM |
2099 | } else { |
2100 | vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC; | |
2101 | } | |
4824a61a | 2102 | |
7cf3f8d2 PM |
2103 | /* |
2104 | * The maximum number of CPUs depends on the GIC version, or on how | |
2105 | * many redistributors we can fit into the memory map (which in turn | |
2106 | * depends on whether this is a GICv3 or v4). | |
4b280b72 | 2107 | */ |
7cf3f8d2 PM |
2108 | if (vms->gic_version == VIRT_GIC_VERSION_2) { |
2109 | virt_max_cpus = GIC_NCPU; | |
2110 | } else { | |
6a48c64e GS |
2111 | virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); |
2112 | if (vms->highmem_redists) { | |
2113 | virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); | |
2114 | } | |
4b280b72 AJ |
2115 | } |
2116 | ||
7ea686f5 | 2117 | if (max_cpus > virt_max_cpus) { |
4b280b72 AJ |
2118 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
2119 | "supported by machine 'mach-virt' (%d)", | |
7ea686f5 | 2120 | max_cpus, virt_max_cpus); |
6a48c64e GS |
2121 | if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { |
2122 | error_printf("Try 'highmem-redists=on' for more CPUs\n"); | |
2123 | } | |
2124 | ||
4b280b72 AJ |
2125 | exit(1); |
2126 | } | |
2127 | ||
78255ce3 PM |
2128 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { |
2129 | error_report("mach-virt: %s does not support providing " | |
2130 | "Security extensions (TrustZone) to the guest CPU", | |
8e4f2b27 | 2131 | current_accel_name()); |
78255ce3 PM |
2132 | exit(1); |
2133 | } | |
2134 | ||
bede0117 AG |
2135 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { |
2136 | error_report("mach-virt: %s does not support providing " | |
2137 | "Virtualization extensions to the guest CPU", | |
8e4f2b27 | 2138 | current_accel_name()); |
f29cacfb PM |
2139 | exit(1); |
2140 | } | |
2141 | ||
d009607d | 2142 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { |
bede0117 AG |
2143 | error_report("mach-virt: %s does not support providing " |
2144 | "MTE to the guest CPU", | |
8e4f2b27 | 2145 | current_accel_name()); |
7f6185ed RH |
2146 | exit(1); |
2147 | } | |
2148 | ||
c8ef2bda | 2149 | create_fdt(vms); |
f5fdcd6e | 2150 | |
9cd07db9 | 2151 | assert(possible_cpus->len == max_cpus); |
17d3d0e2 IM |
2152 | for (n = 0; n < possible_cpus->len; n++) { |
2153 | Object *cpuobj; | |
d9c34f9c | 2154 | CPUState *cs; |
46de5913 | 2155 | |
17d3d0e2 IM |
2156 | if (n >= smp_cpus) { |
2157 | break; | |
2158 | } | |
2159 | ||
d342eb76 | 2160 | cpuobj = object_new(possible_cpus->cpus[n].type); |
5325cc34 MA |
2161 | object_property_set_int(cpuobj, "mp-affinity", |
2162 | possible_cpus->cpus[n].arch_id, NULL); | |
f313369f | 2163 | |
d9c34f9c IM |
2164 | cs = CPU(cpuobj); |
2165 | cs->cpu_index = n; | |
2166 | ||
a0ceb640 IM |
2167 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), |
2168 | &error_fatal); | |
bd4c1bfe | 2169 | |
17ec075a EA |
2170 | aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL); |
2171 | ||
e5a5604f | 2172 | if (!vms->secure) { |
5325cc34 | 2173 | object_property_set_bool(cpuobj, "has_el3", false, NULL); |
e5a5604f GB |
2174 | } |
2175 | ||
efba1595 | 2176 | if (!vms->virt && object_property_find(cpuobj, "has_el2")) { |
5325cc34 | 2177 | object_property_set_bool(cpuobj, "has_el2", false, NULL); |
c25bd18a PM |
2178 | } |
2179 | ||
dea101a1 | 2180 | if (vmc->kvm_no_adjvtime && |
efba1595 | 2181 | object_property_find(cpuobj, "kvm-no-adjvtime")) { |
5325cc34 | 2182 | object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); |
dea101a1 AJ |
2183 | } |
2184 | ||
68970d1e AJ |
2185 | if (vmc->no_kvm_steal_time && |
2186 | object_property_find(cpuobj, "kvm-steal-time")) { | |
2187 | object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); | |
2188 | } | |
2189 | ||
efba1595 | 2190 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { |
5325cc34 | 2191 | object_property_set_bool(cpuobj, "pmu", false, NULL); |
1141d1eb WH |
2192 | } |
2193 | ||
09428204 RH |
2194 | if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) { |
2195 | object_property_set_bool(cpuobj, "lpa2", false, NULL); | |
2196 | } | |
2197 | ||
efba1595 | 2198 | if (object_property_find(cpuobj, "reset-cbar")) { |
5325cc34 MA |
2199 | object_property_set_int(cpuobj, "reset-cbar", |
2200 | vms->memmap[VIRT_CPUPERIPHS].base, | |
2201 | &error_abort); | |
ba750085 PM |
2202 | } |
2203 | ||
5325cc34 | 2204 | object_property_set_link(cpuobj, "memory", OBJECT(sysmem), |
1d939a68 | 2205 | &error_abort); |
3df708eb | 2206 | if (vms->secure) { |
5325cc34 MA |
2207 | object_property_set_link(cpuobj, "secure-memory", |
2208 | OBJECT(secure_sysmem), &error_abort); | |
3df708eb | 2209 | } |
1d939a68 | 2210 | |
6f4e1405 | 2211 | if (vms->mte) { |
d009607d PM |
2212 | /* Create the memory region only once, but link to all cpus. */ |
2213 | if (!tag_sysmem) { | |
2214 | /* | |
2215 | * The property exists only if MemTag is supported. | |
2216 | * If it is, we must allocate the ram to back that up. | |
2217 | */ | |
2218 | if (!object_property_find(cpuobj, "tag-memory")) { | |
2219 | error_report("MTE requested, but not supported " | |
2220 | "by the guest CPU"); | |
2221 | exit(1); | |
6f4e1405 RH |
2222 | } |
2223 | ||
d009607d PM |
2224 | tag_sysmem = g_new(MemoryRegion, 1); |
2225 | memory_region_init(tag_sysmem, OBJECT(machine), | |
2226 | "tag-memory", UINT64_MAX / 32); | |
2227 | ||
8bce44a2 | 2228 | if (vms->secure) { |
d009607d PM |
2229 | secure_tag_sysmem = g_new(MemoryRegion, 1); |
2230 | memory_region_init(secure_tag_sysmem, OBJECT(machine), | |
2231 | "secure-tag-memory", UINT64_MAX / 32); | |
2232 | ||
2233 | /* As with ram, secure-tag takes precedence over tag. */ | |
2234 | memory_region_add_subregion_overlap(secure_tag_sysmem, 0, | |
2235 | tag_sysmem, -1); | |
b320e21c | 2236 | } |
d009607d PM |
2237 | } |
2238 | ||
2239 | object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem), | |
2240 | &error_abort); | |
2241 | if (vms->secure) { | |
2242 | object_property_set_link(cpuobj, "secure-tag-memory", | |
2243 | OBJECT(secure_tag_sysmem), | |
2244 | &error_abort); | |
8bce44a2 RH |
2245 | } |
2246 | } | |
2247 | ||
ce189ab2 | 2248 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
dbb74759 | 2249 | object_unref(cpuobj); |
f5fdcd6e | 2250 | } |
055a7f2b | 2251 | fdt_add_timer_nodes(vms); |
c8ef2bda | 2252 | fdt_add_cpu_nodes(vms); |
f5fdcd6e | 2253 | |
a72f6805 IM |
2254 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, |
2255 | machine->ram); | |
f5fdcd6e | 2256 | |
80734cbd | 2257 | virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); |
acf82361 | 2258 | |
0e5c1c9a | 2259 | create_gic(vms, sysmem); |
f5fdcd6e | 2260 | |
9cd07db9 | 2261 | virt_cpu_post_init(vms, sysmem); |
fe11f058 | 2262 | |
055a7f2b | 2263 | fdt_add_pmu_nodes(vms); |
01fe6b60 | 2264 | |
b8b69f4c | 2265 | create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); |
3df708eb PM |
2266 | |
2267 | if (vms->secure) { | |
8bce44a2 | 2268 | create_secure_ram(vms, secure_sysmem, secure_tag_sysmem); |
b8b69f4c | 2269 | create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); |
3df708eb | 2270 | } |
f5fdcd6e | 2271 | |
8bce44a2 RH |
2272 | if (tag_sysmem) { |
2273 | create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base, | |
2274 | machine->ram_size, "mach-virt.tag"); | |
2275 | } | |
2276 | ||
2dcb74e5 | 2277 | vms->highmem_ecam &= (!firmware_loaded || aarch64); |
17ec075a | 2278 | |
b8b69f4c | 2279 | create_rtc(vms); |
6e411af9 | 2280 | |
b8b69f4c | 2281 | create_pcie(vms); |
4ab29b82 | 2282 | |
17e89077 | 2283 | if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) { |
b8b69f4c | 2284 | vms->acpi_dev = create_acpi_ged(vms); |
1962f31b | 2285 | } else { |
e61bde40 | 2286 | create_gpio_devices(vms, VIRT_GPIO, sysmem); |
cff51ac9 SK |
2287 | } |
2288 | ||
daa726d9 MU |
2289 | if (vms->secure && !vmc->no_secure_gpio) { |
2290 | create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem); | |
2291 | } | |
2292 | ||
c345680c SK |
2293 | /* connect powerdown request */ |
2294 | vms->powerdown_notifier.notify = virt_powerdown_req; | |
2295 | qemu_register_powerdown_notifier(&vms->powerdown_notifier); | |
2296 | ||
f5fdcd6e PM |
2297 | /* Create mmio transports, so the user can create virtio backends |
2298 | * (which will be automatically plugged in to the transports). If | |
2299 | * no backend is created the transport will just sit harmlessly idle. | |
2300 | */ | |
b8b69f4c | 2301 | create_virtio_devices(vms); |
f5fdcd6e | 2302 | |
af1f60a4 AJ |
2303 | vms->fw_cfg = create_fw_cfg(vms, &address_space_memory); |
2304 | rom_set_fw(vms->fw_cfg); | |
d7c2e2db | 2305 | |
b8b69f4c | 2306 | create_platform_bus(vms); |
578f3c7b | 2307 | |
b5a60bee KL |
2308 | if (machine->nvdimms_state->is_enabled) { |
2309 | const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = { | |
2310 | .space_id = AML_AS_SYSTEM_MEMORY, | |
2311 | .address = vms->memmap[VIRT_NVDIMM_ACPI].base, | |
2312 | .bit_width = NVDIMM_ACPI_IO_LEN << 3 | |
2313 | }; | |
2314 | ||
2315 | nvdimm_init_acpi_state(machine->nvdimms_state, sysmem, | |
2316 | arm_virt_nvdimm_acpi_dsmio, | |
2317 | vms->fw_cfg, OBJECT(vms)); | |
2318 | } | |
2319 | ||
c8ef2bda | 2320 | vms->bootinfo.ram_size = machine->ram_size; |
c8ef2bda PM |
2321 | vms->bootinfo.board_id = -1; |
2322 | vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base; | |
2323 | vms->bootinfo.get_dtb = machvirt_dtb; | |
3b77f6c3 | 2324 | vms->bootinfo.skip_dtb_autoload = true; |
c8ef2bda | 2325 | vms->bootinfo.firmware_loaded = firmware_loaded; |
52c235ad | 2326 | vms->bootinfo.psci_conduit = vms->psci_conduit; |
2744ece8 | 2327 | arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); |
5f7a5a0e | 2328 | |
3b77f6c3 IM |
2329 | vms->machine_done.notify = virt_machine_done; |
2330 | qemu_add_machine_init_done_notifier(&vms->machine_done); | |
f5fdcd6e PM |
2331 | } |
2332 | ||
083a5890 GB |
2333 | static bool virt_get_secure(Object *obj, Error **errp) |
2334 | { | |
2335 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2336 | ||
2337 | return vms->secure; | |
2338 | } | |
2339 | ||
2340 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
2341 | { | |
2342 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2343 | ||
2344 | vms->secure = value; | |
2345 | } | |
2346 | ||
f29cacfb PM |
2347 | static bool virt_get_virt(Object *obj, Error **errp) |
2348 | { | |
2349 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2350 | ||
2351 | return vms->virt; | |
2352 | } | |
2353 | ||
2354 | static void virt_set_virt(Object *obj, bool value, Error **errp) | |
2355 | { | |
2356 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2357 | ||
2358 | vms->virt = value; | |
2359 | } | |
2360 | ||
5125f9cd PF |
2361 | static bool virt_get_highmem(Object *obj, Error **errp) |
2362 | { | |
2363 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2364 | ||
2365 | return vms->highmem; | |
2366 | } | |
2367 | ||
2368 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
2369 | { | |
2370 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2371 | ||
2372 | vms->highmem = value; | |
2373 | } | |
2374 | ||
f40408a9 GS |
2375 | static bool virt_get_compact_highmem(Object *obj, Error **errp) |
2376 | { | |
2377 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2378 | ||
2379 | return vms->highmem_compact; | |
2380 | } | |
2381 | ||
2382 | static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) | |
2383 | { | |
2384 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2385 | ||
2386 | vms->highmem_compact = value; | |
2387 | } | |
2388 | ||
6a48c64e GS |
2389 | static bool virt_get_highmem_redists(Object *obj, Error **errp) |
2390 | { | |
2391 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2392 | ||
2393 | return vms->highmem_redists; | |
2394 | } | |
2395 | ||
2396 | static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) | |
2397 | { | |
2398 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2399 | ||
2400 | vms->highmem_redists = value; | |
2401 | } | |
2402 | ||
2403 | static bool virt_get_highmem_ecam(Object *obj, Error **errp) | |
2404 | { | |
2405 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2406 | ||
2407 | return vms->highmem_ecam; | |
2408 | } | |
2409 | ||
2410 | static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) | |
2411 | { | |
2412 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2413 | ||
2414 | vms->highmem_ecam = value; | |
2415 | } | |
2416 | ||
2417 | static bool virt_get_highmem_mmio(Object *obj, Error **errp) | |
2418 | { | |
2419 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2420 | ||
2421 | return vms->highmem_mmio; | |
2422 | } | |
2423 | ||
2424 | static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) | |
2425 | { | |
2426 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2427 | ||
2428 | vms->highmem_mmio = value; | |
2429 | } | |
2430 | ||
2431 | ||
ccc11b02 EA |
2432 | static bool virt_get_its(Object *obj, Error **errp) |
2433 | { | |
2434 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2435 | ||
2436 | return vms->its; | |
2437 | } | |
2438 | ||
2439 | static void virt_set_its(Object *obj, bool value, Error **errp) | |
2440 | { | |
2441 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2442 | ||
2443 | vms->its = value; | |
2444 | } | |
2445 | ||
5242876f | 2446 | static bool virt_get_dtb_randomness(Object *obj, Error **errp) |
33973e1e AB |
2447 | { |
2448 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2449 | ||
5242876f | 2450 | return vms->dtb_randomness; |
33973e1e AB |
2451 | } |
2452 | ||
5242876f | 2453 | static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) |
33973e1e AB |
2454 | { |
2455 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2456 | ||
5242876f | 2457 | vms->dtb_randomness = value; |
33973e1e AB |
2458 | } |
2459 | ||
602b4582 MP |
2460 | static char *virt_get_oem_id(Object *obj, Error **errp) |
2461 | { | |
2462 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2463 | ||
2464 | return g_strdup(vms->oem_id); | |
2465 | } | |
2466 | ||
2467 | static void virt_set_oem_id(Object *obj, const char *value, Error **errp) | |
2468 | { | |
2469 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2470 | size_t len = strlen(value); | |
2471 | ||
2472 | if (len > 6) { | |
2473 | error_setg(errp, | |
2474 | "User specified oem-id value is bigger than 6 bytes in size"); | |
2475 | return; | |
2476 | } | |
2477 | ||
43e229a5 | 2478 | strncpy(vms->oem_id, value, 6); |
602b4582 MP |
2479 | } |
2480 | ||
2481 | static char *virt_get_oem_table_id(Object *obj, Error **errp) | |
2482 | { | |
2483 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2484 | ||
2485 | return g_strdup(vms->oem_table_id); | |
2486 | } | |
2487 | ||
2488 | static void virt_set_oem_table_id(Object *obj, const char *value, | |
2489 | Error **errp) | |
2490 | { | |
2491 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2492 | size_t len = strlen(value); | |
2493 | ||
2494 | if (len > 8) { | |
2495 | error_setg(errp, | |
2496 | "User specified oem-table-id value is bigger than 8 bytes in size"); | |
2497 | return; | |
2498 | } | |
43e229a5 | 2499 | strncpy(vms->oem_table_id, value, 8); |
602b4582 MP |
2500 | } |
2501 | ||
2502 | ||
17e89077 GH |
2503 | bool virt_is_acpi_enabled(VirtMachineState *vms) |
2504 | { | |
2505 | if (vms->acpi == ON_OFF_AUTO_OFF) { | |
2506 | return false; | |
2507 | } | |
2508 | return true; | |
2509 | } | |
2510 | ||
2511 | static void virt_get_acpi(Object *obj, Visitor *v, const char *name, | |
2512 | void *opaque, Error **errp) | |
2513 | { | |
2514 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2515 | OnOffAuto acpi = vms->acpi; | |
2516 | ||
2517 | visit_type_OnOffAuto(v, name, &acpi, errp); | |
2518 | } | |
2519 | ||
2520 | static void virt_set_acpi(Object *obj, Visitor *v, const char *name, | |
2521 | void *opaque, Error **errp) | |
2522 | { | |
2523 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2524 | ||
2525 | visit_type_OnOffAuto(v, name, &vms->acpi, errp); | |
2526 | } | |
2527 | ||
2afa8c85 DG |
2528 | static bool virt_get_ras(Object *obj, Error **errp) |
2529 | { | |
2530 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2531 | ||
2532 | return vms->ras; | |
2533 | } | |
2534 | ||
2535 | static void virt_set_ras(Object *obj, bool value, Error **errp) | |
2536 | { | |
2537 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2538 | ||
2539 | vms->ras = value; | |
2540 | } | |
2541 | ||
6f4e1405 RH |
2542 | static bool virt_get_mte(Object *obj, Error **errp) |
2543 | { | |
2544 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2545 | ||
2546 | return vms->mte; | |
2547 | } | |
2548 | ||
2549 | static void virt_set_mte(Object *obj, bool value, Error **errp) | |
2550 | { | |
2551 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2552 | ||
2553 | vms->mte = value; | |
2554 | } | |
2555 | ||
b92ad394 PF |
2556 | static char *virt_get_gic_version(Object *obj, Error **errp) |
2557 | { | |
2558 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
7cf3f8d2 | 2559 | const char *val; |
b92ad394 | 2560 | |
7cf3f8d2 PM |
2561 | switch (vms->gic_version) { |
2562 | case VIRT_GIC_VERSION_4: | |
2563 | val = "4"; | |
2564 | break; | |
2565 | case VIRT_GIC_VERSION_3: | |
2566 | val = "3"; | |
2567 | break; | |
2568 | default: | |
2569 | val = "2"; | |
2570 | break; | |
2571 | } | |
b92ad394 PF |
2572 | return g_strdup(val); |
2573 | } | |
2574 | ||
2575 | static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | |
2576 | { | |
2577 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2578 | ||
7cf3f8d2 PM |
2579 | if (!strcmp(value, "4")) { |
2580 | vms->gic_version = VIRT_GIC_VERSION_4; | |
2581 | } else if (!strcmp(value, "3")) { | |
d04460e5 | 2582 | vms->gic_version = VIRT_GIC_VERSION_3; |
b92ad394 | 2583 | } else if (!strcmp(value, "2")) { |
d04460e5 | 2584 | vms->gic_version = VIRT_GIC_VERSION_2; |
b92ad394 | 2585 | } else if (!strcmp(value, "host")) { |
d04460e5 | 2586 | vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */ |
dc16538a | 2587 | } else if (!strcmp(value, "max")) { |
d04460e5 | 2588 | vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */ |
b92ad394 | 2589 | } else { |
7b55044f | 2590 | error_setg(errp, "Invalid gic-version value"); |
dc16538a | 2591 | error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); |
b92ad394 PF |
2592 | } |
2593 | } | |
2594 | ||
e24e3454 EA |
2595 | static char *virt_get_iommu(Object *obj, Error **errp) |
2596 | { | |
2597 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2598 | ||
2599 | switch (vms->iommu) { | |
2600 | case VIRT_IOMMU_NONE: | |
2601 | return g_strdup("none"); | |
2602 | case VIRT_IOMMU_SMMUV3: | |
2603 | return g_strdup("smmuv3"); | |
2604 | default: | |
2605 | g_assert_not_reached(); | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | static void virt_set_iommu(Object *obj, const char *value, Error **errp) | |
2610 | { | |
2611 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2612 | ||
2613 | if (!strcmp(value, "smmuv3")) { | |
2614 | vms->iommu = VIRT_IOMMU_SMMUV3; | |
2615 | } else if (!strcmp(value, "none")) { | |
2616 | vms->iommu = VIRT_IOMMU_NONE; | |
2617 | } else { | |
2618 | error_setg(errp, "Invalid iommu value"); | |
2619 | error_append_hint(errp, "Valid values are none, smmuv3.\n"); | |
2620 | } | |
2621 | } | |
2622 | ||
6d7a8548 XW |
2623 | static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp) |
2624 | { | |
2625 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2626 | ||
2627 | return vms->default_bus_bypass_iommu; | |
2628 | } | |
2629 | ||
2630 | static void virt_set_default_bus_bypass_iommu(Object *obj, bool value, | |
2631 | Error **errp) | |
2632 | { | |
2633 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
2634 | ||
2635 | vms->default_bus_bypass_iommu = value; | |
2636 | } | |
2637 | ||
ea089eeb IM |
2638 | static CpuInstanceProperties |
2639 | virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) | |
2640 | { | |
2641 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
2642 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
2643 | ||
2644 | assert(cpu_index < possible_cpus->len); | |
2645 | return possible_cpus->cpus[cpu_index].props; | |
2646 | } | |
2647 | ||
79e07936 IM |
2648 | static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) |
2649 | { | |
4c18bc19 GS |
2650 | int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; |
2651 | ||
2652 | return socket_id % ms->numa_state->num_nodes; | |
79e07936 IM |
2653 | } |
2654 | ||
17d3d0e2 IM |
2655 | static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) |
2656 | { | |
2657 | int n; | |
cc7d44c2 | 2658 | unsigned int max_cpus = ms->smp.max_cpus; |
17d3d0e2 | 2659 | VirtMachineState *vms = VIRT_MACHINE(ms); |
c9ec4cb5 | 2660 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
17d3d0e2 IM |
2661 | |
2662 | if (ms->possible_cpus) { | |
2663 | assert(ms->possible_cpus->len == max_cpus); | |
2664 | return ms->possible_cpus; | |
2665 | } | |
2666 | ||
2667 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + | |
2668 | sizeof(CPUArchId) * max_cpus); | |
2669 | ms->possible_cpus->len = max_cpus; | |
2670 | for (n = 0; n < ms->possible_cpus->len; n++) { | |
d342eb76 | 2671 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
17d3d0e2 IM |
2672 | ms->possible_cpus->cpus[n].arch_id = |
2673 | virt_cpu_mp_affinity(vms, n); | |
c9ec4cb5 GS |
2674 | |
2675 | assert(!mc->smp_props.dies_supported); | |
2676 | ms->possible_cpus->cpus[n].props.has_socket_id = true; | |
2677 | ms->possible_cpus->cpus[n].props.socket_id = | |
2678 | n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); | |
2679 | ms->possible_cpus->cpus[n].props.has_cluster_id = true; | |
2680 | ms->possible_cpus->cpus[n].props.cluster_id = | |
2681 | (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; | |
2682 | ms->possible_cpus->cpus[n].props.has_core_id = true; | |
2683 | ms->possible_cpus->cpus[n].props.core_id = | |
2684 | (n / ms->smp.threads) % ms->smp.cores; | |
17d3d0e2 | 2685 | ms->possible_cpus->cpus[n].props.has_thread_id = true; |
c9ec4cb5 GS |
2686 | ms->possible_cpus->cpus[n].props.thread_id = |
2687 | n % ms->smp.threads; | |
17d3d0e2 IM |
2688 | } |
2689 | return ms->possible_cpus; | |
2690 | } | |
2691 | ||
1f283ae1 EA |
2692 | static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, |
2693 | Error **errp) | |
2694 | { | |
cff51ac9 | 2695 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); |
c2505d1c | 2696 | const MachineState *ms = MACHINE(hotplug_dev); |
cff51ac9 | 2697 | const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); |
1f283ae1 | 2698 | |
cff51ac9 SK |
2699 | if (!vms->acpi_dev) { |
2700 | error_setg(errp, | |
2701 | "memory hotplug is not enabled: missing acpi-ged device"); | |
1f283ae1 EA |
2702 | return; |
2703 | } | |
2704 | ||
19bd6aaf RH |
2705 | if (vms->mte) { |
2706 | error_setg(errp, "memory hotplug is not enabled: MTE is enabled"); | |
2707 | return; | |
2708 | } | |
2709 | ||
c2505d1c SK |
2710 | if (is_nvdimm && !ms->nvdimms_state->is_enabled) { |
2711 | error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'"); | |
2712 | return; | |
2713 | } | |
2714 | ||
1f283ae1 EA |
2715 | pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); |
2716 | } | |
2717 | ||
2718 | static void virt_memory_plug(HotplugHandler *hotplug_dev, | |
2719 | DeviceState *dev, Error **errp) | |
2720 | { | |
2721 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | |
b5a60bee KL |
2722 | MachineState *ms = MACHINE(hotplug_dev); |
2723 | bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); | |
1f283ae1 | 2724 | |
84fd5496 | 2725 | pc_dimm_plug(PC_DIMM(dev), MACHINE(vms)); |
1f283ae1 | 2726 | |
b5a60bee KL |
2727 | if (is_nvdimm) { |
2728 | nvdimm_plug(ms->nvdimms_state); | |
2729 | } | |
2730 | ||
53eccc70 KZ |
2731 | hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev), |
2732 | dev, &error_abort); | |
1f283ae1 EA |
2733 | } |
2734 | ||
2735 | static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | |
2736 | DeviceState *dev, Error **errp) | |
2737 | { | |
1b6f99d8 EA |
2738 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); |
2739 | ||
1f283ae1 EA |
2740 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2741 | virt_memory_pre_plug(hotplug_dev, dev, errp); | |
30ec5ccd DH |
2742 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
2743 | virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
1b6f99d8 EA |
2744 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
2745 | hwaddr db_start = 0, db_end = 0; | |
2746 | char *resv_prop_str; | |
2747 | ||
80d28ccd JPB |
2748 | if (vms->iommu != VIRT_IOMMU_NONE) { |
2749 | error_setg(errp, "virt machine does not support multiple IOMMUs"); | |
2750 | return; | |
2751 | } | |
2752 | ||
1b6f99d8 EA |
2753 | switch (vms->msi_controller) { |
2754 | case VIRT_MSI_CTRL_NONE: | |
2755 | return; | |
2756 | case VIRT_MSI_CTRL_ITS: | |
2757 | /* GITS_TRANSLATER page */ | |
2758 | db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; | |
2759 | db_end = base_memmap[VIRT_GIC_ITS].base + | |
2760 | base_memmap[VIRT_GIC_ITS].size - 1; | |
2761 | break; | |
2762 | case VIRT_MSI_CTRL_GICV2M: | |
2763 | /* MSI_SETSPI_NS page */ | |
2764 | db_start = base_memmap[VIRT_GIC_V2M].base; | |
2765 | db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; | |
2766 | break; | |
2767 | } | |
2768 | resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", | |
2769 | db_start, db_end, | |
2770 | VIRTIO_IOMMU_RESV_MEM_T_MSI); | |
2771 | ||
317500fe JPB |
2772 | object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); |
2773 | object_property_set_str(OBJECT(dev), "reserved-regions[0]", | |
2774 | resv_prop_str, errp); | |
1b6f99d8 | 2775 | g_free(resv_prop_str); |
1f283ae1 EA |
2776 | } |
2777 | } | |
2778 | ||
a3fc8396 IM |
2779 | static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
2780 | DeviceState *dev, Error **errp) | |
2781 | { | |
2782 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | |
2783 | ||
2784 | if (vms->platform_bus_dev) { | |
37fce4dd PM |
2785 | MachineClass *mc = MACHINE_GET_CLASS(vms); |
2786 | ||
2787 | if (device_is_dynamic_sysbus(mc, dev)) { | |
a3fc8396 IM |
2788 | platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev), |
2789 | SYS_BUS_DEVICE(dev)); | |
2790 | } | |
2791 | } | |
30ec5ccd | 2792 | |
1f283ae1 EA |
2793 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2794 | virt_memory_plug(hotplug_dev, dev, errp); | |
30ec5ccd DH |
2795 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
2796 | virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
b1b87327 GS |
2797 | } |
2798 | ||
70e89132 EA |
2799 | if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
2800 | PCIDevice *pdev = PCI_DEVICE(dev); | |
2801 | ||
2802 | vms->iommu = VIRT_IOMMU_VIRTIO; | |
2803 | vms->virtio_iommu_bdf = pci_get_bdf(pdev); | |
0fbddcec | 2804 | create_virtio_iommu_dt_bindings(vms); |
70e89132 | 2805 | } |
1f283ae1 EA |
2806 | } |
2807 | ||
539533b8 SK |
2808 | static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, |
2809 | DeviceState *dev, Error **errp) | |
2810 | { | |
2811 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | |
539533b8 SK |
2812 | |
2813 | if (!vms->acpi_dev) { | |
6c37ebf3 | 2814 | error_setg(errp, |
539533b8 | 2815 | "memory hotplug is not enabled: missing acpi-ged device"); |
6c37ebf3 | 2816 | return; |
539533b8 SK |
2817 | } |
2818 | ||
2819 | if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { | |
6c37ebf3 MA |
2820 | error_setg(errp, "nvdimm device hot unplug is not supported yet."); |
2821 | return; | |
539533b8 SK |
2822 | } |
2823 | ||
2824 | hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, | |
6c37ebf3 | 2825 | errp); |
539533b8 SK |
2826 | } |
2827 | ||
2828 | static void virt_dimm_unplug(HotplugHandler *hotplug_dev, | |
2829 | DeviceState *dev, Error **errp) | |
2830 | { | |
2831 | VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | |
2832 | Error *local_err = NULL; | |
2833 | ||
2834 | hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); | |
2835 | if (local_err) { | |
2836 | goto out; | |
2837 | } | |
2838 | ||
2839 | pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); | |
2840 | qdev_unrealize(dev); | |
2841 | ||
2842 | out: | |
2843 | error_propagate(errp, local_err); | |
2844 | } | |
2845 | ||
1f283ae1 EA |
2846 | static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, |
2847 | DeviceState *dev, Error **errp) | |
2848 | { | |
539533b8 SK |
2849 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { |
2850 | virt_dimm_unplug_request(hotplug_dev, dev, errp); | |
30ec5ccd DH |
2851 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
2852 | virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), | |
2853 | errp); | |
539533b8 SK |
2854 | } else { |
2855 | error_setg(errp, "device unplug request for unsupported device" | |
2856 | " type: %s", object_get_typename(OBJECT(dev))); | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | |
2861 | DeviceState *dev, Error **errp) | |
2862 | { | |
2863 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | |
2864 | virt_dimm_unplug(hotplug_dev, dev, errp); | |
30ec5ccd DH |
2865 | } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { |
2866 | virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); | |
539533b8 SK |
2867 | } else { |
2868 | error_setg(errp, "virt: device unplug for unsupported device" | |
2869 | " type: %s", object_get_typename(OBJECT(dev))); | |
2870 | } | |
a3fc8396 IM |
2871 | } |
2872 | ||
2873 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | |
2874 | DeviceState *dev) | |
2875 | { | |
37fce4dd PM |
2876 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
2877 | ||
2878 | if (device_is_dynamic_sysbus(mc, dev) || | |
092cba03 | 2879 | object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || |
30ec5ccd | 2880 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || |
092cba03 | 2881 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
a3fc8396 IM |
2882 | return HOTPLUG_HANDLER(machine); |
2883 | } | |
a3fc8396 IM |
2884 | return NULL; |
2885 | } | |
2886 | ||
c9650222 EA |
2887 | /* |
2888 | * for arm64 kvm_type [7-0] encodes the requested number of bits | |
2889 | * in the IPA address space | |
2890 | */ | |
2891 | static int virt_kvm_type(MachineState *ms, const char *type_str) | |
2892 | { | |
2893 | VirtMachineState *vms = VIRT_MACHINE(ms); | |
bcb902a1 AJ |
2894 | int max_vm_pa_size, requested_pa_size; |
2895 | bool fixed_ipa; | |
2896 | ||
2897 | max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); | |
c9650222 EA |
2898 | |
2899 | /* we freeze the memory map to compute the highest gpa */ | |
3715c251 | 2900 | virt_set_memmap(vms, max_vm_pa_size); |
c9650222 EA |
2901 | |
2902 | requested_pa_size = 64 - clz64(vms->highest_gpa); | |
2903 | ||
bcb902a1 AJ |
2904 | /* |
2905 | * KVM requires the IPA size to be at least 32 bits. | |
2906 | */ | |
2907 | if (requested_pa_size < 32) { | |
2908 | requested_pa_size = 32; | |
2909 | } | |
2910 | ||
c9650222 EA |
2911 | if (requested_pa_size > max_vm_pa_size) { |
2912 | error_report("-m and ,maxmem option values " | |
2913 | "require an IPA range (%d bits) larger than " | |
2914 | "the one supported by the host (%d bits)", | |
2915 | requested_pa_size, max_vm_pa_size); | |
bcb902a1 | 2916 | exit(1); |
c9650222 EA |
2917 | } |
2918 | /* | |
bcb902a1 AJ |
2919 | * We return the requested PA log size, unless KVM only supports |
2920 | * the implicit legacy 40b IPA setting, in which case the kvm_type | |
2921 | * must be 0. | |
c9650222 | 2922 | */ |
bcb902a1 | 2923 | return fixed_ipa ? 0 : requested_pa_size; |
c9650222 EA |
2924 | } |
2925 | ||
ed796373 WH |
2926 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
2927 | { | |
9c94d8e6 | 2928 | MachineClass *mc = MACHINE_CLASS(oc); |
a3fc8396 | 2929 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
9c94d8e6 WH |
2930 | |
2931 | mc->init = machvirt_init; | |
b10fbd53 EA |
2932 | /* Start with max_cpus set to 512, which is the maximum supported by KVM. |
2933 | * The value may be reduced later when we have more information about the | |
9c94d8e6 WH |
2934 | * configuration of the particular instance. |
2935 | */ | |
b10fbd53 | 2936 | mc->max_cpus = 512; |
6f2062b9 EH |
2937 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC); |
2938 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); | |
94692dcd | 2939 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); |
4ebc0b61 | 2940 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); |
f50be48a | 2941 | #ifdef CONFIG_TPM |
c294ac32 | 2942 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); |
f50be48a | 2943 | #endif |
9c94d8e6 WH |
2944 | mc->block_default_type = IF_VIRTIO; |
2945 | mc->no_cdrom = 1; | |
2946 | mc->pci_allow_0_address = true; | |
a2519ad1 PM |
2947 | /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ |
2948 | mc->minimum_page_bits = 12; | |
17d3d0e2 | 2949 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
ea089eeb | 2950 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; |
6c8a108d | 2951 | #ifdef CONFIG_TCG |
ba1ba5cc | 2952 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
6c8a108d FR |
2953 | #else |
2954 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); | |
2955 | #endif | |
79e07936 | 2956 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
c9650222 | 2957 | mc->kvm_type = virt_kvm_type; |
debbdc00 | 2958 | assert(!mc->get_hotplug_handler); |
a3fc8396 | 2959 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; |
1f283ae1 | 2960 | hc->pre_plug = virt_machine_device_pre_plug_cb; |
a3fc8396 | 2961 | hc->plug = virt_machine_device_plug_cb; |
1f283ae1 | 2962 | hc->unplug_request = virt_machine_device_unplug_request_cb; |
539533b8 | 2963 | hc->unplug = virt_machine_device_unplug_cb; |
c2505d1c | 2964 | mc->nvdimm_supported = true; |
d55c316f | 2965 | mc->smp_props.clusters_supported = true; |
442da7dc | 2966 | mc->auto_enable_numa_with_memhp = true; |
195784a0 | 2967 | mc->auto_enable_numa_with_memdev = true; |
fecff672 GS |
2968 | /* platform instead of architectural choice */ |
2969 | mc->cpu_cluster_has_numa_boundary = true; | |
a72f6805 | 2970 | mc->default_ram_id = "mach-virt.ram"; |
50989d04 | 2971 | mc->default_nic = "virtio-net-pci"; |
17e89077 GH |
2972 | |
2973 | object_class_property_add(oc, "acpi", "OnOffAuto", | |
2974 | virt_get_acpi, virt_set_acpi, | |
d2623129 | 2975 | NULL, NULL); |
17e89077 | 2976 | object_class_property_set_description(oc, "acpi", |
7eecec7d | 2977 | "Enable ACPI"); |
b91def7b EH |
2978 | object_class_property_add_bool(oc, "secure", virt_get_secure, |
2979 | virt_set_secure); | |
2980 | object_class_property_set_description(oc, "secure", | |
2981 | "Set on/off to enable/disable the ARM " | |
2982 | "Security Extensions (TrustZone)"); | |
2983 | ||
2984 | object_class_property_add_bool(oc, "virtualization", virt_get_virt, | |
2985 | virt_set_virt); | |
2986 | object_class_property_set_description(oc, "virtualization", | |
2987 | "Set on/off to enable/disable emulating a " | |
2988 | "guest CPU which implements the ARM " | |
2989 | "Virtualization Extensions"); | |
2990 | ||
2991 | object_class_property_add_bool(oc, "highmem", virt_get_highmem, | |
2992 | virt_set_highmem); | |
2993 | object_class_property_set_description(oc, "highmem", | |
2994 | "Set on/off to enable/disable using " | |
2995 | "physical address space above 32 bits"); | |
2996 | ||
f40408a9 GS |
2997 | object_class_property_add_bool(oc, "compact-highmem", |
2998 | virt_get_compact_highmem, | |
2999 | virt_set_compact_highmem); | |
3000 | object_class_property_set_description(oc, "compact-highmem", | |
3001 | "Set on/off to enable/disable compact " | |
3002 | "layout for high memory regions"); | |
3003 | ||
6a48c64e GS |
3004 | object_class_property_add_bool(oc, "highmem-redists", |
3005 | virt_get_highmem_redists, | |
3006 | virt_set_highmem_redists); | |
3007 | object_class_property_set_description(oc, "highmem-redists", | |
3008 | "Set on/off to enable/disable high " | |
3009 | "memory region for GICv3 or GICv4 " | |
3010 | "redistributor"); | |
3011 | ||
3012 | object_class_property_add_bool(oc, "highmem-ecam", | |
3013 | virt_get_highmem_ecam, | |
3014 | virt_set_highmem_ecam); | |
3015 | object_class_property_set_description(oc, "highmem-ecam", | |
3016 | "Set on/off to enable/disable high " | |
3017 | "memory region for PCI ECAM"); | |
3018 | ||
3019 | object_class_property_add_bool(oc, "highmem-mmio", | |
3020 | virt_get_highmem_mmio, | |
3021 | virt_set_highmem_mmio); | |
3022 | object_class_property_set_description(oc, "highmem-mmio", | |
3023 | "Set on/off to enable/disable high " | |
3024 | "memory region for PCI MMIO"); | |
3025 | ||
b91def7b EH |
3026 | object_class_property_add_str(oc, "gic-version", virt_get_gic_version, |
3027 | virt_set_gic_version); | |
3028 | object_class_property_set_description(oc, "gic-version", | |
3029 | "Set GIC version. " | |
7cf3f8d2 | 3030 | "Valid values are 2, 3, 4, host and max"); |
b91def7b EH |
3031 | |
3032 | object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu); | |
3033 | object_class_property_set_description(oc, "iommu", | |
3034 | "Set the IOMMU type. " | |
3035 | "Valid values are none and smmuv3"); | |
3036 | ||
9dad363a | 3037 | object_class_property_add_bool(oc, "default-bus-bypass-iommu", |
6d7a8548 XW |
3038 | virt_get_default_bus_bypass_iommu, |
3039 | virt_set_default_bus_bypass_iommu); | |
9dad363a | 3040 | object_class_property_set_description(oc, "default-bus-bypass-iommu", |
6d7a8548 XW |
3041 | "Set on/off to enable/disable " |
3042 | "bypass_iommu for default root bus"); | |
3043 | ||
b91def7b EH |
3044 | object_class_property_add_bool(oc, "ras", virt_get_ras, |
3045 | virt_set_ras); | |
3046 | object_class_property_set_description(oc, "ras", | |
3047 | "Set on/off to enable/disable reporting host memory errors " | |
3048 | "to a KVM guest using ACPI and guest external abort exceptions"); | |
3049 | ||
3050 | object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte); | |
3051 | object_class_property_set_description(oc, "mte", | |
3052 | "Set on/off to enable/disable emulating a " | |
3053 | "guest CPU which implements the ARM " | |
3054 | "Memory Tagging Extension"); | |
27edeeaa EH |
3055 | |
3056 | object_class_property_add_bool(oc, "its", virt_get_its, | |
3057 | virt_set_its); | |
3058 | object_class_property_set_description(oc, "its", | |
3059 | "Set on/off to enable/disable " | |
3060 | "ITS instantiation"); | |
3061 | ||
5242876f JD |
3062 | object_class_property_add_bool(oc, "dtb-randomness", |
3063 | virt_get_dtb_randomness, | |
3064 | virt_set_dtb_randomness); | |
3065 | object_class_property_set_description(oc, "dtb-randomness", | |
3066 | "Set off to disable passing random or " | |
3067 | "non-deterministic dtb nodes to guest"); | |
3068 | ||
33973e1e | 3069 | object_class_property_add_bool(oc, "dtb-kaslr-seed", |
5242876f JD |
3070 | virt_get_dtb_randomness, |
3071 | virt_set_dtb_randomness); | |
33973e1e | 3072 | object_class_property_set_description(oc, "dtb-kaslr-seed", |
5242876f | 3073 | "Deprecated synonym of dtb-randomness"); |
33973e1e | 3074 | |
90a66f48 | 3075 | object_class_property_add_str(oc, "x-oem-id", |
602b4582 MP |
3076 | virt_get_oem_id, |
3077 | virt_set_oem_id); | |
90a66f48 | 3078 | object_class_property_set_description(oc, "x-oem-id", |
602b4582 MP |
3079 | "Override the default value of field OEMID " |
3080 | "in ACPI table header." | |
3081 | "The string may be up to 6 bytes in size"); | |
3082 | ||
3083 | ||
90a66f48 | 3084 | object_class_property_add_str(oc, "x-oem-table-id", |
602b4582 MP |
3085 | virt_get_oem_table_id, |
3086 | virt_set_oem_table_id); | |
90a66f48 | 3087 | object_class_property_set_description(oc, "x-oem-table-id", |
602b4582 MP |
3088 | "Override the default value of field OEM Table ID " |
3089 | "in ACPI table header." | |
3090 | "The string may be up to 8 bytes in size"); | |
3091 | ||
ed796373 WH |
3092 | } |
3093 | ||
95159760 | 3094 | static void virt_instance_init(Object *obj) |
083a5890 GB |
3095 | { |
3096 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
ccc11b02 | 3097 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); |
083a5890 | 3098 | |
2d710006 PM |
3099 | /* EL3 is disabled by default on virt: this makes us consistent |
3100 | * between KVM and TCG for this board, and it also allows us to | |
3101 | * boot UEFI blobs which assume no TrustZone support. | |
3102 | */ | |
3103 | vms->secure = false; | |
5125f9cd | 3104 | |
f29cacfb PM |
3105 | /* EL2 is also disabled by default, for similar reasons */ |
3106 | vms->virt = false; | |
f29cacfb | 3107 | |
5125f9cd PF |
3108 | /* High memory is enabled by default */ |
3109 | vms->highmem = true; | |
f40408a9 | 3110 | vms->highmem_compact = !vmc->no_highmem_compact; |
36bf4ec8 | 3111 | vms->gic_version = VIRT_GIC_VERSION_NOSEL; |
9ac4ef77 | 3112 | |
17ec075a | 3113 | vms->highmem_ecam = !vmc->no_highmem_ecam; |
c8f008c4 | 3114 | vms->highmem_mmio = true; |
a63618b1 | 3115 | vms->highmem_redists = true; |
17ec075a | 3116 | |
ccc11b02 EA |
3117 | if (vmc->no_its) { |
3118 | vms->its = false; | |
3119 | } else { | |
3120 | /* Default allows ITS instantiation */ | |
3121 | vms->its = true; | |
0e5c1c9a SM |
3122 | |
3123 | if (vmc->no_tcg_its) { | |
3124 | vms->tcg_its = false; | |
3125 | } else { | |
3126 | vms->tcg_its = true; | |
3127 | } | |
ccc11b02 EA |
3128 | } |
3129 | ||
e24e3454 EA |
3130 | /* Default disallows iommu instantiation */ |
3131 | vms->iommu = VIRT_IOMMU_NONE; | |
e24e3454 | 3132 | |
6d7a8548 XW |
3133 | /* The default root bus is attached to iommu by default */ |
3134 | vms->default_bus_bypass_iommu = false; | |
3135 | ||
2afa8c85 DG |
3136 | /* Default disallows RAS instantiation */ |
3137 | vms->ras = false; | |
2afa8c85 | 3138 | |
6f4e1405 RH |
3139 | /* MTE is disabled by default. */ |
3140 | vms->mte = false; | |
6f4e1405 | 3141 | |
5242876f JD |
3142 | /* Supply kaslr-seed and rng-seed by default */ |
3143 | vms->dtb_randomness = true; | |
33973e1e | 3144 | |
9ac4ef77 | 3145 | vms->irqmap = a15irqmap; |
e0561e60 MA |
3146 | |
3147 | virt_flash_create(vms); | |
602b4582 MP |
3148 | |
3149 | vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); | |
3150 | vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); | |
083a5890 GB |
3151 | } |
3152 | ||
95159760 EH |
3153 | static const TypeInfo virt_machine_info = { |
3154 | .name = TYPE_VIRT_MACHINE, | |
3155 | .parent = TYPE_MACHINE, | |
3156 | .abstract = true, | |
3157 | .instance_size = sizeof(VirtMachineState), | |
3158 | .class_size = sizeof(VirtMachineClass), | |
3159 | .class_init = virt_machine_class_init, | |
bbac02f1 | 3160 | .instance_init = virt_instance_init, |
95159760 EH |
3161 | .interfaces = (InterfaceInfo[]) { |
3162 | { TYPE_HOTPLUG_HANDLER }, | |
3163 | { } | |
3164 | }, | |
3165 | }; | |
3166 | ||
3167 | static void machvirt_machine_init(void) | |
3168 | { | |
3169 | type_register_static(&virt_machine_info); | |
3170 | } | |
3171 | type_init(machvirt_machine_init); | |
3172 | ||
f9be4771 CH |
3173 | static void virt_machine_8_1_options(MachineClass *mc) |
3174 | { | |
3175 | } | |
3176 | DEFINE_VIRT_MACHINE_AS_LATEST(8, 1) | |
3177 | ||
db723c80 CH |
3178 | static void virt_machine_8_0_options(MachineClass *mc) |
3179 | { | |
f9be4771 CH |
3180 | virt_machine_8_1_options(mc); |
3181 | compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len); | |
db723c80 | 3182 | } |
f9be4771 | 3183 | DEFINE_VIRT_MACHINE(8, 0) |
db723c80 | 3184 | |
f514e147 CH |
3185 | static void virt_machine_7_2_options(MachineClass *mc) |
3186 | { | |
db723c80 CH |
3187 | virt_machine_8_0_options(mc); |
3188 | compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len); | |
f514e147 | 3189 | } |
db723c80 | 3190 | DEFINE_VIRT_MACHINE(7, 2) |
f514e147 | 3191 | |
0ca70366 CH |
3192 | static void virt_machine_7_1_options(MachineClass *mc) |
3193 | { | |
f40408a9 GS |
3194 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3195 | ||
f514e147 CH |
3196 | virt_machine_7_2_options(mc); |
3197 | compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); | |
f40408a9 GS |
3198 | /* Compact layout for high memory regions was introduced with 7.2 */ |
3199 | vmc->no_highmem_compact = true; | |
0ca70366 | 3200 | } |
f514e147 | 3201 | DEFINE_VIRT_MACHINE(7, 1) |
0ca70366 | 3202 | |
01854af2 CH |
3203 | static void virt_machine_7_0_options(MachineClass *mc) |
3204 | { | |
0ca70366 CH |
3205 | virt_machine_7_1_options(mc); |
3206 | compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); | |
01854af2 | 3207 | } |
0ca70366 | 3208 | DEFINE_VIRT_MACHINE(7, 0) |
01854af2 | 3209 | |
52e64f5b YW |
3210 | static void virt_machine_6_2_options(MachineClass *mc) |
3211 | { | |
09428204 RH |
3212 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3213 | ||
01854af2 CH |
3214 | virt_machine_7_0_options(mc); |
3215 | compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); | |
09428204 | 3216 | vmc->no_tcg_lpa2 = true; |
52e64f5b | 3217 | } |
01854af2 | 3218 | DEFINE_VIRT_MACHINE(6, 2) |
52e64f5b | 3219 | |
da7e13c0 CH |
3220 | static void virt_machine_6_1_options(MachineClass *mc) |
3221 | { | |
0e5c1c9a SM |
3222 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3223 | ||
52e64f5b YW |
3224 | virt_machine_6_2_options(mc); |
3225 | compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); | |
2b526199 | 3226 | mc->smp_props.prefer_sockets = true; |
31511b6f | 3227 | vmc->no_cpu_topology = true; |
0e5c1c9a SM |
3228 | |
3229 | /* qemu ITS was introduced with 6.2 */ | |
3230 | vmc->no_tcg_its = true; | |
da7e13c0 | 3231 | } |
52e64f5b | 3232 | DEFINE_VIRT_MACHINE(6, 1) |
da7e13c0 | 3233 | |
576a00bd CH |
3234 | static void virt_machine_6_0_options(MachineClass *mc) |
3235 | { | |
75228f05 HS |
3236 | virt_machine_6_1_options(mc); |
3237 | compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); | |
576a00bd | 3238 | } |
da7e13c0 | 3239 | DEFINE_VIRT_MACHINE(6, 0) |
576a00bd | 3240 | |
3ff3c5d3 CH |
3241 | static void virt_machine_5_2_options(MachineClass *mc) |
3242 | { | |
daa726d9 MU |
3243 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3244 | ||
576a00bd CH |
3245 | virt_machine_6_0_options(mc); |
3246 | compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); | |
daa726d9 | 3247 | vmc->no_secure_gpio = true; |
3ff3c5d3 | 3248 | } |
576a00bd | 3249 | DEFINE_VIRT_MACHINE(5, 2) |
3ff3c5d3 | 3250 | |
541aaa1d CH |
3251 | static void virt_machine_5_1_options(MachineClass *mc) |
3252 | { | |
68970d1e AJ |
3253 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3254 | ||
3ff3c5d3 CH |
3255 | virt_machine_5_2_options(mc); |
3256 | compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); | |
68970d1e | 3257 | vmc->no_kvm_steal_time = true; |
541aaa1d | 3258 | } |
3ff3c5d3 | 3259 | DEFINE_VIRT_MACHINE(5, 1) |
541aaa1d | 3260 | |
3eb74d20 CH |
3261 | static void virt_machine_5_0_options(MachineClass *mc) |
3262 | { | |
2c1fb4d5 AJ |
3263 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3264 | ||
541aaa1d | 3265 | virt_machine_5_1_options(mc); |
c6228807 | 3266 | compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); |
32a354dc | 3267 | mc->numa_mem_supported = true; |
2c1fb4d5 | 3268 | vmc->acpi_expose_flash = true; |
195784a0 | 3269 | mc->auto_enable_numa_with_memdev = false; |
3eb74d20 | 3270 | } |
541aaa1d | 3271 | DEFINE_VIRT_MACHINE(5, 0) |
3eb74d20 | 3272 | |
9aec2e52 CH |
3273 | static void virt_machine_4_2_options(MachineClass *mc) |
3274 | { | |
dea101a1 AJ |
3275 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3276 | ||
fa7c8e92 | 3277 | virt_machine_5_0_options(mc); |
5f258577 | 3278 | compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); |
dea101a1 | 3279 | vmc->kvm_no_adjvtime = true; |
9aec2e52 | 3280 | } |
3eb74d20 | 3281 | DEFINE_VIRT_MACHINE(4, 2) |
9aec2e52 | 3282 | |
9bf2650b CH |
3283 | static void virt_machine_4_1_options(MachineClass *mc) |
3284 | { | |
cff51ac9 SK |
3285 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3286 | ||
9aec2e52 CH |
3287 | virt_machine_4_2_options(mc); |
3288 | compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); | |
cff51ac9 | 3289 | vmc->no_ged = true; |
442da7dc | 3290 | mc->auto_enable_numa_with_memhp = false; |
9bf2650b | 3291 | } |
9aec2e52 | 3292 | DEFINE_VIRT_MACHINE(4, 1) |
9bf2650b | 3293 | |
84e060bf AW |
3294 | static void virt_machine_4_0_options(MachineClass *mc) |
3295 | { | |
9bf2650b CH |
3296 | virt_machine_4_1_options(mc); |
3297 | compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); | |
84e060bf | 3298 | } |
9bf2650b | 3299 | DEFINE_VIRT_MACHINE(4, 0) |
84e060bf | 3300 | |
22907d2b AJ |
3301 | static void virt_machine_3_1_options(MachineClass *mc) |
3302 | { | |
84e060bf | 3303 | virt_machine_4_0_options(mc); |
abd93cc7 | 3304 | compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); |
22907d2b | 3305 | } |
84e060bf | 3306 | DEFINE_VIRT_MACHINE(3, 1) |
22907d2b | 3307 | |
8ae9a1ca EA |
3308 | static void virt_machine_3_0_options(MachineClass *mc) |
3309 | { | |
22907d2b | 3310 | virt_machine_3_1_options(mc); |
ddb3235d | 3311 | compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); |
8ae9a1ca | 3312 | } |
22907d2b AJ |
3313 | DEFINE_VIRT_MACHINE(3, 0) |
3314 | ||
a2a05159 PM |
3315 | static void virt_machine_2_12_options(MachineClass *mc) |
3316 | { | |
17ec075a EA |
3317 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3318 | ||
8ae9a1ca | 3319 | virt_machine_3_0_options(mc); |
0d47310b | 3320 | compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); |
17ec075a | 3321 | vmc->no_highmem_ecam = true; |
b10fbd53 | 3322 | mc->max_cpus = 255; |
a2a05159 | 3323 | } |
8ae9a1ca | 3324 | DEFINE_VIRT_MACHINE(2, 12) |
a2a05159 | 3325 | |
79283dda EA |
3326 | static void virt_machine_2_11_options(MachineClass *mc) |
3327 | { | |
dfadc3bf WH |
3328 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3329 | ||
a2a05159 | 3330 | virt_machine_2_12_options(mc); |
43df70a9 | 3331 | compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); |
dfadc3bf | 3332 | vmc->smbios_old_sys_ver = true; |
79283dda | 3333 | } |
a2a05159 | 3334 | DEFINE_VIRT_MACHINE(2, 11) |
79283dda | 3335 | |
f22ab6cb EA |
3336 | static void virt_machine_2_10_options(MachineClass *mc) |
3337 | { | |
79283dda | 3338 | virt_machine_2_11_options(mc); |
503224f4 | 3339 | compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); |
846690de PM |
3340 | /* before 2.11 we never faulted accesses to bad addresses */ |
3341 | mc->ignore_memory_transaction_failures = true; | |
f22ab6cb | 3342 | } |
79283dda | 3343 | DEFINE_VIRT_MACHINE(2, 10) |
f22ab6cb | 3344 | |
e353aac5 PM |
3345 | static void virt_machine_2_9_options(MachineClass *mc) |
3346 | { | |
f22ab6cb | 3347 | virt_machine_2_10_options(mc); |
3e803152 | 3348 | compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); |
e353aac5 | 3349 | } |
f22ab6cb | 3350 | DEFINE_VIRT_MACHINE(2, 9) |
e353aac5 | 3351 | |
96b0439b AJ |
3352 | static void virt_machine_2_8_options(MachineClass *mc) |
3353 | { | |
156bc9a5 PM |
3354 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3355 | ||
e353aac5 | 3356 | virt_machine_2_9_options(mc); |
edc24ccd | 3357 | compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); |
156bc9a5 PM |
3358 | /* For 2.8 and earlier we falsely claimed in the DT that |
3359 | * our timers were edge-triggered, not level-triggered. | |
3360 | */ | |
3361 | vmc->claim_edge_triggered_timers = true; | |
96b0439b | 3362 | } |
e353aac5 | 3363 | DEFINE_VIRT_MACHINE(2, 8) |
96b0439b | 3364 | |
1287f2b3 AJ |
3365 | static void virt_machine_2_7_options(MachineClass *mc) |
3366 | { | |
2231f69b AJ |
3367 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3368 | ||
96b0439b | 3369 | virt_machine_2_8_options(mc); |
5a995064 | 3370 | compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); |
2231f69b AJ |
3371 | /* ITS was introduced with 2.8 */ |
3372 | vmc->no_its = true; | |
a2519ad1 PM |
3373 | /* Stick with 1K pages for migration compatibility */ |
3374 | mc->minimum_page_bits = 0; | |
1287f2b3 | 3375 | } |
96b0439b | 3376 | DEFINE_VIRT_MACHINE(2, 7) |
1287f2b3 | 3377 | |
ab093c3c | 3378 | static void virt_machine_2_6_options(MachineClass *mc) |
c2919690 | 3379 | { |
95eb49c8 AJ |
3380 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
3381 | ||
1287f2b3 | 3382 | virt_machine_2_7_options(mc); |
ff8f261f | 3383 | compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); |
95eb49c8 | 3384 | vmc->disallow_affinity_adjustment = true; |
1141d1eb WH |
3385 | /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ |
3386 | vmc->no_pmu = true; | |
c2919690 | 3387 | } |
1287f2b3 | 3388 | DEFINE_VIRT_MACHINE(2, 6) |