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f5fdcd6e PM |
1 | /* |
2 | * ARM mach-virt emulation | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Emulate a virtual board which works by passing Linux all the information | |
19 | * it needs about what devices are present via the device tree. | |
20 | * There are some restrictions about what we can do here: | |
21 | * + we can only present devices whose Linux drivers will work based | |
22 | * purely on the device tree with no platform data at all | |
23 | * + we want to present a very stripped-down minimalist platform, | |
24 | * both because this reduces the security attack surface from the guest | |
25 | * and also because it reduces our exposure to being broken when | |
26 | * the kernel updates its device tree bindings and requires further | |
27 | * information in a device binding that we aren't providing. | |
28 | * This is essentially the same approach kvmtool uses. | |
29 | */ | |
30 | ||
12b16722 | 31 | #include "qemu/osdep.h" |
da34e65c | 32 | #include "qapi/error.h" |
f5fdcd6e PM |
33 | #include "hw/sysbus.h" |
34 | #include "hw/arm/arm.h" | |
35 | #include "hw/arm/primecell.h" | |
afe0b380 | 36 | #include "hw/arm/virt.h" |
f5fdcd6e PM |
37 | #include "hw/devices.h" |
38 | #include "net/net.h" | |
fa1d36df | 39 | #include "sysemu/block-backend.h" |
f5fdcd6e | 40 | #include "sysemu/device_tree.h" |
9695200a | 41 | #include "sysemu/numa.h" |
f5fdcd6e PM |
42 | #include "sysemu/sysemu.h" |
43 | #include "sysemu/kvm.h" | |
44 | #include "hw/boards.h" | |
1287f2b3 | 45 | #include "hw/compat.h" |
acf82361 | 46 | #include "hw/loader.h" |
f5fdcd6e PM |
47 | #include "exec/address-spaces.h" |
48 | #include "qemu/bitops.h" | |
49 | #include "qemu/error-report.h" | |
4ab29b82 | 50 | #include "hw/pci-host/gpex.h" |
d7c2e2db | 51 | #include "hw/arm/virt-acpi-build.h" |
5f7a5a0e EA |
52 | #include "hw/arm/sysbus-fdt.h" |
53 | #include "hw/platform-bus.h" | |
decf4f80 | 54 | #include "hw/arm/fdt.h" |
95eb49c8 AJ |
55 | #include "hw/intc/arm_gic.h" |
56 | #include "hw/intc/arm_gicv3_common.h" | |
e6fbcbc4 | 57 | #include "kvm_arm.h" |
c30e1565 | 58 | #include "hw/smbios/smbios.h" |
b92ad394 | 59 | #include "qapi/visitor.h" |
3e6ebb64 | 60 | #include "standard-headers/linux/input.h" |
f5fdcd6e | 61 | |
f5fdcd6e | 62 | /* Number of external interrupt lines to configure the GIC with */ |
5f7a5a0e | 63 | #define NUM_IRQS 256 |
f5fdcd6e | 64 | |
5f7a5a0e EA |
65 | #define PLATFORM_BUS_NUM_IRQS 64 |
66 | ||
67 | static ARMPlatformBusSystemParams platform_bus_params; | |
68 | ||
c2919690 GB |
69 | typedef struct { |
70 | MachineClass parent; | |
95eb49c8 | 71 | bool disallow_affinity_adjustment; |
2231f69b | 72 | bool no_its; |
1141d1eb | 73 | bool no_pmu; |
c2919690 GB |
74 | } VirtMachineClass; |
75 | ||
76 | typedef struct { | |
77 | MachineState parent; | |
083a5890 | 78 | bool secure; |
5125f9cd | 79 | bool highmem; |
b92ad394 | 80 | int32_t gic_version; |
9ac4ef77 PM |
81 | struct arm_boot_info bootinfo; |
82 | const MemMapEntry *memmap; | |
83 | const int *irqmap; | |
84 | int smp_cpus; | |
85 | void *fdt; | |
86 | int fdt_size; | |
87 | uint32_t clock_phandle; | |
88 | uint32_t gic_phandle; | |
89 | uint32_t msi_phandle; | |
90 | bool using_psci; | |
c2919690 GB |
91 | } VirtMachineState; |
92 | ||
98cec76a | 93 | #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") |
c2919690 GB |
94 | #define VIRT_MACHINE(obj) \ |
95 | OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE) | |
96 | #define VIRT_MACHINE_GET_CLASS(obj) \ | |
97 | OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE) | |
98 | #define VIRT_MACHINE_CLASS(klass) \ | |
99 | OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE) | |
100 | ||
ab093c3c | 101 | |
3356ebce | 102 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ |
ab093c3c AJ |
103 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ |
104 | void *data) \ | |
105 | { \ | |
106 | MachineClass *mc = MACHINE_CLASS(oc); \ | |
107 | virt_machine_##major##_##minor##_options(mc); \ | |
108 | mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \ | |
3356ebce AJ |
109 | if (latest) { \ |
110 | mc->alias = "virt"; \ | |
111 | } \ | |
ab093c3c AJ |
112 | } \ |
113 | static const TypeInfo machvirt_##major##_##minor##_info = { \ | |
114 | .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \ | |
115 | .parent = TYPE_VIRT_MACHINE, \ | |
116 | .instance_init = virt_##major##_##minor##_instance_init, \ | |
117 | .class_init = virt_##major##_##minor##_class_init, \ | |
118 | }; \ | |
119 | static void machvirt_machine_##major##_##minor##_init(void) \ | |
120 | { \ | |
121 | type_register_static(&machvirt_##major##_##minor##_info); \ | |
122 | } \ | |
123 | type_init(machvirt_machine_##major##_##minor##_init); | |
124 | ||
3356ebce AJ |
125 | #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \ |
126 | DEFINE_VIRT_MACHINE_LATEST(major, minor, true) | |
127 | #define DEFINE_VIRT_MACHINE(major, minor) \ | |
128 | DEFINE_VIRT_MACHINE_LATEST(major, minor, false) | |
129 | ||
ab093c3c | 130 | |
71c27684 PM |
131 | /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means |
132 | * RAM can go up to the 256GB mark, leaving 256GB of the physical | |
133 | * address space unallocated and free for future use between 256G and 512G. | |
134 | * If we need to provide more RAM to VMs in the future then we need to: | |
135 | * * allocate a second bank of RAM starting at 2TB and working up | |
136 | * * fix the DT and ACPI table generation code in QEMU to correctly | |
137 | * report two split lumps of RAM to the guest | |
138 | * * fix KVM in the host kernel to allow guests with >40 bit address spaces | |
139 | * (We don't want to fill all the way up to 512GB with RAM because | |
140 | * we might want it for non-RAM purposes later. Conversely it seems | |
141 | * reasonable to assume that anybody configuring a VM with a quarter | |
142 | * of a terabyte of RAM will be doing it on a host with more than a | |
143 | * terabyte of physical address space.) | |
144 | */ | |
145 | #define RAMLIMIT_GB 255 | |
146 | #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) | |
147 | ||
f5fdcd6e PM |
148 | /* Addresses and sizes of our components. |
149 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | |
150 | * 128MB..256MB is used for miscellaneous device I/O. | |
151 | * 256MB..1GB is reserved for possible future PCI support (ie where the | |
152 | * PCI memory window will go if we add a PCI host controller). | |
153 | * 1GB and up is RAM (which may happily spill over into the | |
154 | * high memory region beyond 4GB). | |
155 | * This represents a compromise between how much RAM can be given to | |
156 | * a 32 bit VM and leaving space for expansion and in particular for PCI. | |
6e411af9 PM |
157 | * Note that devices should generally be placed at multiples of 0x10000, |
158 | * to accommodate guests using 64K pages. | |
f5fdcd6e PM |
159 | */ |
160 | static const MemMapEntry a15memmap[] = { | |
161 | /* Space up to 0x8000000 is reserved for a boot ROM */ | |
94edf02c EA |
162 | [VIRT_FLASH] = { 0, 0x08000000 }, |
163 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | |
f5fdcd6e | 164 | /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */ |
94edf02c EA |
165 | [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 }, |
166 | [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 }, | |
167 | [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }, | |
b92ad394 PF |
168 | /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ |
169 | [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 }, | |
170 | /* This redistributor space allows up to 2*64kB*123 CPUs */ | |
171 | [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, | |
94edf02c EA |
172 | [VIRT_UART] = { 0x09000000, 0x00001000 }, |
173 | [VIRT_RTC] = { 0x09010000, 0x00001000 }, | |
0b341a85 | 174 | [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, |
b0a3721e | 175 | [VIRT_GPIO] = { 0x09030000, 0x00001000 }, |
3df708eb | 176 | [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 }, |
94edf02c | 177 | [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, |
f5fdcd6e | 178 | /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ |
94edf02c | 179 | [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, |
83ec1923 | 180 | [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 }, |
94edf02c EA |
181 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, |
182 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | |
183 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | |
71c27684 | 184 | [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, |
5125f9cd PF |
185 | /* Second PCIe window, 512GB wide at the 512GB boundary */ |
186 | [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, | |
f5fdcd6e PM |
187 | }; |
188 | ||
189 | static const int a15irqmap[] = { | |
190 | [VIRT_UART] = 1, | |
6e411af9 | 191 | [VIRT_RTC] = 2, |
4ab29b82 | 192 | [VIRT_PCIE] = 3, /* ... to 6 */ |
b0a3721e | 193 | [VIRT_GPIO] = 7, |
3df708eb | 194 | [VIRT_SECURE_UART] = 8, |
f5fdcd6e | 195 | [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ |
bd204e63 | 196 | [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ |
5f7a5a0e | 197 | [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ |
f5fdcd6e PM |
198 | }; |
199 | ||
9ac4ef77 PM |
200 | static const char *valid_cpus[] = { |
201 | "cortex-a15", | |
202 | "cortex-a53", | |
203 | "cortex-a57", | |
204 | "host", | |
205 | NULL | |
f5fdcd6e PM |
206 | }; |
207 | ||
9ac4ef77 | 208 | static bool cpuname_valid(const char *cpu) |
f5fdcd6e PM |
209 | { |
210 | int i; | |
211 | ||
9ac4ef77 PM |
212 | for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) { |
213 | if (strcmp(cpu, valid_cpus[i]) == 0) { | |
214 | return true; | |
f5fdcd6e PM |
215 | } |
216 | } | |
9ac4ef77 | 217 | return false; |
f5fdcd6e PM |
218 | } |
219 | ||
9ac4ef77 | 220 | static void create_fdt(VirtMachineState *vbi) |
f5fdcd6e PM |
221 | { |
222 | void *fdt = create_device_tree(&vbi->fdt_size); | |
223 | ||
224 | if (!fdt) { | |
225 | error_report("create_device_tree() failed"); | |
226 | exit(1); | |
227 | } | |
228 | ||
229 | vbi->fdt = fdt; | |
230 | ||
231 | /* Header */ | |
5a4348d1 PC |
232 | qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); |
233 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
234 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
f5fdcd6e PM |
235 | |
236 | /* | |
237 | * /chosen and /memory nodes must exist for load_dtb | |
238 | * to fill in necessary properties later | |
239 | */ | |
5a4348d1 PC |
240 | qemu_fdt_add_subnode(fdt, "/chosen"); |
241 | qemu_fdt_add_subnode(fdt, "/memory"); | |
242 | qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); | |
f5fdcd6e PM |
243 | |
244 | /* Clock node, for the benefit of the UART. The kernel device tree | |
245 | * binding documentation claims the PL011 node clock properties are | |
246 | * optional but in practice if you omit them the kernel refuses to | |
247 | * probe for the device. | |
248 | */ | |
5a4348d1 PC |
249 | vbi->clock_phandle = qemu_fdt_alloc_phandle(fdt); |
250 | qemu_fdt_add_subnode(fdt, "/apb-pclk"); | |
251 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); | |
252 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); | |
253 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); | |
254 | qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", | |
f5fdcd6e | 255 | "clk24mhz"); |
5a4348d1 | 256 | qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vbi->clock_phandle); |
f5fdcd6e | 257 | |
06955739 PS |
258 | } |
259 | ||
9ac4ef77 | 260 | static void fdt_add_psci_node(const VirtMachineState *vbi) |
06955739 | 261 | { |
211b0169 RH |
262 | uint32_t cpu_suspend_fn; |
263 | uint32_t cpu_off_fn; | |
264 | uint32_t cpu_on_fn; | |
265 | uint32_t migrate_fn; | |
06955739 PS |
266 | void *fdt = vbi->fdt; |
267 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); | |
268 | ||
4824a61a PM |
269 | if (!vbi->using_psci) { |
270 | return; | |
271 | } | |
272 | ||
211b0169 RH |
273 | qemu_fdt_add_subnode(fdt, "/psci"); |
274 | if (armcpu->psci_version == 2) { | |
275 | const char comp[] = "arm,psci-0.2\0arm,psci"; | |
276 | qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); | |
863714ba | 277 | |
211b0169 RH |
278 | cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF; |
279 | if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) { | |
280 | cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND; | |
281 | cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON; | |
282 | migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE; | |
283 | } else { | |
284 | cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND; | |
285 | cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON; | |
286 | migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE; | |
06955739 | 287 | } |
211b0169 RH |
288 | } else { |
289 | qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci"); | |
06955739 | 290 | |
211b0169 RH |
291 | cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND; |
292 | cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF; | |
293 | cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON; | |
294 | migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE; | |
f5fdcd6e | 295 | } |
211b0169 RH |
296 | |
297 | /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer | |
298 | * to the instruction that should be used to invoke PSCI functions. | |
299 | * However, the device tree binding uses 'method' instead, so that is | |
300 | * what we should use here. | |
301 | */ | |
302 | qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc"); | |
303 | ||
304 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn); | |
305 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn); | |
306 | qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn); | |
307 | qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn); | |
f5fdcd6e PM |
308 | } |
309 | ||
9ac4ef77 | 310 | static void fdt_add_timer_nodes(const VirtMachineState *vbi, int gictype) |
f5fdcd6e PM |
311 | { |
312 | /* Note that on A15 h/w these interrupts are level-triggered, | |
313 | * but for the GIC implementation provided by both QEMU and KVM | |
314 | * they are edge-triggered. | |
315 | */ | |
b32a9509 | 316 | ARMCPU *armcpu; |
f5fdcd6e PM |
317 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; |
318 | ||
b92ad394 PF |
319 | if (gictype == 2) { |
320 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | |
321 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
322 | (1 << vbi->smp_cpus) - 1); | |
323 | } | |
f5fdcd6e | 324 | |
5a4348d1 | 325 | qemu_fdt_add_subnode(vbi->fdt, "/timer"); |
b32a9509 CF |
326 | |
327 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
328 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
329 | const char compat[] = "arm,armv8-timer\0arm,armv7-timer"; | |
330 | qemu_fdt_setprop(vbi->fdt, "/timer", "compatible", | |
331 | compat, sizeof(compat)); | |
332 | } else { | |
333 | qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible", | |
334 | "arm,armv7-timer"); | |
335 | } | |
caa49adb | 336 | qemu_fdt_setprop(vbi->fdt, "/timer", "always-on", NULL, 0); |
5a4348d1 | 337 | qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts", |
ee246400 SZ |
338 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags, |
339 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags, | |
340 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, | |
341 | GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags); | |
f5fdcd6e PM |
342 | } |
343 | ||
9ac4ef77 | 344 | static void fdt_add_cpu_nodes(const VirtMachineState *vbi) |
f5fdcd6e PM |
345 | { |
346 | int cpu; | |
8d45c54d | 347 | int addr_cells = 1; |
9695200a | 348 | unsigned int i; |
8d45c54d PF |
349 | |
350 | /* | |
351 | * From Documentation/devicetree/bindings/arm/cpus.txt | |
352 | * On ARM v8 64-bit systems value should be set to 2, | |
353 | * that corresponds to the MPIDR_EL1 register size. | |
354 | * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
355 | * in the system, #address-cells can be set to 1, since | |
356 | * MPIDR_EL1[63:32] bits are not used for CPUs | |
357 | * identification. | |
358 | * | |
359 | * Here we actually don't know whether our system is 32- or 64-bit one. | |
360 | * The simplest way to go is to examine affinity IDs of all our CPUs. If | |
361 | * at least one of them has Aff3 populated, we set #address-cells to 2. | |
362 | */ | |
363 | for (cpu = 0; cpu < vbi->smp_cpus; cpu++) { | |
364 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
365 | ||
366 | if (armcpu->mp_affinity & ARM_AFF3_MASK) { | |
367 | addr_cells = 2; | |
368 | break; | |
369 | } | |
370 | } | |
f5fdcd6e | 371 | |
5a4348d1 | 372 | qemu_fdt_add_subnode(vbi->fdt, "/cpus"); |
8d45c54d | 373 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells); |
5a4348d1 | 374 | qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0); |
f5fdcd6e PM |
375 | |
376 | for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) { | |
377 | char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); | |
378 | ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); | |
379 | ||
5a4348d1 PC |
380 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
381 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "cpu"); | |
382 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", | |
f5fdcd6e PM |
383 | armcpu->dtb_compatible); |
384 | ||
4824a61a | 385 | if (vbi->using_psci && vbi->smp_cpus > 1) { |
5a4348d1 | 386 | qemu_fdt_setprop_string(vbi->fdt, nodename, |
f5fdcd6e PM |
387 | "enable-method", "psci"); |
388 | } | |
389 | ||
8d45c54d PF |
390 | if (addr_cells == 2) { |
391 | qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", | |
392 | armcpu->mp_affinity); | |
393 | } else { | |
394 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", | |
395 | armcpu->mp_affinity); | |
396 | } | |
397 | ||
6bea1ddf IM |
398 | i = numa_get_node_for_cpu(cpu); |
399 | if (i < nb_numa_nodes) { | |
400 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "numa-node-id", i); | |
9695200a SZ |
401 | } |
402 | ||
f5fdcd6e PM |
403 | g_free(nodename); |
404 | } | |
405 | } | |
406 | ||
9ac4ef77 | 407 | static void fdt_add_its_gic_node(VirtMachineState *vbi) |
02f98731 PF |
408 | { |
409 | vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); | |
410 | qemu_fdt_add_subnode(vbi->fdt, "/intc/its"); | |
411 | qemu_fdt_setprop_string(vbi->fdt, "/intc/its", "compatible", | |
412 | "arm,gic-v3-its"); | |
413 | qemu_fdt_setprop(vbi->fdt, "/intc/its", "msi-controller", NULL, 0); | |
414 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/its", "reg", | |
415 | 2, vbi->memmap[VIRT_GIC_ITS].base, | |
416 | 2, vbi->memmap[VIRT_GIC_ITS].size); | |
417 | qemu_fdt_setprop_cell(vbi->fdt, "/intc/its", "phandle", vbi->msi_phandle); | |
418 | } | |
419 | ||
9ac4ef77 | 420 | static void fdt_add_v2m_gic_node(VirtMachineState *vbi) |
f5fdcd6e | 421 | { |
02f98731 | 422 | vbi->msi_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
bd204e63 CD |
423 | qemu_fdt_add_subnode(vbi->fdt, "/intc/v2m"); |
424 | qemu_fdt_setprop_string(vbi->fdt, "/intc/v2m", "compatible", | |
425 | "arm,gic-v2m-frame"); | |
426 | qemu_fdt_setprop(vbi->fdt, "/intc/v2m", "msi-controller", NULL, 0); | |
427 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc/v2m", "reg", | |
428 | 2, vbi->memmap[VIRT_GIC_V2M].base, | |
429 | 2, vbi->memmap[VIRT_GIC_V2M].size); | |
02f98731 | 430 | qemu_fdt_setprop_cell(vbi->fdt, "/intc/v2m", "phandle", vbi->msi_phandle); |
bd204e63 | 431 | } |
f5fdcd6e | 432 | |
9ac4ef77 | 433 | static void fdt_add_gic_node(VirtMachineState *vbi, int type) |
bd204e63 | 434 | { |
747d009d CD |
435 | vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
436 | qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle); | |
f5fdcd6e | 437 | |
5a4348d1 | 438 | qemu_fdt_add_subnode(vbi->fdt, "/intc"); |
5a4348d1 PC |
439 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#interrupt-cells", 3); |
440 | qemu_fdt_setprop(vbi->fdt, "/intc", "interrupt-controller", NULL, 0); | |
dfd90a87 CD |
441 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#address-cells", 0x2); |
442 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "#size-cells", 0x2); | |
443 | qemu_fdt_setprop(vbi->fdt, "/intc", "ranges", NULL, 0); | |
b92ad394 PF |
444 | if (type == 3) { |
445 | qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", | |
446 | "arm,gic-v3"); | |
447 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", | |
448 | 2, vbi->memmap[VIRT_GIC_DIST].base, | |
449 | 2, vbi->memmap[VIRT_GIC_DIST].size, | |
450 | 2, vbi->memmap[VIRT_GIC_REDIST].base, | |
451 | 2, vbi->memmap[VIRT_GIC_REDIST].size); | |
452 | } else { | |
453 | /* 'cortex-a15-gic' means 'GIC v2' */ | |
454 | qemu_fdt_setprop_string(vbi->fdt, "/intc", "compatible", | |
455 | "arm,cortex-a15-gic"); | |
456 | qemu_fdt_setprop_sized_cells(vbi->fdt, "/intc", "reg", | |
457 | 2, vbi->memmap[VIRT_GIC_DIST].base, | |
458 | 2, vbi->memmap[VIRT_GIC_DIST].size, | |
459 | 2, vbi->memmap[VIRT_GIC_CPU].base, | |
460 | 2, vbi->memmap[VIRT_GIC_CPU].size); | |
461 | } | |
462 | ||
747d009d | 463 | qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle); |
f5fdcd6e PM |
464 | } |
465 | ||
9ac4ef77 | 466 | static void fdt_add_pmu_nodes(const VirtMachineState *vbi, int gictype) |
01fe6b60 SZ |
467 | { |
468 | CPUState *cpu; | |
469 | ARMCPU *armcpu; | |
470 | uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
471 | ||
472 | CPU_FOREACH(cpu) { | |
473 | armcpu = ARM_CPU(cpu); | |
929e754d | 474 | if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU) || |
01fe6b60 SZ |
475 | !kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ))) { |
476 | return; | |
477 | } | |
478 | } | |
479 | ||
480 | if (gictype == 2) { | |
481 | irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, | |
482 | GIC_FDT_IRQ_PPI_CPU_WIDTH, | |
483 | (1 << vbi->smp_cpus) - 1); | |
484 | } | |
485 | ||
486 | armcpu = ARM_CPU(qemu_get_cpu(0)); | |
487 | qemu_fdt_add_subnode(vbi->fdt, "/pmu"); | |
488 | if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { | |
489 | const char compat[] = "arm,armv8-pmuv3"; | |
490 | qemu_fdt_setprop(vbi->fdt, "/pmu", "compatible", | |
491 | compat, sizeof(compat)); | |
492 | qemu_fdt_setprop_cells(vbi->fdt, "/pmu", "interrupts", | |
493 | GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags); | |
494 | } | |
495 | } | |
496 | ||
9ac4ef77 | 497 | static void create_its(VirtMachineState *vbi, DeviceState *gicdev) |
02f98731 PF |
498 | { |
499 | const char *itsclass = its_class_name(); | |
500 | DeviceState *dev; | |
501 | ||
502 | if (!itsclass) { | |
503 | /* Do nothing if not supported */ | |
504 | return; | |
505 | } | |
506 | ||
507 | dev = qdev_create(NULL, itsclass); | |
508 | ||
509 | object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3", | |
510 | &error_abort); | |
511 | qdev_init_nofail(dev); | |
512 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_ITS].base); | |
513 | ||
514 | fdt_add_its_gic_node(vbi); | |
515 | } | |
516 | ||
9ac4ef77 | 517 | static void create_v2m(VirtMachineState *vbi, qemu_irq *pic) |
bd204e63 CD |
518 | { |
519 | int i; | |
520 | int irq = vbi->irqmap[VIRT_GIC_V2M]; | |
521 | DeviceState *dev; | |
522 | ||
523 | dev = qdev_create(NULL, "arm-gicv2m"); | |
524 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vbi->memmap[VIRT_GIC_V2M].base); | |
525 | qdev_prop_set_uint32(dev, "base-spi", irq); | |
526 | qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); | |
527 | qdev_init_nofail(dev); | |
528 | ||
529 | for (i = 0; i < NUM_GICV2M_SPIS; i++) { | |
530 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
531 | } | |
532 | ||
533 | fdt_add_v2m_gic_node(vbi); | |
534 | } | |
535 | ||
9ac4ef77 | 536 | static void create_gic(VirtMachineState *vbi, qemu_irq *pic, int type, |
2231f69b | 537 | bool secure, bool no_its) |
64204743 | 538 | { |
b92ad394 | 539 | /* We create a standalone GIC */ |
64204743 PM |
540 | DeviceState *gicdev; |
541 | SysBusDevice *gicbusdev; | |
e6fbcbc4 | 542 | const char *gictype; |
64204743 PM |
543 | int i; |
544 | ||
b92ad394 | 545 | gictype = (type == 3) ? gicv3_class_name() : gic_class_name(); |
64204743 PM |
546 | |
547 | gicdev = qdev_create(NULL, gictype); | |
b92ad394 | 548 | qdev_prop_set_uint32(gicdev, "revision", type); |
64204743 PM |
549 | qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); |
550 | /* Note that the num-irq property counts both internal and external | |
551 | * interrupts; there are always 32 of the former (mandated by GIC spec). | |
552 | */ | |
553 | qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); | |
0e21f183 PM |
554 | if (!kvm_irqchip_in_kernel()) { |
555 | qdev_prop_set_bit(gicdev, "has-security-extensions", secure); | |
556 | } | |
64204743 PM |
557 | qdev_init_nofail(gicdev); |
558 | gicbusdev = SYS_BUS_DEVICE(gicdev); | |
559 | sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base); | |
b92ad394 PF |
560 | if (type == 3) { |
561 | sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_REDIST].base); | |
562 | } else { | |
563 | sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base); | |
564 | } | |
64204743 PM |
565 | |
566 | /* Wire the outputs from each CPU's generic timer to the | |
567 | * appropriate GIC PPI inputs, and the GIC's IRQ output to | |
568 | * the CPU's IRQ input. | |
569 | */ | |
570 | for (i = 0; i < smp_cpus; i++) { | |
571 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); | |
0e3e858f | 572 | int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; |
a007b1f8 PM |
573 | int irq; |
574 | /* Mapping from the output timer irq lines from the CPU to the | |
575 | * GIC PPI inputs we use for the virt board. | |
64204743 | 576 | */ |
a007b1f8 PM |
577 | const int timer_irq[] = { |
578 | [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | |
579 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | |
580 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | |
581 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | |
582 | }; | |
583 | ||
584 | for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | |
585 | qdev_connect_gpio_out(cpudev, irq, | |
586 | qdev_get_gpio_in(gicdev, | |
587 | ppibase + timer_irq[irq])); | |
588 | } | |
64204743 PM |
589 | |
590 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
8e7b4ca0 GB |
591 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
592 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
64204743 PM |
593 | } |
594 | ||
595 | for (i = 0; i < NUM_IRQS; i++) { | |
596 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
597 | } | |
598 | ||
b92ad394 | 599 | fdt_add_gic_node(vbi, type); |
bd204e63 | 600 | |
2231f69b | 601 | if (type == 3 && !no_its) { |
02f98731 | 602 | create_its(vbi, gicdev); |
2231f69b | 603 | } else if (type == 2) { |
b92ad394 PF |
604 | create_v2m(vbi, pic); |
605 | } | |
64204743 PM |
606 | } |
607 | ||
9ac4ef77 | 608 | static void create_uart(const VirtMachineState *vbi, qemu_irq *pic, int uart, |
9bbbf649 | 609 | MemoryRegion *mem, CharDriverState *chr) |
f5fdcd6e PM |
610 | { |
611 | char *nodename; | |
3df708eb PM |
612 | hwaddr base = vbi->memmap[uart].base; |
613 | hwaddr size = vbi->memmap[uart].size; | |
614 | int irq = vbi->irqmap[uart]; | |
f5fdcd6e PM |
615 | const char compat[] = "arm,pl011\0arm,primecell"; |
616 | const char clocknames[] = "uartclk\0apb_pclk"; | |
3df708eb PM |
617 | DeviceState *dev = qdev_create(NULL, "pl011"); |
618 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | |
f5fdcd6e | 619 | |
9bbbf649 | 620 | qdev_prop_set_chr(dev, "chardev", chr); |
3df708eb PM |
621 | qdev_init_nofail(dev); |
622 | memory_region_add_subregion(mem, base, | |
623 | sysbus_mmio_get_region(s, 0)); | |
624 | sysbus_connect_irq(s, 0, pic[irq]); | |
f5fdcd6e PM |
625 | |
626 | nodename = g_strdup_printf("/pl011@%" PRIx64, base); | |
5a4348d1 | 627 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
f5fdcd6e | 628 | /* Note that we can't use setprop_string because of the embedded NUL */ |
5a4348d1 | 629 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", |
f5fdcd6e | 630 | compat, sizeof(compat)); |
5a4348d1 | 631 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
f5fdcd6e | 632 | 2, base, 2, size); |
5a4348d1 | 633 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", |
f5fdcd6e | 634 | GIC_FDT_IRQ_TYPE_SPI, irq, |
0be969a2 | 635 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
5a4348d1 | 636 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "clocks", |
f5fdcd6e | 637 | vbi->clock_phandle, vbi->clock_phandle); |
5a4348d1 | 638 | qemu_fdt_setprop(vbi->fdt, nodename, "clock-names", |
f5fdcd6e | 639 | clocknames, sizeof(clocknames)); |
f022b8e9 | 640 | |
3df708eb PM |
641 | if (uart == VIRT_UART) { |
642 | qemu_fdt_setprop_string(vbi->fdt, "/chosen", "stdout-path", nodename); | |
643 | } else { | |
644 | /* Mark as not usable by the normal world */ | |
645 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
646 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
647 | } | |
648 | ||
f5fdcd6e PM |
649 | g_free(nodename); |
650 | } | |
651 | ||
9ac4ef77 | 652 | static void create_rtc(const VirtMachineState *vbi, qemu_irq *pic) |
6e411af9 PM |
653 | { |
654 | char *nodename; | |
655 | hwaddr base = vbi->memmap[VIRT_RTC].base; | |
656 | hwaddr size = vbi->memmap[VIRT_RTC].size; | |
657 | int irq = vbi->irqmap[VIRT_RTC]; | |
658 | const char compat[] = "arm,pl031\0arm,primecell"; | |
659 | ||
660 | sysbus_create_simple("pl031", base, pic[irq]); | |
661 | ||
662 | nodename = g_strdup_printf("/pl031@%" PRIx64, base); | |
663 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
664 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); | |
665 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
666 | 2, base, 2, size); | |
667 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
668 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
0be969a2 | 669 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
6e411af9 PM |
670 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); |
671 | qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); | |
672 | g_free(nodename); | |
673 | } | |
674 | ||
94f02c5e | 675 | static DeviceState *gpio_key_dev; |
4bedd849 SZ |
676 | static void virt_powerdown_req(Notifier *n, void *opaque) |
677 | { | |
678 | /* use gpio Pin 3 for power button event */ | |
94f02c5e | 679 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
4bedd849 SZ |
680 | } |
681 | ||
682 | static Notifier virt_system_powerdown_notifier = { | |
683 | .notify = virt_powerdown_req | |
684 | }; | |
685 | ||
9ac4ef77 | 686 | static void create_gpio(const VirtMachineState *vbi, qemu_irq *pic) |
b0a3721e SZ |
687 | { |
688 | char *nodename; | |
94f02c5e | 689 | DeviceState *pl061_dev; |
b0a3721e SZ |
690 | hwaddr base = vbi->memmap[VIRT_GPIO].base; |
691 | hwaddr size = vbi->memmap[VIRT_GPIO].size; | |
692 | int irq = vbi->irqmap[VIRT_GPIO]; | |
693 | const char compat[] = "arm,pl061\0arm,primecell"; | |
694 | ||
4bedd849 | 695 | pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); |
b0a3721e | 696 | |
3e6ebb64 | 697 | uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt); |
b0a3721e SZ |
698 | nodename = g_strdup_printf("/pl061@%" PRIx64, base); |
699 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
700 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
701 | 2, base, 2, size); | |
702 | qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat)); | |
703 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2); | |
704 | qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0); | |
705 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
706 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
707 | GIC_FDT_IRQ_FLAGS_LEVEL_HI); | |
708 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle); | |
709 | qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk"); | |
3e6ebb64 SZ |
710 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle); |
711 | ||
94f02c5e SZ |
712 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
713 | qdev_get_gpio_in(pl061_dev, 3)); | |
3e6ebb64 SZ |
714 | qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys"); |
715 | qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys"); | |
716 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0); | |
717 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1); | |
718 | ||
719 | qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff"); | |
720 | qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff", | |
721 | "label", "GPIO Key Poweroff"); | |
722 | qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", | |
723 | KEY_POWER); | |
724 | qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff", | |
725 | "gpios", phandle, 3, 0); | |
b0a3721e | 726 | |
4bedd849 SZ |
727 | /* connect powerdown request */ |
728 | qemu_register_powerdown_notifier(&virt_system_powerdown_notifier); | |
729 | ||
b0a3721e SZ |
730 | g_free(nodename); |
731 | } | |
732 | ||
9ac4ef77 | 733 | static void create_virtio_devices(const VirtMachineState *vbi, qemu_irq *pic) |
f5fdcd6e PM |
734 | { |
735 | int i; | |
736 | hwaddr size = vbi->memmap[VIRT_MMIO].size; | |
737 | ||
587078f0 LE |
738 | /* We create the transports in forwards order. Since qbus_realize() |
739 | * prepends (not appends) new child buses, the incrementing loop below will | |
740 | * create a list of virtio-mmio buses with decreasing base addresses. | |
741 | * | |
742 | * When a -device option is processed from the command line, | |
743 | * qbus_find_recursive() picks the next free virtio-mmio bus in forwards | |
744 | * order. The upshot is that -device options in increasing command line | |
745 | * order are mapped to virtio-mmio buses with decreasing base addresses. | |
746 | * | |
747 | * When this code was originally written, that arrangement ensured that the | |
748 | * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to | |
749 | * the first -device on the command line. (The end-to-end order is a | |
750 | * function of this loop, qbus_realize(), qbus_find_recursive(), and the | |
751 | * guest kernel's name-to-address assignment strategy.) | |
752 | * | |
753 | * Meanwhile, the kernel's traversal seems to have been reversed; see eg. | |
754 | * the message, if not necessarily the code, of commit 70161ff336. | |
755 | * Therefore the loop now establishes the inverse of the original intent. | |
756 | * | |
757 | * Unfortunately, we can't counteract the kernel change by reversing the | |
758 | * loop; it would break existing command lines. | |
759 | * | |
760 | * In any case, the kernel makes no guarantee about the stability of | |
761 | * enumeration order of virtio devices (as demonstrated by it changing | |
762 | * between kernel versions). For reliable and stable identification | |
763 | * of disks users must use UUIDs or similar mechanisms. | |
f5fdcd6e PM |
764 | */ |
765 | for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) { | |
766 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
767 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
768 | ||
769 | sysbus_create_simple("virtio-mmio", base, pic[irq]); | |
770 | } | |
771 | ||
587078f0 LE |
772 | /* We add dtb nodes in reverse order so that they appear in the finished |
773 | * device tree lowest address first. | |
774 | * | |
775 | * Note that this mapping is independent of the loop above. The previous | |
776 | * loop influences virtio device to virtio transport assignment, whereas | |
777 | * this loop controls how virtio transports are laid out in the dtb. | |
778 | */ | |
f5fdcd6e PM |
779 | for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { |
780 | char *nodename; | |
781 | int irq = vbi->irqmap[VIRT_MMIO] + i; | |
782 | hwaddr base = vbi->memmap[VIRT_MMIO].base + i * size; | |
783 | ||
784 | nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base); | |
5a4348d1 PC |
785 | qemu_fdt_add_subnode(vbi->fdt, nodename); |
786 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
787 | "compatible", "virtio,mmio"); | |
788 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
789 | 2, base, 2, size); | |
790 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts", | |
791 | GIC_FDT_IRQ_TYPE_SPI, irq, | |
792 | GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); | |
f5fdcd6e PM |
793 | g_free(nodename); |
794 | } | |
795 | } | |
796 | ||
acf82361 | 797 | static void create_one_flash(const char *name, hwaddr flashbase, |
738a5d9f PM |
798 | hwaddr flashsize, const char *file, |
799 | MemoryRegion *sysmem) | |
acf82361 PM |
800 | { |
801 | /* Create and map a single flash device. We use the same | |
802 | * parameters as the flash devices on the Versatile Express board. | |
803 | */ | |
804 | DriveInfo *dinfo = drive_get_next(IF_PFLASH); | |
805 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
16f4a8dc | 806 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
acf82361 PM |
807 | const uint64_t sectorlength = 256 * 1024; |
808 | ||
9b3d111a MA |
809 | if (dinfo) { |
810 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
811 | &error_abort); | |
acf82361 PM |
812 | } |
813 | ||
814 | qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength); | |
815 | qdev_prop_set_uint64(dev, "sector-length", sectorlength); | |
816 | qdev_prop_set_uint8(dev, "width", 4); | |
817 | qdev_prop_set_uint8(dev, "device-width", 2); | |
e9809422 | 818 | qdev_prop_set_bit(dev, "big-endian", false); |
acf82361 PM |
819 | qdev_prop_set_uint16(dev, "id0", 0x89); |
820 | qdev_prop_set_uint16(dev, "id1", 0x18); | |
821 | qdev_prop_set_uint16(dev, "id2", 0x00); | |
822 | qdev_prop_set_uint16(dev, "id3", 0x00); | |
823 | qdev_prop_set_string(dev, "name", name); | |
824 | qdev_init_nofail(dev); | |
825 | ||
738a5d9f PM |
826 | memory_region_add_subregion(sysmem, flashbase, |
827 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); | |
acf82361 | 828 | |
16f4a8dc | 829 | if (file) { |
6e05a12f | 830 | char *fn; |
4de9a883 | 831 | int image_size; |
acf82361 PM |
832 | |
833 | if (drive_get(IF_PFLASH, 0, 0)) { | |
834 | error_report("The contents of the first flash device may be " | |
835 | "specified with -bios or with -drive if=pflash... " | |
836 | "but you cannot use both options at once"); | |
837 | exit(1); | |
838 | } | |
16f4a8dc | 839 | fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file); |
4de9a883 | 840 | if (!fn) { |
16f4a8dc | 841 | error_report("Could not find ROM image '%s'", file); |
4de9a883 SW |
842 | exit(1); |
843 | } | |
16f4a8dc | 844 | image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0)); |
4de9a883 SW |
845 | g_free(fn); |
846 | if (image_size < 0) { | |
16f4a8dc | 847 | error_report("Could not load ROM image '%s'", file); |
acf82361 PM |
848 | exit(1); |
849 | } | |
850 | } | |
16f4a8dc PM |
851 | } |
852 | ||
9ac4ef77 | 853 | static void create_flash(const VirtMachineState *vbi, |
738a5d9f PM |
854 | MemoryRegion *sysmem, |
855 | MemoryRegion *secure_sysmem) | |
16f4a8dc PM |
856 | { |
857 | /* Create two flash devices to fill the VIRT_FLASH space in the memmap. | |
858 | * Any file passed via -bios goes in the first of these. | |
738a5d9f PM |
859 | * sysmem is the system memory space. secure_sysmem is the secure view |
860 | * of the system, and the first flash device should be made visible only | |
861 | * there. The second flash device is visible to both secure and nonsecure. | |
862 | * If sysmem == secure_sysmem this means there is no separate Secure | |
863 | * address space and both flash devices are generally visible. | |
16f4a8dc PM |
864 | */ |
865 | hwaddr flashsize = vbi->memmap[VIRT_FLASH].size / 2; | |
866 | hwaddr flashbase = vbi->memmap[VIRT_FLASH].base; | |
867 | char *nodename; | |
acf82361 | 868 | |
738a5d9f PM |
869 | create_one_flash("virt.flash0", flashbase, flashsize, |
870 | bios_name, secure_sysmem); | |
871 | create_one_flash("virt.flash1", flashbase + flashsize, flashsize, | |
872 | NULL, sysmem); | |
acf82361 | 873 | |
738a5d9f PM |
874 | if (sysmem == secure_sysmem) { |
875 | /* Report both flash devices as a single node in the DT */ | |
876 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
877 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
878 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
879 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
880 | 2, flashbase, 2, flashsize, | |
881 | 2, flashbase + flashsize, 2, flashsize); | |
882 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
883 | g_free(nodename); | |
884 | } else { | |
885 | /* Report the devices as separate nodes so we can mark one as | |
886 | * only visible to the secure world. | |
887 | */ | |
888 | nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase); | |
889 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
890 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
891 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
892 | 2, flashbase, 2, flashsize); | |
893 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
894 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
895 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
896 | g_free(nodename); | |
897 | ||
898 | nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); | |
899 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
900 | qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible", "cfi-flash"); | |
901 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
902 | 2, flashbase + flashsize, 2, flashsize); | |
903 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "bank-width", 4); | |
904 | g_free(nodename); | |
905 | } | |
acf82361 PM |
906 | } |
907 | ||
9ac4ef77 | 908 | static void create_fw_cfg(const VirtMachineState *vbi, AddressSpace *as) |
578f3c7b LE |
909 | { |
910 | hwaddr base = vbi->memmap[VIRT_FW_CFG].base; | |
911 | hwaddr size = vbi->memmap[VIRT_FW_CFG].size; | |
5836d168 | 912 | FWCfgState *fw_cfg; |
578f3c7b LE |
913 | char *nodename; |
914 | ||
5836d168 IM |
915 | fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as); |
916 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); | |
578f3c7b LE |
917 | |
918 | nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); | |
919 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
920 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
921 | "compatible", "qemu,fw-cfg-mmio"); | |
922 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", | |
923 | 2, base, 2, size); | |
924 | g_free(nodename); | |
925 | } | |
926 | ||
9ac4ef77 PM |
927 | static void create_pcie_irq_map(const VirtMachineState *vbi, |
928 | uint32_t gic_phandle, | |
4ab29b82 AG |
929 | int first_irq, const char *nodename) |
930 | { | |
931 | int devfn, pin; | |
dfd90a87 | 932 | uint32_t full_irq_map[4 * 4 * 10] = { 0 }; |
4ab29b82 AG |
933 | uint32_t *irq_map = full_irq_map; |
934 | ||
935 | for (devfn = 0; devfn <= 0x18; devfn += 0x8) { | |
936 | for (pin = 0; pin < 4; pin++) { | |
937 | int irq_type = GIC_FDT_IRQ_TYPE_SPI; | |
938 | int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); | |
939 | int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI; | |
940 | int i; | |
941 | ||
942 | uint32_t map[] = { | |
943 | devfn << 8, 0, 0, /* devfn */ | |
944 | pin + 1, /* PCI pin */ | |
dfd90a87 | 945 | gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */ |
4ab29b82 AG |
946 | |
947 | /* Convert map to big endian */ | |
dfd90a87 | 948 | for (i = 0; i < 10; i++) { |
4ab29b82 AG |
949 | irq_map[i] = cpu_to_be32(map[i]); |
950 | } | |
dfd90a87 | 951 | irq_map += 10; |
4ab29b82 AG |
952 | } |
953 | } | |
954 | ||
955 | qemu_fdt_setprop(vbi->fdt, nodename, "interrupt-map", | |
956 | full_irq_map, sizeof(full_irq_map)); | |
957 | ||
958 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupt-map-mask", | |
959 | 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ | |
960 | 0x7 /* PCI irq */); | |
961 | } | |
962 | ||
9ac4ef77 | 963 | static void create_pcie(const VirtMachineState *vbi, qemu_irq *pic, |
5125f9cd | 964 | bool use_highmem) |
4ab29b82 | 965 | { |
6a1f001b SZ |
966 | hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base; |
967 | hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size; | |
5125f9cd PF |
968 | hwaddr base_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].base; |
969 | hwaddr size_mmio_high = vbi->memmap[VIRT_PCIE_MMIO_HIGH].size; | |
6a1f001b SZ |
970 | hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base; |
971 | hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size; | |
972 | hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base; | |
973 | hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size; | |
974 | hwaddr base = base_mmio; | |
975 | int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN; | |
4ab29b82 AG |
976 | int irq = vbi->irqmap[VIRT_PCIE]; |
977 | MemoryRegion *mmio_alias; | |
978 | MemoryRegion *mmio_reg; | |
979 | MemoryRegion *ecam_alias; | |
980 | MemoryRegion *ecam_reg; | |
981 | DeviceState *dev; | |
982 | char *nodename; | |
983 | int i; | |
fea9b3ca | 984 | PCIHostState *pci; |
4ab29b82 | 985 | |
4ab29b82 AG |
986 | dev = qdev_create(NULL, TYPE_GPEX_HOST); |
987 | qdev_init_nofail(dev); | |
988 | ||
989 | /* Map only the first size_ecam bytes of ECAM space */ | |
990 | ecam_alias = g_new0(MemoryRegion, 1); | |
991 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
992 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", | |
993 | ecam_reg, 0, size_ecam); | |
994 | memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); | |
995 | ||
996 | /* Map the MMIO window into system address space so as to expose | |
997 | * the section of PCI MMIO space which starts at the same base address | |
998 | * (ie 1:1 mapping for that part of PCI MMIO space visible through | |
999 | * the window). | |
1000 | */ | |
1001 | mmio_alias = g_new0(MemoryRegion, 1); | |
1002 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); | |
1003 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", | |
1004 | mmio_reg, base_mmio, size_mmio); | |
1005 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); | |
1006 | ||
5125f9cd PF |
1007 | if (use_highmem) { |
1008 | /* Map high MMIO space */ | |
1009 | MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); | |
1010 | ||
1011 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", | |
1012 | mmio_reg, base_mmio_high, size_mmio_high); | |
1013 | memory_region_add_subregion(get_system_memory(), base_mmio_high, | |
1014 | high_mmio_alias); | |
1015 | } | |
1016 | ||
4ab29b82 | 1017 | /* Map IO port space */ |
6a1f001b | 1018 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); |
4ab29b82 AG |
1019 | |
1020 | for (i = 0; i < GPEX_NUM_IRQS; i++) { | |
1021 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); | |
1022 | } | |
1023 | ||
fea9b3ca AK |
1024 | pci = PCI_HOST_BRIDGE(dev); |
1025 | if (pci->bus) { | |
1026 | for (i = 0; i < nb_nics; i++) { | |
1027 | NICInfo *nd = &nd_table[i]; | |
1028 | ||
1029 | if (!nd->model) { | |
1030 | nd->model = g_strdup("virtio"); | |
1031 | } | |
1032 | ||
1033 | pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); | |
1034 | } | |
1035 | } | |
1036 | ||
4ab29b82 AG |
1037 | nodename = g_strdup_printf("/pcie@%" PRIx64, base); |
1038 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
1039 | qemu_fdt_setprop_string(vbi->fdt, nodename, | |
1040 | "compatible", "pci-host-ecam-generic"); | |
1041 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "pci"); | |
1042 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#address-cells", 3); | |
1043 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 2); | |
1044 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "bus-range", 0, | |
1045 | nr_pcie_buses - 1); | |
5d636e21 | 1046 | qemu_fdt_setprop(vbi->fdt, nodename, "dma-coherent", NULL, 0); |
4ab29b82 | 1047 | |
02f98731 | 1048 | if (vbi->msi_phandle) { |
b92ad394 | 1049 | qemu_fdt_setprop_cells(vbi->fdt, nodename, "msi-parent", |
02f98731 | 1050 | vbi->msi_phandle); |
b92ad394 | 1051 | } |
bd204e63 | 1052 | |
4ab29b82 AG |
1053 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", |
1054 | 2, base_ecam, 2, size_ecam); | |
5125f9cd PF |
1055 | |
1056 | if (use_highmem) { | |
1057 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
1058 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
1059 | 2, base_pio, 2, size_pio, | |
1060 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1061 | 2, base_mmio, 2, size_mmio, | |
1062 | 1, FDT_PCI_RANGE_MMIO_64BIT, | |
1063 | 2, base_mmio_high, | |
1064 | 2, base_mmio_high, 2, size_mmio_high); | |
1065 | } else { | |
1066 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges", | |
1067 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, | |
1068 | 2, base_pio, 2, size_pio, | |
1069 | 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, | |
1070 | 2, base_mmio, 2, size_mmio); | |
1071 | } | |
4ab29b82 AG |
1072 | |
1073 | qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1); | |
747d009d | 1074 | create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename); |
4ab29b82 AG |
1075 | |
1076 | g_free(nodename); | |
1077 | } | |
1078 | ||
9ac4ef77 | 1079 | static void create_platform_bus(VirtMachineState *vbi, qemu_irq *pic) |
5f7a5a0e EA |
1080 | { |
1081 | DeviceState *dev; | |
1082 | SysBusDevice *s; | |
1083 | int i; | |
1084 | ARMPlatformBusFDTParams *fdt_params = g_new(ARMPlatformBusFDTParams, 1); | |
1085 | MemoryRegion *sysmem = get_system_memory(); | |
1086 | ||
1087 | platform_bus_params.platform_bus_base = vbi->memmap[VIRT_PLATFORM_BUS].base; | |
1088 | platform_bus_params.platform_bus_size = vbi->memmap[VIRT_PLATFORM_BUS].size; | |
1089 | platform_bus_params.platform_bus_first_irq = vbi->irqmap[VIRT_PLATFORM_BUS]; | |
1090 | platform_bus_params.platform_bus_num_irqs = PLATFORM_BUS_NUM_IRQS; | |
1091 | ||
1092 | fdt_params->system_params = &platform_bus_params; | |
1093 | fdt_params->binfo = &vbi->bootinfo; | |
1094 | fdt_params->intc = "/intc"; | |
1095 | /* | |
1096 | * register a machine init done notifier that creates the device tree | |
1097 | * nodes of the platform bus and its children dynamic sysbus devices | |
1098 | */ | |
1099 | arm_register_platform_bus_fdt_creator(fdt_params); | |
1100 | ||
1101 | dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); | |
1102 | dev->id = TYPE_PLATFORM_BUS_DEVICE; | |
1103 | qdev_prop_set_uint32(dev, "num_irqs", | |
1104 | platform_bus_params.platform_bus_num_irqs); | |
1105 | qdev_prop_set_uint32(dev, "mmio_size", | |
1106 | platform_bus_params.platform_bus_size); | |
1107 | qdev_init_nofail(dev); | |
1108 | s = SYS_BUS_DEVICE(dev); | |
1109 | ||
1110 | for (i = 0; i < platform_bus_params.platform_bus_num_irqs; i++) { | |
1111 | int irqn = platform_bus_params.platform_bus_first_irq + i; | |
1112 | sysbus_connect_irq(s, i, pic[irqn]); | |
1113 | } | |
1114 | ||
1115 | memory_region_add_subregion(sysmem, | |
1116 | platform_bus_params.platform_bus_base, | |
1117 | sysbus_mmio_get_region(s, 0)); | |
1118 | } | |
1119 | ||
9ac4ef77 PM |
1120 | static void create_secure_ram(VirtMachineState *vbi, |
1121 | MemoryRegion *secure_sysmem) | |
83ec1923 PM |
1122 | { |
1123 | MemoryRegion *secram = g_new(MemoryRegion, 1); | |
1124 | char *nodename; | |
1125 | hwaddr base = vbi->memmap[VIRT_SECURE_MEM].base; | |
1126 | hwaddr size = vbi->memmap[VIRT_SECURE_MEM].size; | |
1127 | ||
1128 | memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); | |
1129 | vmstate_register_ram_global(secram); | |
1130 | memory_region_add_subregion(secure_sysmem, base, secram); | |
1131 | ||
1132 | nodename = g_strdup_printf("/secram@%" PRIx64, base); | |
1133 | qemu_fdt_add_subnode(vbi->fdt, nodename); | |
1134 | qemu_fdt_setprop_string(vbi->fdt, nodename, "device_type", "memory"); | |
1135 | qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size); | |
1136 | qemu_fdt_setprop_string(vbi->fdt, nodename, "status", "disabled"); | |
1137 | qemu_fdt_setprop_string(vbi->fdt, nodename, "secure-status", "okay"); | |
1138 | ||
1139 | g_free(nodename); | |
1140 | } | |
1141 | ||
f5fdcd6e PM |
1142 | static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) |
1143 | { | |
9ac4ef77 PM |
1144 | const VirtMachineState *board = container_of(binfo, VirtMachineState, |
1145 | bootinfo); | |
f5fdcd6e PM |
1146 | |
1147 | *fdt_size = board->fdt_size; | |
1148 | return board->fdt; | |
1149 | } | |
1150 | ||
c30e1565 WH |
1151 | static void virt_build_smbios(VirtGuestInfo *guest_info) |
1152 | { | |
1153 | FWCfgState *fw_cfg = guest_info->fw_cfg; | |
1154 | uint8_t *smbios_tables, *smbios_anchor; | |
1155 | size_t smbios_tables_len, smbios_anchor_len; | |
bab27ea2 | 1156 | const char *product = "QEMU Virtual Machine"; |
c30e1565 WH |
1157 | |
1158 | if (!fw_cfg) { | |
1159 | return; | |
1160 | } | |
1161 | ||
bab27ea2 AJ |
1162 | if (kvm_enabled()) { |
1163 | product = "KVM Virtual Machine"; | |
1164 | } | |
1165 | ||
1166 | smbios_set_defaults("QEMU", product, | |
c30e1565 WH |
1167 | "1.0", false, true, SMBIOS_ENTRY_POINT_30); |
1168 | ||
1169 | smbios_get_tables(NULL, 0, &smbios_tables, &smbios_tables_len, | |
1170 | &smbios_anchor, &smbios_anchor_len); | |
1171 | ||
1172 | if (smbios_anchor) { | |
1173 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", | |
1174 | smbios_tables, smbios_tables_len); | |
1175 | fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", | |
1176 | smbios_anchor, smbios_anchor_len); | |
1177 | } | |
1178 | } | |
1179 | ||
d7c2e2db SZ |
1180 | static |
1181 | void virt_guest_info_machine_done(Notifier *notifier, void *data) | |
1182 | { | |
1183 | VirtGuestInfoState *guest_info_state = container_of(notifier, | |
1184 | VirtGuestInfoState, machine_done); | |
1185 | virt_acpi_setup(&guest_info_state->info); | |
c30e1565 | 1186 | virt_build_smbios(&guest_info_state->info); |
d7c2e2db SZ |
1187 | } |
1188 | ||
3ef96221 | 1189 | static void machvirt_init(MachineState *machine) |
f5fdcd6e | 1190 | { |
e5a5604f | 1191 | VirtMachineState *vms = VIRT_MACHINE(machine); |
95eb49c8 | 1192 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine); |
f5fdcd6e PM |
1193 | qemu_irq pic[NUM_IRQS]; |
1194 | MemoryRegion *sysmem = get_system_memory(); | |
3df708eb | 1195 | MemoryRegion *secure_sysmem = NULL; |
b92ad394 | 1196 | int gic_version = vms->gic_version; |
7ea686f5 | 1197 | int n, virt_max_cpus; |
f5fdcd6e | 1198 | MemoryRegion *ram = g_new(MemoryRegion, 1); |
3ef96221 | 1199 | const char *cpu_model = machine->cpu_model; |
9ac4ef77 | 1200 | VirtMachineState *vbi = vms; |
d7c2e2db SZ |
1201 | VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); |
1202 | VirtGuestInfo *guest_info = &guest_info_state->info; | |
f313369f | 1203 | char **cpustr; |
09f71b05 IM |
1204 | ObjectClass *oc; |
1205 | const char *typename; | |
1206 | CPUClass *cc; | |
1207 | Error *err = NULL; | |
4824a61a | 1208 | bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); |
95eb49c8 | 1209 | uint8_t clustersz; |
f5fdcd6e PM |
1210 | |
1211 | if (!cpu_model) { | |
1212 | cpu_model = "cortex-a15"; | |
1213 | } | |
1214 | ||
b92ad394 PF |
1215 | /* We can probe only here because during property set |
1216 | * KVM is not available yet | |
1217 | */ | |
1218 | if (!gic_version) { | |
0bf8039d CR |
1219 | if (!kvm_enabled()) { |
1220 | error_report("gic-version=host requires KVM"); | |
1221 | exit(1); | |
1222 | } | |
1223 | ||
b92ad394 PF |
1224 | gic_version = kvm_arm_vgic_probe(); |
1225 | if (!gic_version) { | |
faa811f6 | 1226 | error_report("Unable to determine GIC version supported by host"); |
b92ad394 PF |
1227 | exit(1); |
1228 | } | |
1229 | } | |
1230 | ||
f313369f GB |
1231 | /* Separate the actual CPU model name from any appended features */ |
1232 | cpustr = g_strsplit(cpu_model, ",", 2); | |
1233 | ||
9ac4ef77 | 1234 | if (!cpuname_valid(cpustr[0])) { |
f313369f | 1235 | error_report("mach-virt: CPU %s not supported", cpustr[0]); |
f5fdcd6e PM |
1236 | exit(1); |
1237 | } | |
1238 | ||
4824a61a PM |
1239 | /* If we have an EL3 boot ROM then the assumption is that it will |
1240 | * implement PSCI itself, so disable QEMU's internal implementation | |
1241 | * so it doesn't get in the way. Instead of starting secondary | |
1242 | * CPUs in PSCI powerdown state we will start them all running and | |
1243 | * let the boot ROM sort them out. | |
1244 | * The usual case is that we do use QEMU's PSCI implementation. | |
1245 | */ | |
1246 | vbi->using_psci = !(vms->secure && firmware_loaded); | |
1247 | ||
4b280b72 AJ |
1248 | /* The maximum number of CPUs depends on the GIC version, or on how |
1249 | * many redistributors we can fit into the memory map. | |
1250 | */ | |
1251 | if (gic_version == 3) { | |
7ea686f5 | 1252 | virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000; |
95eb49c8 | 1253 | clustersz = GICV3_TARGETLIST_BITS; |
4b280b72 | 1254 | } else { |
7ea686f5 | 1255 | virt_max_cpus = GIC_NCPU; |
95eb49c8 | 1256 | clustersz = GIC_TARGETLIST_BITS; |
4b280b72 AJ |
1257 | } |
1258 | ||
7ea686f5 | 1259 | if (max_cpus > virt_max_cpus) { |
4b280b72 AJ |
1260 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " |
1261 | "supported by machine 'mach-virt' (%d)", | |
7ea686f5 | 1262 | max_cpus, virt_max_cpus); |
4b280b72 AJ |
1263 | exit(1); |
1264 | } | |
1265 | ||
f5fdcd6e PM |
1266 | vbi->smp_cpus = smp_cpus; |
1267 | ||
3ef96221 | 1268 | if (machine->ram_size > vbi->memmap[VIRT_MEM].size) { |
71c27684 | 1269 | error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); |
f5fdcd6e PM |
1270 | exit(1); |
1271 | } | |
1272 | ||
3df708eb PM |
1273 | if (vms->secure) { |
1274 | if (kvm_enabled()) { | |
1275 | error_report("mach-virt: KVM does not support Security extensions"); | |
1276 | exit(1); | |
1277 | } | |
1278 | ||
1279 | /* The Secure view of the world is the same as the NonSecure, | |
1280 | * but with a few extra devices. Create it as a container region | |
1281 | * containing the system memory at low priority; any secure-only | |
1282 | * devices go in at higher priority and take precedence. | |
1283 | */ | |
1284 | secure_sysmem = g_new(MemoryRegion, 1); | |
1285 | memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory", | |
1286 | UINT64_MAX); | |
1287 | memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); | |
1288 | } | |
1289 | ||
f5fdcd6e | 1290 | create_fdt(vbi); |
f5fdcd6e | 1291 | |
09f71b05 IM |
1292 | oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]); |
1293 | if (!oc) { | |
1294 | error_report("Unable to find CPU definition"); | |
1295 | exit(1); | |
1296 | } | |
1297 | typename = object_class_get_name(oc); | |
f5fdcd6e | 1298 | |
09f71b05 IM |
1299 | /* convert -smp CPU options specified by the user into global props */ |
1300 | cc = CPU_CLASS(oc); | |
1301 | cc->parse_features(typename, cpustr[1], &err); | |
1302 | g_strfreev(cpustr); | |
1303 | if (err) { | |
1304 | error_report_err(err); | |
1305 | exit(1); | |
1306 | } | |
1307 | ||
1308 | for (n = 0; n < smp_cpus; n++) { | |
1309 | Object *cpuobj = object_new(typename); | |
95eb49c8 AJ |
1310 | if (!vmc->disallow_affinity_adjustment) { |
1311 | /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the | |
1312 | * GIC's target-list limitations. 32-bit KVM hosts currently | |
1313 | * always create clusters of 4 CPUs, but that is expected to | |
1314 | * change when they gain support for gicv3. When KVM is enabled | |
1315 | * it will override the changes we make here, therefore our | |
1316 | * purposes are to make TCG consistent (with 64-bit KVM hosts) | |
1317 | * and to improve SGI efficiency. | |
1318 | */ | |
1319 | uint8_t aff1 = n / clustersz; | |
1320 | uint8_t aff0 = n % clustersz; | |
1321 | object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0, | |
1322 | "mp-affinity", NULL); | |
1323 | } | |
f313369f | 1324 | |
e5a5604f GB |
1325 | if (!vms->secure) { |
1326 | object_property_set_bool(cpuobj, false, "has_el3", NULL); | |
1327 | } | |
1328 | ||
4824a61a PM |
1329 | if (vbi->using_psci) { |
1330 | object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC, | |
1331 | "psci-conduit", NULL); | |
211b0169 | 1332 | |
4824a61a PM |
1333 | /* Secondary CPUs start in PSCI powered-down state */ |
1334 | if (n > 0) { | |
1335 | object_property_set_bool(cpuobj, true, | |
1336 | "start-powered-off", NULL); | |
1337 | } | |
f5fdcd6e | 1338 | } |
ba750085 | 1339 | |
1141d1eb WH |
1340 | if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) { |
1341 | object_property_set_bool(cpuobj, false, "pmu", NULL); | |
1342 | } | |
1343 | ||
ba750085 PM |
1344 | if (object_property_find(cpuobj, "reset-cbar", NULL)) { |
1345 | object_property_set_int(cpuobj, vbi->memmap[VIRT_CPUPERIPHS].base, | |
1346 | "reset-cbar", &error_abort); | |
1347 | } | |
1348 | ||
1d939a68 PM |
1349 | object_property_set_link(cpuobj, OBJECT(sysmem), "memory", |
1350 | &error_abort); | |
3df708eb PM |
1351 | if (vms->secure) { |
1352 | object_property_set_link(cpuobj, OBJECT(secure_sysmem), | |
1353 | "secure-memory", &error_abort); | |
1354 | } | |
1d939a68 | 1355 | |
f5fdcd6e PM |
1356 | object_property_set_bool(cpuobj, true, "realized", NULL); |
1357 | } | |
b92ad394 | 1358 | fdt_add_timer_nodes(vbi, gic_version); |
f5fdcd6e | 1359 | fdt_add_cpu_nodes(vbi); |
06955739 | 1360 | fdt_add_psci_node(vbi); |
f5fdcd6e | 1361 | |
c8623c02 DM |
1362 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", |
1363 | machine->ram_size); | |
f5fdcd6e PM |
1364 | memory_region_add_subregion(sysmem, vbi->memmap[VIRT_MEM].base, ram); |
1365 | ||
738a5d9f | 1366 | create_flash(vbi, sysmem, secure_sysmem ? secure_sysmem : sysmem); |
acf82361 | 1367 | |
2231f69b | 1368 | create_gic(vbi, pic, gic_version, vms->secure, vmc->no_its); |
f5fdcd6e | 1369 | |
01fe6b60 SZ |
1370 | fdt_add_pmu_nodes(vbi, gic_version); |
1371 | ||
9bbbf649 | 1372 | create_uart(vbi, pic, VIRT_UART, sysmem, serial_hds[0]); |
3df708eb PM |
1373 | |
1374 | if (vms->secure) { | |
83ec1923 | 1375 | create_secure_ram(vbi, secure_sysmem); |
9bbbf649 | 1376 | create_uart(vbi, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); |
3df708eb | 1377 | } |
f5fdcd6e | 1378 | |
6e411af9 PM |
1379 | create_rtc(vbi, pic); |
1380 | ||
5125f9cd | 1381 | create_pcie(vbi, pic, vms->highmem); |
4ab29b82 | 1382 | |
b0a3721e SZ |
1383 | create_gpio(vbi, pic); |
1384 | ||
f5fdcd6e PM |
1385 | /* Create mmio transports, so the user can create virtio backends |
1386 | * (which will be automatically plugged in to the transports). If | |
1387 | * no backend is created the transport will just sit harmlessly idle. | |
1388 | */ | |
1389 | create_virtio_devices(vbi, pic); | |
1390 | ||
0b341a85 | 1391 | create_fw_cfg(vbi, &address_space_memory); |
d7c2e2db SZ |
1392 | rom_set_fw(fw_cfg_find()); |
1393 | ||
1394 | guest_info->smp_cpus = smp_cpus; | |
1395 | guest_info->fw_cfg = fw_cfg_find(); | |
1396 | guest_info->memmap = vbi->memmap; | |
1397 | guest_info->irqmap = vbi->irqmap; | |
5125f9cd | 1398 | guest_info->use_highmem = vms->highmem; |
b92ad394 | 1399 | guest_info->gic_version = gic_version; |
2231f69b | 1400 | guest_info->no_its = vmc->no_its; |
d7c2e2db SZ |
1401 | guest_info_state->machine_done.notify = virt_guest_info_machine_done; |
1402 | qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); | |
578f3c7b | 1403 | |
3ef96221 MA |
1404 | vbi->bootinfo.ram_size = machine->ram_size; |
1405 | vbi->bootinfo.kernel_filename = machine->kernel_filename; | |
1406 | vbi->bootinfo.kernel_cmdline = machine->kernel_cmdline; | |
1407 | vbi->bootinfo.initrd_filename = machine->initrd_filename; | |
f5fdcd6e PM |
1408 | vbi->bootinfo.nb_cpus = smp_cpus; |
1409 | vbi->bootinfo.board_id = -1; | |
1410 | vbi->bootinfo.loader_start = vbi->memmap[VIRT_MEM].base; | |
1411 | vbi->bootinfo.get_dtb = machvirt_dtb; | |
4824a61a | 1412 | vbi->bootinfo.firmware_loaded = firmware_loaded; |
f5fdcd6e | 1413 | arm_load_kernel(ARM_CPU(first_cpu), &vbi->bootinfo); |
5f7a5a0e EA |
1414 | |
1415 | /* | |
1416 | * arm_load_kernel machine init done notifier registration must | |
1417 | * happen before the platform_bus_create call. In this latter, | |
1418 | * another notifier is registered which adds platform bus nodes. | |
1419 | * Notifiers are executed in registration reverse order. | |
1420 | */ | |
1421 | create_platform_bus(vbi, pic); | |
f5fdcd6e PM |
1422 | } |
1423 | ||
083a5890 GB |
1424 | static bool virt_get_secure(Object *obj, Error **errp) |
1425 | { | |
1426 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1427 | ||
1428 | return vms->secure; | |
1429 | } | |
1430 | ||
1431 | static void virt_set_secure(Object *obj, bool value, Error **errp) | |
1432 | { | |
1433 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1434 | ||
1435 | vms->secure = value; | |
1436 | } | |
1437 | ||
5125f9cd PF |
1438 | static bool virt_get_highmem(Object *obj, Error **errp) |
1439 | { | |
1440 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1441 | ||
1442 | return vms->highmem; | |
1443 | } | |
1444 | ||
1445 | static void virt_set_highmem(Object *obj, bool value, Error **errp) | |
1446 | { | |
1447 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1448 | ||
1449 | vms->highmem = value; | |
1450 | } | |
1451 | ||
b92ad394 PF |
1452 | static char *virt_get_gic_version(Object *obj, Error **errp) |
1453 | { | |
1454 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1455 | const char *val = vms->gic_version == 3 ? "3" : "2"; | |
1456 | ||
1457 | return g_strdup(val); | |
1458 | } | |
1459 | ||
1460 | static void virt_set_gic_version(Object *obj, const char *value, Error **errp) | |
1461 | { | |
1462 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1463 | ||
1464 | if (!strcmp(value, "3")) { | |
1465 | vms->gic_version = 3; | |
1466 | } else if (!strcmp(value, "2")) { | |
1467 | vms->gic_version = 2; | |
1468 | } else if (!strcmp(value, "host")) { | |
1469 | vms->gic_version = 0; /* Will probe later */ | |
1470 | } else { | |
7b55044f MA |
1471 | error_setg(errp, "Invalid gic-version value"); |
1472 | error_append_hint(errp, "Valid values are 3, 2, host.\n"); | |
b92ad394 PF |
1473 | } |
1474 | } | |
1475 | ||
ed796373 WH |
1476 | static void virt_machine_class_init(ObjectClass *oc, void *data) |
1477 | { | |
9c94d8e6 WH |
1478 | MachineClass *mc = MACHINE_CLASS(oc); |
1479 | ||
1480 | mc->init = machvirt_init; | |
1481 | /* Start max_cpus at the maximum QEMU supports. We'll further restrict | |
1482 | * it later in machvirt_init, where we have more information about the | |
1483 | * configuration of the particular instance. | |
1484 | */ | |
079019f2 | 1485 | mc->max_cpus = 255; |
9c94d8e6 WH |
1486 | mc->has_dynamic_sysbus = true; |
1487 | mc->block_default_type = IF_VIRTIO; | |
1488 | mc->no_cdrom = 1; | |
1489 | mc->pci_allow_0_address = true; | |
a2519ad1 PM |
1490 | /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ |
1491 | mc->minimum_page_bits = 12; | |
ed796373 WH |
1492 | } |
1493 | ||
1494 | static const TypeInfo virt_machine_info = { | |
1495 | .name = TYPE_VIRT_MACHINE, | |
1496 | .parent = TYPE_MACHINE, | |
1497 | .abstract = true, | |
1498 | .instance_size = sizeof(VirtMachineState), | |
1499 | .class_size = sizeof(VirtMachineClass), | |
1500 | .class_init = virt_machine_class_init, | |
1501 | }; | |
1502 | ||
7a2ecd95 AJ |
1503 | static void machvirt_machine_init(void) |
1504 | { | |
1505 | type_register_static(&virt_machine_info); | |
1506 | } | |
1507 | type_init(machvirt_machine_init); | |
1508 | ||
e353aac5 | 1509 | static void virt_2_9_instance_init(Object *obj) |
083a5890 GB |
1510 | { |
1511 | VirtMachineState *vms = VIRT_MACHINE(obj); | |
1512 | ||
2d710006 PM |
1513 | /* EL3 is disabled by default on virt: this makes us consistent |
1514 | * between KVM and TCG for this board, and it also allows us to | |
1515 | * boot UEFI blobs which assume no TrustZone support. | |
1516 | */ | |
1517 | vms->secure = false; | |
083a5890 GB |
1518 | object_property_add_bool(obj, "secure", virt_get_secure, |
1519 | virt_set_secure, NULL); | |
1520 | object_property_set_description(obj, "secure", | |
1521 | "Set on/off to enable/disable the ARM " | |
1522 | "Security Extensions (TrustZone)", | |
1523 | NULL); | |
5125f9cd PF |
1524 | |
1525 | /* High memory is enabled by default */ | |
1526 | vms->highmem = true; | |
1527 | object_property_add_bool(obj, "highmem", virt_get_highmem, | |
1528 | virt_set_highmem, NULL); | |
1529 | object_property_set_description(obj, "highmem", | |
1530 | "Set on/off to enable/disable using " | |
1531 | "physical address space above 32 bits", | |
1532 | NULL); | |
b92ad394 PF |
1533 | /* Default GIC type is v2 */ |
1534 | vms->gic_version = 2; | |
1535 | object_property_add_str(obj, "gic-version", virt_get_gic_version, | |
1536 | virt_set_gic_version, NULL); | |
1537 | object_property_set_description(obj, "gic-version", | |
1538 | "Set GIC version. " | |
1539 | "Valid values are 2, 3 and host", NULL); | |
9ac4ef77 PM |
1540 | |
1541 | vms->memmap = a15memmap; | |
1542 | vms->irqmap = a15irqmap; | |
083a5890 GB |
1543 | } |
1544 | ||
e353aac5 PM |
1545 | static void virt_machine_2_9_options(MachineClass *mc) |
1546 | { | |
1547 | } | |
1548 | DEFINE_VIRT_MACHINE_AS_LATEST(2, 9) | |
1549 | ||
1550 | #define VIRT_COMPAT_2_8 \ | |
1551 | HW_COMPAT_2_8 | |
1552 | ||
1553 | static void virt_2_8_instance_init(Object *obj) | |
1554 | { | |
1555 | virt_2_9_instance_init(obj); | |
1556 | } | |
1557 | ||
96b0439b AJ |
1558 | static void virt_machine_2_8_options(MachineClass *mc) |
1559 | { | |
e353aac5 PM |
1560 | virt_machine_2_9_options(mc); |
1561 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8); | |
96b0439b | 1562 | } |
e353aac5 | 1563 | DEFINE_VIRT_MACHINE(2, 8) |
96b0439b AJ |
1564 | |
1565 | #define VIRT_COMPAT_2_7 \ | |
1566 | HW_COMPAT_2_7 | |
1567 | ||
1568 | static void virt_2_7_instance_init(Object *obj) | |
1569 | { | |
1570 | virt_2_8_instance_init(obj); | |
1571 | } | |
1572 | ||
1287f2b3 AJ |
1573 | static void virt_machine_2_7_options(MachineClass *mc) |
1574 | { | |
2231f69b AJ |
1575 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1576 | ||
96b0439b AJ |
1577 | virt_machine_2_8_options(mc); |
1578 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_7); | |
2231f69b AJ |
1579 | /* ITS was introduced with 2.8 */ |
1580 | vmc->no_its = true; | |
a2519ad1 PM |
1581 | /* Stick with 1K pages for migration compatibility */ |
1582 | mc->minimum_page_bits = 0; | |
1287f2b3 | 1583 | } |
96b0439b | 1584 | DEFINE_VIRT_MACHINE(2, 7) |
1287f2b3 AJ |
1585 | |
1586 | #define VIRT_COMPAT_2_6 \ | |
1587 | HW_COMPAT_2_6 | |
1588 | ||
1589 | static void virt_2_6_instance_init(Object *obj) | |
1590 | { | |
1591 | virt_2_7_instance_init(obj); | |
1592 | } | |
1593 | ||
ab093c3c | 1594 | static void virt_machine_2_6_options(MachineClass *mc) |
c2919690 | 1595 | { |
95eb49c8 AJ |
1596 | VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); |
1597 | ||
1287f2b3 AJ |
1598 | virt_machine_2_7_options(mc); |
1599 | SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6); | |
95eb49c8 | 1600 | vmc->disallow_affinity_adjustment = true; |
1141d1eb WH |
1601 | /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ |
1602 | vmc->no_pmu = true; | |
c2919690 | 1603 | } |
1287f2b3 | 1604 | DEFINE_VIRT_MACHINE(2, 6) |