[mirror_qemu.git] / hw / arm / xilinx_zynq.c

/*
 * Xilinx Zynq Baseboard System emulation.
 *
 * Copyright (c) 2010 Xilinx.
 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
 * Copyright (c) 2012 Petalogix Pty Ltd.
 * Written by Haibing Ma
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "net/net.h"
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/block/flash.h"
#include "hw/loader.h"
#include "hw/misc/zynq-xadc.h"
#include "hw/ssi/ssi.h"
#include "hw/usb/chipidea.h"
#include "qemu/error-report.h"
#include "hw/sd/sdhci.h"
#include "hw/char/cadence_uart.h"
#include "hw/net/cadence_gem.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/qdev-clock.h"
#include "sysemu/reset.h"

#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
#define ZYNQ_MACHINE(obj) \
    OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)

/* board base frequency: 33.333333 MHz */
#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)

#define NUM_SPI_FLASHES 4
#define NUM_QSPI_FLASHES 2
#define NUM_QSPI_BUSSES 2

#define FLASH_SIZE (64 * 1024 * 1024)
#define FLASH_SECTOR_SIZE (128 * 1024)

#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */

#define MPCORE_PERIPHBASE 0xF8F00000
#define ZYNQ_BOARD_MIDR 0x413FC090

static const int dma_irqs[8] = {
    46, 47, 48, 49, 72, 73, 74, 75
};

#define BOARD_SETUP_ADDR        0x100

#define SLCR_LOCK_OFFSET        0x004
#define SLCR_UNLOCK_OFFSET      0x008
#define SLCR_ARM_PLL_OFFSET     0x100

#define SLCR_XILINX_UNLOCK_KEY  0xdf0d
#define SLCR_XILINX_LOCK_KEY    0x767b

#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080  /* Datasheet: UG585 (v1.12.1) */

#define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
                        extract32((x), 12,  4) << 16)

/* Write immediate val to address r0 + addr. r0 should contain base offset
 * of the SLCR block. Clobbers r1.
 */

#define SLCR_WRITE(addr, val) \
    0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
    0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
    0xe5801000 + (addr)

typedef struct ZynqMachineState {
    MachineState parent;
    Clock *ps_clk;
} ZynqMachineState;

static void zynq_write_board_setup(ARMCPU *cpu,
                                   const struct arm_boot_info *info)
{
    int n;
    uint32_t board_setup_blob[] = {
        0xe3a004f8, /* mov r0, #0xf8000000 */
        SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
        SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
        SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
        0xe12fff1e, /* bx lr */
    };
    for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
        board_setup_blob[n] = tswap32(board_setup_blob[n]);
    }
    rom_add_blob_fixed("board-setup", board_setup_blob,
                       sizeof(board_setup_blob), BOARD_SETUP_ADDR);
}

static struct arm_boot_info zynq_binfo = {};

static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
    DeviceState *dev;
    SysBusDevice *s;

    dev = qdev_new(TYPE_CADENCE_GEM);
    if (nd->used) {
        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
        qdev_set_nic_properties(dev, nd);
    }
    s = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(s, &error_fatal);
    sysbus_mmio_map(s, 0, base);
    sysbus_connect_irq(s, 0, irq);
}

static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
                                         bool is_qspi)
{
    DeviceState *dev;
    SysBusDevice *busdev;
    SSIBus *spi;
    DeviceState *flash_dev;
    int i, j;
    int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
    int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;

    dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
    qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
    qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
    qdev_prop_set_uint8(dev, "num-busses", num_busses);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(busdev, &error_fatal);
    sysbus_mmio_map(busdev, 0, base_addr);
    if (is_qspi) {
        sysbus_mmio_map(busdev, 1, 0xFC000000);
    }
    sysbus_connect_irq(busdev, 0, irq);

    for (i = 0; i < num_busses; ++i) {
        char bus_name[16];
        qemu_irq cs_line;

        snprintf(bus_name, 16, "spi%d", i);
        spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);

        for (j = 0; j < num_ss; ++j) {
            DriveInfo *dinfo = drive_get_next(IF_MTD);
            flash_dev = qdev_new("n25q128");
            if (dinfo) {
                qdev_prop_set_drive(flash_dev, "drive",
                                    blk_by_legacy_dinfo(dinfo), &error_fatal);
            }
            qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);

            cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
            sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
        }
    }

}

static void zynq_init(MachineState *machine)
{
    ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
    ARMCPU *cpu;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
    DeviceState *dev, *slcr;
    SysBusDevice *busdev;
    qemu_irq pic[64];
    int n;

    /* max 2GB ram */
    if (machine->ram_size > 2 * GiB) {
        error_report("RAM size more than 2 GiB is not supported");
        exit(EXIT_FAILURE);
    }

    cpu = ARM_CPU(object_new(machine->cpu_type));

    /* By default A9 CPUs have EL3 enabled.  This board does not
     * currently support EL3 so the CPU EL3 property is disabled before
     * realization.
     */
    if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
        object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
    }

    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
                            &error_fatal);
    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
                            &error_fatal);
    qdev_realize(DEVICE(cpu), NULL, &error_fatal);

    /* DDR remapped to address zero.  */
    memory_region_add_subregion(address_space_mem, 0, machine->ram);

    /* 256K of on-chip memory */
    memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
                           &error_fatal);
    memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);

    DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);

    /* AMD */
    pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          FLASH_SECTOR_SIZE, 1,
                          1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
                          0);

    /* Create slcr, keep a pointer to connect clocks */
    slcr = qdev_new("xilinx,zynq_slcr");
    sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);

    /* Create the main clock source, and feed slcr with it */
    zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
    object_property_add_child(OBJECT(zynq_machine), "ps_clk",
                              OBJECT(zynq_machine->ps_clk));
    object_unref(OBJECT(zynq_machine->ps_clk));
    clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
    qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);

    dev = qdev_new(TYPE_A9MPCORE_PRIV);
    qdev_prop_set_uint32(dev, "num-cpu", 1);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(busdev, &error_fatal);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    sysbus_connect_irq(busdev, 0,
                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));

    for (n = 0; n < 64; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
    zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);

    sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
    sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);

    dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
    qdev_connect_clock_in(dev, "refclk",
                          qdev_get_clock_out(slcr, "uart0_ref_clk"));
    dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
    qdev_connect_clock_in(dev, "refclk",
                          qdev_get_clock_out(slcr, "uart1_ref_clk"));

    sysbus_create_varargs("cadence_ttc", 0xF8001000,
            pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
    sysbus_create_varargs("cadence_ttc", 0xF8002000,
            pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);

    gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
    gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);

    for (n = 0; n < 2; n++) {
        int hci_irq = n ? 79 : 56;
        hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
        DriveInfo *di;
        BlockBackend *blk;
        DeviceState *carddev;

        /* Compatible with:
         * - SD Host Controller Specification Version 2.0 Part A2
         * - SDIO Specification Version 2.0
         * - MMC Specification Version 3.31
         */
        dev = qdev_new(TYPE_SYSBUS_SDHCI);
        qdev_prop_set_uint8(dev, "sd-spec-version", 2);
        qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);

        di = drive_get_next(IF_SD);
        blk = di ? blk_by_legacy_dinfo(di) : NULL;
        carddev = qdev_new(TYPE_SD_CARD);
        qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
        qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
                               &error_fatal);
    }

    dev = qdev_new(TYPE_ZYNQ_XADC);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);

    dev = qdev_new("pl330");
    qdev_prop_set_uint8(dev, "num_chnls",  8);
    qdev_prop_set_uint8(dev, "num_periph_req",  4);
    qdev_prop_set_uint8(dev, "num_events",  16);

    qdev_prop_set_uint8(dev, "data_width",  64);
    qdev_prop_set_uint8(dev, "wr_cap",  8);
    qdev_prop_set_uint8(dev, "wr_q_dep",  16);
    qdev_prop_set_uint8(dev, "rd_cap",  8);
    qdev_prop_set_uint8(dev, "rd_q_dep",  16);
    qdev_prop_set_uint16(dev, "data_buffer_dep",  256);

    busdev = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(busdev, &error_fatal);
    sysbus_mmio_map(busdev, 0, 0xF8003000);
    sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
    for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
        sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
    }

    dev = qdev_new("xlnx.ps7-dev-cfg");
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_realize_and_unref(busdev, &error_fatal);
    sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
    sysbus_mmio_map(busdev, 0, 0xF8007000);

    zynq_binfo.ram_size = machine->ram_size;
    zynq_binfo.nb_cpus = 1;
    zynq_binfo.board_id = 0xd32;
    zynq_binfo.loader_start = 0;
    zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
    zynq_binfo.write_board_setup = zynq_write_board_setup;

    arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
}

static void zynq_machine_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);
    mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
    mc->init = zynq_init;
    mc->max_cpus = 1;
    mc->no_sdcard = 1;
    mc->ignore_memory_transaction_failures = true;
    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
    mc->default_ram_id = "zynq.ext_ram";
}

static const TypeInfo zynq_machine_type = {
    .name = TYPE_ZYNQ_MACHINE,
    .parent = TYPE_MACHINE,
    .class_init = zynq_machine_class_init,
    .instance_size = sizeof(ZynqMachineState),
};

static void zynq_machine_register_types(void)
{
    type_register_static(&zynq_machine_type);
}

type_init(zynq_machine_register_types)
Commit	Line	Data
e3260506 PC	1	/*
	2	* Xilinx Zynq Baseboard System emulation.
	3	*
	4	* Copyright (c) 2010 Xilinx.
	5	* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
	6	* Copyright (c) 2012 Petalogix Pty Ltd.
	7	* Written by Haibing Ma
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
77a7cc61	19	#include "qemu/units.h"
da34e65c	20	#include "qapi/error.h"
4771d756	21	#include "cpu.h"
83c9f4ca	22	#include "hw/sysbus.h"
12ec8bd5	23	#include "hw/arm/boot.h"
1422e32d	24	#include "net/net.h"
022c62cb	25	#include "exec/address-spaces.h"
9c17d615	26	#include "sysemu/sysemu.h"
83c9f4ca	27	#include "hw/boards.h"
0d09e41a	28	#include "hw/block/flash.h"
83c9f4ca	29	#include "hw/loader.h"
74fcbd22	30	#include "hw/misc/zynq-xadc.h"
8fd06719	31	#include "hw/ssi/ssi.h"
616ec12d	32	#include "hw/usb/chipidea.h"
d8bbdcf8	33	#include "qemu/error-report.h"
c2de81e2	34	#include "hw/sd/sdhci.h"
4be12ea0	35	#include "hw/char/cadence_uart.h"
c2de81e2 PMD	36	#include "hw/net/cadence_gem.h"
c2de81e2 PMD	37	#include "hw/cpu/a9mpcore.h"
5b49a34c DH	38	#include "hw/qdev-clock.h"
	39	#include "sysemu/reset.h"
	40
	41	#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
	42	#define ZYNQ_MACHINE(obj) \
	43	OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
	44
	45	/* board base frequency: 33.333333 MHz */
	46	#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
559d489f PC	47
559d489f PC	48	#define NUM_SPI_FLASHES 4
7b482bcf PC	49	#define NUM_QSPI_FLASHES 2
7b482bcf PC	50	#define NUM_QSPI_BUSSES 2
e3260506 PC	51
	52	#define FLASH_SIZE (64 * 1024 * 1024)
	53	#define FLASH_SECTOR_SIZE (128 * 1024)
	54
	55	#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
	56
c2577128	57	#define MPCORE_PERIPHBASE 0xF8F00000
b48adc0d	58	#define ZYNQ_BOARD_MIDR 0x413FC090
c2577128	59
7451afb6 PC	60	static const int dma_irqs[8] = {
	61	46, 47, 48, 49, 72, 73, 74, 75
	62	};
	63
c3a9a689 PC	64	#define BOARD_SETUP_ADDR 0x100
	65
	66	#define SLCR_LOCK_OFFSET 0x004
	67	#define SLCR_UNLOCK_OFFSET 0x008
	68	#define SLCR_ARM_PLL_OFFSET 0x100
	69
	70	#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
	71	#define SLCR_XILINX_LOCK_KEY 0x767b
	72
27a49d3b PMD	73	#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
27a49d3b PMD	74
c3a9a689 PC	75	#define ARMV7_IMM16(x) (extract32((x), 0, 12) \| \
	76	extract32((x), 12, 4) << 16)
	77
	78	/* Write immediate val to address r0 + addr. r0 should contain base offset
	79	* of the SLCR block. Clobbers r1.
	80	*/
	81
	82	#define SLCR_WRITE(addr, val) \
	83	0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
	84	0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
	85	0xe5801000 + (addr)
	86
5b49a34c DH	87	typedef struct ZynqMachineState {
	88	MachineState parent;
	89	Clock *ps_clk;
	90	} ZynqMachineState;
	91
c3a9a689 PC	92	static void zynq_write_board_setup(ARMCPU *cpu,
	93	const struct arm_boot_info *info)
	94	{
	95	int n;
	96	uint32_t board_setup_blob[] = {
	97	0xe3a004f8, /* mov r0, #0xf8000000 */
	98	SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
	99	SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
	100	SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
	101	0xe12fff1e, /* bx lr */
	102	};
	103	for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
	104	board_setup_blob[n] = tswap32(board_setup_blob[n]);
	105	}
	106	rom_add_blob_fixed("board-setup", board_setup_blob,
	107	sizeof(board_setup_blob), BOARD_SETUP_ADDR);
	108	}
	109
e3260506 PC	110	static struct arm_boot_info zynq_binfo = {};
	111
	112	static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
	113	{
	114	DeviceState *dev;
	115	SysBusDevice *s;
	116
3e80f690	117	dev = qdev_new(TYPE_CADENCE_GEM);
7fcd57e8	118	if (nd->used) {
c2de81e2	119	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
7fcd57e8 PC	120	qdev_set_nic_properties(dev, nd);
7fcd57e8 PC	121	}
1356b98d	122	s = SYS_BUS_DEVICE(dev);
3c6ef471	123	sysbus_realize_and_unref(s, &error_fatal);
e3260506 PC	124	sysbus_mmio_map(s, 0, base);
	125	sysbus_connect_irq(s, 0, irq);
	126	}
	127
7b482bcf PC	128	static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
7b482bcf PC	129	bool is_qspi)
559d489f PC	130	{
	131	DeviceState *dev;
	132	SysBusDevice *busdev;
	133	SSIBus *spi;
79f5d67e	134	DeviceState *flash_dev;
7b482bcf PC	135	int i, j;
	136	int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
	137	int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
559d489f	138
3e80f690	139	dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
7b482bcf PC	140	qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
	141	qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
	142	qdev_prop_set_uint8(dev, "num-busses", num_busses);
1356b98d	143	busdev = SYS_BUS_DEVICE(dev);
3c6ef471	144	sysbus_realize_and_unref(busdev, &error_fatal);
559d489f	145	sysbus_mmio_map(busdev, 0, base_addr);
7b482bcf PC	146	if (is_qspi) {
	147	sysbus_mmio_map(busdev, 1, 0xFC000000);
	148	}
559d489f PC	149	sysbus_connect_irq(busdev, 0, irq);
559d489f PC	150
7b482bcf PC	151	for (i = 0; i < num_busses; ++i) {
7b482bcf PC	152	char bus_name[16];
559d489f PC	153	qemu_irq cs_line;
559d489f PC	154
7b482bcf PC	155	snprintf(bus_name, 16, "spi%d", i);
	156	spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
	157
	158	for (j = 0; j < num_ss; ++j) {
73bce518	159	DriveInfo *dinfo = drive_get_next(IF_MTD);
57d479c9	160	flash_dev = qdev_new("n25q128");
73bce518 PB	161	if (dinfo) {
	162	qdev_prop_set_drive(flash_dev, "drive",
	163	blk_by_legacy_dinfo(dinfo), &error_fatal);
	164	}
57d479c9	165	qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
559d489f	166
de77914e	167	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
7b482bcf PC	168	sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
7b482bcf PC	169	}
559d489f PC	170	}
	171
	172	}
	173
3ef96221	174	static void zynq_init(MachineState *machine)
e3260506	175	{
5b49a34c	176	ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
17c2f0bf	177	ARMCPU *cpu;
e3260506	178	MemoryRegion *address_space_mem = get_system_memory();
e3260506	179	MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
5b49a34c	180	DeviceState dev, slcr;
e3260506	181	SysBusDevice *busdev;
e3260506	182	qemu_irq pic[64];
e3260506	183	int n;
e3260506	184
c9800965 IM	185	/* max 2GB ram */
	186	if (machine->ram_size > 2 * GiB) {
	187	error_report("RAM size more than 2 GiB is not supported");
	188	exit(EXIT_FAILURE);
	189	}
	190
ba1ba5cc	191	cpu = ARM_CPU(object_new(machine->cpu_type));
d8bbdcf8	192
61e2f352 GB	193	/* By default A9 CPUs have EL3 enabled. This board does not
	194	* currently support EL3 so the CPU EL3 property is disabled before
	195	* realization.
	196	*/
	197	if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
007b0657	198	object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
b48adc0d AF	199	}
b48adc0d AF	200
007b0657 MA	201	object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
	202	&error_fatal);
	203	object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
	204	&error_fatal);
ce189ab2	205	qdev_realize(DEVICE(cpu), NULL, &error_fatal);
e3260506	206
e3260506	207	/* DDR remapped to address zero. */
8182d3d1	208	memory_region_add_subregion(address_space_mem, 0, machine->ram);
e3260506 PC	209
e3260506 PC	210	/* 256K of on-chip memory */
77a7cc61	211	memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
f8ed85ac	212	&error_fatal);
e3260506 PC	213	memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
	214
	215	DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
	216
	217	/* AMD */
940d5b13	218	pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
4be74634	219	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	220	FLASH_SECTOR_SIZE, 1,
e3260506	221	1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
ce14710f	222	0);
e3260506	223
5b49a34c	224	/* Create slcr, keep a pointer to connect clocks */
3e80f690	225	slcr = qdev_new("xilinx,zynq_slcr");
3c6ef471	226	sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
5b49a34c DH	227	sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
	228
	229	/* Create the main clock source, and feed slcr with it */
	230	zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
	231	object_property_add_child(OBJECT(zynq_machine), "ps_clk",
d2623129	232	OBJECT(zynq_machine->ps_clk));
5b49a34c DH	233	object_unref(OBJECT(zynq_machine->ps_clk));
	234	clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
	235	qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
e3260506	236
3e80f690	237	dev = qdev_new(TYPE_A9MPCORE_PRIV);
e3260506	238	qdev_prop_set_uint32(dev, "num-cpu", 1);
1356b98d	239	busdev = SYS_BUS_DEVICE(dev);
3c6ef471	240	sysbus_realize_and_unref(busdev, &error_fatal);
c2577128	241	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
e4a6540d PM	242	sysbus_connect_irq(busdev, 0,
e4a6540d PM	243	qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
e3260506 PC	244
	245	for (n = 0; n < 64; n++) {
	246	pic[n] = qdev_get_gpio_in(dev, n);
	247	}
	248
7b482bcf PC	249	zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
	250	zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
	251	zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
559d489f	252
616ec12d GR	253	sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
616ec12d GR	254	sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
892776ce	255
5b49a34c DH	256	dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
	257	qdev_connect_clock_in(dev, "refclk",
	258	qdev_get_clock_out(slcr, "uart0_ref_clk"));
	259	dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
	260	qdev_connect_clock_in(dev, "refclk",
	261	qdev_get_clock_out(slcr, "uart1_ref_clk"));
e3260506 PC	262
	263	sysbus_create_varargs("cadence_ttc", 0xF8001000,
	264	pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
	265	sysbus_create_varargs("cadence_ttc", 0xF8002000,
	266	pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
	267
7fcd57e8 PC	268	gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
7fcd57e8 PC	269	gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
e3260506	270
27a49d3b PMD	271	for (n = 0; n < 2; n++) {
	272	int hci_irq = n ? 79 : 56;
	273	hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
	274	DriveInfo *di;
	275	BlockBackend *blk;
	276	DeviceState *carddev;
	277
	278	/* Compatible with:
	279	* - SD Host Controller Specification Version 2.0 Part A2
	280	* - SDIO Specification Version 2.0
	281	* - MMC Specification Version 3.31
	282	*/
3e80f690	283	dev = qdev_new(TYPE_SYSBUS_SDHCI);
27a49d3b PMD	284	qdev_prop_set_uint8(dev, "sd-spec-version", 2);
27a49d3b PMD	285	qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
3c6ef471	286	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
27a49d3b PMD	287	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
	288	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
	289
	290	di = drive_get_next(IF_SD);
	291	blk = di ? blk_by_legacy_dinfo(di) : NULL;
3e80f690	292	carddev = qdev_new(TYPE_SD_CARD);
27a49d3b	293	qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
3e80f690 MA	294	qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
3e80f690 MA	295	&error_fatal);
27a49d3b	296	}
eb4f566b	297
3e80f690	298	dev = qdev_new(TYPE_ZYNQ_XADC);
3c6ef471	299	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
74fcbd22 GR	300	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
	301	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
	302
3e80f690	303	dev = qdev_new("pl330");
7451afb6 PC	304	qdev_prop_set_uint8(dev, "num_chnls", 8);
	305	qdev_prop_set_uint8(dev, "num_periph_req", 4);
	306	qdev_prop_set_uint8(dev, "num_events", 16);
	307
	308	qdev_prop_set_uint8(dev, "data_width", 64);
	309	qdev_prop_set_uint8(dev, "wr_cap", 8);
	310	qdev_prop_set_uint8(dev, "wr_q_dep", 16);
	311	qdev_prop_set_uint8(dev, "rd_cap", 8);
	312	qdev_prop_set_uint8(dev, "rd_q_dep", 16);
	313	qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
	314
7451afb6	315	busdev = SYS_BUS_DEVICE(dev);
3c6ef471	316	sysbus_realize_and_unref(busdev, &error_fatal);
7451afb6 PC	317	sysbus_mmio_map(busdev, 0, 0xF8003000);
7451afb6 PC	318	sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
5e9fcbd7	319	for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
7451afb6 PC	320	sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
	321	}
	322
3e80f690	323	dev = qdev_new("xlnx.ps7-dev-cfg");
f4b99537	324	busdev = SYS_BUS_DEVICE(dev);
3c6ef471	325	sysbus_realize_and_unref(busdev, &error_fatal);
f4b99537 PC	326	sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
	327	sysbus_mmio_map(busdev, 0, 0xF8007000);
	328
c9800965	329	zynq_binfo.ram_size = machine->ram_size;
e3260506 PC	330	zynq_binfo.nb_cpus = 1;
	331	zynq_binfo.board_id = 0xd32;
	332	zynq_binfo.loader_start = 0;
c3a9a689 PC	333	zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
	334	zynq_binfo.write_board_setup = zynq_write_board_setup;
	335
2744ece8	336	arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
e3260506 PC	337	}
e3260506 PC	338
5b49a34c	339	static void zynq_machine_class_init(ObjectClass oc, void data)
e3260506	340	{
5b49a34c	341	MachineClass *mc = MACHINE_CLASS(oc);
e264d29d EH	342	mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
e264d29d EH	343	mc->init = zynq_init;
e264d29d EH	344	mc->max_cpus = 1;
e264d29d EH	345	mc->no_sdcard = 1;
4672cbd7	346	mc->ignore_memory_transaction_failures = true;
ba1ba5cc	347	mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
8182d3d1	348	mc->default_ram_id = "zynq.ext_ram";
e3260506 PC	349	}
e3260506 PC	350
5b49a34c DH	351	static const TypeInfo zynq_machine_type = {
	352	.name = TYPE_ZYNQ_MACHINE,
	353	.parent = TYPE_MACHINE,
	354	.class_init = zynq_machine_class_init,
	355	.instance_size = sizeof(ZynqMachineState),
	356	};
	357
	358	static void zynq_machine_register_types(void)
	359	{
	360	type_register_static(&zynq_machine_type);
	361	}
	362
	363	type_init(zynq_machine_register_types)