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e3260506 PC |
1 | /* |
2 | * Xilinx Zynq Baseboard System emulation. | |
3 | * | |
4 | * Copyright (c) 2010 Xilinx. | |
5 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) | |
6 | * Copyright (c) 2012 Petalogix Pty Ltd. | |
7 | * Written by Haibing Ma | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
12b16722 | 18 | #include "qemu/osdep.h" |
da34e65c | 19 | #include "qapi/error.h" |
83c9f4ca | 20 | #include "hw/sysbus.h" |
bd2be150 | 21 | #include "hw/arm/arm.h" |
1422e32d | 22 | #include "net/net.h" |
022c62cb | 23 | #include "exec/address-spaces.h" |
9c17d615 | 24 | #include "sysemu/sysemu.h" |
83c9f4ca | 25 | #include "hw/boards.h" |
0d09e41a | 26 | #include "hw/block/flash.h" |
fa1d36df | 27 | #include "sysemu/block-backend.h" |
83c9f4ca | 28 | #include "hw/loader.h" |
74fcbd22 | 29 | #include "hw/misc/zynq-xadc.h" |
8fd06719 | 30 | #include "hw/ssi/ssi.h" |
d8bbdcf8 | 31 | #include "qemu/error-report.h" |
eb4f566b | 32 | #include "hw/sd/sd.h" |
559d489f PC |
33 | |
34 | #define NUM_SPI_FLASHES 4 | |
7b482bcf PC |
35 | #define NUM_QSPI_FLASHES 2 |
36 | #define NUM_QSPI_BUSSES 2 | |
e3260506 PC |
37 | |
38 | #define FLASH_SIZE (64 * 1024 * 1024) | |
39 | #define FLASH_SECTOR_SIZE (128 * 1024) | |
40 | ||
41 | #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ | |
42 | ||
c2577128 | 43 | #define MPCORE_PERIPHBASE 0xF8F00000 |
b48adc0d | 44 | #define ZYNQ_BOARD_MIDR 0x413FC090 |
c2577128 | 45 | |
7451afb6 PC |
46 | static const int dma_irqs[8] = { |
47 | 46, 47, 48, 49, 72, 73, 74, 75 | |
48 | }; | |
49 | ||
c3a9a689 PC |
50 | #define BOARD_SETUP_ADDR 0x100 |
51 | ||
52 | #define SLCR_LOCK_OFFSET 0x004 | |
53 | #define SLCR_UNLOCK_OFFSET 0x008 | |
54 | #define SLCR_ARM_PLL_OFFSET 0x100 | |
55 | ||
56 | #define SLCR_XILINX_UNLOCK_KEY 0xdf0d | |
57 | #define SLCR_XILINX_LOCK_KEY 0x767b | |
58 | ||
59 | #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ | |
60 | extract32((x), 12, 4) << 16) | |
61 | ||
62 | /* Write immediate val to address r0 + addr. r0 should contain base offset | |
63 | * of the SLCR block. Clobbers r1. | |
64 | */ | |
65 | ||
66 | #define SLCR_WRITE(addr, val) \ | |
67 | 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ | |
68 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ | |
69 | 0xe5801000 + (addr) | |
70 | ||
71 | static void zynq_write_board_setup(ARMCPU *cpu, | |
72 | const struct arm_boot_info *info) | |
73 | { | |
74 | int n; | |
75 | uint32_t board_setup_blob[] = { | |
76 | 0xe3a004f8, /* mov r0, #0xf8000000 */ | |
77 | SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), | |
78 | SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), | |
79 | SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), | |
80 | 0xe12fff1e, /* bx lr */ | |
81 | }; | |
82 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | |
83 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | |
84 | } | |
85 | rom_add_blob_fixed("board-setup", board_setup_blob, | |
86 | sizeof(board_setup_blob), BOARD_SETUP_ADDR); | |
87 | } | |
88 | ||
e3260506 PC |
89 | static struct arm_boot_info zynq_binfo = {}; |
90 | ||
91 | static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) | |
92 | { | |
93 | DeviceState *dev; | |
94 | SysBusDevice *s; | |
95 | ||
e3260506 | 96 | dev = qdev_create(NULL, "cadence_gem"); |
7fcd57e8 PC |
97 | if (nd->used) { |
98 | qemu_check_nic_model(nd, "cadence_gem"); | |
99 | qdev_set_nic_properties(dev, nd); | |
100 | } | |
e3260506 | 101 | qdev_init_nofail(dev); |
1356b98d | 102 | s = SYS_BUS_DEVICE(dev); |
e3260506 PC |
103 | sysbus_mmio_map(s, 0, base); |
104 | sysbus_connect_irq(s, 0, irq); | |
105 | } | |
106 | ||
7b482bcf PC |
107 | static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, |
108 | bool is_qspi) | |
559d489f PC |
109 | { |
110 | DeviceState *dev; | |
111 | SysBusDevice *busdev; | |
112 | SSIBus *spi; | |
79f5d67e | 113 | DeviceState *flash_dev; |
7b482bcf PC |
114 | int i, j; |
115 | int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; | |
116 | int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; | |
559d489f | 117 | |
6b91f015 | 118 | dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); |
7b482bcf PC |
119 | qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); |
120 | qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); | |
121 | qdev_prop_set_uint8(dev, "num-busses", num_busses); | |
559d489f | 122 | qdev_init_nofail(dev); |
1356b98d | 123 | busdev = SYS_BUS_DEVICE(dev); |
559d489f | 124 | sysbus_mmio_map(busdev, 0, base_addr); |
7b482bcf PC |
125 | if (is_qspi) { |
126 | sysbus_mmio_map(busdev, 1, 0xFC000000); | |
127 | } | |
559d489f PC |
128 | sysbus_connect_irq(busdev, 0, irq); |
129 | ||
7b482bcf PC |
130 | for (i = 0; i < num_busses; ++i) { |
131 | char bus_name[16]; | |
559d489f PC |
132 | qemu_irq cs_line; |
133 | ||
7b482bcf PC |
134 | snprintf(bus_name, 16, "spi%d", i); |
135 | spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); | |
136 | ||
137 | for (j = 0; j < num_ss; ++j) { | |
f1922e36 | 138 | flash_dev = ssi_create_slave(spi, "n25q128"); |
559d489f | 139 | |
de77914e | 140 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
7b482bcf PC |
141 | sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); |
142 | } | |
559d489f PC |
143 | } |
144 | ||
145 | } | |
146 | ||
3ef96221 | 147 | static void zynq_init(MachineState *machine) |
e3260506 | 148 | { |
3ef96221 MA |
149 | ram_addr_t ram_size = machine->ram_size; |
150 | const char *cpu_model = machine->cpu_model; | |
151 | const char *kernel_filename = machine->kernel_filename; | |
152 | const char *kernel_cmdline = machine->kernel_cmdline; | |
153 | const char *initrd_filename = machine->initrd_filename; | |
d8bbdcf8 | 154 | ObjectClass *cpu_oc; |
17c2f0bf | 155 | ARMCPU *cpu; |
e3260506 PC |
156 | MemoryRegion *address_space_mem = get_system_memory(); |
157 | MemoryRegion *ext_ram = g_new(MemoryRegion, 1); | |
158 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); | |
eb4f566b | 159 | DeviceState *dev, *carddev; |
e3260506 | 160 | SysBusDevice *busdev; |
eb4f566b PM |
161 | DriveInfo *di; |
162 | BlockBackend *blk; | |
e3260506 | 163 | qemu_irq pic[64]; |
e3260506 | 164 | int n; |
e3260506 PC |
165 | |
166 | if (!cpu_model) { | |
167 | cpu_model = "cortex-a9"; | |
168 | } | |
d8bbdcf8 | 169 | cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); |
e3260506 | 170 | |
d8bbdcf8 PC |
171 | cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc))); |
172 | ||
61e2f352 GB |
173 | /* By default A9 CPUs have EL3 enabled. This board does not |
174 | * currently support EL3 so the CPU EL3 property is disabled before | |
175 | * realization. | |
176 | */ | |
177 | if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { | |
007b0657 | 178 | object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); |
b48adc0d AF |
179 | } |
180 | ||
007b0657 MA |
181 | object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", |
182 | &error_fatal); | |
183 | object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", | |
184 | &error_fatal); | |
185 | object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); | |
e3260506 PC |
186 | |
187 | /* max 2GB ram */ | |
188 | if (ram_size > 0x80000000) { | |
189 | ram_size = 0x80000000; | |
190 | } | |
191 | ||
192 | /* DDR remapped to address zero. */ | |
c8623c02 DM |
193 | memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", |
194 | ram_size); | |
e3260506 PC |
195 | memory_region_add_subregion(address_space_mem, 0, ext_ram); |
196 | ||
197 | /* 256K of on-chip memory */ | |
49946538 | 198 | memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, |
f8ed85ac | 199 | &error_fatal); |
e3260506 PC |
200 | vmstate_register_ram_global(ocm_ram); |
201 | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); | |
202 | ||
203 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); | |
204 | ||
205 | /* AMD */ | |
206 | pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE, | |
4be74634 | 207 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
fa1d36df | 208 | FLASH_SECTOR_SIZE, |
e3260506 PC |
209 | FLASH_SIZE/FLASH_SECTOR_SIZE, 1, |
210 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, | |
211 | 0); | |
212 | ||
213 | dev = qdev_create(NULL, "xilinx,zynq_slcr"); | |
214 | qdev_init_nofail(dev); | |
1356b98d | 215 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); |
e3260506 PC |
216 | |
217 | dev = qdev_create(NULL, "a9mpcore_priv"); | |
218 | qdev_prop_set_uint32(dev, "num-cpu", 1); | |
219 | qdev_init_nofail(dev); | |
1356b98d | 220 | busdev = SYS_BUS_DEVICE(dev); |
c2577128 | 221 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
e4a6540d PM |
222 | sysbus_connect_irq(busdev, 0, |
223 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | |
e3260506 PC |
224 | |
225 | for (n = 0; n < 64; n++) { | |
226 | pic[n] = qdev_get_gpio_in(dev, n); | |
227 | } | |
228 | ||
7b482bcf PC |
229 | zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); |
230 | zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); | |
231 | zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); | |
559d489f | 232 | |
892776ce | 233 | sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); |
70ef6a5b | 234 | sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); |
892776ce | 235 | |
e3260506 PC |
236 | sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); |
237 | sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); | |
238 | ||
239 | sysbus_create_varargs("cadence_ttc", 0xF8001000, | |
240 | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); | |
241 | sysbus_create_varargs("cadence_ttc", 0xF8002000, | |
242 | pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); | |
243 | ||
7fcd57e8 PC |
244 | gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); |
245 | gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); | |
e3260506 | 246 | |
b972b4e2 PC |
247 | dev = qdev_create(NULL, "generic-sdhci"); |
248 | qdev_init_nofail(dev); | |
249 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000); | |
250 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]); | |
251 | ||
eb4f566b PM |
252 | di = drive_get_next(IF_SD); |
253 | blk = di ? blk_by_legacy_dinfo(di) : NULL; | |
254 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); | |
255 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | |
256 | object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); | |
257 | ||
b972b4e2 PC |
258 | dev = qdev_create(NULL, "generic-sdhci"); |
259 | qdev_init_nofail(dev); | |
260 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); | |
261 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]); | |
262 | ||
eb4f566b PM |
263 | di = drive_get_next(IF_SD); |
264 | blk = di ? blk_by_legacy_dinfo(di) : NULL; | |
265 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); | |
266 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | |
267 | object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal); | |
268 | ||
74fcbd22 GR |
269 | dev = qdev_create(NULL, TYPE_ZYNQ_XADC); |
270 | qdev_init_nofail(dev); | |
271 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); | |
272 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); | |
273 | ||
7451afb6 PC |
274 | dev = qdev_create(NULL, "pl330"); |
275 | qdev_prop_set_uint8(dev, "num_chnls", 8); | |
276 | qdev_prop_set_uint8(dev, "num_periph_req", 4); | |
277 | qdev_prop_set_uint8(dev, "num_events", 16); | |
278 | ||
279 | qdev_prop_set_uint8(dev, "data_width", 64); | |
280 | qdev_prop_set_uint8(dev, "wr_cap", 8); | |
281 | qdev_prop_set_uint8(dev, "wr_q_dep", 16); | |
282 | qdev_prop_set_uint8(dev, "rd_cap", 8); | |
283 | qdev_prop_set_uint8(dev, "rd_q_dep", 16); | |
284 | qdev_prop_set_uint16(dev, "data_buffer_dep", 256); | |
285 | ||
286 | qdev_init_nofail(dev); | |
287 | busdev = SYS_BUS_DEVICE(dev); | |
288 | sysbus_mmio_map(busdev, 0, 0xF8003000); | |
289 | sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ | |
290 | for (n = 0; n < 8; ++n) { /* event irqs */ | |
291 | sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); | |
292 | } | |
293 | ||
e3260506 PC |
294 | zynq_binfo.ram_size = ram_size; |
295 | zynq_binfo.kernel_filename = kernel_filename; | |
296 | zynq_binfo.kernel_cmdline = kernel_cmdline; | |
297 | zynq_binfo.initrd_filename = initrd_filename; | |
298 | zynq_binfo.nb_cpus = 1; | |
299 | zynq_binfo.board_id = 0xd32; | |
300 | zynq_binfo.loader_start = 0; | |
c3a9a689 PC |
301 | zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; |
302 | zynq_binfo.write_board_setup = zynq_write_board_setup; | |
303 | ||
182735ef | 304 | arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); |
e3260506 PC |
305 | } |
306 | ||
e264d29d | 307 | static void zynq_machine_init(MachineClass *mc) |
e3260506 | 308 | { |
e264d29d EH |
309 | mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; |
310 | mc->init = zynq_init; | |
311 | mc->block_default_type = IF_SCSI; | |
312 | mc->max_cpus = 1; | |
313 | mc->no_sdcard = 1; | |
e3260506 PC |
314 | } |
315 | ||
e264d29d | 316 | DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) |