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e3260506 PC |
1 | /* |
2 | * Xilinx Zynq Baseboard System emulation. | |
3 | * | |
4 | * Copyright (c) 2010 Xilinx. | |
5 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) | |
6 | * Copyright (c) 2012 Petalogix Pty Ltd. | |
7 | * Written by Haibing Ma | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along | |
15 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
12b16722 | 18 | #include "qemu/osdep.h" |
77a7cc61 | 19 | #include "qemu/units.h" |
da34e65c | 20 | #include "qapi/error.h" |
4771d756 | 21 | #include "cpu.h" |
83c9f4ca | 22 | #include "hw/sysbus.h" |
12ec8bd5 | 23 | #include "hw/arm/boot.h" |
1422e32d | 24 | #include "net/net.h" |
022c62cb | 25 | #include "exec/address-spaces.h" |
9c17d615 | 26 | #include "sysemu/sysemu.h" |
83c9f4ca | 27 | #include "hw/boards.h" |
0d09e41a | 28 | #include "hw/block/flash.h" |
83c9f4ca | 29 | #include "hw/loader.h" |
74fcbd22 | 30 | #include "hw/misc/zynq-xadc.h" |
8fd06719 | 31 | #include "hw/ssi/ssi.h" |
d8bbdcf8 | 32 | #include "qemu/error-report.h" |
c2de81e2 | 33 | #include "hw/sd/sdhci.h" |
4be12ea0 | 34 | #include "hw/char/cadence_uart.h" |
c2de81e2 PMD |
35 | #include "hw/net/cadence_gem.h" |
36 | #include "hw/cpu/a9mpcore.h" | |
559d489f PC |
37 | |
38 | #define NUM_SPI_FLASHES 4 | |
7b482bcf PC |
39 | #define NUM_QSPI_FLASHES 2 |
40 | #define NUM_QSPI_BUSSES 2 | |
e3260506 PC |
41 | |
42 | #define FLASH_SIZE (64 * 1024 * 1024) | |
43 | #define FLASH_SECTOR_SIZE (128 * 1024) | |
44 | ||
45 | #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ | |
46 | ||
c2577128 | 47 | #define MPCORE_PERIPHBASE 0xF8F00000 |
b48adc0d | 48 | #define ZYNQ_BOARD_MIDR 0x413FC090 |
c2577128 | 49 | |
7451afb6 PC |
50 | static const int dma_irqs[8] = { |
51 | 46, 47, 48, 49, 72, 73, 74, 75 | |
52 | }; | |
53 | ||
c3a9a689 PC |
54 | #define BOARD_SETUP_ADDR 0x100 |
55 | ||
56 | #define SLCR_LOCK_OFFSET 0x004 | |
57 | #define SLCR_UNLOCK_OFFSET 0x008 | |
58 | #define SLCR_ARM_PLL_OFFSET 0x100 | |
59 | ||
60 | #define SLCR_XILINX_UNLOCK_KEY 0xdf0d | |
61 | #define SLCR_XILINX_LOCK_KEY 0x767b | |
62 | ||
27a49d3b PMD |
63 | #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ |
64 | ||
c3a9a689 PC |
65 | #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ |
66 | extract32((x), 12, 4) << 16) | |
67 | ||
68 | /* Write immediate val to address r0 + addr. r0 should contain base offset | |
69 | * of the SLCR block. Clobbers r1. | |
70 | */ | |
71 | ||
72 | #define SLCR_WRITE(addr, val) \ | |
73 | 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ | |
74 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ | |
75 | 0xe5801000 + (addr) | |
76 | ||
77 | static void zynq_write_board_setup(ARMCPU *cpu, | |
78 | const struct arm_boot_info *info) | |
79 | { | |
80 | int n; | |
81 | uint32_t board_setup_blob[] = { | |
82 | 0xe3a004f8, /* mov r0, #0xf8000000 */ | |
83 | SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), | |
84 | SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), | |
85 | SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), | |
86 | 0xe12fff1e, /* bx lr */ | |
87 | }; | |
88 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { | |
89 | board_setup_blob[n] = tswap32(board_setup_blob[n]); | |
90 | } | |
91 | rom_add_blob_fixed("board-setup", board_setup_blob, | |
92 | sizeof(board_setup_blob), BOARD_SETUP_ADDR); | |
93 | } | |
94 | ||
e3260506 PC |
95 | static struct arm_boot_info zynq_binfo = {}; |
96 | ||
97 | static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) | |
98 | { | |
99 | DeviceState *dev; | |
100 | SysBusDevice *s; | |
101 | ||
c2de81e2 | 102 | dev = qdev_create(NULL, TYPE_CADENCE_GEM); |
7fcd57e8 | 103 | if (nd->used) { |
c2de81e2 | 104 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); |
7fcd57e8 PC |
105 | qdev_set_nic_properties(dev, nd); |
106 | } | |
e3260506 | 107 | qdev_init_nofail(dev); |
1356b98d | 108 | s = SYS_BUS_DEVICE(dev); |
e3260506 PC |
109 | sysbus_mmio_map(s, 0, base); |
110 | sysbus_connect_irq(s, 0, irq); | |
111 | } | |
112 | ||
7b482bcf PC |
113 | static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, |
114 | bool is_qspi) | |
559d489f PC |
115 | { |
116 | DeviceState *dev; | |
117 | SysBusDevice *busdev; | |
118 | SSIBus *spi; | |
79f5d67e | 119 | DeviceState *flash_dev; |
7b482bcf PC |
120 | int i, j; |
121 | int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; | |
122 | int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; | |
559d489f | 123 | |
6b91f015 | 124 | dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); |
7b482bcf PC |
125 | qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); |
126 | qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); | |
127 | qdev_prop_set_uint8(dev, "num-busses", num_busses); | |
559d489f | 128 | qdev_init_nofail(dev); |
1356b98d | 129 | busdev = SYS_BUS_DEVICE(dev); |
559d489f | 130 | sysbus_mmio_map(busdev, 0, base_addr); |
7b482bcf PC |
131 | if (is_qspi) { |
132 | sysbus_mmio_map(busdev, 1, 0xFC000000); | |
133 | } | |
559d489f PC |
134 | sysbus_connect_irq(busdev, 0, irq); |
135 | ||
7b482bcf PC |
136 | for (i = 0; i < num_busses; ++i) { |
137 | char bus_name[16]; | |
559d489f PC |
138 | qemu_irq cs_line; |
139 | ||
7b482bcf PC |
140 | snprintf(bus_name, 16, "spi%d", i); |
141 | spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); | |
142 | ||
143 | for (j = 0; j < num_ss; ++j) { | |
73bce518 PB |
144 | DriveInfo *dinfo = drive_get_next(IF_MTD); |
145 | flash_dev = ssi_create_slave_no_init(spi, "n25q128"); | |
146 | if (dinfo) { | |
147 | qdev_prop_set_drive(flash_dev, "drive", | |
148 | blk_by_legacy_dinfo(dinfo), &error_fatal); | |
149 | } | |
150 | qdev_init_nofail(flash_dev); | |
559d489f | 151 | |
de77914e | 152 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
7b482bcf PC |
153 | sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); |
154 | } | |
559d489f PC |
155 | } |
156 | ||
157 | } | |
158 | ||
3ef96221 | 159 | static void zynq_init(MachineState *machine) |
e3260506 | 160 | { |
17c2f0bf | 161 | ARMCPU *cpu; |
e3260506 | 162 | MemoryRegion *address_space_mem = get_system_memory(); |
e3260506 | 163 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); |
27a49d3b | 164 | DeviceState *dev; |
e3260506 | 165 | SysBusDevice *busdev; |
e3260506 | 166 | qemu_irq pic[64]; |
e3260506 | 167 | int n; |
e3260506 | 168 | |
c9800965 IM |
169 | /* max 2GB ram */ |
170 | if (machine->ram_size > 2 * GiB) { | |
171 | error_report("RAM size more than 2 GiB is not supported"); | |
172 | exit(EXIT_FAILURE); | |
173 | } | |
174 | ||
ba1ba5cc | 175 | cpu = ARM_CPU(object_new(machine->cpu_type)); |
d8bbdcf8 | 176 | |
61e2f352 GB |
177 | /* By default A9 CPUs have EL3 enabled. This board does not |
178 | * currently support EL3 so the CPU EL3 property is disabled before | |
179 | * realization. | |
180 | */ | |
181 | if (object_property_find(OBJECT(cpu), "has_el3", NULL)) { | |
007b0657 | 182 | object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal); |
b48adc0d AF |
183 | } |
184 | ||
007b0657 MA |
185 | object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", |
186 | &error_fatal); | |
187 | object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", | |
188 | &error_fatal); | |
189 | object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); | |
e3260506 | 190 | |
e3260506 | 191 | /* DDR remapped to address zero. */ |
8182d3d1 | 192 | memory_region_add_subregion(address_space_mem, 0, machine->ram); |
e3260506 PC |
193 | |
194 | /* 256K of on-chip memory */ | |
77a7cc61 | 195 | memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, |
f8ed85ac | 196 | &error_fatal); |
e3260506 PC |
197 | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); |
198 | ||
199 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); | |
200 | ||
201 | /* AMD */ | |
940d5b13 | 202 | pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, |
4be74634 | 203 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
ce14710f | 204 | FLASH_SECTOR_SIZE, 1, |
e3260506 | 205 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, |
ce14710f | 206 | 0); |
e3260506 PC |
207 | |
208 | dev = qdev_create(NULL, "xilinx,zynq_slcr"); | |
209 | qdev_init_nofail(dev); | |
1356b98d | 210 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); |
e3260506 | 211 | |
c2de81e2 | 212 | dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); |
e3260506 PC |
213 | qdev_prop_set_uint32(dev, "num-cpu", 1); |
214 | qdev_init_nofail(dev); | |
1356b98d | 215 | busdev = SYS_BUS_DEVICE(dev); |
c2577128 | 216 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
e4a6540d PM |
217 | sysbus_connect_irq(busdev, 0, |
218 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | |
e3260506 PC |
219 | |
220 | for (n = 0; n < 64; n++) { | |
221 | pic[n] = qdev_get_gpio_in(dev, n); | |
222 | } | |
223 | ||
7b482bcf PC |
224 | zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); |
225 | zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); | |
226 | zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); | |
559d489f | 227 | |
892776ce | 228 | sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); |
70ef6a5b | 229 | sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); |
892776ce | 230 | |
9bca0edb PM |
231 | cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); |
232 | cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); | |
e3260506 PC |
233 | |
234 | sysbus_create_varargs("cadence_ttc", 0xF8001000, | |
235 | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); | |
236 | sysbus_create_varargs("cadence_ttc", 0xF8002000, | |
237 | pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); | |
238 | ||
7fcd57e8 PC |
239 | gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); |
240 | gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); | |
e3260506 | 241 | |
27a49d3b PMD |
242 | for (n = 0; n < 2; n++) { |
243 | int hci_irq = n ? 79 : 56; | |
244 | hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; | |
245 | DriveInfo *di; | |
246 | BlockBackend *blk; | |
247 | DeviceState *carddev; | |
248 | ||
249 | /* Compatible with: | |
250 | * - SD Host Controller Specification Version 2.0 Part A2 | |
251 | * - SDIO Specification Version 2.0 | |
252 | * - MMC Specification Version 3.31 | |
253 | */ | |
254 | dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); | |
255 | qdev_prop_set_uint8(dev, "sd-spec-version", 2); | |
256 | qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); | |
257 | qdev_init_nofail(dev); | |
258 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); | |
259 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); | |
260 | ||
261 | di = drive_get_next(IF_SD); | |
262 | blk = di ? blk_by_legacy_dinfo(di) : NULL; | |
263 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD); | |
264 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | |
265 | object_property_set_bool(OBJECT(carddev), true, "realized", | |
266 | &error_fatal); | |
267 | } | |
eb4f566b | 268 | |
74fcbd22 GR |
269 | dev = qdev_create(NULL, TYPE_ZYNQ_XADC); |
270 | qdev_init_nofail(dev); | |
271 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); | |
272 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); | |
273 | ||
7451afb6 PC |
274 | dev = qdev_create(NULL, "pl330"); |
275 | qdev_prop_set_uint8(dev, "num_chnls", 8); | |
276 | qdev_prop_set_uint8(dev, "num_periph_req", 4); | |
277 | qdev_prop_set_uint8(dev, "num_events", 16); | |
278 | ||
279 | qdev_prop_set_uint8(dev, "data_width", 64); | |
280 | qdev_prop_set_uint8(dev, "wr_cap", 8); | |
281 | qdev_prop_set_uint8(dev, "wr_q_dep", 16); | |
282 | qdev_prop_set_uint8(dev, "rd_cap", 8); | |
283 | qdev_prop_set_uint8(dev, "rd_q_dep", 16); | |
284 | qdev_prop_set_uint16(dev, "data_buffer_dep", 256); | |
285 | ||
286 | qdev_init_nofail(dev); | |
287 | busdev = SYS_BUS_DEVICE(dev); | |
288 | sysbus_mmio_map(busdev, 0, 0xF8003000); | |
289 | sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ | |
5e9fcbd7 | 290 | for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ |
7451afb6 PC |
291 | sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); |
292 | } | |
293 | ||
f4b99537 PC |
294 | dev = qdev_create(NULL, "xlnx.ps7-dev-cfg"); |
295 | qdev_init_nofail(dev); | |
296 | busdev = SYS_BUS_DEVICE(dev); | |
297 | sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); | |
298 | sysbus_mmio_map(busdev, 0, 0xF8007000); | |
299 | ||
c9800965 | 300 | zynq_binfo.ram_size = machine->ram_size; |
e3260506 PC |
301 | zynq_binfo.nb_cpus = 1; |
302 | zynq_binfo.board_id = 0xd32; | |
303 | zynq_binfo.loader_start = 0; | |
c3a9a689 PC |
304 | zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; |
305 | zynq_binfo.write_board_setup = zynq_write_board_setup; | |
306 | ||
2744ece8 | 307 | arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); |
e3260506 PC |
308 | } |
309 | ||
e264d29d | 310 | static void zynq_machine_init(MachineClass *mc) |
e3260506 | 311 | { |
e264d29d EH |
312 | mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; |
313 | mc->init = zynq_init; | |
e264d29d EH |
314 | mc->max_cpus = 1; |
315 | mc->no_sdcard = 1; | |
4672cbd7 | 316 | mc->ignore_memory_transaction_failures = true; |
ba1ba5cc | 317 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); |
8182d3d1 | 318 | mc->default_ram_id = "zynq.ext_ram"; |
e3260506 PC |
319 | } |
320 | ||
e264d29d | 321 | DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) |