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b89de436 EI |
1 | /* |
2 | * Xilinx Versal SoC model. | |
3 | * | |
4 | * Copyright (c) 2018 Xilinx Inc. | |
5 | * Written by Edgar E. Iglesias | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
13 | #include "qapi/error.h" | |
b89de436 | 14 | #include "qemu/log.h" |
0b8fa32f | 15 | #include "qemu/module.h" |
b89de436 EI |
16 | #include "hw/sysbus.h" |
17 | #include "net/net.h" | |
18 | #include "sysemu/sysemu.h" | |
19 | #include "sysemu/kvm.h" | |
12ec8bd5 | 20 | #include "hw/arm/boot.h" |
b89de436 EI |
21 | #include "kvm_arm.h" |
22 | #include "hw/misc/unimp.h" | |
b89de436 EI |
23 | #include "hw/arm/xlnx-versal.h" |
24 | ||
25 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | |
26 | #define GEM_REVISION 0x40070106 | |
27 | ||
28 | static void versal_create_apu_cpus(Versal *s) | |
29 | { | |
30 | int i; | |
31 | ||
32 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | |
33 | Object *obj; | |
34 | char *name; | |
35 | ||
36 | obj = object_new(XLNX_VERSAL_ACPU_TYPE); | |
37 | if (!obj) { | |
b89de436 EI |
38 | error_report("Unable to create apu.cpu[%d] of type %s", |
39 | i, XLNX_VERSAL_ACPU_TYPE); | |
40 | exit(EXIT_FAILURE); | |
41 | } | |
42 | ||
43 | name = g_strdup_printf("apu-cpu[%d]", i); | |
44 | object_property_add_child(OBJECT(s), name, obj, &error_fatal); | |
45 | g_free(name); | |
46 | ||
47 | object_property_set_int(obj, s->cfg.psci_conduit, | |
48 | "psci-conduit", &error_abort); | |
49 | if (i) { | |
c07c0c37 | 50 | /* Secondary CPUs start in PSCI powered-down state */ |
b89de436 EI |
51 | object_property_set_bool(obj, true, |
52 | "start-powered-off", &error_abort); | |
53 | } | |
54 | ||
55 | object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu), | |
56 | "core-count", &error_abort); | |
57 | object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory", | |
58 | &error_abort); | |
59 | object_property_set_bool(obj, true, "realized", &error_fatal); | |
60 | s->fpd.apu.cpu[i] = ARM_CPU(obj); | |
61 | } | |
62 | } | |
63 | ||
64 | static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | |
65 | { | |
66 | static const uint64_t addrs[] = { | |
67 | MM_GIC_APU_DIST_MAIN, | |
68 | MM_GIC_APU_REDIST_0 | |
69 | }; | |
70 | SysBusDevice *gicbusdev; | |
71 | DeviceState *gicdev; | |
72 | int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); | |
73 | int i; | |
74 | ||
75 | sysbus_init_child_obj(OBJECT(s), "apu-gic", | |
76 | &s->fpd.apu.gic, sizeof(s->fpd.apu.gic), | |
77 | gicv3_class_name()); | |
78 | gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); | |
79 | gicdev = DEVICE(&s->fpd.apu.gic); | |
80 | qdev_prop_set_uint32(gicdev, "revision", 3); | |
81 | qdev_prop_set_uint32(gicdev, "num-cpu", 2); | |
82 | qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32); | |
83 | qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); | |
84 | qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2); | |
85 | qdev_prop_set_bit(gicdev, "has-security-extensions", true); | |
86 | ||
87 | object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized", | |
88 | &error_fatal); | |
89 | ||
90 | for (i = 0; i < ARRAY_SIZE(addrs); i++) { | |
91 | MemoryRegion *mr; | |
92 | ||
93 | mr = sysbus_mmio_get_region(gicbusdev, i); | |
94 | memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr); | |
95 | } | |
96 | ||
97 | for (i = 0; i < nr_apu_cpus; i++) { | |
98 | DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]); | |
99 | int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; | |
100 | qemu_irq maint_irq; | |
101 | int ti; | |
102 | /* Mapping from the output timer irq lines from the CPU to the | |
103 | * GIC PPI inputs. | |
104 | */ | |
105 | const int timer_irq[] = { | |
106 | [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ, | |
107 | [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ, | |
108 | [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ, | |
109 | [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ, | |
110 | }; | |
111 | ||
112 | for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) { | |
113 | qdev_connect_gpio_out(cpudev, ti, | |
114 | qdev_get_gpio_in(gicdev, | |
115 | ppibase + timer_irq[ti])); | |
116 | } | |
117 | maint_irq = qdev_get_gpio_in(gicdev, | |
118 | ppibase + VERSAL_GIC_MAINT_IRQ); | |
119 | qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", | |
120 | 0, maint_irq); | |
121 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | |
122 | sysbus_connect_irq(gicbusdev, i + nr_apu_cpus, | |
123 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | |
124 | sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus, | |
125 | qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | |
126 | sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus, | |
127 | qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | |
128 | } | |
129 | ||
130 | for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) { | |
131 | pic[i] = qdev_get_gpio_in(gicdev, i); | |
132 | } | |
133 | } | |
134 | ||
135 | static void versal_create_uarts(Versal *s, qemu_irq *pic) | |
136 | { | |
137 | int i; | |
138 | ||
139 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { | |
140 | static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0}; | |
141 | static const uint64_t addrs[] = { MM_UART0, MM_UART1 }; | |
142 | char *name = g_strdup_printf("uart%d", i); | |
143 | DeviceState *dev; | |
144 | MemoryRegion *mr; | |
145 | ||
88052ffd EI |
146 | sysbus_init_child_obj(OBJECT(s), name, |
147 | &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]), | |
148 | TYPE_PL011); | |
149 | dev = DEVICE(&s->lpd.iou.uart[i]); | |
b89de436 | 150 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
b89de436 EI |
151 | qdev_init_nofail(dev); |
152 | ||
88052ffd | 153 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
b89de436 EI |
154 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); |
155 | ||
88052ffd | 156 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); |
b89de436 EI |
157 | g_free(name); |
158 | } | |
159 | } | |
160 | ||
161 | static void versal_create_gems(Versal *s, qemu_irq *pic) | |
162 | { | |
163 | int i; | |
164 | ||
165 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { | |
166 | static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0}; | |
167 | static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 }; | |
168 | char *name = g_strdup_printf("gem%d", i); | |
169 | NICInfo *nd = &nd_table[i]; | |
170 | DeviceState *dev; | |
171 | MemoryRegion *mr; | |
172 | ||
4bd9b59c EI |
173 | sysbus_init_child_obj(OBJECT(s), name, |
174 | &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]), | |
175 | TYPE_CADENCE_GEM); | |
176 | dev = DEVICE(&s->lpd.iou.gem[i]); | |
b89de436 EI |
177 | if (nd->used) { |
178 | qemu_check_nic_model(nd, "cadence_gem"); | |
179 | qdev_set_nic_properties(dev, nd); | |
180 | } | |
4bd9b59c | 181 | object_property_set_int(OBJECT(dev), |
b89de436 EI |
182 | 2, "num-priority-queues", |
183 | &error_abort); | |
4bd9b59c | 184 | object_property_set_link(OBJECT(dev), |
b89de436 EI |
185 | OBJECT(&s->mr_ps), "dma", |
186 | &error_abort); | |
187 | qdev_init_nofail(dev); | |
188 | ||
4bd9b59c | 189 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
b89de436 EI |
190 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); |
191 | ||
4bd9b59c | 192 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); |
b89de436 EI |
193 | g_free(name); |
194 | } | |
195 | } | |
196 | ||
8a218651 EI |
197 | static void versal_create_admas(Versal *s, qemu_irq *pic) |
198 | { | |
199 | int i; | |
200 | ||
201 | for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { | |
202 | char *name = g_strdup_printf("adma%d", i); | |
203 | DeviceState *dev; | |
204 | MemoryRegion *mr; | |
205 | ||
f4e3fa37 EI |
206 | sysbus_init_child_obj(OBJECT(s), name, |
207 | &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]), | |
208 | TYPE_XLNX_ZDMA); | |
209 | dev = DEVICE(&s->lpd.iou.adma[i]); | |
210 | object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort); | |
8a218651 EI |
211 | qdev_init_nofail(dev); |
212 | ||
f4e3fa37 | 213 | mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
8a218651 EI |
214 | memory_region_add_subregion(&s->mr_ps, |
215 | MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); | |
216 | ||
f4e3fa37 | 217 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); |
8a218651 EI |
218 | g_free(name); |
219 | } | |
220 | } | |
221 | ||
b89de436 EI |
222 | /* This takes the board allocated linear DDR memory and creates aliases |
223 | * for each split DDR range/aperture on the Versal address map. | |
224 | */ | |
225 | static void versal_map_ddr(Versal *s) | |
226 | { | |
227 | uint64_t size = memory_region_size(s->cfg.mr_ddr); | |
228 | /* Describes the various split DDR access regions. */ | |
229 | static const struct { | |
230 | uint64_t base; | |
231 | uint64_t size; | |
232 | } addr_ranges[] = { | |
233 | { MM_TOP_DDR, MM_TOP_DDR_SIZE }, | |
234 | { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, | |
235 | { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, | |
236 | { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } | |
237 | }; | |
238 | uint64_t offset = 0; | |
239 | int i; | |
240 | ||
241 | assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges)); | |
242 | for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { | |
243 | char *name; | |
244 | uint64_t mapsize; | |
245 | ||
246 | mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size; | |
247 | name = g_strdup_printf("noc-ddr-range%d", i); | |
248 | /* Create the MR alias. */ | |
249 | memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), | |
250 | name, s->cfg.mr_ddr, | |
251 | offset, mapsize); | |
252 | ||
253 | /* Map it onto the NoC MR. */ | |
254 | memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, | |
255 | &s->noc.mr_ddr_ranges[i]); | |
256 | offset += mapsize; | |
257 | size -= mapsize; | |
258 | g_free(name); | |
259 | } | |
260 | } | |
261 | ||
262 | static void versal_unimp_area(Versal *s, const char *name, | |
263 | MemoryRegion *mr, | |
264 | hwaddr base, hwaddr size) | |
265 | { | |
266 | DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE); | |
267 | MemoryRegion *mr_dev; | |
268 | ||
269 | qdev_prop_set_string(dev, "name", name); | |
270 | qdev_prop_set_uint64(dev, "size", size); | |
271 | object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | |
272 | qdev_init_nofail(dev); | |
273 | ||
274 | mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | |
275 | memory_region_add_subregion(mr, base, mr_dev); | |
276 | } | |
277 | ||
278 | static void versal_unimp(Versal *s) | |
279 | { | |
280 | versal_unimp_area(s, "psm", &s->mr_ps, | |
281 | MM_PSM_START, MM_PSM_END - MM_PSM_START); | |
282 | versal_unimp_area(s, "crl", &s->mr_ps, | |
283 | MM_CRL, MM_CRL_SIZE); | |
284 | versal_unimp_area(s, "crf", &s->mr_ps, | |
285 | MM_FPD_CRF, MM_FPD_CRF_SIZE); | |
f0138990 EI |
286 | versal_unimp_area(s, "crp", &s->mr_ps, |
287 | MM_PMC_CRP, MM_PMC_CRP_SIZE); | |
b89de436 EI |
288 | versal_unimp_area(s, "iou-scntr", &s->mr_ps, |
289 | MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); | |
290 | versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, | |
291 | MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); | |
292 | } | |
293 | ||
294 | static void versal_realize(DeviceState *dev, Error **errp) | |
295 | { | |
296 | Versal *s = XLNX_VERSAL(dev); | |
297 | qemu_irq pic[XLNX_VERSAL_NR_IRQS]; | |
298 | ||
299 | versal_create_apu_cpus(s); | |
300 | versal_create_apu_gic(s, pic); | |
301 | versal_create_uarts(s, pic); | |
302 | versal_create_gems(s, pic); | |
8a218651 | 303 | versal_create_admas(s, pic); |
b89de436 EI |
304 | versal_map_ddr(s); |
305 | versal_unimp(s); | |
306 | ||
307 | /* Create the On Chip Memory (OCM). */ | |
308 | memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm", | |
309 | MM_OCM_SIZE, &error_fatal); | |
310 | ||
311 | memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0); | |
312 | memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); | |
313 | } | |
314 | ||
315 | static void versal_init(Object *obj) | |
316 | { | |
317 | Versal *s = XLNX_VERSAL(obj); | |
318 | ||
319 | memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); | |
320 | memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); | |
321 | } | |
322 | ||
323 | static Property versal_properties[] = { | |
324 | DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION, | |
325 | MemoryRegion *), | |
326 | DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0), | |
327 | DEFINE_PROP_END_OF_LIST() | |
328 | }; | |
329 | ||
330 | static void versal_class_init(ObjectClass *klass, void *data) | |
331 | { | |
332 | DeviceClass *dc = DEVICE_CLASS(klass); | |
333 | ||
334 | dc->realize = versal_realize; | |
4f67d30b | 335 | device_class_set_props(dc, versal_properties); |
b89de436 EI |
336 | /* No VMSD since we haven't got any top-level SoC state to save. */ |
337 | } | |
338 | ||
339 | static const TypeInfo versal_info = { | |
340 | .name = TYPE_XLNX_VERSAL, | |
341 | .parent = TYPE_SYS_BUS_DEVICE, | |
342 | .instance_size = sizeof(Versal), | |
343 | .instance_init = versal_init, | |
344 | .class_init = versal_class_init, | |
345 | }; | |
346 | ||
347 | static void versal_register_types(void) | |
348 | { | |
349 | type_register_static(&versal_info); | |
350 | } | |
351 | ||
352 | type_init(versal_register_types); |