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859a0c5b | 1 | /* |
aff3f0f1 | 2 | * Xilinx ZynqMP ZCU102 board |
859a0c5b PC |
3 | * |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
12b16722 | 18 | #include "qemu/osdep.h" |
da34e65c | 19 | #include "qapi/error.h" |
4771d756 | 20 | #include "cpu.h" |
859a0c5b PC |
21 | #include "hw/arm/xlnx-zynqmp.h" |
22 | #include "hw/boards.h" | |
23 | #include "qemu/error-report.h" | |
03dd024f | 24 | #include "qemu/log.h" |
b350ae13 | 25 | #include "sysemu/qtest.h" |
859a0c5b | 26 | |
aff3f0f1 | 27 | typedef struct XlnxZCU102 { |
b70cf33f AF |
28 | MachineState parent_obj; |
29 | ||
859a0c5b | 30 | XlnxZynqMPState soc; |
b79b9d28 | 31 | MemoryRegion ddr_ram; |
b7436e94 AF |
32 | |
33 | bool secure; | |
1946809e | 34 | bool virt; |
aff3f0f1 | 35 | } XlnxZCU102; |
859a0c5b | 36 | |
b70cf33f AF |
37 | #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") |
38 | #define ZCU102_MACHINE(obj) \ | |
39 | OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) | |
40 | ||
aff3f0f1 | 41 | static struct arm_boot_info xlnx_zcu102_binfo; |
082587b7 | 42 | |
b7436e94 AF |
43 | static bool zcu102_get_secure(Object *obj, Error **errp) |
44 | { | |
45 | XlnxZCU102 *s = ZCU102_MACHINE(obj); | |
46 | ||
47 | return s->secure; | |
48 | } | |
49 | ||
50 | static void zcu102_set_secure(Object *obj, bool value, Error **errp) | |
51 | { | |
52 | XlnxZCU102 *s = ZCU102_MACHINE(obj); | |
53 | ||
54 | s->secure = value; | |
55 | } | |
56 | ||
1946809e AF |
57 | static bool zcu102_get_virt(Object *obj, Error **errp) |
58 | { | |
59 | XlnxZCU102 *s = ZCU102_MACHINE(obj); | |
60 | ||
61 | return s->virt; | |
62 | } | |
63 | ||
64 | static void zcu102_set_virt(Object *obj, bool value, Error **errp) | |
65 | { | |
66 | XlnxZCU102 *s = ZCU102_MACHINE(obj); | |
67 | ||
68 | s->virt = value; | |
69 | } | |
70 | ||
da969774 | 71 | static void xlnx_zcu102_init(MachineState *machine) |
859a0c5b | 72 | { |
da969774 | 73 | XlnxZCU102 *s = ZCU102_MACHINE(machine); |
a4b26335 | 74 | int i; |
dc3b89ef AF |
75 | uint64_t ram_size = machine->ram_size; |
76 | ||
77 | /* Create the memory region to pass to the SoC */ | |
78 | if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) { | |
79 | error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of " | |
80 | "0x%llx", ram_size, | |
81 | XLNX_ZYNQMP_MAX_RAM_SIZE); | |
82 | exit(1); | |
83 | } | |
84 | ||
85 | if (ram_size < 0x08000000) { | |
aff3f0f1 | 86 | qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102", |
dc3b89ef AF |
87 | ram_size); |
88 | } | |
89 | ||
90 | memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram", | |
91 | ram_size); | |
859a0c5b | 92 | |
d0313798 PMD |
93 | object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), |
94 | TYPE_XLNX_ZYNQMP, &error_abort, NULL); | |
859a0c5b | 95 | |
dc3b89ef AF |
96 | object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), |
97 | "ddr-ram", &error_abort); | |
b7436e94 AF |
98 | object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", |
99 | &error_fatal); | |
1946809e AF |
100 | object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", |
101 | &error_fatal); | |
dc3b89ef | 102 | |
07d04a02 | 103 | object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); |
b79b9d28 | 104 | |
eb4f566b PM |
105 | /* Create and plug in the SD cards */ |
106 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | |
107 | BusState *bus; | |
108 | DriveInfo *di = drive_get_next(IF_SD); | |
109 | BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; | |
110 | DeviceState *carddev; | |
111 | char *bus_name; | |
112 | ||
113 | bus_name = g_strdup_printf("sd-bus%d", i); | |
114 | bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); | |
115 | g_free(bus_name); | |
116 | if (!bus) { | |
117 | error_report("No SD bus found for SD card %d", i); | |
118 | exit(1); | |
119 | } | |
120 | carddev = qdev_create(bus, TYPE_SD_CARD); | |
121 | qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | |
122 | object_property_set_bool(OBJECT(carddev), true, "realized", | |
123 | &error_fatal); | |
124 | } | |
125 | ||
a4b26335 AF |
126 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { |
127 | SSIBus *spi_bus; | |
128 | DeviceState *flash_dev; | |
129 | qemu_irq cs_line; | |
73bce518 | 130 | DriveInfo *dinfo = drive_get_next(IF_MTD); |
a4b26335 AF |
131 | gchar *bus_name = g_strdup_printf("spi%d", i); |
132 | ||
133 | spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name); | |
134 | g_free(bus_name); | |
135 | ||
73bce518 PB |
136 | flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080"); |
137 | if (dinfo) { | |
138 | qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), | |
139 | &error_fatal); | |
140 | } | |
141 | qdev_init_nofail(flash_dev); | |
142 | ||
a4b26335 AF |
143 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
144 | ||
145 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); | |
146 | } | |
147 | ||
babc1f30 FI |
148 | for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { |
149 | SSIBus *spi_bus; | |
150 | DeviceState *flash_dev; | |
151 | qemu_irq cs_line; | |
152 | DriveInfo *dinfo = drive_get_next(IF_MTD); | |
153 | int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; | |
154 | gchar *bus_name = g_strdup_printf("qspi%d", bus); | |
155 | ||
156 | spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name); | |
157 | g_free(bus_name); | |
158 | ||
159 | flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11"); | |
160 | if (dinfo) { | |
161 | qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), | |
162 | &error_fatal); | |
163 | } | |
164 | qdev_init_nofail(flash_dev); | |
165 | ||
166 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); | |
167 | ||
168 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); | |
169 | } | |
170 | ||
e0319b03 MA |
171 | /* TODO create and connect IDE devices for ide_drive_get() */ |
172 | ||
aff3f0f1 AF |
173 | xlnx_zcu102_binfo.ram_size = ram_size; |
174 | xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename; | |
175 | xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline; | |
176 | xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename; | |
177 | xlnx_zcu102_binfo.loader_start = 0; | |
178 | arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); | |
859a0c5b PC |
179 | } |
180 | ||
b70cf33f AF |
181 | static void xlnx_zcu102_machine_instance_init(Object *obj) |
182 | { | |
b7436e94 AF |
183 | XlnxZCU102 *s = ZCU102_MACHINE(obj); |
184 | ||
185 | /* Default to secure mode being disabled */ | |
186 | s->secure = false; | |
187 | object_property_add_bool(obj, "secure", zcu102_get_secure, | |
188 | zcu102_set_secure, NULL); | |
189 | object_property_set_description(obj, "secure", | |
190 | "Set on/off to enable/disable the ARM " | |
191 | "Security Extensions (TrustZone)", | |
192 | NULL); | |
1946809e AF |
193 | |
194 | /* Default to virt (EL2) being disabled */ | |
195 | s->virt = false; | |
196 | object_property_add_bool(obj, "virtualization", zcu102_get_virt, | |
197 | zcu102_set_virt, NULL); | |
198 | object_property_set_description(obj, "virtualization", | |
199 | "Set on/off to enable/disable emulating a " | |
200 | "guest CPU which implements the ARM " | |
201 | "Virtualization Extensions", | |
202 | NULL); | |
b70cf33f AF |
203 | } |
204 | ||
205 | static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) | |
206 | { | |
207 | MachineClass *mc = MACHINE_CLASS(oc); | |
208 | ||
eb24d4d3 | 209 | mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \ |
6908ec44 | 210 | "the value of smp"; |
aff3f0f1 | 211 | mc->init = xlnx_zcu102_init; |
e0319b03 MA |
212 | mc->block_default_type = IF_IDE; |
213 | mc->units_per_default_bus = 1; | |
4672cbd7 | 214 | mc->ignore_memory_transaction_failures = true; |
0f2bf05c | 215 | mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; |
72649619 | 216 | mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; |
0c18c6c6 AF |
217 | } |
218 | ||
b70cf33f AF |
219 | static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { |
220 | .name = MACHINE_TYPE_NAME("xlnx-zcu102"), | |
221 | .parent = TYPE_MACHINE, | |
222 | .class_init = xlnx_zcu102_machine_class_init, | |
223 | .instance_init = xlnx_zcu102_machine_instance_init, | |
224 | .instance_size = sizeof(XlnxZCU102), | |
225 | }; | |
226 | ||
227 | static void xlnx_zcu102_machine_init_register_types(void) | |
228 | { | |
229 | type_register_static(&xlnx_zcu102_machine_init_typeinfo); | |
230 | } | |
231 | ||
232 | type_init(xlnx_zcu102_machine_init_register_types) |