[mirror_qemu.git] / hw / arm / xlnx-zcu102.c

/*
 * Xilinx ZynqMP ZCU102 board
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "sysemu/qtest.h"

typedef struct XlnxZCU102 {
    MachineState parent_obj;

    XlnxZynqMPState soc;

    bool secure;
    bool virt;

    struct arm_boot_info binfo;
} XlnxZCU102;

#define TYPE_ZCU102_MACHINE   MACHINE_TYPE_NAME("xlnx-zcu102")
#define ZCU102_MACHINE(obj) \
    OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)


static bool zcu102_get_secure(Object *obj, Error **errp)
{
    XlnxZCU102 *s = ZCU102_MACHINE(obj);

    return s->secure;
}

static void zcu102_set_secure(Object *obj, bool value, Error **errp)
{
    XlnxZCU102 *s = ZCU102_MACHINE(obj);

    s->secure = value;
}

static bool zcu102_get_virt(Object *obj, Error **errp)
{
    XlnxZCU102 *s = ZCU102_MACHINE(obj);

    return s->virt;
}

static void zcu102_set_virt(Object *obj, bool value, Error **errp)
{
    XlnxZCU102 *s = ZCU102_MACHINE(obj);

    s->virt = value;
}

static void xlnx_zcu102_init(MachineState *machine)
{
    XlnxZCU102 *s = ZCU102_MACHINE(machine);
    int i;
    uint64_t ram_size = machine->ram_size;

    /* Create the memory region to pass to the SoC */
    if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
        error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
                     "0x%llx", ram_size,
                     XLNX_ZYNQMP_MAX_RAM_SIZE);
        exit(1);
    }

    if (ram_size < 0x08000000) {
        qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
                 ram_size);
    }

    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
                            TYPE_XLNX_ZYNQMP, &error_abort, NULL);

    object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
                         "ddr-ram", &error_abort);
    object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
                             &error_fatal);
    object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
                             &error_fatal);

    object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);

    /* Create and plug in the SD cards */
    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        BusState *bus;
        DriveInfo *di = drive_get_next(IF_SD);
        BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
        DeviceState *carddev;
        char *bus_name;

        bus_name = g_strdup_printf("sd-bus%d", i);
        bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
        g_free(bus_name);
        if (!bus) {
            error_report("No SD bus found for SD card %d", i);
            exit(1);
        }
        carddev = qdev_create(bus, TYPE_SD_CARD);
        qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
        object_property_set_bool(OBJECT(carddev), true, "realized",
                                 &error_fatal);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        SSIBus *spi_bus;
        DeviceState *flash_dev;
        qemu_irq cs_line;
        DriveInfo *dinfo = drive_get_next(IF_MTD);
        gchar *bus_name = g_strdup_printf("spi%d", i);

        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
        g_free(bus_name);

        flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
        if (dinfo) {
            qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
                                &error_fatal);
        }
        qdev_init_nofail(flash_dev);

        cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
        SSIBus *spi_bus;
        DeviceState *flash_dev;
        qemu_irq cs_line;
        DriveInfo *dinfo = drive_get_next(IF_MTD);
        int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
        gchar *bus_name = g_strdup_printf("qspi%d", bus);

        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
        g_free(bus_name);

        flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
        if (dinfo) {
            qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
                                &error_fatal);
        }
        qdev_init_nofail(flash_dev);

        cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
    }

    /* TODO create and connect IDE devices for ide_drive_get() */

    s->binfo.ram_size = ram_size;
    s->binfo.loader_start = 0;
    arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
}

static void xlnx_zcu102_machine_instance_init(Object *obj)
{
    XlnxZCU102 *s = ZCU102_MACHINE(obj);

    /* Default to secure mode being disabled */
    s->secure = false;
    object_property_add_bool(obj, "secure", zcu102_get_secure,
                             zcu102_set_secure, NULL);
    object_property_set_description(obj, "secure",
                                    "Set on/off to enable/disable the ARM "
                                    "Security Extensions (TrustZone)",
                                    NULL);

    /* Default to virt (EL2) being disabled */
    s->virt = false;
    object_property_add_bool(obj, "virtualization", zcu102_get_virt,
                             zcu102_set_virt, NULL);
    object_property_set_description(obj, "virtualization",
                                    "Set on/off to enable/disable emulating a "
                                    "guest CPU which implements the ARM "
                                    "Virtualization Extensions",
                                    NULL);
}

static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
               "the value of smp";
    mc->init = xlnx_zcu102_init;
    mc->block_default_type = IF_IDE;
    mc->units_per_default_bus = 1;
    mc->ignore_memory_transaction_failures = true;
    mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
    mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
    mc->default_ram_id = "ddr-ram";
}

static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
    .name       = MACHINE_TYPE_NAME("xlnx-zcu102"),
    .parent     = TYPE_MACHINE,
    .class_init = xlnx_zcu102_machine_class_init,
    .instance_init = xlnx_zcu102_machine_instance_init,
    .instance_size = sizeof(XlnxZCU102),
};

static void xlnx_zcu102_machine_init_register_types(void)
{
    type_register_static(&xlnx_zcu102_machine_init_typeinfo);
}

type_init(xlnx_zcu102_machine_init_register_types)
Commit	Line	Data
859a0c5b	1	/*
aff3f0f1	2	* Xilinx ZynqMP ZCU102 board
859a0c5b PC	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
4771d756	20	#include "cpu.h"
859a0c5b PC	21	#include "hw/arm/xlnx-zynqmp.h"
	22	#include "hw/boards.h"
	23	#include "qemu/error-report.h"
03dd024f	24	#include "qemu/log.h"
b350ae13	25	#include "sysemu/qtest.h"
859a0c5b	26
aff3f0f1	27	typedef struct XlnxZCU102 {
b70cf33f AF	28	MachineState parent_obj;
b70cf33f AF	29
859a0c5b	30	XlnxZynqMPState soc;
b7436e94 AF	31
b7436e94 AF	32	bool secure;
1946809e	33	bool virt;
4d1ac883 EI	34
4d1ac883 EI	35	struct arm_boot_info binfo;
aff3f0f1	36	} XlnxZCU102;
859a0c5b	37
b70cf33f AF	38	#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
	39	#define ZCU102_MACHINE(obj) \
	40	OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
	41
082587b7	42
b7436e94 AF	43	static bool zcu102_get_secure(Object obj, Error *errp)
	44	{
	45	XlnxZCU102 *s = ZCU102_MACHINE(obj);
	46
	47	return s->secure;
	48	}
	49
	50	static void zcu102_set_secure(Object obj, bool value, Error *errp)
	51	{
	52	XlnxZCU102 *s = ZCU102_MACHINE(obj);
	53
	54	s->secure = value;
	55	}
	56
1946809e AF	57	static bool zcu102_get_virt(Object obj, Error *errp)
	58	{
	59	XlnxZCU102 *s = ZCU102_MACHINE(obj);
	60
	61	return s->virt;
	62	}
	63
	64	static void zcu102_set_virt(Object obj, bool value, Error *errp)
	65	{
	66	XlnxZCU102 *s = ZCU102_MACHINE(obj);
	67
	68	s->virt = value;
	69	}
	70
da969774	71	static void xlnx_zcu102_init(MachineState *machine)
859a0c5b	72	{
da969774	73	XlnxZCU102 *s = ZCU102_MACHINE(machine);
a4b26335	74	int i;
dc3b89ef AF	75	uint64_t ram_size = machine->ram_size;
	76
	77	/* Create the memory region to pass to the SoC */
	78	if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
	79	error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
	80	"0x%llx", ram_size,
	81	XLNX_ZYNQMP_MAX_RAM_SIZE);
	82	exit(1);
	83	}
	84
	85	if (ram_size < 0x08000000) {
aff3f0f1	86	qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
dc3b89ef AF	87	ram_size);
	88	}
	89
d0313798 PMD	90	object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
d0313798 PMD	91	TYPE_XLNX_ZYNQMP, &error_abort, NULL);
859a0c5b	92
87c8047f	93	object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
dc3b89ef	94	"ddr-ram", &error_abort);
b7436e94 AF	95	object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
b7436e94 AF	96	&error_fatal);
1946809e AF	97	object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
1946809e AF	98	&error_fatal);
dc3b89ef	99
07d04a02	100	object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
b79b9d28	101
eb4f566b PM	102	/* Create and plug in the SD cards */
	103	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	104	BusState *bus;
	105	DriveInfo *di = drive_get_next(IF_SD);
	106	BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
	107	DeviceState *carddev;
	108	char *bus_name;
	109
	110	bus_name = g_strdup_printf("sd-bus%d", i);
	111	bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
	112	g_free(bus_name);
	113	if (!bus) {
	114	error_report("No SD bus found for SD card %d", i);
	115	exit(1);
	116	}
	117	carddev = qdev_create(bus, TYPE_SD_CARD);
	118	qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
	119	object_property_set_bool(OBJECT(carddev), true, "realized",
	120	&error_fatal);
	121	}
	122
a4b26335 AF	123	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	124	SSIBus *spi_bus;
	125	DeviceState *flash_dev;
	126	qemu_irq cs_line;
73bce518	127	DriveInfo *dinfo = drive_get_next(IF_MTD);
a4b26335 AF	128	gchar *bus_name = g_strdup_printf("spi%d", i);
	129
	130	spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
	131	g_free(bus_name);
	132
73bce518 PB	133	flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
	134	if (dinfo) {
	135	qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
	136	&error_fatal);
	137	}
	138	qdev_init_nofail(flash_dev);
	139
a4b26335 AF	140	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
	141
	142	sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
	143	}
	144
babc1f30 FI	145	for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
	146	SSIBus *spi_bus;
	147	DeviceState *flash_dev;
	148	qemu_irq cs_line;
	149	DriveInfo *dinfo = drive_get_next(IF_MTD);
	150	int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
	151	gchar *bus_name = g_strdup_printf("qspi%d", bus);
	152
	153	spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
	154	g_free(bus_name);
	155
	156	flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
	157	if (dinfo) {
	158	qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
	159	&error_fatal);
	160	}
	161	qdev_init_nofail(flash_dev);
	162
	163	cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
	164
	165	sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
	166	}
	167
e0319b03 MA	168	/* TODO create and connect IDE devices for ide_drive_get() */
e0319b03 MA	169
4d1ac883 EI	170	s->binfo.ram_size = ram_size;
	171	s->binfo.loader_start = 0;
	172	arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
859a0c5b PC	173	}
859a0c5b PC	174
b70cf33f AF	175	static void xlnx_zcu102_machine_instance_init(Object *obj)
b70cf33f AF	176	{
b7436e94 AF	177	XlnxZCU102 *s = ZCU102_MACHINE(obj);
	178
	179	/* Default to secure mode being disabled */
	180	s->secure = false;
	181	object_property_add_bool(obj, "secure", zcu102_get_secure,
	182	zcu102_set_secure, NULL);
	183	object_property_set_description(obj, "secure",
	184	"Set on/off to enable/disable the ARM "
	185	"Security Extensions (TrustZone)",
	186	NULL);
1946809e AF	187
	188	/* Default to virt (EL2) being disabled */
	189	s->virt = false;
	190	object_property_add_bool(obj, "virtualization", zcu102_get_virt,
	191	zcu102_set_virt, NULL);
	192	object_property_set_description(obj, "virtualization",
	193	"Set on/off to enable/disable emulating a "
	194	"guest CPU which implements the ARM "
	195	"Virtualization Extensions",
	196	NULL);
b70cf33f AF	197	}
	198
	199	static void xlnx_zcu102_machine_class_init(ObjectClass oc, void data)
	200	{
	201	MachineClass *mc = MACHINE_CLASS(oc);
	202
eb24d4d3	203	mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
6908ec44	204	"the value of smp";
aff3f0f1	205	mc->init = xlnx_zcu102_init;
e0319b03 MA	206	mc->block_default_type = IF_IDE;
e0319b03 MA	207	mc->units_per_default_bus = 1;
4672cbd7	208	mc->ignore_memory_transaction_failures = true;
0f2bf05c	209	mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
72649619	210	mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
87c8047f	211	mc->default_ram_id = "ddr-ram";
0c18c6c6 AF	212	}
0c18c6c6 AF	213
b70cf33f AF	214	static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
	215	.name = MACHINE_TYPE_NAME("xlnx-zcu102"),
	216	.parent = TYPE_MACHINE,
	217	.class_init = xlnx_zcu102_machine_class_init,
	218	.instance_init = xlnx_zcu102_machine_instance_init,
	219	.instance_size = sizeof(XlnxZCU102),
	220	};
	221
	222	static void xlnx_zcu102_machine_init_register_types(void)
	223	{
	224	type_register_static(&xlnx_zcu102_machine_init_typeinfo);
	225	}
	226
	227	type_init(xlnx_zcu102_machine_init_register_types)