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859a0c5b 1/*
aff3f0f1 2 * Xilinx ZynqMP ZCU102 board
859a0c5b
PC
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
12b16722 18#include "qemu/osdep.h"
da34e65c 19#include "qapi/error.h"
4771d756 20#include "cpu.h"
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21#include "hw/arm/xlnx-zynqmp.h"
22#include "hw/boards.h"
23#include "qemu/error-report.h"
03dd024f 24#include "qemu/log.h"
b350ae13 25#include "sysemu/qtest.h"
6f7b6947 26#include "sysemu/device_tree.h"
db1015e9 27#include "qom/object.h"
859a0c5b 28
db1015e9 29struct XlnxZCU102 {
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AF
30 MachineState parent_obj;
31
859a0c5b 32 XlnxZynqMPState soc;
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33
34 bool secure;
1946809e 35 bool virt;
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36
37 struct arm_boot_info binfo;
db1015e9
EH
38};
39typedef struct XlnxZCU102 XlnxZCU102;
859a0c5b 40
b70cf33f 41#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
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EH
42DECLARE_INSTANCE_CHECKER(XlnxZCU102, ZCU102_MACHINE,
43 TYPE_ZCU102_MACHINE)
b70cf33f 44
082587b7 45
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46static bool zcu102_get_secure(Object *obj, Error **errp)
47{
48 XlnxZCU102 *s = ZCU102_MACHINE(obj);
49
50 return s->secure;
51}
52
53static void zcu102_set_secure(Object *obj, bool value, Error **errp)
54{
55 XlnxZCU102 *s = ZCU102_MACHINE(obj);
56
57 s->secure = value;
58}
59
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AF
60static bool zcu102_get_virt(Object *obj, Error **errp)
61{
62 XlnxZCU102 *s = ZCU102_MACHINE(obj);
63
64 return s->virt;
65}
66
67static void zcu102_set_virt(Object *obj, bool value, Error **errp)
68{
69 XlnxZCU102 *s = ZCU102_MACHINE(obj);
70
71 s->virt = value;
72}
73
6f7b6947
EI
74static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
75{
76 XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
77 bool method_is_hvc;
78 char **node_path;
79 const char *r;
80 int prop_len;
81 int i;
82
83 /* If EL3 is enabled, we keep all firmware nodes active. */
84 if (!s->secure) {
85 node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
86 &error_fatal);
87
88 for (i = 0; node_path && node_path[i]; i++) {
89 r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
90 method_is_hvc = r && !strcmp("hvc", r);
91
92 /* Allow HVC based firmware if EL2 is enabled. */
93 if (method_is_hvc && s->virt) {
94 continue;
95 }
96 qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
97 }
98 g_strfreev(node_path);
99 }
100}
101
da969774 102static void xlnx_zcu102_init(MachineState *machine)
859a0c5b 103{
da969774 104 XlnxZCU102 *s = ZCU102_MACHINE(machine);
a4b26335 105 int i;
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106 uint64_t ram_size = machine->ram_size;
107
108 /* Create the memory region to pass to the SoC */
109 if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
110 error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
111 "0x%llx", ram_size,
112 XLNX_ZYNQMP_MAX_RAM_SIZE);
113 exit(1);
114 }
115
116 if (ram_size < 0x08000000) {
aff3f0f1 117 qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
dc3b89ef
AF
118 ram_size);
119 }
120
9fc7fc4d 121 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
859a0c5b 122
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MA
123 object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram),
124 &error_abort);
125 object_property_set_bool(OBJECT(&s->soc), "secure", s->secure,
b7436e94 126 &error_fatal);
5325cc34 127 object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
1946809e 128 &error_fatal);
dc3b89ef 129
ce189ab2 130 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
b79b9d28 131
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132 /* Create and plug in the SD cards */
133 for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
134 BusState *bus;
135 DriveInfo *di = drive_get_next(IF_SD);
136 BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
137 DeviceState *carddev;
138 char *bus_name;
139
140 bus_name = g_strdup_printf("sd-bus%d", i);
141 bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
142 g_free(bus_name);
143 if (!bus) {
144 error_report("No SD bus found for SD card %d", i);
145 exit(1);
146 }
3e80f690 147 carddev = qdev_new(TYPE_SD_CARD);
934df912 148 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
3e80f690 149 qdev_realize_and_unref(carddev, bus, &error_fatal);
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150 }
151
a4b26335 152 for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
57d479c9 153 BusState *spi_bus;
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154 DeviceState *flash_dev;
155 qemu_irq cs_line;
73bce518 156 DriveInfo *dinfo = drive_get_next(IF_MTD);
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157 gchar *bus_name = g_strdup_printf("spi%d", i);
158
57d479c9 159 spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
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160 g_free(bus_name);
161
57d479c9 162 flash_dev = qdev_new("sst25wf080");
73bce518 163 if (dinfo) {
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164 qdev_prop_set_drive_err(flash_dev, "drive",
165 blk_by_legacy_dinfo(dinfo), &error_fatal);
73bce518 166 }
57d479c9 167 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
73bce518 168
a4b26335
AF
169 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
170
171 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
172 }
173
babc1f30 174 for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
57d479c9 175 BusState *spi_bus;
babc1f30
FI
176 DeviceState *flash_dev;
177 qemu_irq cs_line;
178 DriveInfo *dinfo = drive_get_next(IF_MTD);
179 int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
180 gchar *bus_name = g_strdup_printf("qspi%d", bus);
181
57d479c9 182 spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
babc1f30
FI
183 g_free(bus_name);
184
57d479c9 185 flash_dev = qdev_new("n25q512a11");
babc1f30 186 if (dinfo) {
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MA
187 qdev_prop_set_drive_err(flash_dev, "drive",
188 blk_by_legacy_dinfo(dinfo), &error_fatal);
babc1f30 189 }
57d479c9 190 qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
babc1f30
FI
191
192 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
193
194 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
195 }
196
e0319b03
MA
197 /* TODO create and connect IDE devices for ide_drive_get() */
198
4d1ac883
EI
199 s->binfo.ram_size = ram_size;
200 s->binfo.loader_start = 0;
6f7b6947 201 s->binfo.modify_dtb = zcu102_modify_dtb;
4d1ac883 202 arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
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203}
204
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205static void xlnx_zcu102_machine_instance_init(Object *obj)
206{
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207 XlnxZCU102 *s = ZCU102_MACHINE(obj);
208
209 /* Default to secure mode being disabled */
210 s->secure = false;
211 object_property_add_bool(obj, "secure", zcu102_get_secure,
d2623129 212 zcu102_set_secure);
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AF
213 object_property_set_description(obj, "secure",
214 "Set on/off to enable/disable the ARM "
7eecec7d 215 "Security Extensions (TrustZone)");
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AF
216
217 /* Default to virt (EL2) being disabled */
218 s->virt = false;
219 object_property_add_bool(obj, "virtualization", zcu102_get_virt,
d2623129 220 zcu102_set_virt);
1946809e
AF
221 object_property_set_description(obj, "virtualization",
222 "Set on/off to enable/disable emulating a "
223 "guest CPU which implements the ARM "
7eecec7d 224 "Virtualization Extensions");
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AF
225}
226
227static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
228{
229 MachineClass *mc = MACHINE_CLASS(oc);
230
eb24d4d3 231 mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
6908ec44 232 "the value of smp";
aff3f0f1 233 mc->init = xlnx_zcu102_init;
e0319b03
MA
234 mc->block_default_type = IF_IDE;
235 mc->units_per_default_bus = 1;
4672cbd7 236 mc->ignore_memory_transaction_failures = true;
0f2bf05c 237 mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
72649619 238 mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
87c8047f 239 mc->default_ram_id = "ddr-ram";
0c18c6c6
AF
240}
241
b70cf33f 242static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
0b43132f 243 .name = TYPE_ZCU102_MACHINE,
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AF
244 .parent = TYPE_MACHINE,
245 .class_init = xlnx_zcu102_machine_class_init,
246 .instance_init = xlnx_zcu102_machine_instance_init,
247 .instance_size = sizeof(XlnxZCU102),
248};
249
250static void xlnx_zcu102_machine_init_register_types(void)
251{
252 type_register_static(&xlnx_zcu102_machine_init_typeinfo);
253}
254
255type_init(xlnx_zcu102_machine_init_register_types)