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Commit | Line | Data |
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f0a902f7 PC |
1 | /* |
2 | * Xilinx Zynq MPSoC emulation | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx Inc | |
5 | * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | */ | |
17 | ||
12b16722 | 18 | #include "qemu/osdep.h" |
da34e65c | 19 | #include "qapi/error.h" |
0b8fa32f | 20 | #include "qemu/module.h" |
f0a902f7 | 21 | #include "hw/arm/xlnx-zynqmp.h" |
bf4cb109 | 22 | #include "hw/intc/arm_gic_common.h" |
d2e6f370 | 23 | #include "hw/misc/unimp.h" |
cc7d44c2 | 24 | #include "hw/boards.h" |
2a0ee672 | 25 | #include "sysemu/kvm.h" |
5a720b1e | 26 | #include "sysemu/sysemu.h" |
2a0ee672 | 27 | #include "kvm_arm.h" |
7729e1f4 PC |
28 | |
29 | #define GIC_NUM_SPI_INTR 160 | |
30 | ||
bf4cb109 PC |
31 | #define ARM_PHYS_TIMER_PPI 30 |
32 | #define ARM_VIRT_TIMER_PPI 27 | |
75b749af LM |
33 | #define ARM_HYP_TIMER_PPI 26 |
34 | #define ARM_SEC_TIMER_PPI 29 | |
35 | #define GIC_MAINTENANCE_PPI 25 | |
bf4cb109 | 36 | |
20bff213 AF |
37 | #define GEM_REVISION 0x40070106 |
38 | ||
7729e1f4 PC |
39 | #define GIC_BASE_ADDR 0xf9000000 |
40 | #define GIC_DIST_ADDR 0xf9010000 | |
41 | #define GIC_CPU_ADDR 0xf9020000 | |
75b749af LM |
42 | #define GIC_VIFACE_ADDR 0xf9040000 |
43 | #define GIC_VCPU_ADDR 0xf9060000 | |
7729e1f4 | 44 | |
6fdf3282 AF |
45 | #define SATA_INTR 133 |
46 | #define SATA_ADDR 0xFD0C0000 | |
47 | #define SATA_NUM_PORTS 2 | |
48 | ||
babc1f30 FI |
49 | #define QSPI_ADDR 0xff0f0000 |
50 | #define LQSPI_ADDR 0xc0000000 | |
51 | #define QSPI_IRQ 15 | |
668351a5 | 52 | #define QSPI_DMA_ADDR 0xff0f0800 |
c74ccb5d | 53 | #define NUM_QSPI_IRQ_LINES 2 |
babc1f30 | 54 | |
63320bca EI |
55 | #define CRF_ADDR 0xfd1a0000 |
56 | #define CRF_IRQ 120 | |
57 | ||
c28d4b86 EI |
58 | /* Serializer/Deserializer. */ |
59 | #define SERDES_ADDR 0xfd400000 | |
60 | #define SERDES_SIZE 0x20000 | |
61 | ||
b93dbcdd | 62 | #define DP_ADDR 0xfd4a0000 |
b3f5cc3f | 63 | #define DP_IRQ 0x77 |
b93dbcdd FK |
64 | |
65 | #define DPDMA_ADDR 0xfd4c0000 | |
b3f5cc3f | 66 | #define DPDMA_IRQ 0x7a |
b93dbcdd | 67 | |
d2e6f370 | 68 | #define APU_ADDR 0xfd5c0000 |
eb7a38ba | 69 | #define APU_IRQ 153 |
d2e6f370 | 70 | |
51af6231 EI |
71 | #define TTC0_ADDR 0xFF110000 |
72 | #define TTC0_IRQ 36 | |
73 | ||
0ab7bbc7 AF |
74 | #define IPI_ADDR 0xFF300000 |
75 | #define IPI_IRQ 64 | |
76 | ||
08b2f15e AF |
77 | #define RTC_ADDR 0xffa60000 |
78 | #define RTC_IRQ 26 | |
79 | ||
7e47e15c TH |
80 | #define BBRAM_ADDR 0xffcd0000 |
81 | #define BBRAM_IRQ 11 | |
82 | ||
db1264df TH |
83 | #define EFUSE_ADDR 0xffcc0000 |
84 | #define EFUSE_IRQ 87 | |
85 | ||
b630d3d4 PMD |
86 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ |
87 | ||
14ca2e46 PC |
88 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { |
89 | 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, | |
90 | }; | |
91 | ||
92 | static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { | |
93 | 57, 59, 61, 63, | |
94 | }; | |
95 | ||
3bade2a9 PC |
96 | static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = { |
97 | 0xFF000000, 0xFF010000, | |
98 | }; | |
99 | ||
100 | static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { | |
101 | 21, 22, | |
102 | }; | |
103 | ||
840c22cd VG |
104 | static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { |
105 | 0xFF060000, 0xFF070000, | |
106 | }; | |
107 | ||
108 | static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { | |
109 | 23, 24, | |
110 | }; | |
111 | ||
33108e9f SPB |
112 | static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { |
113 | 0xFF160000, 0xFF170000, | |
114 | }; | |
115 | ||
116 | static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = { | |
117 | 48, 49, | |
118 | }; | |
119 | ||
02d07eb4 AF |
120 | static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { |
121 | 0xFF040000, 0xFF050000, | |
122 | }; | |
123 | ||
124 | static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { | |
125 | 19, 20, | |
126 | }; | |
127 | ||
04965bca FI |
128 | static const uint64_t gdma_ch_addr[XLNX_ZYNQMP_NUM_GDMA_CH] = { |
129 | 0xFD500000, 0xFD510000, 0xFD520000, 0xFD530000, | |
130 | 0xFD540000, 0xFD550000, 0xFD560000, 0xFD570000 | |
131 | }; | |
132 | ||
133 | static const int gdma_ch_intr[XLNX_ZYNQMP_NUM_GDMA_CH] = { | |
134 | 124, 125, 126, 127, 128, 129, 130, 131 | |
135 | }; | |
136 | ||
137 | static const uint64_t adma_ch_addr[XLNX_ZYNQMP_NUM_ADMA_CH] = { | |
138 | 0xFFA80000, 0xFFA90000, 0xFFAA0000, 0xFFAB0000, | |
139 | 0xFFAC0000, 0xFFAD0000, 0xFFAE0000, 0xFFAF0000 | |
140 | }; | |
141 | ||
142 | static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = { | |
143 | 77, 78, 79, 80, 81, 82, 83, 84 | |
144 | }; | |
145 | ||
acc0b8b0 FI |
146 | static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = { |
147 | 0xFE200000, 0xFE300000 | |
148 | }; | |
149 | ||
150 | static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = { | |
151 | 65, 70 | |
152 | }; | |
153 | ||
7729e1f4 PC |
154 | typedef struct XlnxZynqMPGICRegion { |
155 | int region_index; | |
156 | uint32_t address; | |
75b749af LM |
157 | uint32_t offset; |
158 | bool virt; | |
7729e1f4 PC |
159 | } XlnxZynqMPGICRegion; |
160 | ||
161 | static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = { | |
75b749af LM |
162 | /* Distributor */ |
163 | { | |
164 | .region_index = 0, | |
165 | .address = GIC_DIST_ADDR, | |
166 | .offset = 0, | |
167 | .virt = false | |
168 | }, | |
169 | ||
170 | /* CPU interface */ | |
171 | { | |
172 | .region_index = 1, | |
173 | .address = GIC_CPU_ADDR, | |
174 | .offset = 0, | |
175 | .virt = false | |
176 | }, | |
177 | { | |
178 | .region_index = 1, | |
179 | .address = GIC_CPU_ADDR + 0x10000, | |
180 | .offset = 0x1000, | |
181 | .virt = false | |
182 | }, | |
183 | ||
184 | /* Virtual interface */ | |
185 | { | |
186 | .region_index = 2, | |
187 | .address = GIC_VIFACE_ADDR, | |
188 | .offset = 0, | |
189 | .virt = true | |
190 | }, | |
191 | ||
192 | /* Virtual CPU interface */ | |
193 | { | |
194 | .region_index = 3, | |
195 | .address = GIC_VCPU_ADDR, | |
196 | .offset = 0, | |
197 | .virt = true | |
198 | }, | |
199 | { | |
200 | .region_index = 3, | |
201 | .address = GIC_VCPU_ADDR + 0x10000, | |
202 | .offset = 0x1000, | |
203 | .virt = true | |
204 | }, | |
7729e1f4 | 205 | }; |
f0a902f7 | 206 | |
bf4cb109 PC |
207 | static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) |
208 | { | |
209 | return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; | |
210 | } | |
211 | ||
cc7d44c2 LX |
212 | static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, |
213 | const char *boot_cpu, Error **errp) | |
6ed92b14 | 214 | { |
6ed92b14 | 215 | int i; |
cc7d44c2 LX |
216 | int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, |
217 | XLNX_ZYNQMP_NUM_RPU_CPUS); | |
6ed92b14 | 218 | |
e5b51753 PM |
219 | if (num_rpus <= 0) { |
220 | /* Don't create rpu-cluster object if there's nothing to put in it */ | |
221 | return; | |
222 | } | |
223 | ||
816fd397 | 224 | object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, |
9fc7fc4d | 225 | TYPE_CPU_CLUSTER); |
816fd397 LM |
226 | qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); |
227 | ||
6908ec44 | 228 | for (i = 0; i < num_rpus; i++) { |
7a309cc9 | 229 | const char *name; |
6ed92b14 | 230 | |
d0313798 | 231 | object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]", |
9fc7fc4d MA |
232 | &s->rpu_cpu[i], |
233 | ARM_CPU_TYPE_NAME("cortex-r5f")); | |
6ed92b14 EI |
234 | |
235 | name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); | |
236 | if (strcmp(name, boot_cpu)) { | |
50c785f2 PM |
237 | /* |
238 | * Secondary CPUs start in powered-down state. | |
239 | */ | |
5325cc34 MA |
240 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), |
241 | "start-powered-off", true, &error_abort); | |
6ed92b14 EI |
242 | } else { |
243 | s->boot_cpu_ptr = &s->rpu_cpu[i]; | |
244 | } | |
6ed92b14 | 245 | |
5325cc34 | 246 | object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, |
6ed92b14 | 247 | &error_abort); |
668f62ec | 248 | if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { |
6ed92b14 EI |
249 | return; |
250 | } | |
251 | } | |
fa434424 | 252 | |
ce189ab2 | 253 | qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); |
6ed92b14 EI |
254 | } |
255 | ||
7e47e15c TH |
256 | static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) |
257 | { | |
258 | SysBusDevice *sbd; | |
259 | ||
260 | object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, | |
261 | sizeof(s->bbram), TYPE_XLNX_BBRAM, | |
262 | &error_fatal, | |
263 | "crc-zpads", "1", | |
264 | NULL); | |
265 | sbd = SYS_BUS_DEVICE(&s->bbram); | |
266 | ||
267 | sysbus_realize(sbd, &error_fatal); | |
268 | sysbus_mmio_map(sbd, 0, BBRAM_ADDR); | |
269 | sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); | |
270 | } | |
271 | ||
db1264df TH |
272 | static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) |
273 | { | |
274 | Object *bits = OBJECT(&s->efuse); | |
275 | Object *ctrl = OBJECT(&s->efuse_ctrl); | |
276 | SysBusDevice *sbd; | |
277 | ||
278 | object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, | |
279 | TYPE_XLNX_ZYNQMP_EFUSE); | |
280 | ||
281 | object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, | |
282 | sizeof(s->efuse), | |
283 | TYPE_XLNX_EFUSE, &error_abort, | |
284 | "efuse-nr", "3", | |
285 | "efuse-size", "2048", | |
286 | NULL); | |
287 | ||
288 | qdev_realize(DEVICE(bits), NULL, &error_abort); | |
289 | object_property_set_link(ctrl, "efuse", bits, &error_abort); | |
290 | ||
291 | sbd = SYS_BUS_DEVICE(ctrl); | |
292 | sysbus_realize(sbd, &error_abort); | |
293 | sysbus_mmio_map(sbd, 0, EFUSE_ADDR); | |
294 | sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); | |
295 | } | |
296 | ||
eb7a38ba EI |
297 | static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) |
298 | { | |
299 | SysBusDevice *sbd; | |
300 | int i; | |
301 | ||
302 | object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl, | |
303 | TYPE_XLNX_ZYNQMP_APU_CTRL); | |
304 | sbd = SYS_BUS_DEVICE(&s->apu_ctrl); | |
305 | ||
306 | for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { | |
307 | g_autofree gchar *name = g_strdup_printf("cpu%d", i); | |
308 | ||
309 | object_property_set_link(OBJECT(&s->apu_ctrl), name, | |
310 | OBJECT(&s->apu_cpu[i]), &error_abort); | |
311 | } | |
312 | ||
313 | sysbus_realize(sbd, &error_fatal); | |
314 | sysbus_mmio_map(sbd, 0, APU_ADDR); | |
315 | sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); | |
316 | } | |
317 | ||
63320bca EI |
318 | static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) |
319 | { | |
320 | SysBusDevice *sbd; | |
321 | ||
322 | object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF); | |
323 | sbd = SYS_BUS_DEVICE(&s->crf); | |
324 | ||
325 | sysbus_realize(sbd, &error_fatal); | |
326 | sysbus_mmio_map(sbd, 0, CRF_ADDR); | |
327 | sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); | |
328 | } | |
329 | ||
51af6231 EI |
330 | static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) |
331 | { | |
332 | SysBusDevice *sbd; | |
333 | int i, irq; | |
334 | ||
335 | for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { | |
336 | object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], | |
337 | TYPE_CADENCE_TTC); | |
338 | sbd = SYS_BUS_DEVICE(&s->ttc[i]); | |
339 | ||
340 | sysbus_realize(sbd, &error_fatal); | |
341 | sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); | |
342 | for (irq = 0; irq < 3; irq++) { | |
343 | sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); | |
344 | } | |
345 | } | |
346 | } | |
347 | ||
d2e6f370 TH |
348 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) |
349 | { | |
350 | static const struct UnimpInfo { | |
351 | const char *name; | |
352 | hwaddr base; | |
353 | hwaddr size; | |
354 | } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = { | |
c28d4b86 | 355 | { .name = "serdes", SERDES_ADDR, SERDES_SIZE }, |
d2e6f370 TH |
356 | }; |
357 | unsigned int nr; | |
358 | ||
359 | for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) { | |
360 | const struct UnimpInfo *info = &unimp_areas[nr]; | |
361 | DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); | |
362 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
363 | ||
364 | assert(info->name && info->base && info->size > 0); | |
365 | qdev_prop_set_string(dev, "name", info->name); | |
366 | qdev_prop_set_uint64(dev, "size", info->size); | |
367 | object_property_add_child(OBJECT(s), info->name, OBJECT(dev)); | |
368 | ||
369 | sysbus_realize_and_unref(sbd, &error_fatal); | |
370 | sysbus_mmio_map(sbd, 0, info->base); | |
371 | } | |
372 | } | |
373 | ||
f0a902f7 PC |
374 | static void xlnx_zynqmp_init(Object *obj) |
375 | { | |
cc7d44c2 | 376 | MachineState *ms = MACHINE(qdev_get_machine()); |
f0a902f7 PC |
377 | XlnxZynqMPState *s = XLNX_ZYNQMP(obj); |
378 | int i; | |
cc7d44c2 | 379 | int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); |
f0a902f7 | 380 | |
816fd397 | 381 | object_initialize_child(obj, "apu-cluster", &s->apu_cluster, |
9fc7fc4d | 382 | TYPE_CPU_CLUSTER); |
816fd397 LM |
383 | qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); |
384 | ||
6908ec44 | 385 | for (i = 0; i < num_apus; i++) { |
816fd397 | 386 | object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", |
9fc7fc4d MA |
387 | &s->apu_cpu[i], |
388 | ARM_CPU_TYPE_NAME("cortex-a53")); | |
f0a902f7 | 389 | } |
7729e1f4 | 390 | |
db873cc5 | 391 | object_initialize_child(obj, "gic", &s->gic, gic_class_name()); |
14ca2e46 PC |
392 | |
393 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { | |
db873cc5 | 394 | object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); |
14ca2e46 | 395 | } |
3bade2a9 PC |
396 | |
397 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { | |
db873cc5 MA |
398 | object_initialize_child(obj, "uart[*]", &s->uart[i], |
399 | TYPE_CADENCE_UART); | |
3bade2a9 | 400 | } |
6fdf3282 | 401 | |
840c22cd VG |
402 | for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { |
403 | object_initialize_child(obj, "can[*]", &s->can[i], | |
404 | TYPE_XLNX_ZYNQMP_CAN); | |
405 | } | |
406 | ||
db873cc5 | 407 | object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); |
33108e9f SPB |
408 | |
409 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | |
5a147c8c MA |
410 | object_initialize_child(obj, "sdhci[*]", &s->sdhci[i], |
411 | TYPE_SYSBUS_SDHCI); | |
33108e9f | 412 | } |
02d07eb4 AF |
413 | |
414 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { | |
db873cc5 | 415 | object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_XILINX_SPIPS); |
02d07eb4 | 416 | } |
b93dbcdd | 417 | |
db873cc5 | 418 | object_initialize_child(obj, "qspi", &s->qspi, TYPE_XLNX_ZYNQMP_QSPIPS); |
babc1f30 | 419 | |
db873cc5 | 420 | object_initialize_child(obj, "xxxdp", &s->dp, TYPE_XLNX_DP); |
b93dbcdd | 421 | |
db873cc5 | 422 | object_initialize_child(obj, "dp-dma", &s->dpdma, TYPE_XLNX_DPDMA); |
0ab7bbc7 | 423 | |
db873cc5 | 424 | object_initialize_child(obj, "ipi", &s->ipi, TYPE_XLNX_ZYNQMP_IPI); |
08b2f15e | 425 | |
db873cc5 | 426 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_XLNX_ZYNQMP_RTC); |
04965bca FI |
427 | |
428 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { | |
db873cc5 | 429 | object_initialize_child(obj, "gdma[*]", &s->gdma[i], TYPE_XLNX_ZDMA); |
04965bca FI |
430 | } |
431 | ||
432 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { | |
db873cc5 | 433 | object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDMA); |
04965bca | 434 | } |
668351a5 XC |
435 | |
436 | object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA); | |
c74ccb5d FI |
437 | object_initialize_child(obj, "qspi-irq-orgate", |
438 | &s->qspi_irq_orgate, TYPE_OR_IRQ); | |
acc0b8b0 FI |
439 | |
440 | for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { | |
441 | object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); | |
442 | } | |
f0a902f7 PC |
443 | } |
444 | ||
445 | static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) | |
446 | { | |
cc7d44c2 | 447 | MachineState *ms = MACHINE(qdev_get_machine()); |
f0a902f7 | 448 | XlnxZynqMPState *s = XLNX_ZYNQMP(dev); |
7729e1f4 | 449 | MemoryRegion *system_memory = get_system_memory(); |
f0a902f7 | 450 | uint8_t i; |
dc3b89ef | 451 | uint64_t ram_size; |
cc7d44c2 | 452 | int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); |
6396a193 | 453 | const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; |
dc3b89ef | 454 | ram_addr_t ddr_low_size, ddr_high_size; |
14ca2e46 | 455 | qemu_irq gic_spi[GIC_NUM_SPI_INTR]; |
f0a902f7 PC |
456 | Error *err = NULL; |
457 | ||
dc3b89ef AF |
458 | ram_size = memory_region_size(s->ddr_ram); |
459 | ||
21bce371 XC |
460 | /* |
461 | * Create the DDR Memory Regions. User friendly checks should happen at | |
dc3b89ef AF |
462 | * the board level |
463 | */ | |
464 | if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { | |
21bce371 XC |
465 | /* |
466 | * The RAM size is above the maximum available for the low DDR. | |
dc3b89ef AF |
467 | * Create the high DDR memory region as well. |
468 | */ | |
469 | assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE); | |
470 | ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; | |
471 | ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE; | |
472 | ||
32b9523a PMD |
473 | memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev), |
474 | "ddr-ram-high", s->ddr_ram, ddr_low_size, | |
475 | ddr_high_size); | |
dc3b89ef AF |
476 | memory_region_add_subregion(get_system_memory(), |
477 | XLNX_ZYNQMP_HIGH_RAM_START, | |
478 | &s->ddr_ram_high); | |
479 | } else { | |
480 | /* RAM must be non-zero */ | |
481 | assert(ram_size); | |
482 | ddr_low_size = ram_size; | |
483 | } | |
484 | ||
32b9523a PMD |
485 | memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low", |
486 | s->ddr_ram, 0, ddr_low_size); | |
dc3b89ef AF |
487 | memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low); |
488 | ||
6675d719 AF |
489 | /* Create the four OCM banks */ |
490 | for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) { | |
491 | char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); | |
492 | ||
98a99ce0 | 493 | memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, |
f8ed85ac | 494 | XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); |
6675d719 AF |
495 | memory_region_add_subregion(get_system_memory(), |
496 | XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + | |
497 | i * XLNX_ZYNQMP_OCM_RAM_SIZE, | |
498 | &s->ocm_ram[i]); | |
499 | ||
500 | g_free(ocm_name); | |
501 | } | |
502 | ||
7729e1f4 PC |
503 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); |
504 | qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); | |
6908ec44 | 505 | qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); |
75b749af LM |
506 | qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure); |
507 | qdev_prop_set_bit(DEVICE(&s->gic), | |
508 | "has-virtualization-extensions", s->virt); | |
7729e1f4 | 509 | |
ce189ab2 | 510 | qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); |
816fd397 | 511 | |
0776d967 | 512 | /* Realize APUs before realizing the GIC. KVM requires this. */ |
6908ec44 | 513 | for (i = 0; i < num_apus; i++) { |
7a309cc9 | 514 | const char *name; |
bf4cb109 | 515 | |
6396a193 PC |
516 | name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); |
517 | if (strcmp(name, boot_cpu)) { | |
50c785f2 PM |
518 | /* |
519 | * Secondary CPUs start in powered-down state. | |
520 | */ | |
5325cc34 MA |
521 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), |
522 | "start-powered-off", true, &error_abort); | |
6396a193 PC |
523 | } else { |
524 | s->boot_cpu_ptr = &s->apu_cpu[i]; | |
f0a902f7 PC |
525 | } |
526 | ||
5325cc34 MA |
527 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el3", s->secure, |
528 | NULL); | |
529 | object_property_set_bool(OBJECT(&s->apu_cpu[i]), "has_el2", s->virt, | |
530 | NULL); | |
531 | object_property_set_int(OBJECT(&s->apu_cpu[i]), "reset-cbar", | |
532 | GIC_BASE_ADDR, &error_abort); | |
533 | object_property_set_int(OBJECT(&s->apu_cpu[i]), "core-count", | |
534 | num_apus, &error_abort); | |
668f62ec | 535 | if (!qdev_realize(DEVICE(&s->apu_cpu[i]), NULL, errp)) { |
f0a902f7 PC |
536 | return; |
537 | } | |
0776d967 EI |
538 | } |
539 | ||
668f62ec | 540 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { |
0776d967 EI |
541 | return; |
542 | } | |
543 | ||
544 | assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS); | |
545 | for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { | |
546 | SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic); | |
547 | const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i]; | |
75b749af | 548 | MemoryRegion *mr; |
0776d967 EI |
549 | uint32_t addr = r->address; |
550 | int j; | |
551 | ||
75b749af LM |
552 | if (r->virt && !s->virt) { |
553 | continue; | |
554 | } | |
0776d967 | 555 | |
75b749af | 556 | mr = sysbus_mmio_get_region(gic, r->region_index); |
0776d967 EI |
557 | for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { |
558 | MemoryRegion *alias = &s->gic_mr[i][j]; | |
559 | ||
0776d967 | 560 | memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr, |
75b749af | 561 | r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE); |
0776d967 | 562 | memory_region_add_subregion(system_memory, addr, alias); |
75b749af LM |
563 | |
564 | addr += XLNX_ZYNQMP_GIC_REGION_SIZE; | |
0776d967 EI |
565 | } |
566 | } | |
567 | ||
6908ec44 | 568 | for (i = 0; i < num_apus; i++) { |
0776d967 | 569 | qemu_irq irq; |
7729e1f4 PC |
570 | |
571 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, | |
2e5577bc PC |
572 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), |
573 | ARM_CPU_IRQ)); | |
75b749af LM |
574 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, |
575 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
576 | ARM_CPU_FIQ)); | |
577 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, | |
578 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
579 | ARM_CPU_VIRQ)); | |
580 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, | |
581 | qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), | |
582 | ARM_CPU_VFIQ)); | |
bf4cb109 PC |
583 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
584 | arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); | |
75b749af | 585 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); |
bf4cb109 PC |
586 | irq = qdev_get_gpio_in(DEVICE(&s->gic), |
587 | arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); | |
75b749af LM |
588 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); |
589 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
590 | arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); | |
591 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); | |
592 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
593 | arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); | |
594 | qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); | |
595 | ||
596 | if (s->virt) { | |
597 | irq = qdev_get_gpio_in(DEVICE(&s->gic), | |
598 | arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI)); | |
599 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq); | |
600 | } | |
f0a902f7 | 601 | } |
14ca2e46 | 602 | |
cc7d44c2 | 603 | xlnx_zynqmp_create_rpu(ms, s, boot_cpu, &err); |
6908ec44 AF |
604 | if (err) { |
605 | error_propagate(errp, err); | |
606 | return; | |
b58850e7 PC |
607 | } |
608 | ||
6396a193 | 609 | if (!s->boot_cpu_ptr) { |
9af9e0fe | 610 | error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); |
6396a193 PC |
611 | return; |
612 | } | |
613 | ||
14ca2e46 PC |
614 | for (i = 0; i < GIC_NUM_SPI_INTR; i++) { |
615 | gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); | |
616 | } | |
617 | ||
618 | for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { | |
619 | NICInfo *nd = &nd_table[i]; | |
620 | ||
7ad36e2e | 621 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
14ca2e46 PC |
622 | if (nd->used) { |
623 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
624 | qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); | |
625 | } | |
5325cc34 | 626 | object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, |
20bff213 | 627 | &error_abort); |
dfc38879 BM |
628 | object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23, |
629 | &error_abort); | |
5325cc34 | 630 | object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, |
20bff213 | 631 | &error_abort); |
668f62ec | 632 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { |
14ca2e46 PC |
633 | return; |
634 | } | |
635 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); | |
636 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, | |
637 | gic_spi[gem_intr[i]]); | |
638 | } | |
3bade2a9 PC |
639 | |
640 | for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { | |
9bca0edb | 641 | qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); |
668f62ec | 642 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { |
3bade2a9 PC |
643 | return; |
644 | } | |
645 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]); | |
646 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | |
647 | gic_spi[uart_intr[i]]); | |
648 | } | |
6fdf3282 | 649 | |
840c22cd VG |
650 | for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { |
651 | object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", | |
652 | XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); | |
653 | ||
654 | object_property_set_link(OBJECT(&s->can[i]), "canbus", | |
655 | OBJECT(s->canbus[i]), &error_fatal); | |
656 | ||
657 | sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); | |
658 | if (err) { | |
659 | error_propagate(errp, err); | |
660 | return; | |
661 | } | |
662 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); | |
663 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, | |
664 | gic_spi[can_intr[i]]); | |
665 | } | |
666 | ||
5325cc34 | 667 | object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, |
6fdf3282 | 668 | &error_abort); |
668f62ec | 669 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { |
6fdf3282 AF |
670 | return; |
671 | } | |
672 | ||
673 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); | |
674 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); | |
33108e9f SPB |
675 | |
676 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | |
63fef628 | 677 | char *bus_name; |
b630d3d4 PMD |
678 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]); |
679 | Object *sdhci = OBJECT(&s->sdhci[i]); | |
680 | ||
21bce371 XC |
681 | /* |
682 | * Compatible with: | |
b630d3d4 PMD |
683 | * - SD Host Controller Specification Version 3.00 |
684 | * - SDIO Specification Version 3.0 | |
685 | * - eMMC Specification Version 4.51 | |
686 | */ | |
668f62ec | 687 | if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) { |
660b4e70 PM |
688 | return; |
689 | } | |
778a2dc5 | 690 | if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES, |
668f62ec | 691 | errp)) { |
660b4e70 PM |
692 | return; |
693 | } | |
668f62ec | 694 | if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) { |
660b4e70 PM |
695 | return; |
696 | } | |
668f62ec | 697 | if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) { |
33108e9f SPB |
698 | return; |
699 | } | |
b630d3d4 PMD |
700 | sysbus_mmio_map(sbd, 0, sdhci_addr[i]); |
701 | sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]); | |
702 | ||
eb4f566b | 703 | /* Alias controller SD bus to the SoC itself */ |
63fef628 | 704 | bus_name = g_strdup_printf("sd-bus%d", i); |
d2623129 | 705 | object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus"); |
eb4f566b | 706 | g_free(bus_name); |
33108e9f | 707 | } |
02d07eb4 AF |
708 | |
709 | for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { | |
710 | gchar *bus_name; | |
711 | ||
668f62ec | 712 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
660b4e70 PM |
713 | return; |
714 | } | |
02d07eb4 AF |
715 | |
716 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); | |
717 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
718 | gic_spi[spi_intr[i]]); | |
719 | ||
720 | /* Alias controller SPI bus to the SoC itself */ | |
721 | bus_name = g_strdup_printf("spi%d", i); | |
722 | object_property_add_alias(OBJECT(s), bus_name, | |
d2623129 | 723 | OBJECT(&s->spi[i]), "spi0"); |
b93dbcdd FK |
724 | g_free(bus_name); |
725 | } | |
726 | ||
668f62ec | 727 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) { |
b93dbcdd FK |
728 | return; |
729 | } | |
730 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR); | |
731 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]); | |
732 | ||
668f62ec | 733 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->dpdma), errp)) { |
b93dbcdd | 734 | return; |
02d07eb4 | 735 | } |
5325cc34 | 736 | object_property_set_link(OBJECT(&s->dp), "dpdma", OBJECT(&s->dpdma), |
b93dbcdd FK |
737 | &error_abort); |
738 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR); | |
739 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]); | |
0ab7bbc7 | 740 | |
668f62ec | 741 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ipi), errp)) { |
0ab7bbc7 AF |
742 | return; |
743 | } | |
744 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR); | |
745 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]); | |
08b2f15e | 746 | |
668f62ec | 747 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
08b2f15e AF |
748 | return; |
749 | } | |
750 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); | |
751 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); | |
04965bca | 752 | |
7e47e15c | 753 | xlnx_zynqmp_create_bbram(s, gic_spi); |
db1264df | 754 | xlnx_zynqmp_create_efuse(s, gic_spi); |
eb7a38ba | 755 | xlnx_zynqmp_create_apu_ctrl(s, gic_spi); |
63320bca | 756 | xlnx_zynqmp_create_crf(s, gic_spi); |
51af6231 | 757 | xlnx_zynqmp_create_ttc(s, gic_spi); |
d2e6f370 TH |
758 | xlnx_zynqmp_create_unimp_mmio(s); |
759 | ||
04965bca | 760 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
778a2dc5 | 761 | if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128, |
668f62ec | 762 | errp)) { |
660b4e70 PM |
763 | return; |
764 | } | |
783dbab1 PMD |
765 | if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma", |
766 | OBJECT(system_memory), errp)) { | |
767 | return; | |
768 | } | |
668f62ec | 769 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) { |
04965bca FI |
770 | return; |
771 | } | |
772 | ||
773 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gdma[i]), 0, gdma_ch_addr[i]); | |
774 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gdma[i]), 0, | |
775 | gic_spi[gdma_ch_intr[i]]); | |
776 | } | |
777 | ||
778 | for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { | |
783dbab1 PMD |
779 | if (!object_property_set_link(OBJECT(&s->adma[i]), "dma", |
780 | OBJECT(system_memory), errp)) { | |
781 | return; | |
782 | } | |
668f62ec | 783 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) { |
04965bca FI |
784 | return; |
785 | } | |
786 | ||
787 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->adma[i]), 0, adma_ch_addr[i]); | |
788 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, | |
789 | gic_spi[adma_ch_intr[i]]); | |
790 | } | |
668351a5 | 791 | |
c74ccb5d FI |
792 | object_property_set_int(OBJECT(&s->qspi_irq_orgate), |
793 | "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal); | |
794 | qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal); | |
795 | qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]); | |
796 | ||
c31b7f59 PMD |
797 | if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma", |
798 | OBJECT(system_memory), errp)) { | |
799 | return; | |
800 | } | |
668351a5 XC |
801 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { |
802 | return; | |
803 | } | |
804 | ||
805 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); | |
c74ccb5d FI |
806 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, |
807 | qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0)); | |
34a3a71d PMD |
808 | |
809 | if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", | |
810 | OBJECT(&s->qspi_dma), errp)) { | |
811 | return; | |
812 | } | |
813 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) { | |
814 | return; | |
815 | } | |
816 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); | |
817 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); | |
c74ccb5d FI |
818 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, |
819 | qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1)); | |
34a3a71d PMD |
820 | |
821 | for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { | |
822 | g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i); | |
823 | g_autofree gchar *target_bus = g_strdup_printf("spi%d", i); | |
824 | ||
825 | /* Alias controller SPI bus to the SoC itself */ | |
826 | object_property_add_alias(OBJECT(s), bus_name, | |
827 | OBJECT(&s->qspi), target_bus); | |
828 | } | |
acc0b8b0 FI |
829 | |
830 | for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { | |
831 | if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma", | |
832 | OBJECT(system_memory), errp)) { | |
833 | return; | |
834 | } | |
835 | ||
836 | qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4); | |
837 | qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); | |
838 | ||
839 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) { | |
840 | return; | |
841 | } | |
842 | ||
843 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]); | |
844 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0, | |
845 | gic_spi[usb_intr[i]]); | |
846 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1, | |
847 | gic_spi[usb_intr[i] + 1]); | |
848 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2, | |
849 | gic_spi[usb_intr[i] + 2]); | |
850 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3, | |
851 | gic_spi[usb_intr[i] + 3]); | |
852 | } | |
f0a902f7 PC |
853 | } |
854 | ||
6396a193 PC |
855 | static Property xlnx_zynqmp_props[] = { |
856 | DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), | |
37d42473 | 857 | DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), |
1946809e | 858 | DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), |
c3acfa01 FZ |
859 | DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, |
860 | MemoryRegion *), | |
840c22cd VG |
861 | DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, |
862 | CanBusState *), | |
863 | DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, | |
864 | CanBusState *), | |
6396a193 PC |
865 | DEFINE_PROP_END_OF_LIST() |
866 | }; | |
867 | ||
f0a902f7 PC |
868 | static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) |
869 | { | |
870 | DeviceClass *dc = DEVICE_CLASS(oc); | |
871 | ||
4f67d30b | 872 | device_class_set_props(dc, xlnx_zynqmp_props); |
f0a902f7 | 873 | dc->realize = xlnx_zynqmp_realize; |
d8589144 TH |
874 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
875 | dc->user_creatable = false; | |
f0a902f7 PC |
876 | } |
877 | ||
878 | static const TypeInfo xlnx_zynqmp_type_info = { | |
879 | .name = TYPE_XLNX_ZYNQMP, | |
880 | .parent = TYPE_DEVICE, | |
881 | .instance_size = sizeof(XlnxZynqMPState), | |
882 | .instance_init = xlnx_zynqmp_init, | |
883 | .class_init = xlnx_zynqmp_class_init, | |
884 | }; | |
885 | ||
886 | static void xlnx_zynqmp_register_types(void) | |
887 | { | |
888 | type_register_static(&xlnx_zynqmp_type_info); | |
889 | } | |
890 | ||
891 | type_init(xlnx_zynqmp_register_types) |