[mirror_qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
    0xFF040000, 0xFF050000,
};

static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
    19, 20,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
                                  &error_abort);
    }

    object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
                             (Object **)&s->ddr_ram,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);

    object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          TYPE_XILINX_SPIPS);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        vmstate_register_ram_global(&s->ocm_ram[i]);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        qemu_irq irq;
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        char *name;

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        char *bus_name;

        object_property_set_bool(OBJECT(&s->sdhci[i]), true,
                                 "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                        sdhci_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                           gic_spi[sdhci_intr[i]]);
        /* Alias controller SD bus to the SoC itself */
        bus_name = g_strdup_printf("sd-bus%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->sdhci[i]), "sd-bus",
                                  &error_abort);
        g_free(bus_name);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        gchar *bus_name;

        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           gic_spi[spi_intr[i]]);

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi0",
                                  &error_abort);
	g_free(bus_name);
    }
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;

    /*
     * Reason: creates an ARM CPU, thus use after free(), see
     * arm_cpu_class_init()
     */
    dc->cannot_destroy_with_object_finalize_yet = true;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
4771d756 PB	20	#include "qemu-common.h"
4771d756 PB	21	#include "cpu.h"
f0a902f7	22	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	23	#include "hw/intc/arm_gic_common.h"
7729e1f4 PC	24	#include "exec/address-spaces.h"
	25
	26	#define GIC_NUM_SPI_INTR 160
	27
bf4cb109 PC	28	#define ARM_PHYS_TIMER_PPI 30
	29	#define ARM_VIRT_TIMER_PPI 27
	30
7729e1f4 PC	31	#define GIC_BASE_ADDR 0xf9000000
	32	#define GIC_DIST_ADDR 0xf9010000
	33	#define GIC_CPU_ADDR 0xf9020000
	34
6fdf3282 AF	35	#define SATA_INTR 133
	36	#define SATA_ADDR 0xFD0C0000
	37	#define SATA_NUM_PORTS 2
	38
14ca2e46 PC	39	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	40	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	41	};
	42
	43	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	44	57, 59, 61, 63,
	45	};
	46
3bade2a9 PC	47	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	48	0xFF000000, 0xFF010000,
	49	};
	50
	51	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	52	21, 22,
	53	};
	54
33108e9f SPB	55	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	56	0xFF160000, 0xFF170000,
	57	};
	58
	59	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	60	48, 49,
	61	};
	62
02d07eb4 AF	63	static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
	64	0xFF040000, 0xFF050000,
	65	};
	66
	67	static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
	68	19, 20,
	69	};
	70
7729e1f4 PC	71	typedef struct XlnxZynqMPGICRegion {
	72	int region_index;
	73	uint32_t address;
	74	} XlnxZynqMPGICRegion;
	75
	76	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	77	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	78	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	79	};
f0a902f7	80
bf4cb109 PC	81	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	82	{
	83	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	84	}
	85
f0a902f7 PC	86	static void xlnx_zynqmp_init(Object *obj)
	87	{
	88	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	89	int i;
	90
2e5577bc PC	91	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
2e5577bc PC	92	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	93	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	94	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	95	&error_abort);
f0a902f7 PC	96	}
7729e1f4	97
b58850e7 PC	98	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	99	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	100	"cortex-r5-" TYPE_ARM_CPU);
	101	object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]),
	102	&error_abort);
	103	}
	104
dc3b89ef AF	105	object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
	106	(Object **)&s->ddr_ram,
	107	qdev_prop_allow_set_link_before_realize,
	108	OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
	109
7729e1f4 PC	110	object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
7729e1f4 PC	111	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	112
	113	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	114	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	115	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	116	}
3bade2a9 PC	117
	118	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	119	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	120	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	121	}
6fdf3282 AF	122
	123	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	124	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	125
	126	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	127	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	128	TYPE_SYSBUS_SDHCI);
	129	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	130	sysbus_get_default());
	131	}
02d07eb4 AF	132
	133	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	134	object_initialize(&s->spi[i], sizeof(s->spi[i]),
	135	TYPE_XILINX_SPIPS);
	136	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
	137	}
f0a902f7 PC	138	}
	139
	140	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	141	{
	142	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	143	MemoryRegion *system_memory = get_system_memory();
f0a902f7	144	uint8_t i;
dc3b89ef	145	uint64_t ram_size;
6396a193	146	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	147	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	148	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	149	Error *err = NULL;
f0a902f7 PC	150
dc3b89ef AF	151	ram_size = memory_region_size(s->ddr_ram);
	152
	153	/* Create the DDR Memory Regions. User friendly checks should happen at
	154	* the board level
	155	*/
	156	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	157	/* The RAM size is above the maximum available for the low DDR.
	158	* Create the high DDR memory region as well.
	159	*/
	160	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	161	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	162	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	163
	164	memory_region_init_alias(&s->ddr_ram_high, NULL,
	165	"ddr-ram-high", s->ddr_ram,
	166	ddr_low_size, ddr_high_size);
	167	memory_region_add_subregion(get_system_memory(),
	168	XLNX_ZYNQMP_HIGH_RAM_START,
	169	&s->ddr_ram_high);
	170	} else {
	171	/* RAM must be non-zero */
	172	assert(ram_size);
	173	ddr_low_size = ram_size;
	174	}
	175
	176	memory_region_init_alias(&s->ddr_ram_low, NULL,
	177	"ddr-ram-low", s->ddr_ram,
	178	0, ddr_low_size);
	179	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	180
6675d719 AF	181	/* Create the four OCM banks */
	182	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	183	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	184
	185	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	186	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	187	vmstate_register_ram_global(&s->ocm_ram[i]);
	188	memory_region_add_subregion(get_system_memory(),
	189	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	190	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	191	&s->ocm_ram[i]);
	192
	193	g_free(ocm_name);
	194	}
	195
7729e1f4 PC	196	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	197	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
2e5577bc	198	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
7729e1f4 PC	199	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
7729e1f4 PC	200	if (err) {
24cfc8dc	201	error_propagate(errp, err);
7729e1f4 PC	202	return;
	203	}
	204	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	205	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	206	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	207	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	208	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	209	uint32_t addr = r->address;
	210	int j;
	211
	212	sysbus_mmio_map(gic, r->region_index, addr);
	213
	214	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	215	MemoryRegion *alias = &s->gic_mr[i][j];
	216
	217	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	218	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	219	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	220	memory_region_add_subregion(system_memory, addr, alias);
	221	}
	222	}
	223
2e5577bc	224	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
bf4cb109	225	qemu_irq irq;
6396a193	226	char *name;
bf4cb109	227
2e5577bc	228	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	229	"psci-conduit", &error_abort);
6396a193 PC	230
	231	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	232	if (strcmp(name, boot_cpu)) {
f0a902f7	233	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	234	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	235	"start-powered-off", &error_abort);
6396a193 PC	236	} else {
6396a193 PC	237	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	238	}
5348c62c	239	g_free(name);
f0a902f7	240
2e5577bc	241	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	242	"reset-cbar", &error_abort);
2e5577bc PC	243	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	244	&err);
f0a902f7	245	if (err) {
24cfc8dc	246	error_propagate(errp, err);
f0a902f7 PC	247	return;
f0a902f7 PC	248	}
7729e1f4 PC	249
7729e1f4 PC	250	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	251	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	252	ARM_CPU_IRQ));
bf4cb109 PC	253	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	254	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	255	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	256	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	257	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	258	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	259	}
14ca2e46	260
b58850e7 PC	261	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	262	char *name;
	263
	264	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	265	if (strcmp(name, boot_cpu)) {
	266	/* Secondary CPUs start in PSCI powered-down state */
	267	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	268	"start-powered-off", &error_abort);
	269	} else {
	270	s->boot_cpu_ptr = &s->rpu_cpu[i];
	271	}
5348c62c	272	g_free(name);
b58850e7 PC	273
b58850e7 PC	274	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
e1292517	275	&error_abort);
b58850e7 PC	276	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	277	&err);
	278	if (err) {
24cfc8dc	279	error_propagate(errp, err);
b58850e7 PC	280	return;
	281	}
	282	}
	283
6396a193	284	if (!s->boot_cpu_ptr) {
9af9e0fe	285	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	286	return;
	287	}
	288
14ca2e46 PC	289	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	290	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	291	}
	292
	293	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	294	NICInfo *nd = &nd_table[i];
	295
	296	if (nd->used) {
	297	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	298	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	299	}
	300	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
	301	if (err) {
24cfc8dc	302	error_propagate(errp, err);
14ca2e46 PC	303	return;
	304	}
	305	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	306	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	307	gic_spi[gem_intr[i]]);
	308	}
3bade2a9 PC	309
	310	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	311	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	312	if (err) {
24cfc8dc	313	error_propagate(errp, err);
3bade2a9 PC	314	return;
	315	}
	316	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	317	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	318	gic_spi[uart_intr[i]]);
	319	}
6fdf3282 AF	320
	321	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	322	&error_abort);
	323	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	324	if (err) {
	325	error_propagate(errp, err);
	326	return;
	327	}
	328
	329	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	330	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	331
33108e9f SPB	332	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
eb4f566b PM	333	char *bus_name;
eb4f566b PM	334
33108e9f SPB	335	object_property_set_bool(OBJECT(&s->sdhci[i]), true,
	336	"realized", &err);
	337	if (err) {
	338	error_propagate(errp, err);
	339	return;
	340	}
	341	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	342	sdhci_addr[i]);
	343	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	344	gic_spi[sdhci_intr[i]]);
eb4f566b PM	345	/* Alias controller SD bus to the SoC itself */
	346	bus_name = g_strdup_printf("sd-bus%d", i);
	347	object_property_add_alias(OBJECT(s), bus_name,
	348	OBJECT(&s->sdhci[i]), "sd-bus",
	349	&error_abort);
	350	g_free(bus_name);
33108e9f	351	}
02d07eb4 AF	352
	353	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	354	gchar *bus_name;
	355
	356	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	357
	358	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	359	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	360	gic_spi[spi_intr[i]]);
	361
	362	/* Alias controller SPI bus to the SoC itself */
	363	bus_name = g_strdup_printf("spi%d", i);
	364	object_property_add_alias(OBJECT(s), bus_name,
	365	OBJECT(&s->spi[i]), "spi0",
	366	&error_abort);
	367	g_free(bus_name);
	368	}
f0a902f7 PC	369	}
f0a902f7 PC	370
6396a193 PC	371	static Property xlnx_zynqmp_props[] = {
	372	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
	373	DEFINE_PROP_END_OF_LIST()
	374	};
	375
f0a902f7 PC	376	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	377	{
	378	DeviceClass *dc = DEVICE_CLASS(oc);
	379
6396a193	380	dc->props = xlnx_zynqmp_props;
f0a902f7	381	dc->realize = xlnx_zynqmp_realize;
4c315c27 MA	382
	383	/*
	384	* Reason: creates an ARM CPU, thus use after free(), see
	385	* arm_cpu_class_init()
	386	*/
	387	dc->cannot_destroy_with_object_finalize_yet = true;
f0a902f7 PC	388	}
	389
	390	static const TypeInfo xlnx_zynqmp_type_info = {
	391	.name = TYPE_XLNX_ZYNQMP,
	392	.parent = TYPE_DEVICE,
	393	.instance_size = sizeof(XlnxZynqMPState),
	394	.instance_init = xlnx_zynqmp_init,
	395	.class_init = xlnx_zynqmp_class_init,
	396	};
	397
	398	static void xlnx_zynqmp_register_types(void)
	399	{
	400	type_register_static(&xlnx_zynqmp_type_info);
	401	}
	402
	403	type_init(xlnx_zynqmp_register_types)