[mirror_qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GEM_REVISION        0x40070106

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

#define DP_ADDR             0xfd4a0000
#define DP_IRQ              113

#define DPDMA_ADDR          0xfd4c0000
#define DPDMA_IRQ           116

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
    0xFF040000, 0xFF050000,
};

static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
    19, 20,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
                                   Error **errp)
{
    Error *err = NULL;
    int i;

    for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
        char *name;

        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(OBJECT(s), "rpu-cpu[*]",
                                  OBJECT(&s->rpu_cpu[i]), &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
                             (Object **)&s->ddr_ram,
                             qdev_prop_allow_set_link_before_realize,
                             OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);

    object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          TYPE_XILINX_SPIPS);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }

    object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
    qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());

    object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
    qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);

    /* Realize APUs before realizing the GIC. KVM requires this.  */
    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 s->secure, "has_el3", NULL);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 false, "has_el2", NULL);
        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
        qemu_irq irq;

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    if (s->has_rpu) {
        xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
                                &error_abort);
        object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
                                &error_abort);
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        char *bus_name;

        object_property_set_bool(OBJECT(&s->sdhci[i]), true,
                                 "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                        sdhci_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                           gic_spi[sdhci_intr[i]]);
        /* Alias controller SD bus to the SoC itself */
        bus_name = g_strdup_printf("sd-bus%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->sdhci[i]), "sd-bus",
                                  &error_abort);
        g_free(bus_name);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        gchar *bus_name;

        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           gic_spi[spi_intr[i]]);

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi0",
                                  &error_abort);
        g_free(bus_name);
    }

    object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);

    object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
                             &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
    DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
4771d756 PB	20	#include "qemu-common.h"
4771d756 PB	21	#include "cpu.h"
f0a902f7	22	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	23	#include "hw/intc/arm_gic_common.h"
7729e1f4	24	#include "exec/address-spaces.h"
2a0ee672 EI	25	#include "sysemu/kvm.h"
2a0ee672 EI	26	#include "kvm_arm.h"
7729e1f4 PC	27
	28	#define GIC_NUM_SPI_INTR 160
	29
bf4cb109 PC	30	#define ARM_PHYS_TIMER_PPI 30
	31	#define ARM_VIRT_TIMER_PPI 27
	32
20bff213 AF	33	#define GEM_REVISION 0x40070106
20bff213 AF	34
7729e1f4 PC	35	#define GIC_BASE_ADDR 0xf9000000
	36	#define GIC_DIST_ADDR 0xf9010000
	37	#define GIC_CPU_ADDR 0xf9020000
	38
6fdf3282 AF	39	#define SATA_INTR 133
	40	#define SATA_ADDR 0xFD0C0000
	41	#define SATA_NUM_PORTS 2
	42
b93dbcdd FK	43	#define DP_ADDR 0xfd4a0000
	44	#define DP_IRQ 113
	45
	46	#define DPDMA_ADDR 0xfd4c0000
	47	#define DPDMA_IRQ 116
	48
14ca2e46 PC	49	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	50	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	51	};
	52
	53	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	54	57, 59, 61, 63,
	55	};
	56
3bade2a9 PC	57	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	58	0xFF000000, 0xFF010000,
	59	};
	60
	61	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	62	21, 22,
	63	};
	64
33108e9f SPB	65	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	66	0xFF160000, 0xFF170000,
	67	};
	68
	69	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	70	48, 49,
	71	};
	72
02d07eb4 AF	73	static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
	74	0xFF040000, 0xFF050000,
	75	};
	76
	77	static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
	78	19, 20,
	79	};
	80
7729e1f4 PC	81	typedef struct XlnxZynqMPGICRegion {
	82	int region_index;
	83	uint32_t address;
	84	} XlnxZynqMPGICRegion;
	85
	86	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	87	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	88	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	89	};
f0a902f7	90
bf4cb109 PC	91	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	92	{
	93	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	94	}
	95
6ed92b14 EI	96	static void xlnx_zynqmp_create_rpu(XlnxZynqMPState s, const char boot_cpu,
	97	Error **errp)
	98	{
	99	Error *err = NULL;
	100	int i;
	101
	102	for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) {
	103	char *name;
	104
	105	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	106	"cortex-r5-" TYPE_ARM_CPU);
	107	object_property_add_child(OBJECT(s), "rpu-cpu[*]",
	108	OBJECT(&s->rpu_cpu[i]), &error_abort);
	109
	110	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	111	if (strcmp(name, boot_cpu)) {
	112	/* Secondary CPUs start in PSCI powered-down state */
	113	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	114	"start-powered-off", &error_abort);
	115	} else {
	116	s->boot_cpu_ptr = &s->rpu_cpu[i];
	117	}
	118	g_free(name);
	119
	120	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
	121	&error_abort);
	122	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	123	&err);
	124	if (err) {
	125	error_propagate(errp, err);
	126	return;
	127	}
	128	}
	129	}
	130
f0a902f7 PC	131	static void xlnx_zynqmp_init(Object *obj)
	132	{
	133	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	134	int i;
	135
2e5577bc PC	136	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
2e5577bc PC	137	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	138	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	139	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	140	&error_abort);
f0a902f7 PC	141	}
7729e1f4	142
dc3b89ef AF	143	object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION,
	144	(Object **)&s->ddr_ram,
	145	qdev_prop_allow_set_link_before_realize,
	146	OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
	147
2a0ee672	148	object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
7729e1f4	149	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	150
	151	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	152	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	153	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	154	}
3bade2a9 PC	155
	156	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	157	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	158	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	159	}
6fdf3282 AF	160
	161	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	162	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	163
	164	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	165	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	166	TYPE_SYSBUS_SDHCI);
	167	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	168	sysbus_get_default());
	169	}
02d07eb4 AF	170
	171	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	172	object_initialize(&s->spi[i], sizeof(s->spi[i]),
	173	TYPE_XILINX_SPIPS);
	174	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
	175	}
b93dbcdd FK	176
	177	object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
	178	qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
	179
	180	object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
	181	qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
f0a902f7 PC	182	}
	183
	184	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	185	{
	186	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	187	MemoryRegion *system_memory = get_system_memory();
f0a902f7	188	uint8_t i;
dc3b89ef	189	uint64_t ram_size;
6396a193	190	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	191	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	192	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	193	Error *err = NULL;
f0a902f7 PC	194
dc3b89ef AF	195	ram_size = memory_region_size(s->ddr_ram);
	196
	197	/* Create the DDR Memory Regions. User friendly checks should happen at
	198	* the board level
	199	*/
	200	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	201	/* The RAM size is above the maximum available for the low DDR.
	202	* Create the high DDR memory region as well.
	203	*/
	204	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	205	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	206	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	207
	208	memory_region_init_alias(&s->ddr_ram_high, NULL,
	209	"ddr-ram-high", s->ddr_ram,
	210	ddr_low_size, ddr_high_size);
	211	memory_region_add_subregion(get_system_memory(),
	212	XLNX_ZYNQMP_HIGH_RAM_START,
	213	&s->ddr_ram_high);
	214	} else {
	215	/* RAM must be non-zero */
	216	assert(ram_size);
	217	ddr_low_size = ram_size;
	218	}
	219
	220	memory_region_init_alias(&s->ddr_ram_low, NULL,
	221	"ddr-ram-low", s->ddr_ram,
	222	0, ddr_low_size);
	223	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	224
6675d719 AF	225	/* Create the four OCM banks */
	226	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	227	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	228
98a99ce0	229	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	230	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	231	memory_region_add_subregion(get_system_memory(),
	232	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	233	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	234	&s->ocm_ram[i]);
	235
	236	g_free(ocm_name);
	237	}
	238
7729e1f4 PC	239	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	240	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
2e5577bc	241	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS);
7729e1f4	242
0776d967	243	/* Realize APUs before realizing the GIC. KVM requires this. */
2e5577bc	244	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
6396a193	245	char *name;
bf4cb109	246
2e5577bc	247	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	248	"psci-conduit", &error_abort);
6396a193 PC	249
	250	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	251	if (strcmp(name, boot_cpu)) {
f0a902f7	252	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	253	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	254	"start-powered-off", &error_abort);
6396a193 PC	255	} else {
6396a193 PC	256	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	257	}
5348c62c	258	g_free(name);
f0a902f7	259
37d42473 EI	260	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
37d42473 EI	261	s->secure, "has_el3", NULL);
c25bd18a PM	262	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
c25bd18a PM	263	false, "has_el2", NULL);
2e5577bc	264	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	265	"reset-cbar", &error_abort);
2e5577bc PC	266	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	267	&err);
f0a902f7	268	if (err) {
24cfc8dc	269	error_propagate(errp, err);
f0a902f7 PC	270	return;
f0a902f7 PC	271	}
0776d967 EI	272	}
	273
	274	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
	275	if (err) {
	276	error_propagate(errp, err);
	277	return;
	278	}
	279
	280	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	281	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	282	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	283	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	284	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	285	uint32_t addr = r->address;
	286	int j;
	287
	288	sysbus_mmio_map(gic, r->region_index, addr);
	289
	290	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	291	MemoryRegion *alias = &s->gic_mr[i][j];
	292
	293	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	294	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	295	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	296	memory_region_add_subregion(system_memory, addr, alias);
	297	}
	298	}
	299
	300	for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
	301	qemu_irq irq;
7729e1f4 PC	302
7729e1f4 PC	303	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	304	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	305	ARM_CPU_IRQ));
bf4cb109 PC	306	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	307	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	308	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	309	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	310	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	311	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	312	}
14ca2e46	313
6ed92b14 EI	314	if (s->has_rpu) {
6ed92b14 EI	315	xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
b58850e7	316	if (err) {
24cfc8dc	317	error_propagate(errp, err);
b58850e7 PC	318	return;
	319	}
	320	}
	321
6396a193	322	if (!s->boot_cpu_ptr) {
9af9e0fe	323	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	324	return;
	325	}
	326
14ca2e46 PC	327	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	328	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	329	}
	330
	331	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	332	NICInfo *nd = &nd_table[i];
	333
	334	if (nd->used) {
	335	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	336	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	337	}
20bff213 AF	338	object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
20bff213 AF	339	&error_abort);
1372fc0b	340	object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
20bff213	341	&error_abort);
14ca2e46 PC	342	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
14ca2e46 PC	343	if (err) {
24cfc8dc	344	error_propagate(errp, err);
14ca2e46 PC	345	return;
	346	}
	347	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	348	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	349	gic_spi[gem_intr[i]]);
	350	}
3bade2a9 PC	351
3bade2a9 PC	352	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
4be12ea0	353	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
3bade2a9 PC	354	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
3bade2a9 PC	355	if (err) {
24cfc8dc	356	error_propagate(errp, err);
3bade2a9 PC	357	return;
	358	}
	359	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	360	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	361	gic_spi[uart_intr[i]]);
	362	}
6fdf3282 AF	363
	364	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	365	&error_abort);
	366	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	367	if (err) {
	368	error_propagate(errp, err);
	369	return;
	370	}
	371
	372	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	373	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	374
33108e9f SPB	375	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
eb4f566b PM	376	char *bus_name;
eb4f566b PM	377
33108e9f SPB	378	object_property_set_bool(OBJECT(&s->sdhci[i]), true,
	379	"realized", &err);
	380	if (err) {
	381	error_propagate(errp, err);
	382	return;
	383	}
	384	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	385	sdhci_addr[i]);
	386	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	387	gic_spi[sdhci_intr[i]]);
eb4f566b PM	388	/* Alias controller SD bus to the SoC itself */
	389	bus_name = g_strdup_printf("sd-bus%d", i);
	390	object_property_add_alias(OBJECT(s), bus_name,
	391	OBJECT(&s->sdhci[i]), "sd-bus",
	392	&error_abort);
	393	g_free(bus_name);
33108e9f	394	}
02d07eb4 AF	395
	396	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	397	gchar *bus_name;
	398
	399	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	400
	401	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	402	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	403	gic_spi[spi_intr[i]]);
	404
	405	/* Alias controller SPI bus to the SoC itself */
	406	bus_name = g_strdup_printf("spi%d", i);
	407	object_property_add_alias(OBJECT(s), bus_name,
	408	OBJECT(&s->spi[i]), "spi0",
	409	&error_abort);
b93dbcdd FK	410	g_free(bus_name);
	411	}
	412
	413	object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
	414	if (err) {
	415	error_propagate(errp, err);
	416	return;
	417	}
	418	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
	419	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
	420
	421	object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
	422	if (err) {
	423	error_propagate(errp, err);
	424	return;
02d07eb4	425	}
b93dbcdd FK	426	object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
	427	&error_abort);
	428	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
	429	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
f0a902f7 PC	430	}
f0a902f7 PC	431
6396a193 PC	432	static Property xlnx_zynqmp_props[] = {
6396a193 PC	433	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
37d42473	434	DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
6ed92b14	435	DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
6396a193 PC	436	DEFINE_PROP_END_OF_LIST()
	437	};
	438
f0a902f7 PC	439	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	440	{
	441	DeviceClass *dc = DEVICE_CLASS(oc);
	442
6396a193	443	dc->props = xlnx_zynqmp_props;
f0a902f7 PC	444	dc->realize = xlnx_zynqmp_realize;
	445	}
	446
	447	static const TypeInfo xlnx_zynqmp_type_info = {
	448	.name = TYPE_XLNX_ZYNQMP,
	449	.parent = TYPE_DEVICE,
	450	.instance_size = sizeof(XlnxZynqMPState),
	451	.instance_init = xlnx_zynqmp_init,
	452	.class_init = xlnx_zynqmp_class_init,
	453	};
	454
	455	static void xlnx_zynqmp_register_types(void)
	456	{
	457	type_register_static(&xlnx_zynqmp_type_info);
	458	}
	459
	460	type_init(xlnx_zynqmp_register_types)