[mirror_qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GEM_REVISION        0x40070106

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

#define QSPI_ADDR           0xff0f0000
#define LQSPI_ADDR          0xc0000000
#define QSPI_IRQ            15

#define DP_ADDR             0xfd4a0000
#define DP_IRQ              113

#define DPDMA_ADDR          0xfd4c0000
#define DPDMA_IRQ           116

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
    0xFF040000, 0xFF050000,
};

static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
    19, 20,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
                                   Error **errp)
{
    Error *err = NULL;
    int i;
    int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);

    for (i = 0; i < num_rpus; i++) {
        char *name;

        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(OBJECT(s), "rpu-cpu[*]",
                                  OBJECT(&s->rpu_cpu[i]), &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;
    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);

    for (i = 0; i < num_apus; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          TYPE_XILINX_SPIPS);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }

    object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
    qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());

    object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
    qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());

    object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
    qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);

    /* Realize APUs before realizing the GIC. KVM requires this.  */
    for (i = 0; i < num_apus; i++) {
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 s->secure, "has_el3", NULL);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 s->virt, "has_el2", NULL);
        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < num_apus; i++) {
        qemu_irq irq;

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    if (s->has_rpu) {
        info_report("The 'has_rpu' property is no longer required, to use the "
                    "RPUs just use -smp 6.");
    }

    xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
                                &error_abort);
        object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
                                &error_abort);
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        char *bus_name;

        object_property_set_bool(OBJECT(&s->sdhci[i]), true,
                                 "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                        sdhci_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
                           gic_spi[sdhci_intr[i]]);
        /* Alias controller SD bus to the SoC itself */
        bus_name = g_strdup_printf("sd-bus%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->sdhci[i]), "sd-bus",
                                  &error_abort);
        g_free(bus_name);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        gchar *bus_name;

        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           gic_spi[spi_intr[i]]);

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi0",
                                  &error_abort);
        g_free(bus_name);
    }

    object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
        gchar *bus_name;
        gchar *target_bus;

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("qspi%d", i);
        target_bus = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->qspi), target_bus,
                                  &error_abort);
        g_free(bus_name);
        g_free(target_bus);
    }

    object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);

    object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
                             &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
    DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
    DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
    DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;
    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
    dc->user_creatable = false;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
4771d756 PB	20	#include "qemu-common.h"
4771d756 PB	21	#include "cpu.h"
f0a902f7	22	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	23	#include "hw/intc/arm_gic_common.h"
7729e1f4	24	#include "exec/address-spaces.h"
2a0ee672 EI	25	#include "sysemu/kvm.h"
2a0ee672 EI	26	#include "kvm_arm.h"
7729e1f4 PC	27
	28	#define GIC_NUM_SPI_INTR 160
	29
bf4cb109 PC	30	#define ARM_PHYS_TIMER_PPI 30
	31	#define ARM_VIRT_TIMER_PPI 27
	32
20bff213 AF	33	#define GEM_REVISION 0x40070106
20bff213 AF	34
7729e1f4 PC	35	#define GIC_BASE_ADDR 0xf9000000
	36	#define GIC_DIST_ADDR 0xf9010000
	37	#define GIC_CPU_ADDR 0xf9020000
	38
6fdf3282 AF	39	#define SATA_INTR 133
	40	#define SATA_ADDR 0xFD0C0000
	41	#define SATA_NUM_PORTS 2
	42
babc1f30 FI	43	#define QSPI_ADDR 0xff0f0000
	44	#define LQSPI_ADDR 0xc0000000
	45	#define QSPI_IRQ 15
	46
b93dbcdd FK	47	#define DP_ADDR 0xfd4a0000
	48	#define DP_IRQ 113
	49
	50	#define DPDMA_ADDR 0xfd4c0000
	51	#define DPDMA_IRQ 116
	52
14ca2e46 PC	53	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	54	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	55	};
	56
	57	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	58	57, 59, 61, 63,
	59	};
	60
3bade2a9 PC	61	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	62	0xFF000000, 0xFF010000,
	63	};
	64
	65	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	66	21, 22,
	67	};
	68
33108e9f SPB	69	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	70	0xFF160000, 0xFF170000,
	71	};
	72
	73	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	74	48, 49,
	75	};
	76
02d07eb4 AF	77	static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
	78	0xFF040000, 0xFF050000,
	79	};
	80
	81	static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
	82	19, 20,
	83	};
	84
7729e1f4 PC	85	typedef struct XlnxZynqMPGICRegion {
	86	int region_index;
	87	uint32_t address;
	88	} XlnxZynqMPGICRegion;
	89
	90	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	91	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	92	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	93	};
f0a902f7	94
bf4cb109 PC	95	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	96	{
	97	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	98	}
	99
6ed92b14 EI	100	static void xlnx_zynqmp_create_rpu(XlnxZynqMPState s, const char boot_cpu,
	101	Error **errp)
	102	{
	103	Error *err = NULL;
	104	int i;
6908ec44	105	int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
6ed92b14	106
6908ec44	107	for (i = 0; i < num_rpus; i++) {
6ed92b14 EI	108	char *name;
	109
	110	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	111	"cortex-r5-" TYPE_ARM_CPU);
	112	object_property_add_child(OBJECT(s), "rpu-cpu[*]",
	113	OBJECT(&s->rpu_cpu[i]), &error_abort);
	114
	115	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	116	if (strcmp(name, boot_cpu)) {
	117	/* Secondary CPUs start in PSCI powered-down state */
	118	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	119	"start-powered-off", &error_abort);
	120	} else {
	121	s->boot_cpu_ptr = &s->rpu_cpu[i];
	122	}
	123	g_free(name);
	124
	125	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
	126	&error_abort);
	127	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	128	&err);
	129	if (err) {
	130	error_propagate(errp, err);
	131	return;
	132	}
	133	}
	134	}
	135
f0a902f7 PC	136	static void xlnx_zynqmp_init(Object *obj)
	137	{
	138	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	139	int i;
6908ec44	140	int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
f0a902f7	141
6908ec44	142	for (i = 0; i < num_apus; i++) {
2e5577bc	143	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	144	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	145	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	146	&error_abort);
f0a902f7 PC	147	}
7729e1f4	148
2a0ee672	149	object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
7729e1f4	150	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	151
	152	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	153	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	154	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	155	}
3bade2a9 PC	156
	157	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	158	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	159	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	160	}
6fdf3282 AF	161
	162	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	163	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	164
	165	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	166	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	167	TYPE_SYSBUS_SDHCI);
	168	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	169	sysbus_get_default());
	170	}
02d07eb4 AF	171
	172	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	173	object_initialize(&s->spi[i], sizeof(s->spi[i]),
	174	TYPE_XILINX_SPIPS);
	175	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
	176	}
b93dbcdd	177
babc1f30 FI	178	object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
	179	qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());
	180
b93dbcdd FK	181	object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
	182	qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
	183
	184	object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
	185	qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
f0a902f7 PC	186	}
	187
	188	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	189	{
	190	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	191	MemoryRegion *system_memory = get_system_memory();
f0a902f7	192	uint8_t i;
dc3b89ef	193	uint64_t ram_size;
6908ec44	194	int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
6396a193	195	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	196	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	197	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	198	Error *err = NULL;
f0a902f7 PC	199
dc3b89ef AF	200	ram_size = memory_region_size(s->ddr_ram);
	201
	202	/* Create the DDR Memory Regions. User friendly checks should happen at
	203	* the board level
	204	*/
	205	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	206	/* The RAM size is above the maximum available for the low DDR.
	207	* Create the high DDR memory region as well.
	208	*/
	209	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	210	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	211	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	212
	213	memory_region_init_alias(&s->ddr_ram_high, NULL,
	214	"ddr-ram-high", s->ddr_ram,
	215	ddr_low_size, ddr_high_size);
	216	memory_region_add_subregion(get_system_memory(),
	217	XLNX_ZYNQMP_HIGH_RAM_START,
	218	&s->ddr_ram_high);
	219	} else {
	220	/* RAM must be non-zero */
	221	assert(ram_size);
	222	ddr_low_size = ram_size;
	223	}
	224
	225	memory_region_init_alias(&s->ddr_ram_low, NULL,
	226	"ddr-ram-low", s->ddr_ram,
	227	0, ddr_low_size);
	228	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	229
6675d719 AF	230	/* Create the four OCM banks */
	231	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	232	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	233
98a99ce0	234	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	235	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	236	memory_region_add_subregion(get_system_memory(),
	237	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	238	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	239	&s->ocm_ram[i]);
	240
	241	g_free(ocm_name);
	242	}
	243
7729e1f4 PC	244	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	245	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
6908ec44	246	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
7729e1f4	247
0776d967	248	/* Realize APUs before realizing the GIC. KVM requires this. */
6908ec44	249	for (i = 0; i < num_apus; i++) {
6396a193	250	char *name;
bf4cb109	251
2e5577bc	252	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	253	"psci-conduit", &error_abort);
6396a193 PC	254
	255	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	256	if (strcmp(name, boot_cpu)) {
f0a902f7	257	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	258	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	259	"start-powered-off", &error_abort);
6396a193 PC	260	} else {
6396a193 PC	261	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	262	}
5348c62c	263	g_free(name);
f0a902f7	264
37d42473 EI	265	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
37d42473 EI	266	s->secure, "has_el3", NULL);
c25bd18a	267	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
1946809e	268	s->virt, "has_el2", NULL);
2e5577bc	269	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	270	"reset-cbar", &error_abort);
2e5577bc PC	271	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	272	&err);
f0a902f7	273	if (err) {
24cfc8dc	274	error_propagate(errp, err);
f0a902f7 PC	275	return;
f0a902f7 PC	276	}
0776d967 EI	277	}
	278
	279	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
	280	if (err) {
	281	error_propagate(errp, err);
	282	return;
	283	}
	284
	285	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	286	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	287	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	288	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	289	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	290	uint32_t addr = r->address;
	291	int j;
	292
	293	sysbus_mmio_map(gic, r->region_index, addr);
	294
	295	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	296	MemoryRegion *alias = &s->gic_mr[i][j];
	297
	298	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	299	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	300	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	301	memory_region_add_subregion(system_memory, addr, alias);
	302	}
	303	}
	304
6908ec44	305	for (i = 0; i < num_apus; i++) {
0776d967	306	qemu_irq irq;
7729e1f4 PC	307
7729e1f4 PC	308	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	309	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	310	ARM_CPU_IRQ));
bf4cb109 PC	311	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	312	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	313	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	314	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	315	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	316	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	317	}
14ca2e46	318
6ed92b14	319	if (s->has_rpu) {
6908ec44 AF	320	info_report("The 'has_rpu' property is no longer required, to use the "
	321	"RPUs just use -smp 6.");
	322	}
	323
	324	xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
	325	if (err) {
	326	error_propagate(errp, err);
	327	return;
b58850e7 PC	328	}
b58850e7 PC	329
6396a193	330	if (!s->boot_cpu_ptr) {
9af9e0fe	331	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	332	return;
	333	}
	334
14ca2e46 PC	335	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	336	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	337	}
	338
	339	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	340	NICInfo *nd = &nd_table[i];
	341
	342	if (nd->used) {
	343	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	344	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	345	}
20bff213 AF	346	object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
20bff213 AF	347	&error_abort);
1372fc0b	348	object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
20bff213	349	&error_abort);
14ca2e46 PC	350	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
14ca2e46 PC	351	if (err) {
24cfc8dc	352	error_propagate(errp, err);
14ca2e46 PC	353	return;
	354	}
	355	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	356	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	357	gic_spi[gem_intr[i]]);
	358	}
3bade2a9 PC	359
3bade2a9 PC	360	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
4be12ea0	361	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
3bade2a9 PC	362	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
3bade2a9 PC	363	if (err) {
24cfc8dc	364	error_propagate(errp, err);
3bade2a9 PC	365	return;
	366	}
	367	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	368	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	369	gic_spi[uart_intr[i]]);
	370	}
6fdf3282 AF	371
	372	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	373	&error_abort);
	374	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	375	if (err) {
	376	error_propagate(errp, err);
	377	return;
	378	}
	379
	380	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	381	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	382
33108e9f SPB	383	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
eb4f566b PM	384	char *bus_name;
eb4f566b PM	385
33108e9f SPB	386	object_property_set_bool(OBJECT(&s->sdhci[i]), true,
	387	"realized", &err);
	388	if (err) {
	389	error_propagate(errp, err);
	390	return;
	391	}
	392	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	393	sdhci_addr[i]);
	394	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
	395	gic_spi[sdhci_intr[i]]);
eb4f566b PM	396	/* Alias controller SD bus to the SoC itself */
	397	bus_name = g_strdup_printf("sd-bus%d", i);
	398	object_property_add_alias(OBJECT(s), bus_name,
	399	OBJECT(&s->sdhci[i]), "sd-bus",
	400	&error_abort);
	401	g_free(bus_name);
33108e9f	402	}
02d07eb4 AF	403
	404	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	405	gchar *bus_name;
	406
	407	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	408
	409	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	410	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	411	gic_spi[spi_intr[i]]);
	412
	413	/* Alias controller SPI bus to the SoC itself */
	414	bus_name = g_strdup_printf("spi%d", i);
	415	object_property_add_alias(OBJECT(s), bus_name,
	416	OBJECT(&s->spi[i]), "spi0",
	417	&error_abort);
b93dbcdd FK	418	g_free(bus_name);
	419	}
	420
babc1f30 FI	421	object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
	422	sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
	423	sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
	424	sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
	425
	426	for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
	427	gchar *bus_name;
	428	gchar *target_bus;
	429
	430	/* Alias controller SPI bus to the SoC itself */
	431	bus_name = g_strdup_printf("qspi%d", i);
	432	target_bus = g_strdup_printf("spi%d", i);
	433	object_property_add_alias(OBJECT(s), bus_name,
	434	OBJECT(&s->qspi), target_bus,
	435	&error_abort);
	436	g_free(bus_name);
	437	g_free(target_bus);
	438	}
	439
b93dbcdd FK	440	object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
	441	if (err) {
	442	error_propagate(errp, err);
	443	return;
	444	}
	445	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
	446	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
	447
	448	object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
	449	if (err) {
	450	error_propagate(errp, err);
	451	return;
02d07eb4	452	}
b93dbcdd FK	453	object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
	454	&error_abort);
	455	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
	456	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
f0a902f7 PC	457	}
f0a902f7 PC	458
6396a193 PC	459	static Property xlnx_zynqmp_props[] = {
6396a193 PC	460	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
37d42473	461	DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
1946809e	462	DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
6ed92b14	463	DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
c3acfa01 FZ	464	DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
c3acfa01 FZ	465	MemoryRegion *),
6396a193 PC	466	DEFINE_PROP_END_OF_LIST()
	467	};
	468
f0a902f7 PC	469	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	470	{
	471	DeviceClass *dc = DEVICE_CLASS(oc);
	472
6396a193	473	dc->props = xlnx_zynqmp_props;
f0a902f7	474	dc->realize = xlnx_zynqmp_realize;
d8589144 TH	475	/* Reason: Uses serial_hds in realize function, thus can't be used twice */
d8589144 TH	476	dc->user_creatable = false;
f0a902f7 PC	477	}
	478
	479	static const TypeInfo xlnx_zynqmp_type_info = {
	480	.name = TYPE_XLNX_ZYNQMP,
	481	.parent = TYPE_DEVICE,
	482	.instance_size = sizeof(XlnxZynqMPState),
	483	.instance_init = xlnx_zynqmp_init,
	484	.class_init = xlnx_zynqmp_class_init,
	485	};
	486
	487	static void xlnx_zynqmp_register_types(void)
	488	{
	489	type_register_static(&xlnx_zynqmp_type_info);
	490	}
	491
	492	type_init(xlnx_zynqmp_register_types)