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Commit | Line | Data |
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5fafdf24 | 1 | /* |
16406950 PB |
2 | * ARM kernel loader. |
3 | * | |
9ee6e8bb | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
16406950 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
16406950 PB |
8 | */ |
9 | ||
412beee6 | 10 | #include "config.h" |
87ecb68b PB |
11 | #include "hw.h" |
12 | #include "arm-misc.h" | |
13 | #include "sysemu.h" | |
412beee6 | 14 | #include "boards.h" |
ca20cf32 BS |
15 | #include "loader.h" |
16 | #include "elf.h" | |
412beee6 | 17 | #include "device_tree.h" |
16406950 PB |
18 | |
19 | #define KERNEL_ARGS_ADDR 0x100 | |
20 | #define KERNEL_LOAD_ADDR 0x00010000 | |
16406950 PB |
21 | |
22 | /* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */ | |
23 | static uint32_t bootloader[] = { | |
24 | 0xe3a00000, /* mov r0, #0 */ | |
f8414cb5 PM |
25 | 0xe59f1004, /* ldr r1, [pc, #4] */ |
26 | 0xe59f2004, /* ldr r2, [pc, #4] */ | |
27 | 0xe59ff004, /* ldr pc, [pc, #4] */ | |
28 | 0, /* Board ID */ | |
16406950 PB |
29 | 0, /* Address of kernel args. Set by integratorcp_init. */ |
30 | 0 /* Kernel entry point. Set by integratorcp_init. */ | |
31 | }; | |
32 | ||
9d5ba9bf ML |
33 | /* Handling for secondary CPU boot in a multicore system. |
34 | * Unlike the uniprocessor/primary CPU boot, this is platform | |
35 | * dependent. The default code here is based on the secondary | |
36 | * CPU boot protocol used on realview/vexpress boards, with | |
37 | * some parameterisation to increase its flexibility. | |
38 | * QEMU platform models for which this code is not appropriate | |
39 | * should override write_secondary_boot and secondary_cpu_reset_hook | |
40 | * instead. | |
41 | * | |
42 | * This code enables the interrupt controllers for the secondary | |
43 | * CPUs and then puts all the secondary CPUs into a loop waiting | |
44 | * for an interprocessor interrupt and polling a configurable | |
45 | * location for the kernel secondary CPU entry point. | |
46 | */ | |
9ee6e8bb | 47 | static uint32_t smpboot[] = { |
96eacf64 | 48 | 0xe59f201c, /* ldr r2, gic_cpu_if */ |
078758d0 EV |
49 | 0xe59f001c, /* ldr r0, startaddr */ |
50 | 0xe3a01001, /* mov r1, #1 */ | |
96eacf64 | 51 | 0xe5821000, /* str r1, [r2] */ |
9ee6e8bb PB |
52 | 0xe320f003, /* wfi */ |
53 | 0xe5901000, /* ldr r1, [r0] */ | |
be0f204a PB |
54 | 0xe1110001, /* tst r1, r1 */ |
55 | 0x0afffffb, /* beq <wfi> */ | |
f7c70325 | 56 | 0xe12fff11, /* bx r1 */ |
96eacf64 | 57 | 0, /* gic_cpu_if: base address of GIC CPU interface */ |
078758d0 | 58 | 0 /* bootreg: Boot register address is held here */ |
9ee6e8bb PB |
59 | }; |
60 | ||
9543b0cd | 61 | static void default_write_secondary(ARMCPU *cpu, |
9d5ba9bf ML |
62 | const struct arm_boot_info *info) |
63 | { | |
64 | int n; | |
65 | smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; | |
96eacf64 | 66 | smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; |
9d5ba9bf ML |
67 | for (n = 0; n < ARRAY_SIZE(smpboot); n++) { |
68 | smpboot[n] = tswap32(smpboot[n]); | |
69 | } | |
70 | rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), | |
71 | info->smp_loader_start); | |
72 | } | |
73 | ||
5d309320 | 74 | static void default_reset_secondary(ARMCPU *cpu, |
9d5ba9bf ML |
75 | const struct arm_boot_info *info) |
76 | { | |
5d309320 AF |
77 | CPUARMState *env = &cpu->env; |
78 | ||
9d5ba9bf ML |
79 | stl_phys_notdirty(info->smp_bootreg_addr, 0); |
80 | env->regs[15] = info->smp_loader_start; | |
81 | } | |
82 | ||
52b43737 PB |
83 | #define WRITE_WORD(p, value) do { \ |
84 | stl_phys_notdirty(p, value); \ | |
85 | p += 4; \ | |
86 | } while (0) | |
87 | ||
761c9eb0 | 88 | static void set_kernel_args(const struct arm_boot_info *info) |
16406950 | 89 | { |
761c9eb0 | 90 | int initrd_size = info->initrd_size; |
a8170e5e AK |
91 | hwaddr base = info->loader_start; |
92 | hwaddr p; | |
16406950 | 93 | |
52b43737 | 94 | p = base + KERNEL_ARGS_ADDR; |
16406950 | 95 | /* ATAG_CORE */ |
52b43737 PB |
96 | WRITE_WORD(p, 5); |
97 | WRITE_WORD(p, 0x54410001); | |
98 | WRITE_WORD(p, 1); | |
99 | WRITE_WORD(p, 0x1000); | |
100 | WRITE_WORD(p, 0); | |
16406950 | 101 | /* ATAG_MEM */ |
f93eb9ff | 102 | /* TODO: handle multiple chips on one ATAG list */ |
52b43737 PB |
103 | WRITE_WORD(p, 4); |
104 | WRITE_WORD(p, 0x54410002); | |
105 | WRITE_WORD(p, info->ram_size); | |
106 | WRITE_WORD(p, info->loader_start); | |
16406950 PB |
107 | if (initrd_size) { |
108 | /* ATAG_INITRD2 */ | |
52b43737 PB |
109 | WRITE_WORD(p, 4); |
110 | WRITE_WORD(p, 0x54420005); | |
fc53b7d4 | 111 | WRITE_WORD(p, info->initrd_start); |
52b43737 | 112 | WRITE_WORD(p, initrd_size); |
16406950 | 113 | } |
f93eb9ff | 114 | if (info->kernel_cmdline && *info->kernel_cmdline) { |
16406950 PB |
115 | /* ATAG_CMDLINE */ |
116 | int cmdline_size; | |
117 | ||
f93eb9ff | 118 | cmdline_size = strlen(info->kernel_cmdline); |
52b43737 PB |
119 | cpu_physical_memory_write(p + 8, (void *)info->kernel_cmdline, |
120 | cmdline_size + 1); | |
16406950 | 121 | cmdline_size = (cmdline_size >> 2) + 1; |
52b43737 PB |
122 | WRITE_WORD(p, cmdline_size + 2); |
123 | WRITE_WORD(p, 0x54410009); | |
124 | p += cmdline_size * 4; | |
16406950 | 125 | } |
f93eb9ff AZ |
126 | if (info->atag_board) { |
127 | /* ATAG_BOARD */ | |
128 | int atag_board_len; | |
52b43737 | 129 | uint8_t atag_board_buf[0x1000]; |
f93eb9ff | 130 | |
52b43737 PB |
131 | atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3; |
132 | WRITE_WORD(p, (atag_board_len + 8) >> 2); | |
133 | WRITE_WORD(p, 0x414f4d50); | |
134 | cpu_physical_memory_write(p, atag_board_buf, atag_board_len); | |
f93eb9ff AZ |
135 | p += atag_board_len; |
136 | } | |
16406950 | 137 | /* ATAG_END */ |
52b43737 PB |
138 | WRITE_WORD(p, 0); |
139 | WRITE_WORD(p, 0); | |
16406950 PB |
140 | } |
141 | ||
761c9eb0 | 142 | static void set_kernel_args_old(const struct arm_boot_info *info) |
2b8f2d41 | 143 | { |
a8170e5e | 144 | hwaddr p; |
52b43737 | 145 | const char *s; |
761c9eb0 | 146 | int initrd_size = info->initrd_size; |
a8170e5e | 147 | hwaddr base = info->loader_start; |
2b8f2d41 AZ |
148 | |
149 | /* see linux/include/asm-arm/setup.h */ | |
52b43737 | 150 | p = base + KERNEL_ARGS_ADDR; |
2b8f2d41 | 151 | /* page_size */ |
52b43737 | 152 | WRITE_WORD(p, 4096); |
2b8f2d41 | 153 | /* nr_pages */ |
52b43737 | 154 | WRITE_WORD(p, info->ram_size / 4096); |
2b8f2d41 | 155 | /* ramdisk_size */ |
52b43737 | 156 | WRITE_WORD(p, 0); |
2b8f2d41 AZ |
157 | #define FLAG_READONLY 1 |
158 | #define FLAG_RDLOAD 4 | |
159 | #define FLAG_RDPROMPT 8 | |
160 | /* flags */ | |
52b43737 | 161 | WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT); |
2b8f2d41 | 162 | /* rootdev */ |
52b43737 | 163 | WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */ |
2b8f2d41 | 164 | /* video_num_cols */ |
52b43737 | 165 | WRITE_WORD(p, 0); |
2b8f2d41 | 166 | /* video_num_rows */ |
52b43737 | 167 | WRITE_WORD(p, 0); |
2b8f2d41 | 168 | /* video_x */ |
52b43737 | 169 | WRITE_WORD(p, 0); |
2b8f2d41 | 170 | /* video_y */ |
52b43737 | 171 | WRITE_WORD(p, 0); |
2b8f2d41 | 172 | /* memc_control_reg */ |
52b43737 | 173 | WRITE_WORD(p, 0); |
2b8f2d41 AZ |
174 | /* unsigned char sounddefault */ |
175 | /* unsigned char adfsdrives */ | |
176 | /* unsigned char bytes_per_char_h */ | |
177 | /* unsigned char bytes_per_char_v */ | |
52b43737 | 178 | WRITE_WORD(p, 0); |
2b8f2d41 | 179 | /* pages_in_bank[4] */ |
52b43737 PB |
180 | WRITE_WORD(p, 0); |
181 | WRITE_WORD(p, 0); | |
182 | WRITE_WORD(p, 0); | |
183 | WRITE_WORD(p, 0); | |
2b8f2d41 | 184 | /* pages_in_vram */ |
52b43737 | 185 | WRITE_WORD(p, 0); |
2b8f2d41 | 186 | /* initrd_start */ |
fc53b7d4 PM |
187 | if (initrd_size) { |
188 | WRITE_WORD(p, info->initrd_start); | |
189 | } else { | |
52b43737 | 190 | WRITE_WORD(p, 0); |
fc53b7d4 | 191 | } |
2b8f2d41 | 192 | /* initrd_size */ |
52b43737 | 193 | WRITE_WORD(p, initrd_size); |
2b8f2d41 | 194 | /* rd_start */ |
52b43737 | 195 | WRITE_WORD(p, 0); |
2b8f2d41 | 196 | /* system_rev */ |
52b43737 | 197 | WRITE_WORD(p, 0); |
2b8f2d41 | 198 | /* system_serial_low */ |
52b43737 | 199 | WRITE_WORD(p, 0); |
2b8f2d41 | 200 | /* system_serial_high */ |
52b43737 | 201 | WRITE_WORD(p, 0); |
2b8f2d41 | 202 | /* mem_fclk_21285 */ |
52b43737 | 203 | WRITE_WORD(p, 0); |
2b8f2d41 | 204 | /* zero unused fields */ |
52b43737 PB |
205 | while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) { |
206 | WRITE_WORD(p, 0); | |
207 | } | |
208 | s = info->kernel_cmdline; | |
209 | if (s) { | |
210 | cpu_physical_memory_write(p, (void *)s, strlen(s) + 1); | |
211 | } else { | |
212 | WRITE_WORD(p, 0); | |
213 | } | |
2b8f2d41 AZ |
214 | } |
215 | ||
a8170e5e | 216 | static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo) |
412beee6 GL |
217 | { |
218 | #ifdef CONFIG_FDT | |
9bfa659e PM |
219 | uint32_t *mem_reg_property; |
220 | uint32_t mem_reg_propsize; | |
412beee6 GL |
221 | void *fdt = NULL; |
222 | char *filename; | |
223 | int size, rc; | |
9bfa659e | 224 | uint32_t acells, scells, hival; |
412beee6 GL |
225 | |
226 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); | |
227 | if (!filename) { | |
228 | fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename); | |
229 | return -1; | |
230 | } | |
231 | ||
232 | fdt = load_device_tree(filename, &size); | |
233 | if (!fdt) { | |
234 | fprintf(stderr, "Couldn't open dtb file %s\n", filename); | |
235 | g_free(filename); | |
236 | return -1; | |
237 | } | |
238 | g_free(filename); | |
239 | ||
9bfa659e PM |
240 | acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); |
241 | scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); | |
242 | if (acells == 0 || scells == 0) { | |
243 | fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); | |
244 | return -1; | |
245 | } | |
246 | ||
247 | mem_reg_propsize = acells + scells; | |
248 | mem_reg_property = g_new0(uint32_t, mem_reg_propsize); | |
249 | mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start); | |
250 | hival = cpu_to_be32(binfo->loader_start >> 32); | |
251 | if (acells > 1) { | |
252 | mem_reg_property[acells - 2] = hival; | |
253 | } else if (hival != 0) { | |
254 | fprintf(stderr, "qemu: dtb file not compatible with " | |
255 | "RAM start address > 4GB\n"); | |
256 | exit(1); | |
257 | } | |
258 | mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size); | |
259 | hival = cpu_to_be32(binfo->ram_size >> 32); | |
260 | if (scells > 1) { | |
261 | mem_reg_property[acells + scells - 2] = hival; | |
262 | } else if (hival != 0) { | |
263 | fprintf(stderr, "qemu: dtb file not compatible with " | |
264 | "RAM size > 4GB\n"); | |
265 | exit(1); | |
266 | } | |
267 | ||
412beee6 | 268 | rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
9bfa659e | 269 | mem_reg_propsize * sizeof(uint32_t)); |
412beee6 GL |
270 | if (rc < 0) { |
271 | fprintf(stderr, "couldn't set /memory/reg\n"); | |
272 | } | |
273 | ||
5e87975c PC |
274 | if (binfo->kernel_cmdline && *binfo->kernel_cmdline) { |
275 | rc = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", | |
276 | binfo->kernel_cmdline); | |
277 | if (rc < 0) { | |
278 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
279 | } | |
412beee6 GL |
280 | } |
281 | ||
282 | if (binfo->initrd_size) { | |
283 | rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", | |
fc53b7d4 | 284 | binfo->initrd_start); |
412beee6 GL |
285 | if (rc < 0) { |
286 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | |
287 | } | |
288 | ||
289 | rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", | |
fc53b7d4 | 290 | binfo->initrd_start + binfo->initrd_size); |
412beee6 GL |
291 | if (rc < 0) { |
292 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | |
293 | } | |
294 | } | |
295 | ||
296 | cpu_physical_memory_write(addr, fdt, size); | |
297 | ||
298 | return 0; | |
299 | ||
300 | #else | |
301 | fprintf(stderr, "Device tree requested, " | |
302 | "but qemu was compiled without fdt support\n"); | |
303 | return -1; | |
304 | #endif | |
305 | } | |
306 | ||
6ed221b6 | 307 | static void do_cpu_reset(void *opaque) |
f2d74978 | 308 | { |
351d5666 AF |
309 | ARMCPU *cpu = opaque; |
310 | CPUARMState *env = &cpu->env; | |
462a8bc6 | 311 | const struct arm_boot_info *info = env->boot_info; |
f2d74978 | 312 | |
351d5666 | 313 | cpu_reset(CPU(cpu)); |
f2d74978 PB |
314 | if (info) { |
315 | if (!info->is_linux) { | |
316 | /* Jump to the entry point. */ | |
317 | env->regs[15] = info->entry & 0xfffffffe; | |
318 | env->thumb = info->entry & 1; | |
319 | } else { | |
6ed221b6 AL |
320 | if (env == first_cpu) { |
321 | env->regs[15] = info->loader_start; | |
412beee6 GL |
322 | if (!info->dtb_filename) { |
323 | if (old_param) { | |
324 | set_kernel_args_old(info); | |
325 | } else { | |
326 | set_kernel_args(info); | |
327 | } | |
6ed221b6 | 328 | } |
f2d74978 | 329 | } else { |
5d309320 | 330 | info->secondary_cpu_reset_hook(cpu, info); |
f2d74978 PB |
331 | } |
332 | } | |
333 | } | |
f2d74978 PB |
334 | } |
335 | ||
3aaa8dfa | 336 | void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) |
16406950 | 337 | { |
3aaa8dfa | 338 | CPUARMState *env = &cpu->env; |
16406950 PB |
339 | int kernel_size; |
340 | int initrd_size; | |
341 | int n; | |
1c7b3754 PB |
342 | int is_linux = 0; |
343 | uint64_t elf_entry; | |
a8170e5e | 344 | hwaddr entry; |
ca20cf32 | 345 | int big_endian; |
412beee6 | 346 | QemuOpts *machine_opts; |
16406950 PB |
347 | |
348 | /* Load the kernel. */ | |
f93eb9ff | 349 | if (!info->kernel_filename) { |
16406950 PB |
350 | fprintf(stderr, "Kernel image must be specified\n"); |
351 | exit(1); | |
352 | } | |
daf90626 | 353 | |
412beee6 GL |
354 | machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); |
355 | if (machine_opts) { | |
356 | info->dtb_filename = qemu_opt_get(machine_opts, "dtb"); | |
357 | } else { | |
358 | info->dtb_filename = NULL; | |
359 | } | |
360 | ||
9d5ba9bf ML |
361 | if (!info->secondary_cpu_reset_hook) { |
362 | info->secondary_cpu_reset_hook = default_reset_secondary; | |
363 | } | |
364 | if (!info->write_secondary_boot) { | |
365 | info->write_secondary_boot = default_write_secondary; | |
366 | } | |
367 | ||
f2d74978 PB |
368 | if (info->nb_cpus == 0) |
369 | info->nb_cpus = 1; | |
f93eb9ff | 370 | |
ca20cf32 BS |
371 | #ifdef TARGET_WORDS_BIGENDIAN |
372 | big_endian = 1; | |
373 | #else | |
374 | big_endian = 0; | |
375 | #endif | |
376 | ||
fc53b7d4 PM |
377 | /* We want to put the initrd far enough into RAM that when the |
378 | * kernel is uncompressed it will not clobber the initrd. However | |
379 | * on boards without much RAM we must ensure that we still leave | |
380 | * enough room for a decent sized initrd, and on boards with large | |
381 | * amounts of RAM we must avoid the initrd being so far up in RAM | |
382 | * that it is outside lowmem and inaccessible to the kernel. | |
383 | * So for boards with less than 256MB of RAM we put the initrd | |
384 | * halfway into RAM, and for boards with 256MB of RAM or more we put | |
385 | * the initrd at 128MB. | |
386 | */ | |
387 | info->initrd_start = info->loader_start + | |
388 | MIN(info->ram_size / 2, 128 * 1024 * 1024); | |
389 | ||
1c7b3754 | 390 | /* Assume that raw images are linux kernels, and ELF images are not. */ |
409dbce5 AJ |
391 | kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry, |
392 | NULL, NULL, big_endian, ELF_MACHINE, 1); | |
1c7b3754 PB |
393 | entry = elf_entry; |
394 | if (kernel_size < 0) { | |
5a9154e0 AL |
395 | kernel_size = load_uimage(info->kernel_filename, &entry, NULL, |
396 | &is_linux); | |
1c7b3754 PB |
397 | } |
398 | if (kernel_size < 0) { | |
f93eb9ff | 399 | entry = info->loader_start + KERNEL_LOAD_ADDR; |
3b760e04 | 400 | kernel_size = load_image_targphys(info->kernel_filename, entry, |
0b944384 | 401 | info->ram_size - KERNEL_LOAD_ADDR); |
1c7b3754 PB |
402 | is_linux = 1; |
403 | } | |
404 | if (kernel_size < 0) { | |
f93eb9ff AZ |
405 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
406 | info->kernel_filename); | |
1c7b3754 PB |
407 | exit(1); |
408 | } | |
f2d74978 PB |
409 | info->entry = entry; |
410 | if (is_linux) { | |
f93eb9ff | 411 | if (info->initrd_filename) { |
3b760e04 | 412 | initrd_size = load_image_targphys(info->initrd_filename, |
fc53b7d4 PM |
413 | info->initrd_start, |
414 | info->ram_size - | |
415 | info->initrd_start); | |
daf90626 PB |
416 | if (initrd_size < 0) { |
417 | fprintf(stderr, "qemu: could not load initrd '%s'\n", | |
f93eb9ff | 418 | info->initrd_filename); |
daf90626 PB |
419 | exit(1); |
420 | } | |
421 | } else { | |
422 | initrd_size = 0; | |
423 | } | |
412beee6 GL |
424 | info->initrd_size = initrd_size; |
425 | ||
f8414cb5 | 426 | bootloader[4] = info->board_id; |
412beee6 GL |
427 | |
428 | /* for device tree boot, we pass the DTB directly in r2. Otherwise | |
429 | * we point to the kernel args. | |
430 | */ | |
431 | if (info->dtb_filename) { | |
432 | /* Place the DTB after the initrd in memory */ | |
fc53b7d4 PM |
433 | hwaddr dtb_start = TARGET_PAGE_ALIGN(info->initrd_start + |
434 | initrd_size); | |
412beee6 GL |
435 | if (load_dtb(dtb_start, info)) { |
436 | exit(1); | |
437 | } | |
438 | bootloader[5] = dtb_start; | |
439 | } else { | |
440 | bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR; | |
3871481c PM |
441 | if (info->ram_size >= (1ULL << 32)) { |
442 | fprintf(stderr, "qemu: RAM size must be less than 4GB to boot" | |
443 | " Linux kernel using ATAGS (try passing a device tree" | |
444 | " using -dtb)\n"); | |
445 | exit(1); | |
446 | } | |
412beee6 | 447 | } |
1c7b3754 | 448 | bootloader[6] = entry; |
52b43737 | 449 | for (n = 0; n < sizeof(bootloader) / 4; n++) { |
f2d74978 | 450 | bootloader[n] = tswap32(bootloader[n]); |
52b43737 | 451 | } |
f2d74978 PB |
452 | rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader), |
453 | info->loader_start); | |
52b43737 | 454 | if (info->nb_cpus > 1) { |
9543b0cd | 455 | info->write_secondary_boot(cpu, info); |
52b43737 | 456 | } |
16406950 | 457 | } |
f2d74978 | 458 | info->is_linux = is_linux; |
6ed221b6 AL |
459 | |
460 | for (; env; env = env->next_cpu) { | |
351d5666 | 461 | cpu = arm_env_get_cpu(env); |
6ed221b6 | 462 | env->boot_info = info; |
351d5666 | 463 | qemu_register_reset(do_cpu_reset, cpu); |
6ed221b6 | 464 | } |
16406950 | 465 | } |