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Commit | Line | Data |
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5fafdf24 | 1 | /* |
cdbdb648 PB |
2 | * ARM PrimeCell Timer modules. |
3 | * | |
4 | * Copyright (c) 2005-2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
6a824ec3 | 10 | #include "sysbus.h" |
87ecb68b | 11 | #include "qemu-timer.h" |
cdbdb648 PB |
12 | |
13 | /* Common timer implementation. */ | |
14 | ||
15 | #define TIMER_CTRL_ONESHOT (1 << 0) | |
16 | #define TIMER_CTRL_32BIT (1 << 1) | |
17 | #define TIMER_CTRL_DIV1 (0 << 2) | |
18 | #define TIMER_CTRL_DIV16 (1 << 2) | |
19 | #define TIMER_CTRL_DIV256 (2 << 2) | |
20 | #define TIMER_CTRL_IE (1 << 5) | |
21 | #define TIMER_CTRL_PERIODIC (1 << 6) | |
22 | #define TIMER_CTRL_ENABLE (1 << 7) | |
23 | ||
24 | typedef struct { | |
423f0742 | 25 | ptimer_state *timer; |
cdbdb648 | 26 | uint32_t control; |
cdbdb648 | 27 | uint32_t limit; |
cdbdb648 PB |
28 | int freq; |
29 | int int_level; | |
d537cf6c | 30 | qemu_irq irq; |
cdbdb648 PB |
31 | } arm_timer_state; |
32 | ||
cdbdb648 PB |
33 | /* Check all active timers, and schedule the next timer interrupt. */ |
34 | ||
423f0742 | 35 | static void arm_timer_update(arm_timer_state *s) |
cdbdb648 | 36 | { |
cdbdb648 PB |
37 | /* Update interrupts. */ |
38 | if (s->int_level && (s->control & TIMER_CTRL_IE)) { | |
d537cf6c | 39 | qemu_irq_raise(s->irq); |
cdbdb648 | 40 | } else { |
d537cf6c | 41 | qemu_irq_lower(s->irq); |
cdbdb648 | 42 | } |
cdbdb648 PB |
43 | } |
44 | ||
c227f099 | 45 | static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset) |
cdbdb648 PB |
46 | { |
47 | arm_timer_state *s = (arm_timer_state *)opaque; | |
48 | ||
49 | switch (offset >> 2) { | |
50 | case 0: /* TimerLoad */ | |
51 | case 6: /* TimerBGLoad */ | |
52 | return s->limit; | |
53 | case 1: /* TimerValue */ | |
423f0742 | 54 | return ptimer_get_count(s->timer); |
cdbdb648 PB |
55 | case 2: /* TimerControl */ |
56 | return s->control; | |
57 | case 4: /* TimerRIS */ | |
58 | return s->int_level; | |
59 | case 5: /* TimerMIS */ | |
60 | if ((s->control & TIMER_CTRL_IE) == 0) | |
61 | return 0; | |
62 | return s->int_level; | |
63 | default: | |
4abc7ebf | 64 | hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
cdbdb648 PB |
65 | return 0; |
66 | } | |
67 | } | |
68 | ||
423f0742 PB |
69 | /* Reset the timer limit after settings have changed. */ |
70 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) | |
71 | { | |
72 | uint32_t limit; | |
73 | ||
a9cf98d9 | 74 | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
423f0742 PB |
75 | /* Free running. */ |
76 | if (s->control & TIMER_CTRL_32BIT) | |
77 | limit = 0xffffffff; | |
78 | else | |
79 | limit = 0xffff; | |
80 | } else { | |
81 | /* Periodic. */ | |
82 | limit = s->limit; | |
83 | } | |
84 | ptimer_set_limit(s->timer, limit, reload); | |
85 | } | |
86 | ||
c227f099 | 87 | static void arm_timer_write(void *opaque, target_phys_addr_t offset, |
cdbdb648 PB |
88 | uint32_t value) |
89 | { | |
90 | arm_timer_state *s = (arm_timer_state *)opaque; | |
423f0742 | 91 | int freq; |
cdbdb648 | 92 | |
cdbdb648 PB |
93 | switch (offset >> 2) { |
94 | case 0: /* TimerLoad */ | |
95 | s->limit = value; | |
423f0742 | 96 | arm_timer_recalibrate(s, 1); |
cdbdb648 PB |
97 | break; |
98 | case 1: /* TimerValue */ | |
99 | /* ??? Linux seems to want to write to this readonly register. | |
100 | Ignore it. */ | |
101 | break; | |
102 | case 2: /* TimerControl */ | |
103 | if (s->control & TIMER_CTRL_ENABLE) { | |
104 | /* Pause the timer if it is running. This may cause some | |
105 | inaccuracy dure to rounding, but avoids a whole lot of other | |
106 | messyness. */ | |
423f0742 | 107 | ptimer_stop(s->timer); |
cdbdb648 PB |
108 | } |
109 | s->control = value; | |
423f0742 | 110 | freq = s->freq; |
cdbdb648 PB |
111 | /* ??? Need to recalculate expiry time after changing divisor. */ |
112 | switch ((value >> 2) & 3) { | |
423f0742 PB |
113 | case 1: freq >>= 4; break; |
114 | case 2: freq >>= 8; break; | |
cdbdb648 | 115 | } |
d6759902 | 116 | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
423f0742 | 117 | ptimer_set_freq(s->timer, freq); |
cdbdb648 PB |
118 | if (s->control & TIMER_CTRL_ENABLE) { |
119 | /* Restart the timer if still enabled. */ | |
423f0742 | 120 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); |
cdbdb648 PB |
121 | } |
122 | break; | |
123 | case 3: /* TimerIntClr */ | |
124 | s->int_level = 0; | |
125 | break; | |
126 | case 6: /* TimerBGLoad */ | |
127 | s->limit = value; | |
423f0742 | 128 | arm_timer_recalibrate(s, 0); |
cdbdb648 PB |
129 | break; |
130 | default: | |
4abc7ebf | 131 | hw_error("%s: Bad offset %x\n", __func__, (int)offset); |
cdbdb648 | 132 | } |
423f0742 | 133 | arm_timer_update(s); |
cdbdb648 PB |
134 | } |
135 | ||
136 | static void arm_timer_tick(void *opaque) | |
137 | { | |
423f0742 PB |
138 | arm_timer_state *s = (arm_timer_state *)opaque; |
139 | s->int_level = 1; | |
140 | arm_timer_update(s); | |
cdbdb648 PB |
141 | } |
142 | ||
eecd33a5 JQ |
143 | static const VMStateDescription vmstate_arm_timer = { |
144 | .name = "arm_timer", | |
145 | .version_id = 1, | |
146 | .minimum_version_id = 1, | |
147 | .minimum_version_id_old = 1, | |
148 | .fields = (VMStateField[]) { | |
149 | VMSTATE_UINT32(control, arm_timer_state), | |
150 | VMSTATE_UINT32(limit, arm_timer_state), | |
151 | VMSTATE_INT32(int_level, arm_timer_state), | |
152 | VMSTATE_PTIMER(timer, arm_timer_state), | |
153 | VMSTATE_END_OF_LIST() | |
154 | } | |
155 | }; | |
23e39294 | 156 | |
6a824ec3 | 157 | static arm_timer_state *arm_timer_init(uint32_t freq) |
cdbdb648 PB |
158 | { |
159 | arm_timer_state *s; | |
423f0742 | 160 | QEMUBH *bh; |
cdbdb648 | 161 | |
7267c094 | 162 | s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); |
423f0742 | 163 | s->freq = freq; |
cdbdb648 | 164 | s->control = TIMER_CTRL_IE; |
cdbdb648 | 165 | |
423f0742 PB |
166 | bh = qemu_bh_new(arm_timer_tick, s); |
167 | s->timer = ptimer_init(bh); | |
eecd33a5 | 168 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); |
cdbdb648 PB |
169 | return s; |
170 | } | |
171 | ||
172 | /* ARM PrimeCell SP804 dual timer module. | |
7b4252e8 PC |
173 | * Docs at |
174 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html | |
175 | */ | |
cdbdb648 PB |
176 | |
177 | typedef struct { | |
6a824ec3 | 178 | SysBusDevice busdev; |
e219dea2 | 179 | MemoryRegion iomem; |
6a824ec3 | 180 | arm_timer_state *timer[2]; |
cdbdb648 | 181 | int level[2]; |
d537cf6c | 182 | qemu_irq irq; |
cdbdb648 PB |
183 | } sp804_state; |
184 | ||
7b4252e8 PC |
185 | static const uint8_t sp804_ids[] = { |
186 | /* Timer ID */ | |
187 | 0x04, 0x18, 0x14, 0, | |
188 | /* PrimeCell ID */ | |
189 | 0xd, 0xf0, 0x05, 0xb1 | |
190 | }; | |
191 | ||
d537cf6c | 192 | /* Merge the IRQs from the two component devices. */ |
cdbdb648 PB |
193 | static void sp804_set_irq(void *opaque, int irq, int level) |
194 | { | |
195 | sp804_state *s = (sp804_state *)opaque; | |
196 | ||
197 | s->level[irq] = level; | |
d537cf6c | 198 | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
cdbdb648 PB |
199 | } |
200 | ||
e219dea2 AK |
201 | static uint64_t sp804_read(void *opaque, target_phys_addr_t offset, |
202 | unsigned size) | |
cdbdb648 PB |
203 | { |
204 | sp804_state *s = (sp804_state *)opaque; | |
205 | ||
cdbdb648 PB |
206 | if (offset < 0x20) { |
207 | return arm_timer_read(s->timer[0], offset); | |
7b4252e8 PC |
208 | } |
209 | if (offset < 0x40) { | |
cdbdb648 PB |
210 | return arm_timer_read(s->timer[1], offset - 0x20); |
211 | } | |
7b4252e8 PC |
212 | |
213 | /* TimerPeriphID */ | |
214 | if (offset >= 0xfe0 && offset <= 0xffc) { | |
215 | return sp804_ids[(offset - 0xfe0) >> 2]; | |
216 | } | |
217 | ||
218 | switch (offset) { | |
219 | /* Integration Test control registers, which we won't support */ | |
220 | case 0xf00: /* TimerITCR */ | |
221 | case 0xf04: /* TimerITOP (strictly write only but..) */ | |
222 | return 0; | |
223 | } | |
224 | ||
225 | hw_error("%s: Bad offset %x\n", __func__, (int)offset); | |
226 | return 0; | |
cdbdb648 PB |
227 | } |
228 | ||
c227f099 | 229 | static void sp804_write(void *opaque, target_phys_addr_t offset, |
e219dea2 | 230 | uint64_t value, unsigned size) |
cdbdb648 PB |
231 | { |
232 | sp804_state *s = (sp804_state *)opaque; | |
233 | ||
cdbdb648 PB |
234 | if (offset < 0x20) { |
235 | arm_timer_write(s->timer[0], offset, value); | |
7b4252e8 PC |
236 | return; |
237 | } | |
238 | ||
239 | if (offset < 0x40) { | |
cdbdb648 | 240 | arm_timer_write(s->timer[1], offset - 0x20, value); |
7b4252e8 | 241 | return; |
cdbdb648 | 242 | } |
7b4252e8 PC |
243 | |
244 | /* Technically we could be writing to the Test Registers, but not likely */ | |
245 | hw_error("%s: Bad offset %x\n", __func__, (int)offset); | |
cdbdb648 PB |
246 | } |
247 | ||
e219dea2 AK |
248 | static const MemoryRegionOps sp804_ops = { |
249 | .read = sp804_read, | |
250 | .write = sp804_write, | |
251 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
252 | }; |
253 | ||
81986ac4 JQ |
254 | static const VMStateDescription vmstate_sp804 = { |
255 | .name = "sp804", | |
256 | .version_id = 1, | |
257 | .minimum_version_id = 1, | |
258 | .minimum_version_id_old = 1, | |
259 | .fields = (VMStateField[]) { | |
260 | VMSTATE_INT32_ARRAY(level, sp804_state, 2), | |
261 | VMSTATE_END_OF_LIST() | |
262 | } | |
263 | }; | |
23e39294 | 264 | |
81a322d4 | 265 | static int sp804_init(SysBusDevice *dev) |
cdbdb648 | 266 | { |
6a824ec3 | 267 | sp804_state *s = FROM_SYSBUS(sp804_state, dev); |
d537cf6c | 268 | qemu_irq *qi; |
cdbdb648 | 269 | |
d537cf6c | 270 | qi = qemu_allocate_irqs(sp804_set_irq, s, 2); |
6a824ec3 | 271 | sysbus_init_irq(dev, &s->irq); |
cdbdb648 PB |
272 | /* ??? The timers are actually configurable between 32kHz and 1MHz, but |
273 | we don't implement that. */ | |
6a824ec3 PB |
274 | s->timer[0] = arm_timer_init(1000000); |
275 | s->timer[1] = arm_timer_init(1000000); | |
276 | s->timer[0]->irq = qi[0]; | |
277 | s->timer[1]->irq = qi[1]; | |
e219dea2 | 278 | memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000); |
750ecd44 | 279 | sysbus_init_mmio(dev, &s->iomem); |
81986ac4 | 280 | vmstate_register(&dev->qdev, -1, &vmstate_sp804, s); |
81a322d4 | 281 | return 0; |
cdbdb648 PB |
282 | } |
283 | ||
284 | ||
285 | /* Integrator/CP timer module. */ | |
286 | ||
287 | typedef struct { | |
6a824ec3 | 288 | SysBusDevice busdev; |
e219dea2 | 289 | MemoryRegion iomem; |
6a824ec3 | 290 | arm_timer_state *timer[3]; |
cdbdb648 PB |
291 | } icp_pit_state; |
292 | ||
e219dea2 AK |
293 | static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset, |
294 | unsigned size) | |
cdbdb648 PB |
295 | { |
296 | icp_pit_state *s = (icp_pit_state *)opaque; | |
297 | int n; | |
298 | ||
299 | /* ??? Don't know the PrimeCell ID for this device. */ | |
cdbdb648 | 300 | n = offset >> 8; |
ee71c984 | 301 | if (n > 2) { |
4abc7ebf | 302 | hw_error("%s: Bad timer %d\n", __func__, n); |
2ac71179 | 303 | } |
cdbdb648 PB |
304 | |
305 | return arm_timer_read(s->timer[n], offset & 0xff); | |
306 | } | |
307 | ||
c227f099 | 308 | static void icp_pit_write(void *opaque, target_phys_addr_t offset, |
e219dea2 | 309 | uint64_t value, unsigned size) |
cdbdb648 PB |
310 | { |
311 | icp_pit_state *s = (icp_pit_state *)opaque; | |
312 | int n; | |
313 | ||
cdbdb648 | 314 | n = offset >> 8; |
ee71c984 | 315 | if (n > 2) { |
4abc7ebf | 316 | hw_error("%s: Bad timer %d\n", __func__, n); |
2ac71179 | 317 | } |
cdbdb648 PB |
318 | |
319 | arm_timer_write(s->timer[n], offset & 0xff, value); | |
320 | } | |
321 | ||
e219dea2 AK |
322 | static const MemoryRegionOps icp_pit_ops = { |
323 | .read = icp_pit_read, | |
324 | .write = icp_pit_write, | |
325 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
326 | }; |
327 | ||
81a322d4 | 328 | static int icp_pit_init(SysBusDevice *dev) |
cdbdb648 | 329 | { |
6a824ec3 | 330 | icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); |
cdbdb648 | 331 | |
cdbdb648 | 332 | /* Timer 0 runs at the system clock speed (40MHz). */ |
6a824ec3 | 333 | s->timer[0] = arm_timer_init(40000000); |
cdbdb648 | 334 | /* The other two timers run at 1MHz. */ |
6a824ec3 PB |
335 | s->timer[1] = arm_timer_init(1000000); |
336 | s->timer[2] = arm_timer_init(1000000); | |
337 | ||
338 | sysbus_init_irq(dev, &s->timer[0]->irq); | |
339 | sysbus_init_irq(dev, &s->timer[1]->irq); | |
340 | sysbus_init_irq(dev, &s->timer[2]->irq); | |
cdbdb648 | 341 | |
e219dea2 | 342 | memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000); |
750ecd44 | 343 | sysbus_init_mmio(dev, &s->iomem); |
23e39294 PB |
344 | /* This device has no state to save/restore. The component timers will |
345 | save themselves. */ | |
81a322d4 | 346 | return 0; |
cdbdb648 | 347 | } |
6a824ec3 PB |
348 | |
349 | static void arm_timer_register_devices(void) | |
350 | { | |
351 | sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init); | |
352 | sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init); | |
353 | } | |
354 | ||
355 | device_init(arm_timer_register_devices) |