[mirror_qemu.git] / hw / arm_timer.c

/*
 * ARM PrimeCell Timer modules.
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "primecell.h"

/* Common timer implementation.  */

#define TIMER_CTRL_ONESHOT      (1 << 0)
#define TIMER_CTRL_32BIT        (1 << 1)
#define TIMER_CTRL_DIV1         (0 << 2)
#define TIMER_CTRL_DIV16        (1 << 2)
#define TIMER_CTRL_DIV256       (2 << 2)
#define TIMER_CTRL_IE           (1 << 5)
#define TIMER_CTRL_PERIODIC     (1 << 6)
#define TIMER_CTRL_ENABLE       (1 << 7)

typedef struct {
    ptimer_state *timer;
    uint32_t control;
    uint32_t limit;
    int freq;
    int int_level;
    qemu_irq irq;
} arm_timer_state;

/* Check all active timers, and schedule the next timer interrupt.  */

static void arm_timer_update(arm_timer_state *s)
{
    /* Update interrupts.  */
    if (s->int_level && (s->control & TIMER_CTRL_IE)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
    case 6: /* TimerBGLoad */
        return s->limit;
    case 1: /* TimerValue */
        return ptimer_get_count(s->timer);
    case 2: /* TimerControl */
        return s->control;
    case 4: /* TimerRIS */
        return s->int_level;
    case 5: /* TimerMIS */
        if ((s->control & TIMER_CTRL_IE) == 0)
            return 0;
        return s->int_level;
    default:
        cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
                   (int)offset);
        return 0;
    }
}

/* Reset the timer limit after settings have changed.  */
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
    uint32_t limit;

    if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
        /* Free running.  */
        if (s->control & TIMER_CTRL_32BIT)
            limit = 0xffffffff;
        else
            limit = 0xffff;
    } else {
          /* Periodic.  */
          limit = s->limit;
    }
    ptimer_set_limit(s->timer, limit, reload);
}

static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                            uint32_t value)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 1);
        break;
    case 1: /* TimerValue */
        /* ??? Linux seems to want to write to this readonly register.
           Ignore it.  */
        break;
    case 2: /* TimerControl */
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        s->control = value;
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch ((value >> 2) & 3) {
        case 1: freq >>= 4; break;
        case 2: freq >>= 8; break;
        }
        arm_timer_recalibrate(s, 0);
        ptimer_set_freq(s->timer, freq);
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
        }
        break;
    case 3: /* TimerIntClr */
        s->int_level = 0;
        break;
    case 6: /* TimerBGLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 0);
        break;
    default:
        cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
                   (int)offset);
    }
    arm_timer_update(s);
}

static void arm_timer_tick(void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    s->int_level = 1;
    arm_timer_update(s);
}

static void arm_timer_save(QEMUFile *f, void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    qemu_put_be32(f, s->control);
    qemu_put_be32(f, s->limit);
    qemu_put_be32(f, s->int_level);
    qemu_put_ptimer(f, s->timer);
}

static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    if (version_id != 1)
        return -EINVAL;

    s->control = qemu_get_be32(f);
    s->limit = qemu_get_be32(f);
    s->int_level = qemu_get_be32(f);
    qemu_get_ptimer(f, s->timer);
    return 0;
}

static void *arm_timer_init(uint32_t freq, qemu_irq irq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
    s->irq = irq;
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
    register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
    return s;
}

/* ARM PrimeCell SP804 dual timer module.
   Docs for this device don't seem to be publicly available.  This
   implementation is based on guesswork, the linux kernel sources and the
   Integrator/CP timer modules.  */

typedef struct {
    void *timer[2];
    int level[2];
    qemu_irq irq;
} sp804_state;

/* Merge the IRQs from the two component devices.  */
static void sp804_set_irq(void *opaque, int irq, int level)
{
    sp804_state *s = (sp804_state *)opaque;

    s->level[irq] = level;
    qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}

static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
    sp804_state *s = (sp804_state *)opaque;

    /* ??? Don't know the PrimeCell ID for this device.  */
    if (offset < 0x20) {
        return arm_timer_read(s->timer[0], offset);
    } else {
        return arm_timer_read(s->timer[1], offset - 0x20);
    }
}

static void sp804_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    sp804_state *s = (sp804_state *)opaque;

    if (offset < 0x20) {
        arm_timer_write(s->timer[0], offset, value);
    } else {
        arm_timer_write(s->timer[1], offset - 0x20, value);
    }
}

static CPUReadMemoryFunc *sp804_readfn[] = {
   sp804_read,
   sp804_read,
   sp804_read
};

static CPUWriteMemoryFunc *sp804_writefn[] = {
   sp804_write,
   sp804_write,
   sp804_write
};

static void sp804_save(QEMUFile *f, void *opaque)
{
    sp804_state *s = (sp804_state *)opaque;
    qemu_put_be32(f, s->level[0]);
    qemu_put_be32(f, s->level[1]);
}

static int sp804_load(QEMUFile *f, void *opaque, int version_id)
{
    sp804_state *s = (sp804_state *)opaque;

    if (version_id != 1)
        return -EINVAL;

    s->level[0] = qemu_get_be32(f);
    s->level[1] = qemu_get_be32(f);
    return 0;
}

void sp804_init(uint32_t base, qemu_irq irq)
{
    int iomemtype;
    sp804_state *s;
    qemu_irq *qi;

    s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    s->irq = irq;
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000, qi[0]);
    s->timer[1] = arm_timer_init(1000000, qi[1]);
    iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                       sp804_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
}


/* Integrator/CP timer module.  */

typedef struct {
    void *timer[3];
} icp_pit_state;

static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    /* ??? Don't know the PrimeCell ID for this device.  */
    n = offset >> 8;
    if (n > 3)
        cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);

    return arm_timer_read(s->timer[n], offset & 0xff);
}

static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    n = offset >> 8;
    if (n > 3)
        cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);

    arm_timer_write(s->timer[n], offset & 0xff, value);
}


static CPUReadMemoryFunc *icp_pit_readfn[] = {
   icp_pit_read,
   icp_pit_read,
   icp_pit_read
};

static CPUWriteMemoryFunc *icp_pit_writefn[] = {
   icp_pit_write,
   icp_pit_write,
   icp_pit_write
};

void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
{
    int iomemtype;
    icp_pit_state *s;

    s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
    /* Timer 0 runs at the system clock speed (40MHz).  */
    s->timer[0] = arm_timer_init(40000000, pic[irq]);
    /* The other two timers run at 1MHz.  */
    s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
    s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);

    iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
                                       icp_pit_writefn, s);
    cpu_register_physical_memory(base, 0x00001000, iomemtype);
    /* This device has no state to save/restore.  The component timers will
       save themselves.  */
}
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* ARM PrimeCell Timer modules.
	3	*
	4	* Copyright (c) 2005-2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
87ecb68b	10	#include "hw.h"
87ecb68b	11	#include "qemu-timer.h"
9596ebb7	12	#include "primecell.h"
cdbdb648 PB	13
	14	/* Common timer implementation. */
	15
	16	#define TIMER_CTRL_ONESHOT (1 << 0)
	17	#define TIMER_CTRL_32BIT (1 << 1)
	18	#define TIMER_CTRL_DIV1 (0 << 2)
	19	#define TIMER_CTRL_DIV16 (1 << 2)
	20	#define TIMER_CTRL_DIV256 (2 << 2)
	21	#define TIMER_CTRL_IE (1 << 5)
	22	#define TIMER_CTRL_PERIODIC (1 << 6)
	23	#define TIMER_CTRL_ENABLE (1 << 7)
	24
	25	typedef struct {
423f0742	26	ptimer_state *timer;
cdbdb648	27	uint32_t control;
cdbdb648	28	uint32_t limit;
cdbdb648 PB	29	int freq;
cdbdb648 PB	30	int int_level;
d537cf6c	31	qemu_irq irq;
cdbdb648 PB	32	} arm_timer_state;
cdbdb648 PB	33
cdbdb648 PB	34	/* Check all active timers, and schedule the next timer interrupt. */
cdbdb648 PB	35
423f0742	36	static void arm_timer_update(arm_timer_state *s)
cdbdb648	37	{
cdbdb648 PB	38	/* Update interrupts. */
cdbdb648 PB	39	if (s->int_level && (s->control & TIMER_CTRL_IE)) {
d537cf6c	40	qemu_irq_raise(s->irq);
cdbdb648	41	} else {
d537cf6c	42	qemu_irq_lower(s->irq);
cdbdb648	43	}
cdbdb648 PB	44	}
cdbdb648 PB	45
9596ebb7	46	static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	47	{
	48	arm_timer_state s = (arm_timer_state )opaque;
	49
	50	switch (offset >> 2) {
	51	case 0: /* TimerLoad */
	52	case 6: /* TimerBGLoad */
	53	return s->limit;
	54	case 1: /* TimerValue */
423f0742	55	return ptimer_get_count(s->timer);
cdbdb648 PB	56	case 2: /* TimerControl */
	57	return s->control;
	58	case 4: /* TimerRIS */
	59	return s->int_level;
	60	case 5: /* TimerMIS */
	61	if ((s->control & TIMER_CTRL_IE) == 0)
	62	return 0;
	63	return s->int_level;
	64	default:
423f0742 PB	65	cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",
423f0742 PB	66	(int)offset);
cdbdb648 PB	67	return 0;
	68	}
	69	}
	70
423f0742 PB	71	/* Reset the timer limit after settings have changed. */
	72	static void arm_timer_recalibrate(arm_timer_state *s, int reload)
	73	{
	74	uint32_t limit;
	75
	76	if ((s->control & TIMER_CTRL_PERIODIC) == 0) {
	77	/* Free running. */
	78	if (s->control & TIMER_CTRL_32BIT)
	79	limit = 0xffffffff;
	80	else
	81	limit = 0xffff;
	82	} else {
	83	/* Periodic. */
	84	limit = s->limit;
	85	}
	86	ptimer_set_limit(s->timer, limit, reload);
	87	}
	88
cdbdb648 PB	89	static void arm_timer_write(void *opaque, target_phys_addr_t offset,
	90	uint32_t value)
	91	{
	92	arm_timer_state s = (arm_timer_state )opaque;
423f0742	93	int freq;
cdbdb648	94
cdbdb648 PB	95	switch (offset >> 2) {
	96	case 0: /* TimerLoad */
	97	s->limit = value;
423f0742	98	arm_timer_recalibrate(s, 1);
cdbdb648 PB	99	break;
	100	case 1: /* TimerValue */
	101	/* ??? Linux seems to want to write to this readonly register.
	102	Ignore it. */
	103	break;
	104	case 2: /* TimerControl */
	105	if (s->control & TIMER_CTRL_ENABLE) {
	106	/* Pause the timer if it is running. This may cause some
	107	inaccuracy dure to rounding, but avoids a whole lot of other
	108	messyness. */
423f0742	109	ptimer_stop(s->timer);
cdbdb648 PB	110	}
cdbdb648 PB	111	s->control = value;
423f0742	112	freq = s->freq;
cdbdb648 PB	113	/* ??? Need to recalculate expiry time after changing divisor. */
cdbdb648 PB	114	switch ((value >> 2) & 3) {
423f0742 PB	115	case 1: freq >>= 4; break;
423f0742 PB	116	case 2: freq >>= 8; break;
cdbdb648	117	}
423f0742 PB	118	arm_timer_recalibrate(s, 0);
423f0742 PB	119	ptimer_set_freq(s->timer, freq);
cdbdb648 PB	120	if (s->control & TIMER_CTRL_ENABLE) {
cdbdb648 PB	121	/* Restart the timer if still enabled. */
423f0742	122	ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
cdbdb648 PB	123	}
	124	break;
	125	case 3: /* TimerIntClr */
	126	s->int_level = 0;
	127	break;
	128	case 6: /* TimerBGLoad */
	129	s->limit = value;
423f0742	130	arm_timer_recalibrate(s, 0);
cdbdb648 PB	131	break;
cdbdb648 PB	132	default:
423f0742 PB	133	cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",
423f0742 PB	134	(int)offset);
cdbdb648	135	}
423f0742	136	arm_timer_update(s);
cdbdb648 PB	137	}
	138
	139	static void arm_timer_tick(void *opaque)
	140	{
423f0742 PB	141	arm_timer_state s = (arm_timer_state )opaque;
	142	s->int_level = 1;
	143	arm_timer_update(s);
cdbdb648 PB	144	}
cdbdb648 PB	145
23e39294 PB	146	static void arm_timer_save(QEMUFile f, void opaque)
	147	{
	148	arm_timer_state s = (arm_timer_state )opaque;
	149	qemu_put_be32(f, s->control);
	150	qemu_put_be32(f, s->limit);
	151	qemu_put_be32(f, s->int_level);
	152	qemu_put_ptimer(f, s->timer);
	153	}
	154
	155	static int arm_timer_load(QEMUFile f, void opaque, int version_id)
	156	{
	157	arm_timer_state s = (arm_timer_state )opaque;
	158
	159	if (version_id != 1)
	160	return -EINVAL;
	161
	162	s->control = qemu_get_be32(f);
	163	s->limit = qemu_get_be32(f);
	164	s->int_level = qemu_get_be32(f);
	165	qemu_get_ptimer(f, s->timer);
	166	return 0;
	167	}
	168
d537cf6c	169	static void *arm_timer_init(uint32_t freq, qemu_irq irq)
cdbdb648 PB	170	{
cdbdb648 PB	171	arm_timer_state *s;
423f0742	172	QEMUBH *bh;
cdbdb648 PB	173
cdbdb648 PB	174	s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
cdbdb648	175	s->irq = irq;
423f0742	176	s->freq = freq;
cdbdb648	177	s->control = TIMER_CTRL_IE;
cdbdb648	178
423f0742 PB	179	bh = qemu_bh_new(arm_timer_tick, s);
423f0742 PB	180	s->timer = ptimer_init(bh);
23e39294	181	register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
cdbdb648 PB	182	return s;
	183	}
	184
	185	/* ARM PrimeCell SP804 dual timer module.
	186	Docs for this device don't seem to be publicly available. This
d85fb99b	187	implementation is based on guesswork, the linux kernel sources and the
cdbdb648 PB	188	Integrator/CP timer modules. */
	189
	190	typedef struct {
cdbdb648 PB	191	void *timer[2];
cdbdb648 PB	192	int level[2];
d537cf6c	193	qemu_irq irq;
cdbdb648 PB	194	} sp804_state;
cdbdb648 PB	195
d537cf6c	196	/* Merge the IRQs from the two component devices. */
cdbdb648 PB	197	static void sp804_set_irq(void *opaque, int irq, int level)
	198	{
	199	sp804_state s = (sp804_state )opaque;
	200
	201	s->level[irq] = level;
d537cf6c	202	qemu_set_irq(s->irq, s->level[0] \|\| s->level[1]);
cdbdb648 PB	203	}
	204
	205	static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
	206	{
	207	sp804_state s = (sp804_state )opaque;
	208
	209	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648 PB	210	if (offset < 0x20) {
	211	return arm_timer_read(s->timer[0], offset);
	212	} else {
	213	return arm_timer_read(s->timer[1], offset - 0x20);
	214	}
	215	}
	216
	217	static void sp804_write(void *opaque, target_phys_addr_t offset,
	218	uint32_t value)
	219	{
	220	sp804_state s = (sp804_state )opaque;
	221
cdbdb648 PB	222	if (offset < 0x20) {
	223	arm_timer_write(s->timer[0], offset, value);
	224	} else {
	225	arm_timer_write(s->timer[1], offset - 0x20, value);
	226	}
	227	}
	228
	229	static CPUReadMemoryFunc *sp804_readfn[] = {
	230	sp804_read,
	231	sp804_read,
	232	sp804_read
	233	};
	234
	235	static CPUWriteMemoryFunc *sp804_writefn[] = {
	236	sp804_write,
	237	sp804_write,
	238	sp804_write
	239	};
	240
23e39294 PB	241	static void sp804_save(QEMUFile f, void opaque)
	242	{
	243	sp804_state s = (sp804_state )opaque;
	244	qemu_put_be32(f, s->level[0]);
	245	qemu_put_be32(f, s->level[1]);
	246	}
	247
	248	static int sp804_load(QEMUFile f, void opaque, int version_id)
	249	{
	250	sp804_state s = (sp804_state )opaque;
	251
	252	if (version_id != 1)
	253	return -EINVAL;
	254
	255	s->level[0] = qemu_get_be32(f);
	256	s->level[1] = qemu_get_be32(f);
	257	return 0;
	258	}
	259
d537cf6c	260	void sp804_init(uint32_t base, qemu_irq irq)
cdbdb648 PB	261	{
	262	int iomemtype;
	263	sp804_state *s;
d537cf6c	264	qemu_irq *qi;
cdbdb648 PB	265
cdbdb648 PB	266	s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
d537cf6c	267	qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
cdbdb648 PB	268	s->irq = irq;
	269	/* ??? The timers are actually configurable between 32kHz and 1MHz, but
	270	we don't implement that. */
d537cf6c PB	271	s->timer[0] = arm_timer_init(1000000, qi[0]);
d537cf6c PB	272	s->timer[1] = arm_timer_init(1000000, qi[1]);
cdbdb648 PB	273	iomemtype = cpu_register_io_memory(0, sp804_readfn,
cdbdb648 PB	274	sp804_writefn, s);
187337f8	275	cpu_register_physical_memory(base, 0x00001000, iomemtype);
23e39294	276	register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
cdbdb648 PB	277	}
	278
	279
	280	/* Integrator/CP timer module. */
	281
	282	typedef struct {
	283	void *timer[3];
cdbdb648 PB	284	} icp_pit_state;
	285
	286	static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
	287	{
	288	icp_pit_state s = (icp_pit_state )opaque;
	289	int n;
	290
	291	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648 PB	292	n = offset >> 8;
	293	if (n > 3)
	294	cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
	295
	296	return arm_timer_read(s->timer[n], offset & 0xff);
	297	}
	298
	299	static void icp_pit_write(void *opaque, target_phys_addr_t offset,
	300	uint32_t value)
	301	{
	302	icp_pit_state s = (icp_pit_state )opaque;
	303	int n;
	304
cdbdb648 PB	305	n = offset >> 8;
	306	if (n > 3)
	307	cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
	308
	309	arm_timer_write(s->timer[n], offset & 0xff, value);
	310	}
	311
	312
	313	static CPUReadMemoryFunc *icp_pit_readfn[] = {
	314	icp_pit_read,
	315	icp_pit_read,
	316	icp_pit_read
	317	};
	318
	319	static CPUWriteMemoryFunc *icp_pit_writefn[] = {
	320	icp_pit_write,
	321	icp_pit_write,
	322	icp_pit_write
	323	};
	324
d537cf6c	325	void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
cdbdb648 PB	326	{
	327	int iomemtype;
	328	icp_pit_state *s;
	329
	330	s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
cdbdb648	331	/* Timer 0 runs at the system clock speed (40MHz). */
d537cf6c	332	s->timer[0] = arm_timer_init(40000000, pic[irq]);
cdbdb648	333	/* The other two timers run at 1MHz. */
d537cf6c PB	334	s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
d537cf6c PB	335	s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
cdbdb648 PB	336
	337	iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
	338	icp_pit_writefn, s);
187337f8	339	cpu_register_physical_memory(base, 0x00001000, iomemtype);
23e39294 PB	340	/* This device has no state to save/restore. The component timers will
23e39294 PB	341	save themselves. */
cdbdb648	342	}