]> git.proxmox.com Git - mirror_qemu.git/blame - hw/block/fdc.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Replaced get_tick_per_sec() by NANOSECONDS_PER_SECOND
[mirror_qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a 32#include "hw/block/fdc.h"
da34e65c 33#include "qapi/error.h"
1de7afc9
PB		 34#include "qemu/error-report.h"
35#include "qemu/timer.h"
0d09e41a 36#include "hw/isa/isa.h"
83c9f4ca 37#include "hw/sysbus.h"
fa1d36df 38#include "sysemu/block-backend.h"
9c17d615
PB		 39#include "sysemu/blockdev.h"
40#include "sysemu/sysemu.h"
1de7afc9 41#include "qemu/log.h"
8977f3c1
FB		 42
43/********************************************************/
44/* debug Floppy devices */
8977f3c1 45
c691320f
JS		 46#define DEBUG_FLOPPY 0
47
001faf32 48#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 49 do { \
50 if (DEBUG_FLOPPY) { \
51 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
52 } \
53 } while (0)
8977f3c1 54
8977f3c1
FB		 55/********************************************************/
56/* Floppy drive emulation */
57
61a8d649
MA		 58typedef enum FDriveRate {
59 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
60 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
61 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
62 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
63} FDriveRate;
64
109c17bc
JS		 65typedef enum FDriveSize {
66 FDRIVE_SIZE_UNKNOWN,
67 FDRIVE_SIZE_350,
68 FDRIVE_SIZE_525,
69} FDriveSize;
70
61a8d649 71typedef struct FDFormat {
2da44dd0 72 FloppyDriveType drive;
61a8d649
MA		 73 uint8_t last_sect;
74 uint8_t max_track;
75 uint8_t max_head;
76 FDriveRate rate;
77} FDFormat;
78
109c17bc
JS		 79/* In many cases, the total sector size of a format is enough to uniquely
80 * identify it. However, there are some total sector collisions between
81 * formats of different physical size, and these are noted below by
82 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 83static const FDFormat fd_formats[] = {
84 /* First entry is default format */
85 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 86 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
87 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 88 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
89 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
90 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
91 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
92 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
93 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 94 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 95 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
96 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
97 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
98 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
99 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 100 /* 720 kB 3"1/2 floppy disks */
109c17bc 101 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 102 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
104 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
105 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
106 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 107 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 108 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 109 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 110 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
111 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 112 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 113 /* 720 kB 5"1/4 floppy disks */
109c17bc 114 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 115 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 116 /* 360 kB 5"1/4 floppy disks */
109c17bc 117 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 118 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
119 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
120 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 121 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 122 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
123 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 124 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 125 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 126 /* end */
2da44dd0 127 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 128};
129
109c17bc
JS		 130static FDriveSize drive_size(FloppyDriveType drive)
131{
132 switch (drive) {
133 case FLOPPY_DRIVE_TYPE_120:
134 return FDRIVE_SIZE_525;
135 case FLOPPY_DRIVE_TYPE_144:
136 case FLOPPY_DRIVE_TYPE_288:
137 return FDRIVE_SIZE_350;
138 default:
139 return FDRIVE_SIZE_UNKNOWN;
140 }
141}
142
cefec4f5
BS		 143#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
144#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
145
8977f3c1 146/* Will always be a fixed parameter for us */
f2d81b33
BS		 147#define FD_SECTOR_LEN 512
148#define FD_SECTOR_SC 2 /* Sector size code */
149#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1 150
844f65d6
HP		 151typedef struct FDCtrl FDCtrl;
152
8977f3c1 153/* Floppy disk drive emulation */
5c02c033 154typedef enum FDiskFlags {
baca51fa 155 FDISK_DBL_SIDES = 0x01,
5c02c033 156} FDiskFlags;
baca51fa 157
5c02c033 158typedef struct FDrive {
844f65d6 159 FDCtrl *fdctrl;
4be74634 160 BlockBackend *blk;
8977f3c1 161 /* Drive status */
2da44dd0 162 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 163 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 164 /* Position */
165 uint8_t head;
166 uint8_t track;
167 uint8_t sect;
8977f3c1 168 /* Media */
16c1e3ec 169 FloppyDriveType disk; /* Current disk type */
5c02c033 170 FDiskFlags flags;
8977f3c1
FB		 171 uint8_t last_sect; /* Nb sector per track */
172 uint8_t max_track; /* Nb of tracks */
baca51fa 173 uint16_t bps; /* Bytes per sector */
8977f3c1 174 uint8_t ro; /* Is read-only */
7d905f71 175 uint8_t media_changed; /* Is media changed */
844f65d6 176 uint8_t media_rate; /* Data rate of medium */
2e1280e8 177
d5d47efc 178 bool media_validated; /* Have we validated the media? */
5c02c033 179} FDrive;
8977f3c1 180
a73275dd
JS		 181
182static FloppyDriveType get_fallback_drive_type(FDrive *drv);
183
fd9bdbd3
JS		 184/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
185 * currently goes through some pains to keep seeks within the bounds
186 * established by last_sect and max_track. Correcting this is difficult,
187 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
188 *
189 * For now: allow empty drives to have large bounds so we can seek around,
190 * with the understanding that when a diskette is inserted, the bounds will
191 * properly tighten to match the geometry of that inserted medium.
192 */
193static void fd_empty_seek_hack(FDrive *drv)
194{
195 drv->last_sect = 0xFF;
196 drv->max_track = 0xFF;
197}
198
5c02c033 199static void fd_init(FDrive *drv)
8977f3c1
FB		 200{
201 /* Drive */
8977f3c1 202 drv->perpendicular = 0;
8977f3c1 203 /* Disk */
16c1e3ec 204 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 205 drv->last_sect = 0;
8977f3c1 206 drv->max_track = 0;
d5d47efc
JS		 207 drv->ro = true;
208 drv->media_changed = 1;
8977f3c1
FB		 209}
210
08388273
HP		 211#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
212
7859cb98 213static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 214 uint8_t last_sect, uint8_t num_sides)
8977f3c1 215{
08388273 216 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 217}
218
219/* Returns current position, in sectors, for given drive */
5c02c033 220static int fd_sector(FDrive *drv)
8977f3c1 221{
08388273
HP		 222 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
223 NUM_SIDES(drv));
8977f3c1
FB		 224}
225
77370520
BS		 226/* Seek to a new position:
227 * returns 0 if already on right track
228 * returns 1 if track changed
229 * returns 2 if track is invalid
230 * returns 3 if sector is invalid
231 * returns 4 if seek is disabled
232 */
5c02c033
BS		 233static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
234 int enable_seek)
8977f3c1
FB		 235{
236 uint32_t sector;
baca51fa
FB		 237 int ret;
238
239 if (track > drv->max_track ||
4f431960 240 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 241 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
242 head, track, sect, 1,
243 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
244 drv->max_track, drv->last_sect);
8977f3c1
FB		 245 return 2;
246 }
247 if (sect > drv->last_sect) {
ed5fd2cc
FB		 248 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
249 head, track, sect, 1,
250 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
251 drv->max_track, drv->last_sect);
8977f3c1
FB		 252 return 3;
253 }
08388273 254 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 255 ret = 0;
8977f3c1
FB		 256 if (sector != fd_sector(drv)) {
257#if 0
258 if (!enable_seek) {
cced7a13
BS		 259 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
260 " (max=%d %02x %02x)\n",
261 head, track, sect, 1, drv->max_track,
262 drv->last_sect);
8977f3c1
FB		 263 return 4;
264 }
265#endif
266 drv->head = head;
6be01b1e 267 if (drv->track != track) {
abb3e55b 268 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 269 drv->media_changed = 0;
270 }
4f431960 271 ret = 1;
6be01b1e 272 }
8977f3c1
FB		 273 drv->track = track;
274 drv->sect = sect;
8977f3c1
FB		 275 }
276
abb3e55b 277 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 278 ret = 2;
279 }
280
baca51fa 281 return ret;
8977f3c1
FB		 282}
283
284/* Set drive back to track 0 */
5c02c033 285static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 286{
287 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 288 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 289}
290
d5d47efc
JS		 291/**
292 * Determine geometry based on inserted diskette.
293 * Will not operate on an empty drive.
294 *
295 * @return: 0 on success, -1 if the drive is empty.
296 */
297static int pick_geometry(FDrive *drv)
9a972233 298{
21862658 299 BlockBackend *blk = drv->blk;
9a972233
JS		 300 const FDFormat *parse;
301 uint64_t nb_sectors, size;
f31937aa
JS		 302 int i;
303 int match, size_match, type_match;
304 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 305
d5d47efc 306 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 307 if (!drv->blk || !blk_is_inserted(drv->blk) ||
308 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
309 {
d5d47efc
JS		 310 return -1;
311 }
312
f31937aa
JS		 313 /* We need to determine the likely geometry of the inserted medium.
314 * In order of preference, we look for:
315 * (1) The same drive type and number of sectors,
316 * (2) The same diskette size and number of sectors,
317 * (3) The same drive type.
318 *
319 * In all cases, matches that occur higher in the drive table will take
320 * precedence over matches that occur later in the table.
321 */
9a972233 322 blk_get_geometry(blk, &nb_sectors);
f31937aa 323 match = size_match = type_match = -1;
9a972233
JS		 324 for (i = 0; ; i++) {
325 parse = &fd_formats[i];
2da44dd0 326 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 327 break;
328 }
f31937aa
JS		 329 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
330 if (nb_sectors == size) {
331 if (magic || parse->drive == drv->drive) {
332 /* (1) perfect match -- nb_sectors and drive type */
333 goto out;
334 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
335 /* (2) size match -- nb_sectors and physical medium size */
336 match = (match == -1) ? i : match;
337 } else {
338 /* This is suspicious -- Did the user misconfigure? */
339 size_match = (size_match == -1) ? i : size_match;
9a972233 340 }
f31937aa
JS		 341 } else if (type_match == -1) {
342 if ((parse->drive == drv->drive) ||
343 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
344 /* (3) type match -- nb_sectors mismatch, but matches the type
345 * specified explicitly by the user, or matches the fallback
346 * default type when using the drive autodetect mechanism */
347 type_match = i;
9a972233
JS		 348 }
349 }
350 }
f31937aa
JS		 351
352 /* No exact match found */
9a972233 353 if (match == -1) {
f31937aa
JS		 354 if (size_match != -1) {
355 parse = &fd_formats[size_match];
356 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
357 "but inserted medium appears to be a "
c691320f 358 "%"PRId64" sector '%s' type\n",
f31937aa
JS		 359 FloppyDriveType_lookup[drv->drive],
360 nb_sectors,
361 FloppyDriveType_lookup[parse->drive]);
9a972233 362 }
f31937aa 363 match = type_match;
9a972233 364 }
21862658 365
f31937aa
JS		 366 /* No match of any kind found -- fd_format is misconfigured, abort. */
367 if (match == -1) {
368 error_setg(&error_abort, "No candidate geometries present in table "
369 " for floppy drive type '%s'",
370 FloppyDriveType_lookup[drv->drive]);
371 }
372
373 parse = &(fd_formats[match]);
374
375 out:
21862658
JS		 376 if (parse->max_head == 0) {
377 drv->flags &= ~FDISK_DBL_SIDES;
378 } else {
379 drv->flags |= FDISK_DBL_SIDES;
380 }
381 drv->max_track = parse->max_track;
382 drv->last_sect = parse->last_sect;
d5d47efc 383 drv->disk = parse->drive;
21862658 384 drv->media_rate = parse->rate;
d5d47efc
JS		 385 return 0;
386}
387
388static void pick_drive_type(FDrive *drv)
389{
fff4687b
JS		 390 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
391 return;
392 }
393
d5d47efc
JS		 394 if (pick_geometry(drv) == 0) {
395 drv->drive = drv->disk;
396 } else {
a73275dd 397 drv->drive = get_fallback_drive_type(drv);
d5d47efc 398 }
fff4687b
JS		 399
400 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 401}
402
8977f3c1 403/* Revalidate a disk drive after a disk change */
5c02c033 404static void fd_revalidate(FDrive *drv)
8977f3c1 405{
d5d47efc
JS		 406 int rc;
407
8977f3c1 408 FLOPPY_DPRINTF("revalidate\n");
4be74634 409 if (drv->blk != NULL) {
21862658 410 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 411 if (!blk_is_inserted(drv->blk)) {
cfb08fba 412 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 413 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 414 fd_empty_seek_hack(drv);
d5d47efc
JS		 415 } else if (!drv->media_validated) {
416 rc = pick_geometry(drv);
417 if (rc) {
418 FLOPPY_DPRINTF("Could not validate floppy drive media");
419 } else {
420 drv->media_validated = true;
421 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
422 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
423 drv->max_track, drv->last_sect,
424 drv->ro ? "ro" : "rw");
425 }
4f431960 426 }
8977f3c1 427 } else {
cfb08fba 428 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 429 drv->last_sect = 0;
4f431960
JM		 430 drv->max_track = 0;
431 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 432 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
433 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 434 }
caed8802
FB		 435}
436
8977f3c1 437/********************************************************/
4b19ec0c 438/* Intel 82078 floppy disk controller emulation */
8977f3c1 439
5c02c033 440static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 441static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 442static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 443 int dma_pos, int dma_len);
d497d534 444static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 445static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 446
447static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
448static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
449static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
450static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
451static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
452static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
453static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
454static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
455static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
456static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
457static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 458static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 459
8977f3c1
FB		 460enum {
461 FD_DIR_WRITE = 0,
462 FD_DIR_READ = 1,
463 FD_DIR_SCANE = 2,
464 FD_DIR_SCANL = 3,
465 FD_DIR_SCANH = 4,
7ea004ed 466 FD_DIR_VERIFY = 5,
8977f3c1
FB		 467};
468
469enum {
b9b3d225
BS		 470 FD_STATE_MULTI = 0x01, /* multi track flag */
471 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 472};
473
9fea808a 474enum {
8c6a4d77
BS		 475 FD_REG_SRA = 0x00,
476 FD_REG_SRB = 0x01,
9fea808a
BS		 477 FD_REG_DOR = 0x02,
478 FD_REG_TDR = 0x03,
479 FD_REG_MSR = 0x04,
480 FD_REG_DSR = 0x04,
481 FD_REG_FIFO = 0x05,
482 FD_REG_DIR = 0x07,
a758f8f4 483 FD_REG_CCR = 0x07,
9fea808a
BS		 484};
485
486enum {
65cef780 487 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 488 FD_CMD_SPECIFY = 0x03,
489 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 490 FD_CMD_WRITE = 0x05,
491 FD_CMD_READ = 0x06,
9fea808a
BS		 492 FD_CMD_RECALIBRATE = 0x07,
493 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 494 FD_CMD_WRITE_DELETED = 0x09,
495 FD_CMD_READ_ID = 0x0a,
496 FD_CMD_READ_DELETED = 0x0c,
497 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 498 FD_CMD_DUMPREG = 0x0e,
499 FD_CMD_SEEK = 0x0f,
500 FD_CMD_VERSION = 0x10,
65cef780 501 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 502 FD_CMD_PERPENDICULAR_MODE = 0x12,
503 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 504 FD_CMD_LOCK = 0x14,
505 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 506 FD_CMD_POWERDOWN_MODE = 0x17,
507 FD_CMD_PART_ID = 0x18,
65cef780
BS		 508 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
509 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 510 FD_CMD_SAVE = 0x2e,
9fea808a 511 FD_CMD_OPTION = 0x33,
bb350a5e 512 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 513 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
514 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 515 FD_CMD_FORMAT_AND_WRITE = 0xcd,
516 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
517};
518
519enum {
520 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
521 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
522 FD_CONFIG_POLL = 0x10, /* Poll enabled */
523 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
524 FD_CONFIG_EIS = 0x40, /* No implied seeks */
525};
526
527enum {
2fee0088
PH		 528 FD_SR0_DS0 = 0x01,
529 FD_SR0_DS1 = 0x02,
530 FD_SR0_HEAD = 0x04,
9fea808a
BS		 531 FD_SR0_EQPMT = 0x10,
532 FD_SR0_SEEK = 0x20,
533 FD_SR0_ABNTERM = 0x40,
534 FD_SR0_INVCMD = 0x80,
535 FD_SR0_RDYCHG = 0xc0,
536};
537
77370520 538enum {
844f65d6 539 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 540 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 541 FD_SR1_EC = 0x80, /* End of cylinder */
542};
543
544enum {
545 FD_SR2_SNS = 0x04, /* Scan not satisfied */
546 FD_SR2_SEH = 0x08, /* Scan equal hit */
547};
548
8c6a4d77
BS		 549enum {
550 FD_SRA_DIR = 0x01,
551 FD_SRA_nWP = 0x02,
552 FD_SRA_nINDX = 0x04,
553 FD_SRA_HDSEL = 0x08,
554 FD_SRA_nTRK0 = 0x10,
555 FD_SRA_STEP = 0x20,
556 FD_SRA_nDRV2 = 0x40,
557 FD_SRA_INTPEND = 0x80,
558};
559
560enum {
561 FD_SRB_MTR0 = 0x01,
562 FD_SRB_MTR1 = 0x02,
563 FD_SRB_WGATE = 0x04,
564 FD_SRB_RDATA = 0x08,
565 FD_SRB_WDATA = 0x10,
566 FD_SRB_DR0 = 0x20,
567};
568
9fea808a 569enum {
78ae820c
BS		 570#if MAX_FD == 4
571 FD_DOR_SELMASK = 0x03,
572#else
9fea808a 573 FD_DOR_SELMASK = 0x01,
78ae820c 574#endif
9fea808a
BS		 575 FD_DOR_nRESET = 0x04,
576 FD_DOR_DMAEN = 0x08,
577 FD_DOR_MOTEN0 = 0x10,
578 FD_DOR_MOTEN1 = 0x20,
579 FD_DOR_MOTEN2 = 0x40,
580 FD_DOR_MOTEN3 = 0x80,
581};
582
583enum {
78ae820c 584#if MAX_FD == 4
9fea808a 585 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 586#else
587 FD_TDR_BOOTSEL = 0x04,
588#endif
9fea808a
BS		 589};
590
591enum {
592 FD_DSR_DRATEMASK= 0x03,
593 FD_DSR_PWRDOWN = 0x40,
594 FD_DSR_SWRESET = 0x80,
595};
596
597enum {
598 FD_MSR_DRV0BUSY = 0x01,
599 FD_MSR_DRV1BUSY = 0x02,
600 FD_MSR_DRV2BUSY = 0x04,
601 FD_MSR_DRV3BUSY = 0x08,
602 FD_MSR_CMDBUSY = 0x10,
603 FD_MSR_NONDMA = 0x20,
604 FD_MSR_DIO = 0x40,
605 FD_MSR_RQM = 0x80,
606};
607
608enum {
609 FD_DIR_DSKCHG = 0x80,
610};
611
85d291a0
KW		 612/*
613 * See chapter 5.0 "Controller phases" of the spec:
614 *
615 * Command phase:
616 * The host writes a command and its parameters into the FIFO. The command
617 * phase is completed when all parameters for the command have been supplied,
618 * and execution phase is entered.
619 *
620 * Execution phase:
621 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
622 * contains the payload now, otherwise it's unused. When all bytes of the
623 * required data have been transferred, the state is switched to either result
624 * phase (if the command produces status bytes) or directly back into the
625 * command phase for the next command.
626 *
627 * Result phase:
628 * The host reads out the FIFO, which contains one or more result bytes now.
629 */
630enum {
631 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
632 FD_PHASE_RECONSTRUCT = 0,
633
634 FD_PHASE_COMMAND = 1,
635 FD_PHASE_EXECUTION = 2,
636 FD_PHASE_RESULT = 3,
637};
638
8977f3c1 639#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 640#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 641
5c02c033 642struct FDCtrl {
dc6c1b37 643 MemoryRegion iomem;
d537cf6c 644 qemu_irq irq;
4b19ec0c 645 /* Controller state */
ed5fd2cc 646 QEMUTimer *result_timer;
242cca4f 647 int dma_chann;
85d291a0 648 uint8_t phase;
c8a35f1c 649 IsaDma *dma;
242cca4f
BS		 650 /* Controller's identification */
651 uint8_t version;
652 /* HW */
8c6a4d77
BS		 653 uint8_t sra;
654 uint8_t srb;
368df94d 655 uint8_t dor;
d7a6c270 656 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 657 uint8_t tdr;
b9b3d225 658 uint8_t dsr;
368df94d 659 uint8_t msr;
8977f3c1 660 uint8_t cur_drv;
77370520
BS		 661 uint8_t status0;
662 uint8_t status1;
663 uint8_t status2;
8977f3c1 664 /* Command FIFO */
33f00271 665 uint8_t *fifo;
d7a6c270 666 int32_t fifo_size;
8977f3c1
FB		 667 uint32_t data_pos;
668 uint32_t data_len;
669 uint8_t data_state;
670 uint8_t data_dir;
890fa6be 671 uint8_t eot; /* last wanted sector */
8977f3c1 672 /* States kept only to be returned back */
8977f3c1
FB		 673 /* precompensation */
674 uint8_t precomp_trk;
675 uint8_t config;
676 uint8_t lock;
677 /* Power down config (also with status regB access mode */
678 uint8_t pwrd;
679 /* Floppy drives */
d7a6c270 680 uint8_t num_floppies;
5c02c033 681 FDrive drives[MAX_FD];
f2d81b33 682 int reset_sensei;
09c6d585 683 uint32_t check_media_rate;
a73275dd 684 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 685 /* Timers state */
686 uint8_t timer0;
687 uint8_t timer1;
baca51fa
FB		 688};
689
a73275dd
JS		 690static FloppyDriveType get_fallback_drive_type(FDrive *drv)
691{
692 return drv->fdctrl->fallback;
693}
694
19d46d71 695#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 696#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
697
5c02c033 698typedef struct FDCtrlSysBus {
dd3be742
HT		 699 /*< private >*/
700 SysBusDevice parent_obj;
701 /*< public >*/
702
5c02c033
BS		 703 struct FDCtrl state;
704} FDCtrlSysBus;
8baf73ad 705
020c8e76
AF		 706#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
707
5c02c033 708typedef struct FDCtrlISABus {
020c8e76
AF		 709 ISADevice parent_obj;
710
c9ae703d
HP		 711 uint32_t iobase;
712 uint32_t irq;
713 uint32_t dma;
5c02c033 714 struct FDCtrl state;
1ca4d09a
GN		 715 int32_t bootindexA;
716 int32_t bootindexB;
5c02c033 717} FDCtrlISABus;
8baf73ad 718
baca51fa
FB		 719static uint32_t fdctrl_read (void *opaque, uint32_t reg)
720{
5c02c033 721 FDCtrl *fdctrl = opaque;
baca51fa
FB		 722 uint32_t retval;
723
a18e67f5 724 reg &= 7;
e64d7d59 725 switch (reg) {
8c6a4d77
BS		 726 case FD_REG_SRA:
727 retval = fdctrl_read_statusA(fdctrl);
4f431960 728 break;
8c6a4d77 729 case FD_REG_SRB:
4f431960
JM		 730 retval = fdctrl_read_statusB(fdctrl);
731 break;
9fea808a 732 case FD_REG_DOR:
4f431960
JM		 733 retval = fdctrl_read_dor(fdctrl);
734 break;
9fea808a 735 case FD_REG_TDR:
baca51fa 736 retval = fdctrl_read_tape(fdctrl);
4f431960 737 break;
9fea808a 738 case FD_REG_MSR:
baca51fa 739 retval = fdctrl_read_main_status(fdctrl);
4f431960 740 break;
9fea808a 741 case FD_REG_FIFO:
baca51fa 742 retval = fdctrl_read_data(fdctrl);
4f431960 743 break;
9fea808a 744 case FD_REG_DIR:
baca51fa 745 retval = fdctrl_read_dir(fdctrl);
4f431960 746 break;
a541f297 747 default:
4f431960
JM		 748 retval = (uint32_t)(-1);
749 break;
a541f297 750 }
ed5fd2cc 751 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
baca51fa
FB		 752
753 return retval;
754}
755
756static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
757{
5c02c033 758 FDCtrl *fdctrl = opaque;
baca51fa 759
ed5fd2cc
FB		 760 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
761
a18e67f5 762 reg &= 7;
e64d7d59 763 switch (reg) {
9fea808a 764 case FD_REG_DOR:
4f431960
JM		 765 fdctrl_write_dor(fdctrl, value);
766 break;
9fea808a 767 case FD_REG_TDR:
baca51fa 768 fdctrl_write_tape(fdctrl, value);
4f431960 769 break;
9fea808a 770 case FD_REG_DSR:
baca51fa 771 fdctrl_write_rate(fdctrl, value);
4f431960 772 break;
9fea808a 773 case FD_REG_FIFO:
baca51fa 774 fdctrl_write_data(fdctrl, value);
4f431960 775 break;
a758f8f4
HP		 776 case FD_REG_CCR:
777 fdctrl_write_ccr(fdctrl, value);
778 break;
a541f297 779 default:
4f431960 780 break;
a541f297 781 }
baca51fa
FB		 782}
783
a8170e5e 784static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 785 unsigned ize)
62a46c61 786{
5dcb6b91 787 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 788}
789
a8170e5e 790static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 791 uint64_t value, unsigned size)
62a46c61 792{
5dcb6b91 793 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 794}
795
dc6c1b37
AK		 796static const MemoryRegionOps fdctrl_mem_ops = {
797 .read = fdctrl_read_mem,
798 .write = fdctrl_write_mem,
799 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 800};
801
dc6c1b37
AK		 802static const MemoryRegionOps fdctrl_mem_strict_ops = {
803 .read = fdctrl_read_mem,
804 .write = fdctrl_write_mem,
805 .endianness = DEVICE_NATIVE_ENDIAN,
806 .valid = {
807 .min_access_size = 1,
808 .max_access_size = 1,
809 },
7c560456
BS		 810};
811
7d905f71
JW		 812static bool fdrive_media_changed_needed(void *opaque)
813{
814 FDrive *drive = opaque;
815
abb3e55b 816 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 817}
818
819static const VMStateDescription vmstate_fdrive_media_changed = {
820 .name = "fdrive/media_changed",
821 .version_id = 1,
822 .minimum_version_id = 1,
5cd8cada 823 .needed = fdrive_media_changed_needed,
d49805ae 824 .fields = (VMStateField[]) {
7d905f71
JW		 825 VMSTATE_UINT8(media_changed, FDrive),
826 VMSTATE_END_OF_LIST()
827 }
828};
829
844f65d6
HP		 830static bool fdrive_media_rate_needed(void *opaque)
831{
832 FDrive *drive = opaque;
833
834 return drive->fdctrl->check_media_rate;
835}
836
837static const VMStateDescription vmstate_fdrive_media_rate = {
838 .name = "fdrive/media_rate",
839 .version_id = 1,
840 .minimum_version_id = 1,
5cd8cada 841 .needed = fdrive_media_rate_needed,
d49805ae 842 .fields = (VMStateField[]) {
844f65d6
HP		 843 VMSTATE_UINT8(media_rate, FDrive),
844 VMSTATE_END_OF_LIST()
845 }
846};
847
c0b92f30
PD		 848static bool fdrive_perpendicular_needed(void *opaque)
849{
850 FDrive *drive = opaque;
851
852 return drive->perpendicular != 0;
853}
854
855static const VMStateDescription vmstate_fdrive_perpendicular = {
856 .name = "fdrive/perpendicular",
857 .version_id = 1,
858 .minimum_version_id = 1,
5cd8cada 859 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 860 .fields = (VMStateField[]) {
861 VMSTATE_UINT8(perpendicular, FDrive),
862 VMSTATE_END_OF_LIST()
863 }
864};
865
866static int fdrive_post_load(void *opaque, int version_id)
867{
868 fd_revalidate(opaque);
869 return 0;
870}
871
d7a6c270
JQ		 872static const VMStateDescription vmstate_fdrive = {
873 .name = "fdrive",
874 .version_id = 1,
875 .minimum_version_id = 1,
c0b92f30 876 .post_load = fdrive_post_load,
d49805ae 877 .fields = (VMStateField[]) {
5c02c033
BS		 878 VMSTATE_UINT8(head, FDrive),
879 VMSTATE_UINT8(track, FDrive),
880 VMSTATE_UINT8(sect, FDrive),
d7a6c270 881 VMSTATE_END_OF_LIST()
7d905f71 882 },
5cd8cada
JQ		 883 .subsections = (const VMStateDescription*[]) {
884 &vmstate_fdrive_media_changed,
885 &vmstate_fdrive_media_rate,
886 &vmstate_fdrive_perpendicular,
887 NULL
d7a6c270
JQ		 888 }
889};
3ccacc4a 890
85d291a0
KW		 891/*
892 * Reconstructs the phase from register values according to the logic that was
893 * implemented in qemu 2.3. This is the default value that is used if the phase
894 * subsection is not present on migration.
895 *
896 * Don't change this function to reflect newer qemu versions, it is part of
897 * the migration ABI.
898 */
899static int reconstruct_phase(FDCtrl *fdctrl)
900{
901 if (fdctrl->msr & FD_MSR_NONDMA) {
902 return FD_PHASE_EXECUTION;
903 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
904 /* qemu 2.3 disabled RQM only during DMA transfers */
905 return FD_PHASE_EXECUTION;
906 } else if (fdctrl->msr & FD_MSR_DIO) {
907 return FD_PHASE_RESULT;
908 } else {
909 return FD_PHASE_COMMAND;
910 }
911}
912
d4bfa4d7 913static void fdc_pre_save(void *opaque)
3ccacc4a 914{
5c02c033 915 FDCtrl *s = opaque;
3ccacc4a 916
d7a6c270 917 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
3ccacc4a
BS		 918}
919
85d291a0
KW		 920static int fdc_pre_load(void *opaque)
921{
922 FDCtrl *s = opaque;
923 s->phase = FD_PHASE_RECONSTRUCT;
924 return 0;
925}
926
e59fb374 927static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 928{
5c02c033 929 FDCtrl *s = opaque;
3ccacc4a 930
d7a6c270
JQ		 931 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
932 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 933
934 if (s->phase == FD_PHASE_RECONSTRUCT) {
935 s->phase = reconstruct_phase(s);
936 }
937
3ccacc4a
BS		 938 return 0;
939}
940
c0b92f30
PD		 941static bool fdc_reset_sensei_needed(void *opaque)
942{
943 FDCtrl *s = opaque;
944
945 return s->reset_sensei != 0;
946}
947
948static const VMStateDescription vmstate_fdc_reset_sensei = {
949 .name = "fdc/reset_sensei",
950 .version_id = 1,
951 .minimum_version_id = 1,
5cd8cada 952 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 953 .fields = (VMStateField[]) {
954 VMSTATE_INT32(reset_sensei, FDCtrl),
955 VMSTATE_END_OF_LIST()
956 }
957};
958
959static bool fdc_result_timer_needed(void *opaque)
960{
961 FDCtrl *s = opaque;
962
963 return timer_pending(s->result_timer);
964}
965
966static const VMStateDescription vmstate_fdc_result_timer = {
967 .name = "fdc/result_timer",
968 .version_id = 1,
969 .minimum_version_id = 1,
5cd8cada 970 .needed = fdc_result_timer_needed,
c0b92f30 971 .fields = (VMStateField[]) {
e720677e 972 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 973 VMSTATE_END_OF_LIST()
974 }
975};
976
85d291a0
KW		 977static bool fdc_phase_needed(void *opaque)
978{
979 FDCtrl *fdctrl = opaque;
980
981 return reconstruct_phase(fdctrl) != fdctrl->phase;
982}
983
984static const VMStateDescription vmstate_fdc_phase = {
985 .name = "fdc/phase",
986 .version_id = 1,
987 .minimum_version_id = 1,
5cd8cada 988 .needed = fdc_phase_needed,
85d291a0
KW		 989 .fields = (VMStateField[]) {
990 VMSTATE_UINT8(phase, FDCtrl),
991 VMSTATE_END_OF_LIST()
992 }
993};
994
d7a6c270 995static const VMStateDescription vmstate_fdc = {
aef30c3c 996 .name = "fdc",
d7a6c270
JQ		 997 .version_id = 2,
998 .minimum_version_id = 2,
d7a6c270 999 .pre_save = fdc_pre_save,
85d291a0 1000 .pre_load = fdc_pre_load,
d7a6c270 1001 .post_load = fdc_post_load,
d49805ae 1002 .fields = (VMStateField[]) {
d7a6c270 1003 /* Controller State */
5c02c033
BS		 1004 VMSTATE_UINT8(sra, FDCtrl),
1005 VMSTATE_UINT8(srb, FDCtrl),
1006 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1007 VMSTATE_UINT8(tdr, FDCtrl),
1008 VMSTATE_UINT8(dsr, FDCtrl),
1009 VMSTATE_UINT8(msr, FDCtrl),
1010 VMSTATE_UINT8(status0, FDCtrl),
1011 VMSTATE_UINT8(status1, FDCtrl),
1012 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1013 /* Command FIFO */
8ec68b06
BS		 1014 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1015 uint8_t),
5c02c033
BS		 1016 VMSTATE_UINT32(data_pos, FDCtrl),
1017 VMSTATE_UINT32(data_len, FDCtrl),
1018 VMSTATE_UINT8(data_state, FDCtrl),
1019 VMSTATE_UINT8(data_dir, FDCtrl),
1020 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1021 /* States kept only to be returned back */
5c02c033
BS		 1022 VMSTATE_UINT8(timer0, FDCtrl),
1023 VMSTATE_UINT8(timer1, FDCtrl),
1024 VMSTATE_UINT8(precomp_trk, FDCtrl),
1025 VMSTATE_UINT8(config, FDCtrl),
1026 VMSTATE_UINT8(lock, FDCtrl),
1027 VMSTATE_UINT8(pwrd, FDCtrl),
1028 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1029 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1030 vmstate_fdrive, FDrive),
d7a6c270 1031 VMSTATE_END_OF_LIST()
c0b92f30 1032 },
5cd8cada
JQ		 1033 .subsections = (const VMStateDescription*[]) {
1034 &vmstate_fdc_reset_sensei,
1035 &vmstate_fdc_result_timer,
1036 &vmstate_fdc_phase,
1037 NULL
78ae820c 1038 }
d7a6c270 1039};
3ccacc4a 1040
2be37833 1041static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1042{
dd3be742 1043 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1044 FDCtrl *s = &sys->state;
2be37833
BS		 1045
1046 fdctrl_reset(s, 0);
1047}
1048
1049static void fdctrl_external_reset_isa(DeviceState *d)
1050{
020c8e76 1051 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1052 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1053
1054 fdctrl_reset(s, 0);
1055}
1056
2be17ebd
BS		 1057static void fdctrl_handle_tc(void *opaque, int irq, int level)
1058{
5c02c033 1059 //FDCtrl *s = opaque;
2be17ebd
BS		 1060
1061 if (level) {
1062 // XXX
1063 FLOPPY_DPRINTF("TC pulsed\n");
1064 }
1065}
1066
8977f3c1 1067/* Change IRQ state */
5c02c033 1068static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1069{
d497d534 1070 fdctrl->status0 = 0;
8c6a4d77
BS		 1071 if (!(fdctrl->sra & FD_SRA_INTPEND))
1072 return;
ed5fd2cc 1073 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1074 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1075 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1076}
1077
d497d534 1078static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1079{
8c6a4d77 1080 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1081 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1082 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1083 }
21fcf360 1084
f2d81b33 1085 fdctrl->reset_sensei = 0;
77370520 1086 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1087}
1088
4b19ec0c 1089/* Reset controller */
5c02c033 1090static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1091{
1092 int i;
1093
4b19ec0c 1094 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1095 fdctrl_reset_irq(fdctrl);
4b19ec0c 1096 /* Initialise controller */
8c6a4d77
BS		 1097 fdctrl->sra = 0;
1098 fdctrl->srb = 0xc0;
4be74634 1099 if (!fdctrl->drives[1].blk) {
8c6a4d77 1100 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1101 }
baca51fa 1102 fdctrl->cur_drv = 0;
1c346df2 1103 fdctrl->dor = FD_DOR_nRESET;
368df94d 1104 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1105 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1106 fdctrl->reset_sensei = 0;
1107 timer_del(fdctrl->result_timer);
8977f3c1 1108 /* FIFO state */
baca51fa
FB		 1109 fdctrl->data_pos = 0;
1110 fdctrl->data_len = 0;
b9b3d225 1111 fdctrl->data_state = 0;
baca51fa 1112 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1113 for (i = 0; i < MAX_FD; i++)
1c346df2 1114 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1115 fdctrl_to_command_phase(fdctrl);
77370520 1116 if (do_irq) {
d497d534
HP		 1117 fdctrl->status0 |= FD_SR0_RDYCHG;
1118 fdctrl_raise_irq(fdctrl);
f2d81b33 1119 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1120 }
baca51fa
FB		 1121}
1122
5c02c033 1123static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1124{
46d3233b 1125 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1126}
1127
5c02c033 1128static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1129{
46d3233b
BS		 1130 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1131 return &fdctrl->drives[1];
1132 else
1133 return &fdctrl->drives[0];
baca51fa
FB		 1134}
1135
78ae820c 1136#if MAX_FD == 4
5c02c033 1137static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1138{
1139 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1140 return &fdctrl->drives[2];
1141 else
1142 return &fdctrl->drives[1];
1143}
1144
5c02c033 1145static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1146{
1147 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1148 return &fdctrl->drives[3];
1149 else
1150 return &fdctrl->drives[2];
1151}
1152#endif
1153
5c02c033 1154static FDrive *get_cur_drv(FDCtrl *fdctrl)
baca51fa 1155{
78ae820c
BS		 1156 switch (fdctrl->cur_drv) {
1157 case 0: return drv0(fdctrl);
1158 case 1: return drv1(fdctrl);
1159#if MAX_FD == 4
1160 case 2: return drv2(fdctrl);
1161 case 3: return drv3(fdctrl);
1162#endif
1163 default: return NULL;
1164 }
8977f3c1
FB		 1165}
1166
8c6a4d77 1167/* Status A register : 0x00 (read-only) */
5c02c033 1168static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1169{
1170 uint32_t retval = fdctrl->sra;
1171
1172 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1173
1174 return retval;
1175}
1176
8977f3c1 1177/* Status B register : 0x01 (read-only) */
5c02c033 1178static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1179{
8c6a4d77
BS		 1180 uint32_t retval = fdctrl->srb;
1181
1182 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1183
1184 return retval;
8977f3c1
FB		 1185}
1186
1187/* Digital output register : 0x02 */
5c02c033 1188static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1189{
1c346df2 1190 uint32_t retval = fdctrl->dor;
8977f3c1 1191
8977f3c1 1192 /* Selected drive */
baca51fa 1193 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1194 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1195
1196 return retval;
1197}
1198
5c02c033 1199static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1200{
8977f3c1 1201 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1202
1203 /* Motors */
1204 if (value & FD_DOR_MOTEN0)
1205 fdctrl->srb |= FD_SRB_MTR0;
1206 else
1207 fdctrl->srb &= ~FD_SRB_MTR0;
1208 if (value & FD_DOR_MOTEN1)
1209 fdctrl->srb |= FD_SRB_MTR1;
1210 else
1211 fdctrl->srb &= ~FD_SRB_MTR1;
1212
1213 /* Drive */
1214 if (value & 1)
1215 fdctrl->srb |= FD_SRB_DR0;
1216 else
1217 fdctrl->srb &= ~FD_SRB_DR0;
1218
8977f3c1 1219 /* Reset */
9fea808a 1220 if (!(value & FD_DOR_nRESET)) {
1c346df2 1221 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1222 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1223 }
1224 } else {
1c346df2 1225 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1226 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1227 fdctrl_reset(fdctrl, 1);
b9b3d225 1228 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1229 }
1230 }
1231 /* Selected drive */
9fea808a 1232 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1233
1234 fdctrl->dor = value;
8977f3c1
FB		 1235}
1236
1237/* Tape drive register : 0x03 */
5c02c033 1238static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1239{
46d3233b 1240 uint32_t retval = fdctrl->tdr;
8977f3c1 1241
8977f3c1
FB		 1242 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1243
1244 return retval;
1245}
1246
5c02c033 1247static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1248{
8977f3c1 1249 /* Reset mode */
1c346df2 1250 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1251 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1252 return;
1253 }
1254 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1255 /* Disk boot selection indicator */
46d3233b 1256 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1257 /* Tape indicators: never allow */
1258}
1259
1260/* Main status register : 0x04 (read) */
5c02c033 1261static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1262{
b9b3d225 1263 uint32_t retval = fdctrl->msr;
8977f3c1 1264
b9b3d225 1265 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1266 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1267
8977f3c1
FB		 1268 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1269
1270 return retval;
1271}
1272
1273/* Data select rate register : 0x04 (write) */
5c02c033 1274static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1275{
8977f3c1 1276 /* Reset mode */
1c346df2 1277 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1278 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1279 return;
1280 }
8977f3c1
FB		 1281 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1282 /* Reset: autoclear */
9fea808a 1283 if (value & FD_DSR_SWRESET) {
1c346df2 1284 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1285 fdctrl_reset(fdctrl, 1);
1c346df2 1286 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1287 }
9fea808a 1288 if (value & FD_DSR_PWRDOWN) {
baca51fa 1289 fdctrl_reset(fdctrl, 1);
8977f3c1 1290 }
b9b3d225 1291 fdctrl->dsr = value;
8977f3c1
FB		 1292}
1293
a758f8f4
HP		 1294/* Configuration control register: 0x07 (write) */
1295static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1296{
1297 /* Reset mode */
1298 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1299 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1300 return;
1301 }
1302 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1303
1304 /* Only the rate selection bits used in AT mode, and we
1305 * store those in the DSR.
1306 */
1307 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1308 (value & FD_DSR_DRATEMASK);
1309}
1310
5c02c033 1311static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1312{
21fcf360 1313 return drv->media_changed;
ea185bbd
FB		 1314}
1315
8977f3c1 1316/* Digital input register : 0x07 (read-only) */
5c02c033 1317static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1318{
8977f3c1
FB		 1319 uint32_t retval = 0;
1320
a2df5fa3 1321 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1322 retval |= FD_DIR_DSKCHG;
a2df5fa3 1323 }
3c83eb4f 1324 if (retval != 0) {
baca51fa 1325 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1326 }
8977f3c1
FB		 1327
1328 return retval;
1329}
1330
07e415f2
KW		 1331/* Clear the FIFO and update the state for receiving the next command */
1332static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1333{
85d291a0 1334 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1335 fdctrl->data_dir = FD_DIR_WRITE;
1336 fdctrl->data_pos = 0;
6cc8a11c 1337 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1338 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1339 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1340}
1341
83a26013
KW		 1342/* Update the state to allow the guest to read out the command status.
1343 * @fifo_len is the number of result bytes to be read out. */
1344static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1345{
85d291a0 1346 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1347 fdctrl->data_dir = FD_DIR_READ;
1348 fdctrl->data_len = fifo_len;
1349 fdctrl->data_pos = 0;
b9b3d225 1350 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1351}
1352
1353/* Set an error: unimplemented/unknown command */
5c02c033 1354static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1355{
cced7a13
BS		 1356 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1357 fdctrl->fifo[0]);
9fea808a 1358 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1359 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1360}
1361
6be01b1e
PH		 1362/* Seek to next sector
1363 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1364 * otherwise returns 1
1365 */
5c02c033 1366static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1367{
1368 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1369 cur_drv->head, cur_drv->track, cur_drv->sect,
1370 fd_sector(cur_drv));
1371 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1372 error in fact */
6be01b1e
PH		 1373 uint8_t new_head = cur_drv->head;
1374 uint8_t new_track = cur_drv->track;
1375 uint8_t new_sect = cur_drv->sect;
1376
1377 int ret = 1;
1378
1379 if (new_sect >= cur_drv->last_sect ||
1380 new_sect == fdctrl->eot) {
1381 new_sect = 1;
746d6de7 1382 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1383 if (new_head == 0 &&
746d6de7 1384 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1385 new_head = 1;
746d6de7 1386 } else {
6be01b1e
PH		 1387 new_head = 0;
1388 new_track++;
c5139bd9 1389 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1390 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1391 ret = 0;
1392 }
746d6de7
BS		 1393 }
1394 } else {
c5139bd9 1395 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1396 new_track++;
1397 ret = 0;
1398 }
1399 if (ret == 1) {
1400 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1401 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1402 }
746d6de7 1403 } else {
6be01b1e 1404 new_sect++;
746d6de7 1405 }
6be01b1e
PH		 1406 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1407 return ret;
746d6de7
BS		 1408}
1409
8977f3c1 1410/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1411static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1412 uint8_t status1, uint8_t status2)
8977f3c1 1413{
5c02c033 1414 FDrive *cur_drv;
baca51fa 1415 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1416
1417 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1418 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1419 if (cur_drv->head) {
1420 fdctrl->status0 |= FD_SR0_HEAD;
1421 }
1422 fdctrl->status0 |= status0;
2fee0088 1423
8977f3c1 1424 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1425 status0, status1, status2, fdctrl->status0);
1426 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1427 fdctrl->fifo[1] = status1;
1428 fdctrl->fifo[2] = status2;
1429 fdctrl->fifo[3] = cur_drv->track;
1430 fdctrl->fifo[4] = cur_drv->head;
1431 fdctrl->fifo[5] = cur_drv->sect;
1432 fdctrl->fifo[6] = FD_SECTOR_SC;
1433 fdctrl->data_dir = FD_DIR_READ;
368df94d 1434 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1435 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1436 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1437 }
b9b3d225 1438 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1439 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1440
83a26013 1441 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1442 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1443}
1444
1445/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1446static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1447{
5c02c033 1448 FDrive *cur_drv;
8977f3c1 1449 uint8_t kh, kt, ks;
8977f3c1 1450
cefec4f5 1451 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1452 cur_drv = get_cur_drv(fdctrl);
1453 kt = fdctrl->fifo[2];
1454 kh = fdctrl->fifo[3];
1455 ks = fdctrl->fifo[4];
4b19ec0c 1456 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1457 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1458 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1459 NUM_SIDES(cur_drv)));
77370520 1460 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1461 case 2:
1462 /* sect too big */
9fea808a 1463 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1464 fdctrl->fifo[3] = kt;
1465 fdctrl->fifo[4] = kh;
1466 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1467 return;
1468 case 3:
1469 /* track too big */
77370520 1470 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1471 fdctrl->fifo[3] = kt;
1472 fdctrl->fifo[4] = kh;
1473 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1474 return;
1475 case 4:
1476 /* No seek enabled */
9fea808a 1477 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1478 fdctrl->fifo[3] = kt;
1479 fdctrl->fifo[4] = kh;
1480 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1481 return;
1482 case 1:
d6ed4e21 1483 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1484 break;
1485 default:
1486 break;
1487 }
b9b3d225 1488
844f65d6
HP		 1489 /* Check the data rate. If the programmed data rate does not match
1490 * the currently inserted medium, the operation has to fail. */
1491 if (fdctrl->check_media_rate &&
1492 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1493 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1494 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1495 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1496 fdctrl->fifo[3] = kt;
1497 fdctrl->fifo[4] = kh;
1498 fdctrl->fifo[5] = ks;
1499 return;
1500 }
1501
8977f3c1 1502 /* Set the FIFO state */
baca51fa
FB		 1503 fdctrl->data_dir = direction;
1504 fdctrl->data_pos = 0;
27c86e24 1505 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1506 if (fdctrl->fifo[0] & 0x80)
1507 fdctrl->data_state |= FD_STATE_MULTI;
1508 else
1509 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1510 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1511 fdctrl->data_len = fdctrl->fifo[8];
1512 } else {
4f431960 1513 int tmp;
3bcb80f1 1514 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1515 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1516 if (fdctrl->fifo[0] & 0x80)
771effeb 1517 tmp += fdctrl->fifo[6];
4f431960 1518 fdctrl->data_len *= tmp;
baca51fa 1519 }
890fa6be 1520 fdctrl->eot = fdctrl->fifo[6];
368df94d 1521 if (fdctrl->dor & FD_DOR_DMAEN) {
c8a35f1c
HP		 1522 IsaDmaTransferMode dma_mode;
1523 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1524 bool dma_mode_ok;
8977f3c1 1525 /* DMA transfer are enabled. Check if DMA channel is well programmed */
c8a35f1c 1526 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
baca51fa 1527 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1528 dma_mode, direction,
baca51fa 1529 (128 << fdctrl->fifo[5]) *
4f431960 1530 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
c8a35f1c
HP		 1531 switch (direction) {
1532 case FD_DIR_SCANE:
1533 case FD_DIR_SCANL:
1534 case FD_DIR_SCANH:
1535 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1536 break;
1537 case FD_DIR_WRITE:
1538 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1539 break;
1540 case FD_DIR_READ:
1541 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1542 break;
1543 case FD_DIR_VERIFY:
1544 dma_mode_ok = true;
1545 break;
1546 default:
1547 dma_mode_ok = false;
1548 break;
1549 }
1550 if (dma_mode_ok) {
8977f3c1 1551 /* No access is allowed until DMA transfer has completed */
b9b3d225 1552 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1553 if (direction != FD_DIR_VERIFY) {
1554 /* Now, we just have to wait for the DMA controller to
1555 * recall us...
1556 */
c8a35f1c
HP		 1557 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1558 k->schedule(fdctrl->dma);
7ea004ed
HP		 1559 } else {
1560 /* Start transfer */
1561 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1562 fdctrl->data_len);
1563 }
8977f3c1 1564 return;
baca51fa 1565 } else {
cced7a13
BS		 1566 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1567 direction);
8977f3c1
FB		 1568 }
1569 }
1570 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1571 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1572 if (direction != FD_DIR_WRITE)
1573 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1574 /* IO based transfer: calculate len */
d497d534 1575 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1576}
1577
1578/* Prepare a transfer of deleted data */
5c02c033 1579static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1580{
cced7a13 1581 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1582
8977f3c1
FB		 1583 /* We don't handle deleted data,
1584 * so we don't return *ANYTHING*
1585 */
9fea808a 1586 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1587}
1588
1589/* handlers for DMA transfers */
85571bc7
FB		 1590static int fdctrl_transfer_handler (void *opaque, int nchan,
1591 int dma_pos, int dma_len)
8977f3c1 1592{
5c02c033
BS		 1593 FDCtrl *fdctrl;
1594 FDrive *cur_drv;
baca51fa 1595 int len, start_pos, rel_pos;
8977f3c1 1596 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1597 IsaDmaClass *k;
8977f3c1 1598
baca51fa 1599 fdctrl = opaque;
b9b3d225 1600 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1601 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1602 return 0;
1603 }
c8a35f1c 1604 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1605 cur_drv = get_cur_drv(fdctrl);
1606 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1607 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1608 status2 = FD_SR2_SNS;
85571bc7
FB		 1609 if (dma_len > fdctrl->data_len)
1610 dma_len = fdctrl->data_len;
4be74634 1611 if (cur_drv->blk == NULL) {
4f431960 1612 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1613 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1614 else
9fea808a 1615 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1616 len = 0;
890fa6be
FB		 1617 goto transfer_error;
1618 }
baca51fa 1619 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1620 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1621 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1622 if (len + rel_pos > FD_SECTOR_LEN)
1623 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1624 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1625 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1626 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1627 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1628 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1629 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1630 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1631 /* READ & SCAN commands and realign to a sector for WRITE */
4be74634
MA		 1632 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1633 fdctrl->fifo, 1) < 0) {
8977f3c1
FB		 1634 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1635 fd_sector(cur_drv));
1636 /* Sure, image size is too small... */
baca51fa 1637 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1638 }
890fa6be 1639 }
4f431960
JM		 1640 switch (fdctrl->data_dir) {
1641 case FD_DIR_READ:
1642 /* READ commands */
c8a35f1c
HP		 1643 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1644 fdctrl->data_pos, len);
4f431960
JM		 1645 break;
1646 case FD_DIR_WRITE:
baca51fa 1647 /* WRITE commands */
8510854e
HP		 1648 if (cur_drv->ro) {
1649 /* Handle readonly medium early, no need to do DMA, touch the
1650 * LED or attempt any writes. A real floppy doesn't attempt
1651 * to write to readonly media either. */
1652 fdctrl_stop_transfer(fdctrl,
1653 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1654 0x00);
1655 goto transfer_error;
1656 }
1657
c8a35f1c
HP		 1658 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1659 fdctrl->data_pos, len);
4be74634
MA		 1660 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1661 fdctrl->fifo, 1) < 0) {
cced7a13
BS		 1662 FLOPPY_DPRINTF("error writing sector %d\n",
1663 fd_sector(cur_drv));
9fea808a 1664 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1665 goto transfer_error;
890fa6be 1666 }
4f431960 1667 break;
7ea004ed
HP		 1668 case FD_DIR_VERIFY:
1669 /* VERIFY commands */
1670 break;
4f431960
JM		 1671 default:
1672 /* SCAN commands */
baca51fa 1673 {
4f431960 1674 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1675 int ret;
c8a35f1c
HP		 1676 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1677 len);
baca51fa 1678 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1679 if (ret == 0) {
77370520 1680 status2 = FD_SR2_SEH;
8977f3c1
FB		 1681 goto end_transfer;
1682 }
baca51fa
FB		 1683 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1684 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1685 status2 = 0x00;
1686 goto end_transfer;
1687 }
1688 }
4f431960 1689 break;
8977f3c1 1690 }
4f431960
JM		 1691 fdctrl->data_pos += len;
1692 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1693 if (rel_pos == 0) {
8977f3c1 1694 /* Seek to next sector */
746d6de7
BS		 1695 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1696 break;
8977f3c1
FB		 1697 }
1698 }
4f431960 1699 end_transfer:
baca51fa
FB		 1700 len = fdctrl->data_pos - start_pos;
1701 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1702 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1703 if (fdctrl->data_dir == FD_DIR_SCANE ||
1704 fdctrl->data_dir == FD_DIR_SCANL ||
1705 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1706 status2 = FD_SR2_SEH;
baca51fa 1707 fdctrl->data_len -= len;
890fa6be 1708 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1709 transfer_error:
8977f3c1 1710
baca51fa 1711 return len;
8977f3c1
FB		 1712}
1713
8977f3c1 1714/* Data register : 0x05 */
5c02c033 1715static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1716{
5c02c033 1717 FDrive *cur_drv;
8977f3c1 1718 uint32_t retval = 0;
e9077462 1719 uint32_t pos;
8977f3c1 1720
baca51fa 1721 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1722 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1723 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1724 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1725 return 0;
1726 }
f6c2d1d8
KW		 1727
1728 /* If data_len spans multiple sectors, the current position in the FIFO
1729 * wraps around while fdctrl->data_pos is the real position in the whole
1730 * request. */
baca51fa 1731 pos = fdctrl->data_pos;
e9077462 1732 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1733
1734 switch (fdctrl->phase) {
1735 case FD_PHASE_EXECUTION:
1736 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1737 if (pos == 0) {
746d6de7
BS		 1738 if (fdctrl->data_pos != 0)
1739 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1740 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1741 fd_sector(cur_drv));
1742 return 0;
1743 }
4be74634
MA		 1744 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1745 < 0) {
77370520
BS		 1746 FLOPPY_DPRINTF("error getting sector %d\n",
1747 fd_sector(cur_drv));
1748 /* Sure, image size is too small... */
1749 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1750 }
8977f3c1 1751 }
f6c2d1d8
KW		 1752
1753 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1754 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1755 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1756 }
1757 break;
1758
1759 case FD_PHASE_RESULT:
1760 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1761 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1762 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1763 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1764 fdctrl_reset_irq(fdctrl);
1765 }
f6c2d1d8
KW		 1766 break;
1767
1768 case FD_PHASE_COMMAND:
1769 default:
1770 abort();
8977f3c1 1771 }
f6c2d1d8
KW		 1772
1773 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1774 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1775
1776 return retval;
1777}
1778
5c02c033 1779static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1780{
5c02c033 1781 FDrive *cur_drv;
baca51fa 1782 uint8_t kh, kt, ks;
8977f3c1 1783
cefec4f5 1784 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1785 cur_drv = get_cur_drv(fdctrl);
1786 kt = fdctrl->fifo[6];
1787 kh = fdctrl->fifo[7];
1788 ks = fdctrl->fifo[8];
1789 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1790 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1791 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1792 NUM_SIDES(cur_drv)));
9fea808a 1793 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1794 case 2:
1795 /* sect too big */
9fea808a 1796 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1797 fdctrl->fifo[3] = kt;
1798 fdctrl->fifo[4] = kh;
1799 fdctrl->fifo[5] = ks;
1800 return;
1801 case 3:
1802 /* track too big */
77370520 1803 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1804 fdctrl->fifo[3] = kt;
1805 fdctrl->fifo[4] = kh;
1806 fdctrl->fifo[5] = ks;
1807 return;
1808 case 4:
1809 /* No seek enabled */
9fea808a 1810 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1811 fdctrl->fifo[3] = kt;
1812 fdctrl->fifo[4] = kh;
1813 fdctrl->fifo[5] = ks;
1814 return;
1815 case 1:
cd30b53d 1816 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 1817 break;
1818 default:
1819 break;
1820 }
1821 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634
MA		 1822 if (cur_drv->blk == NULL ||
1823 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
cced7a13 1824 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 1825 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1826 } else {
4f431960
JM		 1827 if (cur_drv->sect == cur_drv->last_sect) {
1828 fdctrl->data_state &= ~FD_STATE_FORMAT;
1829 /* Last sector done */
cd30b53d 1830 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 1831 } else {
1832 /* More to do */
1833 fdctrl->data_pos = 0;
1834 fdctrl->data_len = 4;
1835 }
baca51fa
FB		 1836 }
1837}
1838
5c02c033 1839static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 1840{
1841 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1842 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 1843 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1844}
1845
5c02c033 1846static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 1847{
5c02c033 1848 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1849
1850 /* Drives position */
1851 fdctrl->fifo[0] = drv0(fdctrl)->track;
1852 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 1853#if MAX_FD == 4
1854 fdctrl->fifo[2] = drv2(fdctrl)->track;
1855 fdctrl->fifo[3] = drv3(fdctrl)->track;
1856#else
65cef780
BS		 1857 fdctrl->fifo[2] = 0;
1858 fdctrl->fifo[3] = 0;
78ae820c 1859#endif
65cef780
BS		 1860 /* timers */
1861 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 1862 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 1863 fdctrl->fifo[6] = cur_drv->last_sect;
1864 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1865 (cur_drv->perpendicular << 2);
1866 fdctrl->fifo[8] = fdctrl->config;
1867 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 1868 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 1869}
1870
5c02c033 1871static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 1872{
1873 /* Controller's version */
1874 fdctrl->fifo[0] = fdctrl->version;
83a26013 1875 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1876}
1877
5c02c033 1878static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 1879{
1880 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 1881 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1882}
1883
5c02c033 1884static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 1885{
5c02c033 1886 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1887
1888 /* Drives position */
1889 drv0(fdctrl)->track = fdctrl->fifo[3];
1890 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 1891#if MAX_FD == 4
1892 drv2(fdctrl)->track = fdctrl->fifo[5];
1893 drv3(fdctrl)->track = fdctrl->fifo[6];
1894#endif
65cef780
BS		 1895 /* timers */
1896 fdctrl->timer0 = fdctrl->fifo[7];
1897 fdctrl->timer1 = fdctrl->fifo[8];
1898 cur_drv->last_sect = fdctrl->fifo[9];
1899 fdctrl->lock = fdctrl->fifo[10] >> 7;
1900 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1901 fdctrl->config = fdctrl->fifo[11];
1902 fdctrl->precomp_trk = fdctrl->fifo[12];
1903 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 1904 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1905}
1906
5c02c033 1907static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 1908{
5c02c033 1909 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1910
1911 fdctrl->fifo[0] = 0;
1912 fdctrl->fifo[1] = 0;
1913 /* Drives position */
1914 fdctrl->fifo[2] = drv0(fdctrl)->track;
1915 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 1916#if MAX_FD == 4
1917 fdctrl->fifo[4] = drv2(fdctrl)->track;
1918 fdctrl->fifo[5] = drv3(fdctrl)->track;
1919#else
65cef780
BS		 1920 fdctrl->fifo[4] = 0;
1921 fdctrl->fifo[5] = 0;
78ae820c 1922#endif
65cef780
BS		 1923 /* timers */
1924 fdctrl->fifo[6] = fdctrl->timer0;
1925 fdctrl->fifo[7] = fdctrl->timer1;
1926 fdctrl->fifo[8] = cur_drv->last_sect;
1927 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1928 (cur_drv->perpendicular << 2);
1929 fdctrl->fifo[10] = fdctrl->config;
1930 fdctrl->fifo[11] = fdctrl->precomp_trk;
1931 fdctrl->fifo[12] = fdctrl->pwrd;
1932 fdctrl->fifo[13] = 0;
1933 fdctrl->fifo[14] = 0;
83a26013 1934 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 1935}
1936
5c02c033 1937static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 1938{
5c02c033 1939 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1940
65cef780 1941 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 1942 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1943 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 1944}
1945
5c02c033 1946static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 1947{
5c02c033 1948 FDrive *cur_drv;
65cef780 1949
cefec4f5 1950 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1951 cur_drv = get_cur_drv(fdctrl);
1952 fdctrl->data_state |= FD_STATE_FORMAT;
1953 if (fdctrl->fifo[0] & 0x80)
1954 fdctrl->data_state |= FD_STATE_MULTI;
1955 else
1956 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 1957 cur_drv->bps =
1958 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1959#if 0
1960 cur_drv->last_sect =
1961 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1962 fdctrl->fifo[3] / 2;
1963#else
1964 cur_drv->last_sect = fdctrl->fifo[3];
1965#endif
1966 /* TODO: implement format using DMA expected by the Bochs BIOS
1967 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1968 * the sector with the specified fill byte
1969 */
1970 fdctrl->data_state &= ~FD_STATE_FORMAT;
1971 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1972}
1973
5c02c033 1974static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 1975{
1976 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1977 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 1978 if (fdctrl->fifo[2] & 1)
1979 fdctrl->dor &= ~FD_DOR_DMAEN;
1980 else
1981 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 1982 /* No result back */
07e415f2 1983 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1984}
1985
5c02c033 1986static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 1987{
5c02c033 1988 FDrive *cur_drv;
65cef780 1989
cefec4f5 1990 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1991 cur_drv = get_cur_drv(fdctrl);
1992 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1993 /* 1 Byte status back */
1994 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1995 (cur_drv->track == 0 ? 0x10 : 0x00) |
1996 (cur_drv->head << 2) |
cefec4f5 1997 GET_CUR_DRV(fdctrl) |
65cef780 1998 0x28;
83a26013 1999 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2000}
2001
5c02c033 2002static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2003{
5c02c033 2004 FDrive *cur_drv;
65cef780 2005
cefec4f5 2006 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2007 cur_drv = get_cur_drv(fdctrl);
2008 fd_recalibrate(cur_drv);
07e415f2 2009 fdctrl_to_command_phase(fdctrl);
65cef780 2010 /* Raise Interrupt */
d497d534
HP		 2011 fdctrl->status0 |= FD_SR0_SEEK;
2012 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2013}
2014
5c02c033 2015static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2016{
5c02c033 2017 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2018
2fee0088 2019 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2020 fdctrl->fifo[0] =
2021 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2022 fdctrl->reset_sensei--;
2fee0088
PH		 2023 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2024 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2025 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2026 return;
f2d81b33 2027 } else {
f2d81b33 2028 fdctrl->fifo[0] =
2fee0088
PH		 2029 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2030 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2031 }
2032
65cef780 2033 fdctrl->fifo[1] = cur_drv->track;
83a26013 2034 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2035 fdctrl_reset_irq(fdctrl);
77370520 2036 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2037}
2038
5c02c033 2039static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2040{
5c02c033 2041 FDrive *cur_drv;
65cef780 2042
cefec4f5 2043 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2044 cur_drv = get_cur_drv(fdctrl);
07e415f2 2045 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2046 /* The seek command just sends step pulses to the drive and doesn't care if
2047 * there is a medium inserted of if it's banging the head against the drive.
2048 */
6be01b1e 2049 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2050 /* Raise Interrupt */
d497d534
HP		 2051 fdctrl->status0 |= FD_SR0_SEEK;
2052 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2053}
2054
5c02c033 2055static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2056{
5c02c033 2057 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2058
2059 if (fdctrl->fifo[1] & 0x80)
2060 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2061 /* No result back */
07e415f2 2062 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2063}
2064
5c02c033 2065static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2066{
2067 fdctrl->config = fdctrl->fifo[2];
2068 fdctrl->precomp_trk = fdctrl->fifo[3];
2069 /* No result back */
07e415f2 2070 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2071}
2072
5c02c033 2073static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2074{
2075 fdctrl->pwrd = fdctrl->fifo[1];
2076 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2077 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2078}
2079
5c02c033 2080static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2081{
2082 /* No result back */
07e415f2 2083 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2084}
2085
5c02c033 2086static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2087{
5c02c033 2088 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2089 uint32_t pos;
65cef780 2090
e9077462
PM		 2091 pos = fdctrl->data_pos - 1;
2092 pos %= FD_SECTOR_LEN;
2093 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2094 /* Command parameters done */
e9077462 2095 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2096 fdctrl->fifo[0] = fdctrl->fifo[1];
2097 fdctrl->fifo[2] = 0;
2098 fdctrl->fifo[3] = 0;
83a26013 2099 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2100 } else {
07e415f2 2101 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2102 }
2103 } else if (fdctrl->data_len > 7) {
2104 /* ERROR */
2105 fdctrl->fifo[0] = 0x80 |
cefec4f5 2106 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2107 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2108 }
2109}
2110
6d013772 2111static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2112{
5c02c033 2113 FDrive *cur_drv;
65cef780 2114
cefec4f5 2115 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2116 cur_drv = get_cur_drv(fdctrl);
65cef780 2117 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2118 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2119 cur_drv->sect, 1);
65cef780 2120 } else {
6d013772
PH		 2121 fd_seek(cur_drv, cur_drv->head,
2122 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2123 }
07e415f2 2124 fdctrl_to_command_phase(fdctrl);
77370520 2125 /* Raise Interrupt */
d497d534
HP		 2126 fdctrl->status0 |= FD_SR0_SEEK;
2127 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2128}
2129
6d013772 2130static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2131{
5c02c033 2132 FDrive *cur_drv;
65cef780 2133
cefec4f5 2134 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2135 cur_drv = get_cur_drv(fdctrl);
65cef780 2136 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2137 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2138 } else {
6d013772
PH		 2139 fd_seek(cur_drv, cur_drv->head,
2140 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2141 }
07e415f2 2142 fdctrl_to_command_phase(fdctrl);
65cef780 2143 /* Raise Interrupt */
d497d534
HP		 2144 fdctrl->status0 |= FD_SR0_SEEK;
2145 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2146}
2147
85d291a0
KW		 2148/*
2149 * Handlers for the execution phase of each command
2150 */
d275b33d 2151typedef struct FDCtrlCommand {
678803ab
BS		 2152 uint8_t value;
2153 uint8_t mask;
2154 const char* name;
2155 int parameters;
5c02c033 2156 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2157 int direction;
d275b33d
KW		 2158} FDCtrlCommand;
2159
2160static const FDCtrlCommand handlers[] = {
678803ab
BS		 2161 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2162 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2163 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2164 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2165 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2166 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2167 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2168 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2169 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2170 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2171 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2172 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2173 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2174 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2175 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2176 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2177 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2178 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2179 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2180 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2181 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2182 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2183 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2184 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2185 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2186 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2187 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2188 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2189 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2190 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2191 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2192 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2193};
2194/* Associate command to an index in the 'handlers' array */
2195static uint8_t command_to_handler[256];
2196
d275b33d
KW		 2197static const FDCtrlCommand *get_command(uint8_t cmd)
2198{
2199 int idx;
2200
2201 idx = command_to_handler[cmd];
2202 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2203 return &handlers[idx];
2204}
2205
5c02c033 2206static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2207{
5c02c033 2208 FDrive *cur_drv;
d275b33d 2209 const FDCtrlCommand *cmd;
e9077462 2210 uint32_t pos;
baca51fa 2211
8977f3c1 2212 /* Reset mode */
1c346df2 2213 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2214 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2215 return;
2216 }
b9b3d225 2217 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2218 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2219 return;
2220 }
b9b3d225 2221 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2222
d275b33d
KW		 2223 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2224
2225 /* If data_len spans multiple sectors, the current position in the FIFO
2226 * wraps around while fdctrl->data_pos is the real position in the whole
2227 * request. */
2228 pos = fdctrl->data_pos++;
2229 pos %= FD_SECTOR_LEN;
2230 fdctrl->fifo[pos] = value;
2231
6cc8a11c
KW		 2232 if (fdctrl->data_pos == fdctrl->data_len) {
2233 fdctrl->msr &= ~FD_MSR_RQM;
2234 }
2235
5b0a25e8
KW		 2236 switch (fdctrl->phase) {
2237 case FD_PHASE_EXECUTION:
2238 /* For DMA requests, RQM should be cleared during execution phase, so
2239 * we would have errored out above. */
2240 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2241
8977f3c1 2242 /* FIFO data write */
b3bc1540 2243 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2244 fdctrl->data_pos == fdctrl->data_len) {
77370520 2245 cur_drv = get_cur_drv(fdctrl);
4be74634
MA		 2246 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
2247 < 0) {
cced7a13
BS		 2248 FLOPPY_DPRINTF("error writing sector %d\n",
2249 fd_sector(cur_drv));
5b0a25e8 2250 break;
77370520 2251 }
746d6de7
BS		 2252 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2253 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2254 fd_sector(cur_drv));
5b0a25e8 2255 break;
746d6de7 2256 }
8977f3c1 2257 }
d275b33d
KW		 2258
2259 /* Switch to result phase when done with the transfer */
2260 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2261 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2262 }
5b0a25e8 2263 break;
678803ab 2264
5b0a25e8
KW		 2265 case FD_PHASE_COMMAND:
2266 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2267 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2268
d275b33d
KW		 2269 if (pos == 0) {
2270 /* The first byte specifies the command. Now we start reading
2271 * as many parameters as this command requires. */
2272 cmd = get_command(value);
2273 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2274 if (cmd->parameters) {
2275 fdctrl->msr |= FD_MSR_RQM;
2276 }
5b0a25e8 2277 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2278 }
65cef780 2279
5b0a25e8 2280 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2281 /* We have all parameters now, execute the command */
5b0a25e8 2282 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2283
5b0a25e8
KW		 2284 if (fdctrl->data_state & FD_STATE_FORMAT) {
2285 fdctrl_format_sector(fdctrl);
2286 break;
2287 }
2288
d275b33d
KW		 2289 cmd = get_command(fdctrl->fifo[0]);
2290 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2291 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2292 }
2293 break;
2294
2295 case FD_PHASE_RESULT:
2296 default:
2297 abort();
8977f3c1
FB		 2298 }
2299}
ed5fd2cc
FB		 2300
2301static void fdctrl_result_timer(void *opaque)
2302{
5c02c033
BS		 2303 FDCtrl *fdctrl = opaque;
2304 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2305
b7ffa3b1
TS		 2306 /* Pretend we are spinning.
2307 * This is needed for Coherent, which uses READ ID to check for
2308 * sector interleaving.
2309 */
2310 if (cur_drv->last_sect != 0) {
2311 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2312 }
844f65d6
HP		 2313 /* READ_ID can't automatically succeed! */
2314 if (fdctrl->check_media_rate &&
2315 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2316 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2317 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2318 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2319 } else {
2320 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2321 }
ed5fd2cc 2322}
678803ab 2323
7d4b4ba5 2324static void fdctrl_change_cb(void *opaque, bool load)
8e49ca46
MA		 2325{
2326 FDrive *drive = opaque;
2327
2328 drive->media_changed = 1;
d5d47efc 2329 drive->media_validated = false;
21fcf360 2330 fd_revalidate(drive);
8e49ca46
MA		 2331}
2332
2333static const BlockDevOps fdctrl_block_ops = {
2334 .change_media_cb = fdctrl_change_cb,
2335};
2336
678803ab 2337/* Init functions */
a3ef7a61 2338static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
678803ab 2339{
12a71a02 2340 unsigned int i;
7d0d6950 2341 FDrive *drive;
678803ab 2342
678803ab 2343 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2344 drive = &fdctrl->drives[i];
844f65d6 2345 drive->fdctrl = fdctrl;
7d0d6950 2346
4be74634
MA		 2347 if (drive->blk) {
2348 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
a3ef7a61
AF		 2349 error_setg(errp, "fdc doesn't support drive option werror");
2350 return;
b47b3525 2351 }
4be74634 2352 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
a3ef7a61
AF		 2353 error_setg(errp, "fdc doesn't support drive option rerror");
2354 return;
b47b3525
MA		 2355 }
2356 }
2357
7d0d6950 2358 fd_init(drive);
4be74634
MA		 2359 if (drive->blk) {
2360 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
d5d47efc 2361 pick_drive_type(drive);
7d0d6950 2362 }
d5d47efc 2363 fd_revalidate(drive);
678803ab 2364 }
678803ab
BS		 2365}
2366
dfc65f1f
MA		 2367ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2368{
4a17cc4f
AF		 2369 DeviceState *dev;
2370 ISADevice *isadev;
dfc65f1f 2371
4a17cc4f
AF		 2372 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2373 if (!isadev) {
dfc65f1f
MA		 2374 return NULL;
2375 }
4a17cc4f 2376 dev = DEVICE(isadev);
dfc65f1f
MA		 2377
2378 if (fds[0]) {
6231a6da
MA		 2379 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2380 &error_fatal);
dfc65f1f
MA		 2381 }
2382 if (fds[1]) {
6231a6da
MA		 2383 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2384 &error_fatal);
dfc65f1f 2385 }
4a17cc4f 2386 qdev_init_nofail(dev);
dfc65f1f 2387
4a17cc4f 2388 return isadev;
dfc65f1f
MA		 2389}
2390
63ffb564 2391void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2392 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2393{
5c02c033 2394 FDCtrl *fdctrl;
2091ba23 2395 DeviceState *dev;
dd3be742 2396 SysBusDevice *sbd;
5c02c033 2397 FDCtrlSysBus *sys;
2091ba23 2398
19d46d71 2399 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2400 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2401 fdctrl = &sys->state;
2402 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2403 if (fds[0]) {
6231a6da
MA		 2404 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2405 &error_fatal);
995bf0ca
GH		 2406 }
2407 if (fds[1]) {
6231a6da
MA		 2408 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2409 &error_fatal);
995bf0ca 2410 }
e23a1b33 2411 qdev_init_nofail(dev);
dd3be742
HT		 2412 sbd = SYS_BUS_DEVICE(dev);
2413 sysbus_connect_irq(sbd, 0, irq);
2414 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2415}
2416
a8170e5e 2417void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2418 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2419{
f64ab228 2420 DeviceState *dev;
5c02c033 2421 FDCtrlSysBus *sys;
678803ab 2422
12a71a02 2423 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2424 if (fds[0]) {
6231a6da
MA		 2425 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2426 &error_fatal);
995bf0ca 2427 }
e23a1b33 2428 qdev_init_nofail(dev);
dd3be742
HT		 2429 sys = SYSBUS_FDC(dev);
2430 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2431 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2432 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2433}
f64ab228 2434
a3ef7a61 2435static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
f64ab228 2436{
12a71a02
BS		 2437 int i, j;
2438 static int command_tables_inited = 0;
f64ab228 2439
a73275dd
JS		 2440 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2441 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2442 }
2443
12a71a02
BS		 2444 /* Fill 'command_to_handler' lookup table */
2445 if (!command_tables_inited) {
2446 command_tables_inited = 1;
2447 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2448 for (j = 0; j < sizeof(command_to_handler); j++) {
2449 if ((j & handlers[i].mask) == handlers[i].value) {
2450 command_to_handler[j] = i;
2451 }
2452 }
2453 }
2454 }
2455
2456 FLOPPY_DPRINTF("init controller\n");
2457 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 2458 fdctrl->fifo_size = 512;
bc72ad67 2459 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2460 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2461
2462 fdctrl->version = 0x90; /* Intel 82078 controller */
2463 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2464 fdctrl->num_floppies = MAX_FD;
12a71a02 2465
a3ef7a61 2466 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2467 IsaDmaClass *k;
2468 assert(fdctrl->dma);
2469 k = ISADMA_GET_CLASS(fdctrl->dma);
2470 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2471 &fdctrl_transfer_handler, fdctrl);
a3ef7a61
AF		 2472 }
2473 fdctrl_connect_drives(fdctrl, errp);
f64ab228
BS		 2474}
2475
212ec7ba 2476static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2477 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2478 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2479 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2480};
2481
db895a1e 2482static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2483{
db895a1e 2484 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2485 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2486 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2487 Error *err = NULL;
8baf73ad 2488
db895a1e
AF		 2489 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2490 "fdc");
dee41d58 2491
db895a1e 2492 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2493 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2494 if (fdctrl->dma_chann != -1) {
2495 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2496 assert(fdctrl->dma);
2497 }
8baf73ad 2498
db895a1e 2499 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
a3ef7a61
AF		 2500 fdctrl_realize_common(fdctrl, &err);
2501 if (err != NULL) {
2502 error_propagate(errp, err);
db895a1e
AF		 2503 return;
2504 }
8baf73ad
GH		 2505}
2506
940194c2 2507static void sysbus_fdc_initfn(Object *obj)
12a71a02 2508{
19d46d71 2509 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2510 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2511 FDCtrl *fdctrl = &sys->state;
12a71a02 2512
19d46d71
AF		 2513 fdctrl->dma_chann = -1;
2514
940194c2 2515 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2516 "fdc", 0x08);
19d46d71 2517 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2518}
2519
19d46d71 2520static void sun4m_fdc_initfn(Object *obj)
940194c2 2521{
19d46d71
AF		 2522 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2523 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2524 FDCtrl *fdctrl = &sys->state;
940194c2 2525
dd446051
HP		 2526 fdctrl->dma_chann = -1;
2527
19d46d71
AF		 2528 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2529 fdctrl, "fdctrl", 0x08);
2530 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2531}
2be37833 2532
19d46d71 2533static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2534{
19d46d71
AF		 2535 DeviceState *dev = DEVICE(obj);
2536 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2537 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2538 FDCtrl *fdctrl = &sys->state;
2539
19d46d71
AF		 2540 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2541
2542 sysbus_init_irq(sbd, &fdctrl->irq);
2543 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2544}
2545
19d46d71 2546static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2547{
dd3be742
HT		 2548 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2549 FDCtrl *fdctrl = &sys->state;
12a71a02 2550
19d46d71 2551 fdctrl_realize_common(fdctrl, errp);
12a71a02 2552}
f64ab228 2553
2da44dd0 2554FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2555{
020c8e76 2556 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2557
61a8d649 2558 return isa->state.drives[i].drive;
34d4260e
KW		 2559}
2560
e08fde0c
RK		 2561void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2562 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2563{
2564 const FDFormat *fdf;
2565
2566 *maxc = *maxh = *maxs = 0;
2567 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2568 if (fdf->drive != type) {
2569 continue;
2570 }
2571 if (*maxc < fdf->max_track) {
2572 *maxc = fdf->max_track;
2573 }
2574 if (*maxh < fdf->max_head) {
2575 *maxh = fdf->max_head;
2576 }
2577 if (*maxs < fdf->last_sect) {
2578 *maxs = fdf->last_sect;
2579 }
2580 }
2581 (*maxc)--;
2582}
2583
a64405d1
JK		 2584static const VMStateDescription vmstate_isa_fdc ={
2585 .name = "fdc",
2586 .version_id = 2,
2587 .minimum_version_id = 2,
d49805ae 2588 .fields = (VMStateField[]) {
a64405d1
JK		 2589 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2590 VMSTATE_END_OF_LIST()
2591 }
2592};
2593
39bffca2 2594static Property isa_fdc_properties[] = {
c7bcc85d 2595 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2596 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2597 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
4be74634
MA		 2598 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2599 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
09c6d585
HP		 2600 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2601 0, true),
fff4687b
JS		 2602 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2603 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2604 FloppyDriveType),
2605 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2606 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2607 FloppyDriveType),
a73275dd 2608 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
4812fa27 2609 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2610 FloppyDriveType),
39bffca2
AL		 2611 DEFINE_PROP_END_OF_LIST(),
2612};
2613
020c8e76 2614static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2615{
39bffca2 2616 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2617
2618 dc->realize = isabus_fdc_realize;
39bffca2 2619 dc->fw_name = "fdc";
39bffca2
AL		 2620 dc->reset = fdctrl_external_reset_isa;
2621 dc->vmsd = &vmstate_isa_fdc;
2622 dc->props = isa_fdc_properties;
125ee0ed 2623 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2624}
2625
81782b6a
GA		 2626static void isabus_fdc_instance_init(Object *obj)
2627{
2628 FDCtrlISABus *isa = ISA_FDC(obj);
2629
2630 device_add_bootindex_property(obj, &isa->bootindexA,
2631 "bootindexA", "/floppy@0",
2632 DEVICE(obj), NULL);
2633 device_add_bootindex_property(obj, &isa->bootindexB,
2634 "bootindexB", "/floppy@1",
2635 DEVICE(obj), NULL);
2636}
2637
8c43a6f0 2638static const TypeInfo isa_fdc_info = {
020c8e76 2639 .name = TYPE_ISA_FDC,
39bffca2
AL		 2640 .parent = TYPE_ISA_DEVICE,
2641 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2642 .class_init = isabus_fdc_class_init,
81782b6a 2643 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2644};
2645
a64405d1
JK		 2646static const VMStateDescription vmstate_sysbus_fdc ={
2647 .name = "fdc",
2648 .version_id = 2,
2649 .minimum_version_id = 2,
d49805ae 2650 .fields = (VMStateField[]) {
a64405d1
JK		 2651 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2652 VMSTATE_END_OF_LIST()
2653 }
2654};
2655
999e12bb 2656static Property sysbus_fdc_properties[] = {
4be74634
MA		 2657 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2658 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
fff4687b
JS		 2659 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2660 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2661 FloppyDriveType),
2662 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2663 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2664 FloppyDriveType),
a73275dd
JS		 2665 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2666 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2667 FloppyDriveType),
999e12bb 2668 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2669};
2670
999e12bb
AL		 2671static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2672{
39bffca2 2673 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2674
39bffca2 2675 dc->props = sysbus_fdc_properties;
125ee0ed 2676 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2677}
2678
8c43a6f0 2679static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2680 .name = "sysbus-fdc",
2681 .parent = TYPE_SYSBUS_FDC,
940194c2 2682 .instance_init = sysbus_fdc_initfn,
39bffca2 2683 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2684};
2685
2686static Property sun4m_fdc_properties[] = {
4be74634 2687 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
fff4687b
JS		 2688 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2689 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2690 FloppyDriveType),
a73275dd
JS		 2691 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2692 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2693 FloppyDriveType),
999e12bb
AL		 2694 DEFINE_PROP_END_OF_LIST(),
2695};
2696
2697static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2698{
39bffca2 2699 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2700
39bffca2 2701 dc->props = sun4m_fdc_properties;
125ee0ed 2702 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2703}
2704
8c43a6f0 2705static const TypeInfo sun4m_fdc_info = {
39bffca2 2706 .name = "SUNW,fdtwo",
19d46d71 2707 .parent = TYPE_SYSBUS_FDC,
940194c2 2708 .instance_init = sun4m_fdc_initfn,
39bffca2 2709 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2710};
2711
19d46d71
AF		 2712static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2713{
2714 DeviceClass *dc = DEVICE_CLASS(klass);
2715
2716 dc->realize = sysbus_fdc_common_realize;
2717 dc->reset = fdctrl_external_reset_sysbus;
2718 dc->vmsd = &vmstate_sysbus_fdc;
2719}
2720
2721static const TypeInfo sysbus_fdc_type_info = {
2722 .name = TYPE_SYSBUS_FDC,
2723 .parent = TYPE_SYS_BUS_DEVICE,
2724 .instance_size = sizeof(FDCtrlSysBus),
2725 .instance_init = sysbus_fdc_common_initfn,
2726 .abstract = true,
2727 .class_init = sysbus_fdc_common_class_init,
2728};
2729
83f7d43a 2730static void fdc_register_types(void)
f64ab228 2731{
39bffca2 2732 type_register_static(&isa_fdc_info);
19d46d71 2733 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2734 type_register_static(&sysbus_fdc_info);
2735 type_register_static(&sun4m_fdc_info);
f64ab228
BS		 2736}
2737
83f7d43a 2738type_init(fdc_register_types)
QEMU mirror