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fdc: rework pick_geometry
[mirror_qemu.git] / hw / block / fdc.c
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8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a 32#include "hw/block/fdc.h"
1de7afc9
PB		 33#include "qemu/error-report.h"
34#include "qemu/timer.h"
0d09e41a 35#include "hw/isa/isa.h"
83c9f4ca 36#include "hw/sysbus.h"
fa1d36df 37#include "sysemu/block-backend.h"
9c17d615
PB		 38#include "sysemu/blockdev.h"
39#include "sysemu/sysemu.h"
1de7afc9 40#include "qemu/log.h"
8977f3c1
FB		 41
42/********************************************************/
43/* debug Floppy devices */
44//#define DEBUG_FLOPPY
45
46#ifdef DEBUG_FLOPPY
001faf32
BS		 47#define FLOPPY_DPRINTF(fmt, ...) \
48 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
8977f3c1 49#else
001faf32 50#define FLOPPY_DPRINTF(fmt, ...)
8977f3c1
FB		 51#endif
52
8977f3c1
FB		 53/********************************************************/
54/* Floppy drive emulation */
55
61a8d649
MA		 56typedef enum FDriveRate {
57 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
58 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
59 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
60 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
61} FDriveRate;
62
109c17bc
JS		 63typedef enum FDriveSize {
64 FDRIVE_SIZE_UNKNOWN,
65 FDRIVE_SIZE_350,
66 FDRIVE_SIZE_525,
67} FDriveSize;
68
61a8d649 69typedef struct FDFormat {
2da44dd0 70 FloppyDriveType drive;
61a8d649
MA		 71 uint8_t last_sect;
72 uint8_t max_track;
73 uint8_t max_head;
74 FDriveRate rate;
75} FDFormat;
76
109c17bc
JS		 77/* In many cases, the total sector size of a format is enough to uniquely
78 * identify it. However, there are some total sector collisions between
79 * formats of different physical size, and these are noted below by
80 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 81static const FDFormat fd_formats[] = {
82 /* First entry is default format */
83 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 84 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
85 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 86 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
87 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
88 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
89 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
90 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
91 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 92 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 93 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
94 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
95 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
96 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
97 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 98 /* 720 kB 3"1/2 floppy disks */
109c17bc 99 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 100 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
101 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
102 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
104 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 105 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 106 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 107 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 108 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
109 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 110 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 111 /* 720 kB 5"1/4 floppy disks */
109c17bc 112 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 113 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 114 /* 360 kB 5"1/4 floppy disks */
109c17bc 115 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 116 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
117 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
118 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 119 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 120 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
121 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 122 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 123 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 124 /* end */
2da44dd0 125 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 126};
127
109c17bc
JS		 128static FDriveSize drive_size(FloppyDriveType drive)
129{
130 switch (drive) {
131 case FLOPPY_DRIVE_TYPE_120:
132 return FDRIVE_SIZE_525;
133 case FLOPPY_DRIVE_TYPE_144:
134 case FLOPPY_DRIVE_TYPE_288:
135 return FDRIVE_SIZE_350;
136 default:
137 return FDRIVE_SIZE_UNKNOWN;
138 }
139}
140
cefec4f5
BS		 141#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
142#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
143
8977f3c1 144/* Will always be a fixed parameter for us */
f2d81b33
BS		 145#define FD_SECTOR_LEN 512
146#define FD_SECTOR_SC 2 /* Sector size code */
147#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1 148
844f65d6
HP		 149typedef struct FDCtrl FDCtrl;
150
8977f3c1 151/* Floppy disk drive emulation */
5c02c033 152typedef enum FDiskFlags {
baca51fa 153 FDISK_DBL_SIDES = 0x01,
5c02c033 154} FDiskFlags;
baca51fa 155
5c02c033 156typedef struct FDrive {
844f65d6 157 FDCtrl *fdctrl;
4be74634 158 BlockBackend *blk;
8977f3c1 159 /* Drive status */
2da44dd0 160 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 161 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 162 /* Position */
163 uint8_t head;
164 uint8_t track;
165 uint8_t sect;
8977f3c1 166 /* Media */
16c1e3ec 167 FloppyDriveType disk; /* Current disk type */
5c02c033 168 FDiskFlags flags;
8977f3c1
FB		 169 uint8_t last_sect; /* Nb sector per track */
170 uint8_t max_track; /* Nb of tracks */
baca51fa 171 uint16_t bps; /* Bytes per sector */
8977f3c1 172 uint8_t ro; /* Is read-only */
7d905f71 173 uint8_t media_changed; /* Is media changed */
844f65d6 174 uint8_t media_rate; /* Data rate of medium */
2e1280e8
HR		 175
176 bool media_inserted; /* Is there a medium in the tray */
d5d47efc 177 bool media_validated; /* Have we validated the media? */
5c02c033 178} FDrive;
8977f3c1 179
a73275dd
JS		 180
181static FloppyDriveType get_fallback_drive_type(FDrive *drv);
182
5c02c033 183static void fd_init(FDrive *drv)
8977f3c1
FB		 184{
185 /* Drive */
8977f3c1 186 drv->perpendicular = 0;
8977f3c1 187 /* Disk */
16c1e3ec 188 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 189 drv->last_sect = 0;
8977f3c1 190 drv->max_track = 0;
d5d47efc
JS		 191 drv->ro = true;
192 drv->media_changed = 1;
8977f3c1
FB		 193}
194
08388273
HP		 195#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
196
7859cb98 197static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 198 uint8_t last_sect, uint8_t num_sides)
8977f3c1 199{
08388273 200 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 201}
202
203/* Returns current position, in sectors, for given drive */
5c02c033 204static int fd_sector(FDrive *drv)
8977f3c1 205{
08388273
HP		 206 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
207 NUM_SIDES(drv));
8977f3c1
FB		 208}
209
77370520
BS		 210/* Seek to a new position:
211 * returns 0 if already on right track
212 * returns 1 if track changed
213 * returns 2 if track is invalid
214 * returns 3 if sector is invalid
215 * returns 4 if seek is disabled
216 */
5c02c033
BS		 217static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
218 int enable_seek)
8977f3c1
FB		 219{
220 uint32_t sector;
baca51fa
FB		 221 int ret;
222
223 if (track > drv->max_track ||
4f431960 224 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 225 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
226 head, track, sect, 1,
227 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
228 drv->max_track, drv->last_sect);
8977f3c1
FB		 229 return 2;
230 }
231 if (sect > drv->last_sect) {
ed5fd2cc
FB		 232 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
233 head, track, sect, 1,
234 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
235 drv->max_track, drv->last_sect);
8977f3c1
FB		 236 return 3;
237 }
08388273 238 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 239 ret = 0;
8977f3c1
FB		 240 if (sector != fd_sector(drv)) {
241#if 0
242 if (!enable_seek) {
cced7a13
BS		 243 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
244 " (max=%d %02x %02x)\n",
245 head, track, sect, 1, drv->max_track,
246 drv->last_sect);
8977f3c1
FB		 247 return 4;
248 }
249#endif
250 drv->head = head;
6be01b1e 251 if (drv->track != track) {
2e1280e8 252 if (drv->media_inserted) {
6be01b1e
PH		 253 drv->media_changed = 0;
254 }
4f431960 255 ret = 1;
6be01b1e 256 }
8977f3c1
FB		 257 drv->track = track;
258 drv->sect = sect;
8977f3c1
FB		 259 }
260
2e1280e8 261 if (!drv->media_inserted) {
c52acf60
PH		 262 ret = 2;
263 }
264
baca51fa 265 return ret;
8977f3c1
FB		 266}
267
268/* Set drive back to track 0 */
5c02c033 269static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 270{
271 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 272 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 273}
274
d5d47efc
JS		 275/**
276 * Determine geometry based on inserted diskette.
277 * Will not operate on an empty drive.
278 *
279 * @return: 0 on success, -1 if the drive is empty.
280 */
281static int pick_geometry(FDrive *drv)
9a972233 282{
21862658 283 BlockBackend *blk = drv->blk;
9a972233
JS		 284 const FDFormat *parse;
285 uint64_t nb_sectors, size;
f31937aa
JS		 286 int i;
287 int match, size_match, type_match;
288 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 289
d5d47efc 290 /* We can only pick a geometry if we have a diskette. */
fff4687b 291 if (!drv->media_inserted || drv->drive == FLOPPY_DRIVE_TYPE_NONE) {
d5d47efc
JS		 292 return -1;
293 }
294
f31937aa
JS		 295 /* We need to determine the likely geometry of the inserted medium.
296 * In order of preference, we look for:
297 * (1) The same drive type and number of sectors,
298 * (2) The same diskette size and number of sectors,
299 * (3) The same drive type.
300 *
301 * In all cases, matches that occur higher in the drive table will take
302 * precedence over matches that occur later in the table.
303 */
9a972233 304 blk_get_geometry(blk, &nb_sectors);
f31937aa 305 match = size_match = type_match = -1;
9a972233
JS		 306 for (i = 0; ; i++) {
307 parse = &fd_formats[i];
2da44dd0 308 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 309 break;
310 }
f31937aa
JS		 311 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
312 if (nb_sectors == size) {
313 if (magic || parse->drive == drv->drive) {
314 /* (1) perfect match -- nb_sectors and drive type */
315 goto out;
316 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
317 /* (2) size match -- nb_sectors and physical medium size */
318 match = (match == -1) ? i : match;
319 } else {
320 /* This is suspicious -- Did the user misconfigure? */
321 size_match = (size_match == -1) ? i : size_match;
9a972233 322 }
f31937aa
JS		 323 } else if (type_match == -1) {
324 if ((parse->drive == drv->drive) ||
325 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
326 /* (3) type match -- nb_sectors mismatch, but matches the type
327 * specified explicitly by the user, or matches the fallback
328 * default type when using the drive autodetect mechanism */
329 type_match = i;
9a972233
JS		 330 }
331 }
332 }
f31937aa
JS		 333
334 /* No exact match found */
9a972233 335 if (match == -1) {
f31937aa
JS		 336 if (size_match != -1) {
337 parse = &fd_formats[size_match];
338 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
339 "but inserted medium appears to be a "
340 "%d sector '%s' type\n",
341 FloppyDriveType_lookup[drv->drive],
342 nb_sectors,
343 FloppyDriveType_lookup[parse->drive]);
9a972233 344 }
f31937aa 345 match = type_match;
9a972233 346 }
21862658 347
f31937aa
JS		 348 /* No match of any kind found -- fd_format is misconfigured, abort. */
349 if (match == -1) {
350 error_setg(&error_abort, "No candidate geometries present in table "
351 " for floppy drive type '%s'",
352 FloppyDriveType_lookup[drv->drive]);
353 }
354
355 parse = &(fd_formats[match]);
356
357 out:
21862658
JS		 358 if (parse->max_head == 0) {
359 drv->flags &= ~FDISK_DBL_SIDES;
360 } else {
361 drv->flags |= FDISK_DBL_SIDES;
362 }
363 drv->max_track = parse->max_track;
364 drv->last_sect = parse->last_sect;
d5d47efc 365 drv->disk = parse->drive;
21862658 366 drv->media_rate = parse->rate;
d5d47efc
JS		 367 return 0;
368}
369
370static void pick_drive_type(FDrive *drv)
371{
fff4687b
JS		 372 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
373 return;
374 }
375
d5d47efc
JS		 376 if (pick_geometry(drv) == 0) {
377 drv->drive = drv->disk;
378 } else {
a73275dd 379 drv->drive = get_fallback_drive_type(drv);
d5d47efc 380 }
fff4687b
JS		 381
382 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 383}
384
8977f3c1 385/* Revalidate a disk drive after a disk change */
5c02c033 386static void fd_revalidate(FDrive *drv)
8977f3c1 387{
d5d47efc
JS		 388 int rc;
389
8977f3c1 390 FLOPPY_DPRINTF("revalidate\n");
4be74634 391 if (drv->blk != NULL) {
21862658 392 drv->ro = blk_is_read_only(drv->blk);
2e1280e8 393 if (!drv->media_inserted) {
cfb08fba 394 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc
JS		 395 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
396 } else if (!drv->media_validated) {
397 rc = pick_geometry(drv);
398 if (rc) {
399 FLOPPY_DPRINTF("Could not validate floppy drive media");
400 } else {
401 drv->media_validated = true;
402 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
403 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
404 drv->max_track, drv->last_sect,
405 drv->ro ? "ro" : "rw");
406 }
4f431960 407 }
8977f3c1 408 } else {
cfb08fba 409 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 410 drv->last_sect = 0;
4f431960
JM		 411 drv->max_track = 0;
412 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 413 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
414 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 415 }
caed8802
FB		 416}
417
8977f3c1 418/********************************************************/
4b19ec0c 419/* Intel 82078 floppy disk controller emulation */
8977f3c1 420
5c02c033 421static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 422static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 423static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 424 int dma_pos, int dma_len);
d497d534 425static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 426static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 427
428static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
429static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
430static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
431static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
432static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
433static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
434static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
435static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
436static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
437static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
438static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 439static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 440
8977f3c1
FB		 441enum {
442 FD_DIR_WRITE = 0,
443 FD_DIR_READ = 1,
444 FD_DIR_SCANE = 2,
445 FD_DIR_SCANL = 3,
446 FD_DIR_SCANH = 4,
7ea004ed 447 FD_DIR_VERIFY = 5,
8977f3c1
FB		 448};
449
450enum {
b9b3d225
BS		 451 FD_STATE_MULTI = 0x01, /* multi track flag */
452 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 453};
454
9fea808a 455enum {
8c6a4d77
BS		 456 FD_REG_SRA = 0x00,
457 FD_REG_SRB = 0x01,
9fea808a
BS		 458 FD_REG_DOR = 0x02,
459 FD_REG_TDR = 0x03,
460 FD_REG_MSR = 0x04,
461 FD_REG_DSR = 0x04,
462 FD_REG_FIFO = 0x05,
463 FD_REG_DIR = 0x07,
a758f8f4 464 FD_REG_CCR = 0x07,
9fea808a
BS		 465};
466
467enum {
65cef780 468 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 469 FD_CMD_SPECIFY = 0x03,
470 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 471 FD_CMD_WRITE = 0x05,
472 FD_CMD_READ = 0x06,
9fea808a
BS		 473 FD_CMD_RECALIBRATE = 0x07,
474 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 475 FD_CMD_WRITE_DELETED = 0x09,
476 FD_CMD_READ_ID = 0x0a,
477 FD_CMD_READ_DELETED = 0x0c,
478 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 479 FD_CMD_DUMPREG = 0x0e,
480 FD_CMD_SEEK = 0x0f,
481 FD_CMD_VERSION = 0x10,
65cef780 482 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 483 FD_CMD_PERPENDICULAR_MODE = 0x12,
484 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 485 FD_CMD_LOCK = 0x14,
486 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 487 FD_CMD_POWERDOWN_MODE = 0x17,
488 FD_CMD_PART_ID = 0x18,
65cef780
BS		 489 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
490 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 491 FD_CMD_SAVE = 0x2e,
9fea808a 492 FD_CMD_OPTION = 0x33,
bb350a5e 493 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 494 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
495 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 496 FD_CMD_FORMAT_AND_WRITE = 0xcd,
497 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
498};
499
500enum {
501 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
502 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
503 FD_CONFIG_POLL = 0x10, /* Poll enabled */
504 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
505 FD_CONFIG_EIS = 0x40, /* No implied seeks */
506};
507
508enum {
2fee0088
PH		 509 FD_SR0_DS0 = 0x01,
510 FD_SR0_DS1 = 0x02,
511 FD_SR0_HEAD = 0x04,
9fea808a
BS		 512 FD_SR0_EQPMT = 0x10,
513 FD_SR0_SEEK = 0x20,
514 FD_SR0_ABNTERM = 0x40,
515 FD_SR0_INVCMD = 0x80,
516 FD_SR0_RDYCHG = 0xc0,
517};
518
77370520 519enum {
844f65d6 520 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 521 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 522 FD_SR1_EC = 0x80, /* End of cylinder */
523};
524
525enum {
526 FD_SR2_SNS = 0x04, /* Scan not satisfied */
527 FD_SR2_SEH = 0x08, /* Scan equal hit */
528};
529
8c6a4d77
BS		 530enum {
531 FD_SRA_DIR = 0x01,
532 FD_SRA_nWP = 0x02,
533 FD_SRA_nINDX = 0x04,
534 FD_SRA_HDSEL = 0x08,
535 FD_SRA_nTRK0 = 0x10,
536 FD_SRA_STEP = 0x20,
537 FD_SRA_nDRV2 = 0x40,
538 FD_SRA_INTPEND = 0x80,
539};
540
541enum {
542 FD_SRB_MTR0 = 0x01,
543 FD_SRB_MTR1 = 0x02,
544 FD_SRB_WGATE = 0x04,
545 FD_SRB_RDATA = 0x08,
546 FD_SRB_WDATA = 0x10,
547 FD_SRB_DR0 = 0x20,
548};
549
9fea808a 550enum {
78ae820c
BS		 551#if MAX_FD == 4
552 FD_DOR_SELMASK = 0x03,
553#else
9fea808a 554 FD_DOR_SELMASK = 0x01,
78ae820c 555#endif
9fea808a
BS		 556 FD_DOR_nRESET = 0x04,
557 FD_DOR_DMAEN = 0x08,
558 FD_DOR_MOTEN0 = 0x10,
559 FD_DOR_MOTEN1 = 0x20,
560 FD_DOR_MOTEN2 = 0x40,
561 FD_DOR_MOTEN3 = 0x80,
562};
563
564enum {
78ae820c 565#if MAX_FD == 4
9fea808a 566 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 567#else
568 FD_TDR_BOOTSEL = 0x04,
569#endif
9fea808a
BS		 570};
571
572enum {
573 FD_DSR_DRATEMASK= 0x03,
574 FD_DSR_PWRDOWN = 0x40,
575 FD_DSR_SWRESET = 0x80,
576};
577
578enum {
579 FD_MSR_DRV0BUSY = 0x01,
580 FD_MSR_DRV1BUSY = 0x02,
581 FD_MSR_DRV2BUSY = 0x04,
582 FD_MSR_DRV3BUSY = 0x08,
583 FD_MSR_CMDBUSY = 0x10,
584 FD_MSR_NONDMA = 0x20,
585 FD_MSR_DIO = 0x40,
586 FD_MSR_RQM = 0x80,
587};
588
589enum {
590 FD_DIR_DSKCHG = 0x80,
591};
592
85d291a0
KW		 593/*
594 * See chapter 5.0 "Controller phases" of the spec:
595 *
596 * Command phase:
597 * The host writes a command and its parameters into the FIFO. The command
598 * phase is completed when all parameters for the command have been supplied,
599 * and execution phase is entered.
600 *
601 * Execution phase:
602 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
603 * contains the payload now, otherwise it's unused. When all bytes of the
604 * required data have been transferred, the state is switched to either result
605 * phase (if the command produces status bytes) or directly back into the
606 * command phase for the next command.
607 *
608 * Result phase:
609 * The host reads out the FIFO, which contains one or more result bytes now.
610 */
611enum {
612 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
613 FD_PHASE_RECONSTRUCT = 0,
614
615 FD_PHASE_COMMAND = 1,
616 FD_PHASE_EXECUTION = 2,
617 FD_PHASE_RESULT = 3,
618};
619
8977f3c1 620#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 621#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 622
5c02c033 623struct FDCtrl {
dc6c1b37 624 MemoryRegion iomem;
d537cf6c 625 qemu_irq irq;
4b19ec0c 626 /* Controller state */
ed5fd2cc 627 QEMUTimer *result_timer;
242cca4f 628 int dma_chann;
85d291a0 629 uint8_t phase;
242cca4f
BS		 630 /* Controller's identification */
631 uint8_t version;
632 /* HW */
8c6a4d77
BS		 633 uint8_t sra;
634 uint8_t srb;
368df94d 635 uint8_t dor;
d7a6c270 636 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 637 uint8_t tdr;
b9b3d225 638 uint8_t dsr;
368df94d 639 uint8_t msr;
8977f3c1 640 uint8_t cur_drv;
77370520
BS		 641 uint8_t status0;
642 uint8_t status1;
643 uint8_t status2;
8977f3c1 644 /* Command FIFO */
33f00271 645 uint8_t *fifo;
d7a6c270 646 int32_t fifo_size;
8977f3c1
FB		 647 uint32_t data_pos;
648 uint32_t data_len;
649 uint8_t data_state;
650 uint8_t data_dir;
890fa6be 651 uint8_t eot; /* last wanted sector */
8977f3c1 652 /* States kept only to be returned back */
8977f3c1
FB		 653 /* precompensation */
654 uint8_t precomp_trk;
655 uint8_t config;
656 uint8_t lock;
657 /* Power down config (also with status regB access mode */
658 uint8_t pwrd;
659 /* Floppy drives */
d7a6c270 660 uint8_t num_floppies;
5c02c033 661 FDrive drives[MAX_FD];
f2d81b33 662 int reset_sensei;
09c6d585 663 uint32_t check_media_rate;
a73275dd 664 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 665 /* Timers state */
666 uint8_t timer0;
667 uint8_t timer1;
baca51fa
FB		 668};
669
a73275dd
JS		 670static FloppyDriveType get_fallback_drive_type(FDrive *drv)
671{
672 return drv->fdctrl->fallback;
673}
674
19d46d71 675#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 676#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
677
5c02c033 678typedef struct FDCtrlSysBus {
dd3be742
HT		 679 /*< private >*/
680 SysBusDevice parent_obj;
681 /*< public >*/
682
5c02c033
BS		 683 struct FDCtrl state;
684} FDCtrlSysBus;
8baf73ad 685
020c8e76
AF		 686#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
687
5c02c033 688typedef struct FDCtrlISABus {
020c8e76
AF		 689 ISADevice parent_obj;
690
c9ae703d
HP		 691 uint32_t iobase;
692 uint32_t irq;
693 uint32_t dma;
5c02c033 694 struct FDCtrl state;
1ca4d09a
GN		 695 int32_t bootindexA;
696 int32_t bootindexB;
5c02c033 697} FDCtrlISABus;
8baf73ad 698
baca51fa
FB		 699static uint32_t fdctrl_read (void *opaque, uint32_t reg)
700{
5c02c033 701 FDCtrl *fdctrl = opaque;
baca51fa
FB		 702 uint32_t retval;
703
a18e67f5 704 reg &= 7;
e64d7d59 705 switch (reg) {
8c6a4d77
BS		 706 case FD_REG_SRA:
707 retval = fdctrl_read_statusA(fdctrl);
4f431960 708 break;
8c6a4d77 709 case FD_REG_SRB:
4f431960
JM		 710 retval = fdctrl_read_statusB(fdctrl);
711 break;
9fea808a 712 case FD_REG_DOR:
4f431960
JM		 713 retval = fdctrl_read_dor(fdctrl);
714 break;
9fea808a 715 case FD_REG_TDR:
baca51fa 716 retval = fdctrl_read_tape(fdctrl);
4f431960 717 break;
9fea808a 718 case FD_REG_MSR:
baca51fa 719 retval = fdctrl_read_main_status(fdctrl);
4f431960 720 break;
9fea808a 721 case FD_REG_FIFO:
baca51fa 722 retval = fdctrl_read_data(fdctrl);
4f431960 723 break;
9fea808a 724 case FD_REG_DIR:
baca51fa 725 retval = fdctrl_read_dir(fdctrl);
4f431960 726 break;
a541f297 727 default:
4f431960
JM		 728 retval = (uint32_t)(-1);
729 break;
a541f297 730 }
ed5fd2cc 731 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
baca51fa
FB		 732
733 return retval;
734}
735
736static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
737{
5c02c033 738 FDCtrl *fdctrl = opaque;
baca51fa 739
ed5fd2cc
FB		 740 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
741
a18e67f5 742 reg &= 7;
e64d7d59 743 switch (reg) {
9fea808a 744 case FD_REG_DOR:
4f431960
JM		 745 fdctrl_write_dor(fdctrl, value);
746 break;
9fea808a 747 case FD_REG_TDR:
baca51fa 748 fdctrl_write_tape(fdctrl, value);
4f431960 749 break;
9fea808a 750 case FD_REG_DSR:
baca51fa 751 fdctrl_write_rate(fdctrl, value);
4f431960 752 break;
9fea808a 753 case FD_REG_FIFO:
baca51fa 754 fdctrl_write_data(fdctrl, value);
4f431960 755 break;
a758f8f4
HP		 756 case FD_REG_CCR:
757 fdctrl_write_ccr(fdctrl, value);
758 break;
a541f297 759 default:
4f431960 760 break;
a541f297 761 }
baca51fa
FB		 762}
763
a8170e5e 764static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 765 unsigned ize)
62a46c61 766{
5dcb6b91 767 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 768}
769
a8170e5e 770static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 771 uint64_t value, unsigned size)
62a46c61 772{
5dcb6b91 773 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 774}
775
dc6c1b37
AK		 776static const MemoryRegionOps fdctrl_mem_ops = {
777 .read = fdctrl_read_mem,
778 .write = fdctrl_write_mem,
779 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 780};
781
dc6c1b37
AK		 782static const MemoryRegionOps fdctrl_mem_strict_ops = {
783 .read = fdctrl_read_mem,
784 .write = fdctrl_write_mem,
785 .endianness = DEVICE_NATIVE_ENDIAN,
786 .valid = {
787 .min_access_size = 1,
788 .max_access_size = 1,
789 },
7c560456
BS		 790};
791
7d905f71
JW		 792static bool fdrive_media_changed_needed(void *opaque)
793{
794 FDrive *drive = opaque;
795
2e1280e8 796 return (drive->media_inserted && drive->media_changed != 1);
7d905f71
JW		 797}
798
799static const VMStateDescription vmstate_fdrive_media_changed = {
800 .name = "fdrive/media_changed",
801 .version_id = 1,
802 .minimum_version_id = 1,
5cd8cada 803 .needed = fdrive_media_changed_needed,
d49805ae 804 .fields = (VMStateField[]) {
7d905f71
JW		 805 VMSTATE_UINT8(media_changed, FDrive),
806 VMSTATE_END_OF_LIST()
807 }
808};
809
844f65d6
HP		 810static bool fdrive_media_rate_needed(void *opaque)
811{
812 FDrive *drive = opaque;
813
814 return drive->fdctrl->check_media_rate;
815}
816
817static const VMStateDescription vmstate_fdrive_media_rate = {
818 .name = "fdrive/media_rate",
819 .version_id = 1,
820 .minimum_version_id = 1,
5cd8cada 821 .needed = fdrive_media_rate_needed,
d49805ae 822 .fields = (VMStateField[]) {
844f65d6
HP		 823 VMSTATE_UINT8(media_rate, FDrive),
824 VMSTATE_END_OF_LIST()
825 }
826};
827
c0b92f30
PD		 828static bool fdrive_perpendicular_needed(void *opaque)
829{
830 FDrive *drive = opaque;
831
832 return drive->perpendicular != 0;
833}
834
835static const VMStateDescription vmstate_fdrive_perpendicular = {
836 .name = "fdrive/perpendicular",
837 .version_id = 1,
838 .minimum_version_id = 1,
5cd8cada 839 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 840 .fields = (VMStateField[]) {
841 VMSTATE_UINT8(perpendicular, FDrive),
842 VMSTATE_END_OF_LIST()
843 }
844};
845
846static int fdrive_post_load(void *opaque, int version_id)
847{
848 fd_revalidate(opaque);
849 return 0;
850}
851
d7a6c270
JQ		 852static const VMStateDescription vmstate_fdrive = {
853 .name = "fdrive",
854 .version_id = 1,
855 .minimum_version_id = 1,
c0b92f30 856 .post_load = fdrive_post_load,
d49805ae 857 .fields = (VMStateField[]) {
5c02c033
BS		 858 VMSTATE_UINT8(head, FDrive),
859 VMSTATE_UINT8(track, FDrive),
860 VMSTATE_UINT8(sect, FDrive),
d7a6c270 861 VMSTATE_END_OF_LIST()
7d905f71 862 },
5cd8cada
JQ		 863 .subsections = (const VMStateDescription*[]) {
864 &vmstate_fdrive_media_changed,
865 &vmstate_fdrive_media_rate,
866 &vmstate_fdrive_perpendicular,
867 NULL
d7a6c270
JQ		 868 }
869};
3ccacc4a 870
85d291a0
KW		 871/*
872 * Reconstructs the phase from register values according to the logic that was
873 * implemented in qemu 2.3. This is the default value that is used if the phase
874 * subsection is not present on migration.
875 *
876 * Don't change this function to reflect newer qemu versions, it is part of
877 * the migration ABI.
878 */
879static int reconstruct_phase(FDCtrl *fdctrl)
880{
881 if (fdctrl->msr & FD_MSR_NONDMA) {
882 return FD_PHASE_EXECUTION;
883 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
884 /* qemu 2.3 disabled RQM only during DMA transfers */
885 return FD_PHASE_EXECUTION;
886 } else if (fdctrl->msr & FD_MSR_DIO) {
887 return FD_PHASE_RESULT;
888 } else {
889 return FD_PHASE_COMMAND;
890 }
891}
892
d4bfa4d7 893static void fdc_pre_save(void *opaque)
3ccacc4a 894{
5c02c033 895 FDCtrl *s = opaque;
3ccacc4a 896
d7a6c270 897 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
3ccacc4a
BS		 898}
899
85d291a0
KW		 900static int fdc_pre_load(void *opaque)
901{
902 FDCtrl *s = opaque;
903 s->phase = FD_PHASE_RECONSTRUCT;
904 return 0;
905}
906
e59fb374 907static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 908{
5c02c033 909 FDCtrl *s = opaque;
3ccacc4a 910
d7a6c270
JQ		 911 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
912 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 913
914 if (s->phase == FD_PHASE_RECONSTRUCT) {
915 s->phase = reconstruct_phase(s);
916 }
917
3ccacc4a
BS		 918 return 0;
919}
920
c0b92f30
PD		 921static bool fdc_reset_sensei_needed(void *opaque)
922{
923 FDCtrl *s = opaque;
924
925 return s->reset_sensei != 0;
926}
927
928static const VMStateDescription vmstate_fdc_reset_sensei = {
929 .name = "fdc/reset_sensei",
930 .version_id = 1,
931 .minimum_version_id = 1,
5cd8cada 932 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 933 .fields = (VMStateField[]) {
934 VMSTATE_INT32(reset_sensei, FDCtrl),
935 VMSTATE_END_OF_LIST()
936 }
937};
938
939static bool fdc_result_timer_needed(void *opaque)
940{
941 FDCtrl *s = opaque;
942
943 return timer_pending(s->result_timer);
944}
945
946static const VMStateDescription vmstate_fdc_result_timer = {
947 .name = "fdc/result_timer",
948 .version_id = 1,
949 .minimum_version_id = 1,
5cd8cada 950 .needed = fdc_result_timer_needed,
c0b92f30 951 .fields = (VMStateField[]) {
e720677e 952 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 953 VMSTATE_END_OF_LIST()
954 }
955};
956
85d291a0
KW		 957static bool fdc_phase_needed(void *opaque)
958{
959 FDCtrl *fdctrl = opaque;
960
961 return reconstruct_phase(fdctrl) != fdctrl->phase;
962}
963
964static const VMStateDescription vmstate_fdc_phase = {
965 .name = "fdc/phase",
966 .version_id = 1,
967 .minimum_version_id = 1,
5cd8cada 968 .needed = fdc_phase_needed,
85d291a0
KW		 969 .fields = (VMStateField[]) {
970 VMSTATE_UINT8(phase, FDCtrl),
971 VMSTATE_END_OF_LIST()
972 }
973};
974
d7a6c270 975static const VMStateDescription vmstate_fdc = {
aef30c3c 976 .name = "fdc",
d7a6c270
JQ		 977 .version_id = 2,
978 .minimum_version_id = 2,
d7a6c270 979 .pre_save = fdc_pre_save,
85d291a0 980 .pre_load = fdc_pre_load,
d7a6c270 981 .post_load = fdc_post_load,
d49805ae 982 .fields = (VMStateField[]) {
d7a6c270 983 /* Controller State */
5c02c033
BS		 984 VMSTATE_UINT8(sra, FDCtrl),
985 VMSTATE_UINT8(srb, FDCtrl),
986 VMSTATE_UINT8(dor_vmstate, FDCtrl),
987 VMSTATE_UINT8(tdr, FDCtrl),
988 VMSTATE_UINT8(dsr, FDCtrl),
989 VMSTATE_UINT8(msr, FDCtrl),
990 VMSTATE_UINT8(status0, FDCtrl),
991 VMSTATE_UINT8(status1, FDCtrl),
992 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 993 /* Command FIFO */
8ec68b06
BS		 994 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
995 uint8_t),
5c02c033
BS		 996 VMSTATE_UINT32(data_pos, FDCtrl),
997 VMSTATE_UINT32(data_len, FDCtrl),
998 VMSTATE_UINT8(data_state, FDCtrl),
999 VMSTATE_UINT8(data_dir, FDCtrl),
1000 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1001 /* States kept only to be returned back */
5c02c033
BS		 1002 VMSTATE_UINT8(timer0, FDCtrl),
1003 VMSTATE_UINT8(timer1, FDCtrl),
1004 VMSTATE_UINT8(precomp_trk, FDCtrl),
1005 VMSTATE_UINT8(config, FDCtrl),
1006 VMSTATE_UINT8(lock, FDCtrl),
1007 VMSTATE_UINT8(pwrd, FDCtrl),
1008 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1009 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1010 vmstate_fdrive, FDrive),
d7a6c270 1011 VMSTATE_END_OF_LIST()
c0b92f30 1012 },
5cd8cada
JQ		 1013 .subsections = (const VMStateDescription*[]) {
1014 &vmstate_fdc_reset_sensei,
1015 &vmstate_fdc_result_timer,
1016 &vmstate_fdc_phase,
1017 NULL
78ae820c 1018 }
d7a6c270 1019};
3ccacc4a 1020
2be37833 1021static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1022{
dd3be742 1023 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1024 FDCtrl *s = &sys->state;
2be37833
BS		 1025
1026 fdctrl_reset(s, 0);
1027}
1028
1029static void fdctrl_external_reset_isa(DeviceState *d)
1030{
020c8e76 1031 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1032 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1033
1034 fdctrl_reset(s, 0);
1035}
1036
2be17ebd
BS		 1037static void fdctrl_handle_tc(void *opaque, int irq, int level)
1038{
5c02c033 1039 //FDCtrl *s = opaque;
2be17ebd
BS		 1040
1041 if (level) {
1042 // XXX
1043 FLOPPY_DPRINTF("TC pulsed\n");
1044 }
1045}
1046
8977f3c1 1047/* Change IRQ state */
5c02c033 1048static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1049{
d497d534 1050 fdctrl->status0 = 0;
8c6a4d77
BS		 1051 if (!(fdctrl->sra & FD_SRA_INTPEND))
1052 return;
ed5fd2cc 1053 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1054 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1055 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1056}
1057
d497d534 1058static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1059{
8c6a4d77 1060 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1061 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1062 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1063 }
21fcf360 1064
f2d81b33 1065 fdctrl->reset_sensei = 0;
77370520 1066 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1067}
1068
4b19ec0c 1069/* Reset controller */
5c02c033 1070static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1071{
1072 int i;
1073
4b19ec0c 1074 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1075 fdctrl_reset_irq(fdctrl);
4b19ec0c 1076 /* Initialise controller */
8c6a4d77
BS		 1077 fdctrl->sra = 0;
1078 fdctrl->srb = 0xc0;
4be74634 1079 if (!fdctrl->drives[1].blk) {
8c6a4d77 1080 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1081 }
baca51fa 1082 fdctrl->cur_drv = 0;
1c346df2 1083 fdctrl->dor = FD_DOR_nRESET;
368df94d 1084 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1085 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1086 fdctrl->reset_sensei = 0;
1087 timer_del(fdctrl->result_timer);
8977f3c1 1088 /* FIFO state */
baca51fa
FB		 1089 fdctrl->data_pos = 0;
1090 fdctrl->data_len = 0;
b9b3d225 1091 fdctrl->data_state = 0;
baca51fa 1092 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1093 for (i = 0; i < MAX_FD; i++)
1c346df2 1094 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1095 fdctrl_to_command_phase(fdctrl);
77370520 1096 if (do_irq) {
d497d534
HP		 1097 fdctrl->status0 |= FD_SR0_RDYCHG;
1098 fdctrl_raise_irq(fdctrl);
f2d81b33 1099 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1100 }
baca51fa
FB		 1101}
1102
5c02c033 1103static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1104{
46d3233b 1105 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1106}
1107
5c02c033 1108static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1109{
46d3233b
BS		 1110 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1111 return &fdctrl->drives[1];
1112 else
1113 return &fdctrl->drives[0];
baca51fa
FB		 1114}
1115
78ae820c 1116#if MAX_FD == 4
5c02c033 1117static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1118{
1119 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1120 return &fdctrl->drives[2];
1121 else
1122 return &fdctrl->drives[1];
1123}
1124
5c02c033 1125static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1126{
1127 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1128 return &fdctrl->drives[3];
1129 else
1130 return &fdctrl->drives[2];
1131}
1132#endif
1133
5c02c033 1134static FDrive *get_cur_drv(FDCtrl *fdctrl)
baca51fa 1135{
78ae820c
BS		 1136 switch (fdctrl->cur_drv) {
1137 case 0: return drv0(fdctrl);
1138 case 1: return drv1(fdctrl);
1139#if MAX_FD == 4
1140 case 2: return drv2(fdctrl);
1141 case 3: return drv3(fdctrl);
1142#endif
1143 default: return NULL;
1144 }
8977f3c1
FB		 1145}
1146
8c6a4d77 1147/* Status A register : 0x00 (read-only) */
5c02c033 1148static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1149{
1150 uint32_t retval = fdctrl->sra;
1151
1152 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1153
1154 return retval;
1155}
1156
8977f3c1 1157/* Status B register : 0x01 (read-only) */
5c02c033 1158static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1159{
8c6a4d77
BS		 1160 uint32_t retval = fdctrl->srb;
1161
1162 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1163
1164 return retval;
8977f3c1
FB		 1165}
1166
1167/* Digital output register : 0x02 */
5c02c033 1168static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1169{
1c346df2 1170 uint32_t retval = fdctrl->dor;
8977f3c1 1171
8977f3c1 1172 /* Selected drive */
baca51fa 1173 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1174 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1175
1176 return retval;
1177}
1178
5c02c033 1179static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1180{
8977f3c1 1181 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1182
1183 /* Motors */
1184 if (value & FD_DOR_MOTEN0)
1185 fdctrl->srb |= FD_SRB_MTR0;
1186 else
1187 fdctrl->srb &= ~FD_SRB_MTR0;
1188 if (value & FD_DOR_MOTEN1)
1189 fdctrl->srb |= FD_SRB_MTR1;
1190 else
1191 fdctrl->srb &= ~FD_SRB_MTR1;
1192
1193 /* Drive */
1194 if (value & 1)
1195 fdctrl->srb |= FD_SRB_DR0;
1196 else
1197 fdctrl->srb &= ~FD_SRB_DR0;
1198
8977f3c1 1199 /* Reset */
9fea808a 1200 if (!(value & FD_DOR_nRESET)) {
1c346df2 1201 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1202 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1203 }
1204 } else {
1c346df2 1205 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1206 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1207 fdctrl_reset(fdctrl, 1);
b9b3d225 1208 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1209 }
1210 }
1211 /* Selected drive */
9fea808a 1212 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1213
1214 fdctrl->dor = value;
8977f3c1
FB		 1215}
1216
1217/* Tape drive register : 0x03 */
5c02c033 1218static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1219{
46d3233b 1220 uint32_t retval = fdctrl->tdr;
8977f3c1 1221
8977f3c1
FB		 1222 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1223
1224 return retval;
1225}
1226
5c02c033 1227static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1228{
8977f3c1 1229 /* Reset mode */
1c346df2 1230 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1231 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1232 return;
1233 }
1234 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1235 /* Disk boot selection indicator */
46d3233b 1236 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1237 /* Tape indicators: never allow */
1238}
1239
1240/* Main status register : 0x04 (read) */
5c02c033 1241static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1242{
b9b3d225 1243 uint32_t retval = fdctrl->msr;
8977f3c1 1244
b9b3d225 1245 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1246 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1247
8977f3c1
FB		 1248 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1249
1250 return retval;
1251}
1252
1253/* Data select rate register : 0x04 (write) */
5c02c033 1254static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1255{
8977f3c1 1256 /* Reset mode */
1c346df2 1257 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1258 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1259 return;
1260 }
8977f3c1
FB		 1261 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1262 /* Reset: autoclear */
9fea808a 1263 if (value & FD_DSR_SWRESET) {
1c346df2 1264 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1265 fdctrl_reset(fdctrl, 1);
1c346df2 1266 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1267 }
9fea808a 1268 if (value & FD_DSR_PWRDOWN) {
baca51fa 1269 fdctrl_reset(fdctrl, 1);
8977f3c1 1270 }
b9b3d225 1271 fdctrl->dsr = value;
8977f3c1
FB		 1272}
1273
a758f8f4
HP		 1274/* Configuration control register: 0x07 (write) */
1275static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1276{
1277 /* Reset mode */
1278 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1279 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1280 return;
1281 }
1282 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1283
1284 /* Only the rate selection bits used in AT mode, and we
1285 * store those in the DSR.
1286 */
1287 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1288 (value & FD_DSR_DRATEMASK);
1289}
1290
5c02c033 1291static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1292{
21fcf360 1293 return drv->media_changed;
ea185bbd
FB		 1294}
1295
8977f3c1 1296/* Digital input register : 0x07 (read-only) */
5c02c033 1297static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1298{
8977f3c1
FB		 1299 uint32_t retval = 0;
1300
a2df5fa3 1301 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1302 retval |= FD_DIR_DSKCHG;
a2df5fa3 1303 }
3c83eb4f 1304 if (retval != 0) {
baca51fa 1305 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1306 }
8977f3c1
FB		 1307
1308 return retval;
1309}
1310
07e415f2
KW		 1311/* Clear the FIFO and update the state for receiving the next command */
1312static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1313{
85d291a0 1314 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1315 fdctrl->data_dir = FD_DIR_WRITE;
1316 fdctrl->data_pos = 0;
6cc8a11c 1317 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1318 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1319 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1320}
1321
83a26013
KW		 1322/* Update the state to allow the guest to read out the command status.
1323 * @fifo_len is the number of result bytes to be read out. */
1324static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1325{
85d291a0 1326 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1327 fdctrl->data_dir = FD_DIR_READ;
1328 fdctrl->data_len = fifo_len;
1329 fdctrl->data_pos = 0;
b9b3d225 1330 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1331}
1332
1333/* Set an error: unimplemented/unknown command */
5c02c033 1334static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1335{
cced7a13
BS		 1336 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1337 fdctrl->fifo[0]);
9fea808a 1338 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1339 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1340}
1341
6be01b1e
PH		 1342/* Seek to next sector
1343 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1344 * otherwise returns 1
1345 */
5c02c033 1346static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1347{
1348 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1349 cur_drv->head, cur_drv->track, cur_drv->sect,
1350 fd_sector(cur_drv));
1351 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1352 error in fact */
6be01b1e
PH		 1353 uint8_t new_head = cur_drv->head;
1354 uint8_t new_track = cur_drv->track;
1355 uint8_t new_sect = cur_drv->sect;
1356
1357 int ret = 1;
1358
1359 if (new_sect >= cur_drv->last_sect ||
1360 new_sect == fdctrl->eot) {
1361 new_sect = 1;
746d6de7 1362 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1363 if (new_head == 0 &&
746d6de7 1364 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1365 new_head = 1;
746d6de7 1366 } else {
6be01b1e
PH		 1367 new_head = 0;
1368 new_track++;
c5139bd9 1369 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1370 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1371 ret = 0;
1372 }
746d6de7
BS		 1373 }
1374 } else {
c5139bd9 1375 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1376 new_track++;
1377 ret = 0;
1378 }
1379 if (ret == 1) {
1380 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1381 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1382 }
746d6de7 1383 } else {
6be01b1e 1384 new_sect++;
746d6de7 1385 }
6be01b1e
PH		 1386 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1387 return ret;
746d6de7
BS		 1388}
1389
8977f3c1 1390/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1391static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1392 uint8_t status1, uint8_t status2)
8977f3c1 1393{
5c02c033 1394 FDrive *cur_drv;
baca51fa 1395 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1396
1397 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1398 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1399 if (cur_drv->head) {
1400 fdctrl->status0 |= FD_SR0_HEAD;
1401 }
1402 fdctrl->status0 |= status0;
2fee0088 1403
8977f3c1 1404 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1405 status0, status1, status2, fdctrl->status0);
1406 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1407 fdctrl->fifo[1] = status1;
1408 fdctrl->fifo[2] = status2;
1409 fdctrl->fifo[3] = cur_drv->track;
1410 fdctrl->fifo[4] = cur_drv->head;
1411 fdctrl->fifo[5] = cur_drv->sect;
1412 fdctrl->fifo[6] = FD_SECTOR_SC;
1413 fdctrl->data_dir = FD_DIR_READ;
368df94d 1414 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
baca51fa 1415 DMA_release_DREQ(fdctrl->dma_chann);
ed5fd2cc 1416 }
b9b3d225 1417 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1418 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1419
83a26013 1420 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1421 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1422}
1423
1424/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1425static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1426{
5c02c033 1427 FDrive *cur_drv;
8977f3c1 1428 uint8_t kh, kt, ks;
8977f3c1 1429
cefec4f5 1430 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1431 cur_drv = get_cur_drv(fdctrl);
1432 kt = fdctrl->fifo[2];
1433 kh = fdctrl->fifo[3];
1434 ks = fdctrl->fifo[4];
4b19ec0c 1435 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1436 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1437 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1438 NUM_SIDES(cur_drv)));
77370520 1439 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1440 case 2:
1441 /* sect too big */
9fea808a 1442 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1443 fdctrl->fifo[3] = kt;
1444 fdctrl->fifo[4] = kh;
1445 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1446 return;
1447 case 3:
1448 /* track too big */
77370520 1449 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1450 fdctrl->fifo[3] = kt;
1451 fdctrl->fifo[4] = kh;
1452 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1453 return;
1454 case 4:
1455 /* No seek enabled */
9fea808a 1456 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1457 fdctrl->fifo[3] = kt;
1458 fdctrl->fifo[4] = kh;
1459 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1460 return;
1461 case 1:
d6ed4e21 1462 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1463 break;
1464 default:
1465 break;
1466 }
b9b3d225 1467
844f65d6
HP		 1468 /* Check the data rate. If the programmed data rate does not match
1469 * the currently inserted medium, the operation has to fail. */
1470 if (fdctrl->check_media_rate &&
1471 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1472 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1473 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1474 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1475 fdctrl->fifo[3] = kt;
1476 fdctrl->fifo[4] = kh;
1477 fdctrl->fifo[5] = ks;
1478 return;
1479 }
1480
8977f3c1 1481 /* Set the FIFO state */
baca51fa
FB		 1482 fdctrl->data_dir = direction;
1483 fdctrl->data_pos = 0;
27c86e24 1484 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1485 if (fdctrl->fifo[0] & 0x80)
1486 fdctrl->data_state |= FD_STATE_MULTI;
1487 else
1488 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1489 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1490 fdctrl->data_len = fdctrl->fifo[8];
1491 } else {
4f431960 1492 int tmp;
3bcb80f1 1493 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1494 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1495 if (fdctrl->fifo[0] & 0x80)
771effeb 1496 tmp += fdctrl->fifo[6];
4f431960 1497 fdctrl->data_len *= tmp;
baca51fa 1498 }
890fa6be 1499 fdctrl->eot = fdctrl->fifo[6];
368df94d 1500 if (fdctrl->dor & FD_DOR_DMAEN) {
8977f3c1
FB		 1501 int dma_mode;
1502 /* DMA transfer are enabled. Check if DMA channel is well programmed */
baca51fa 1503 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
8977f3c1 1504 dma_mode = (dma_mode >> 2) & 3;
baca51fa 1505 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1506 dma_mode, direction,
baca51fa 1507 (128 << fdctrl->fifo[5]) *
4f431960 1508 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
8977f3c1
FB		 1509 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1510 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1511 (direction == FD_DIR_WRITE && dma_mode == 2) ||
7ea004ed
HP		 1512 (direction == FD_DIR_READ && dma_mode == 1) ||
1513 (direction == FD_DIR_VERIFY)) {
8977f3c1 1514 /* No access is allowed until DMA transfer has completed */
b9b3d225 1515 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1516 if (direction != FD_DIR_VERIFY) {
1517 /* Now, we just have to wait for the DMA controller to
1518 * recall us...
1519 */
1520 DMA_hold_DREQ(fdctrl->dma_chann);
19d2b5e6 1521 DMA_schedule();
7ea004ed
HP		 1522 } else {
1523 /* Start transfer */
1524 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1525 fdctrl->data_len);
1526 }
8977f3c1 1527 return;
baca51fa 1528 } else {
cced7a13
BS		 1529 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1530 direction);
8977f3c1
FB		 1531 }
1532 }
1533 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1534 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1535 if (direction != FD_DIR_WRITE)
1536 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1537 /* IO based transfer: calculate len */
d497d534 1538 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1539}
1540
1541/* Prepare a transfer of deleted data */
5c02c033 1542static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1543{
cced7a13 1544 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1545
8977f3c1
FB		 1546 /* We don't handle deleted data,
1547 * so we don't return *ANYTHING*
1548 */
9fea808a 1549 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1550}
1551
1552/* handlers for DMA transfers */
85571bc7
FB		 1553static int fdctrl_transfer_handler (void *opaque, int nchan,
1554 int dma_pos, int dma_len)
8977f3c1 1555{
5c02c033
BS		 1556 FDCtrl *fdctrl;
1557 FDrive *cur_drv;
baca51fa 1558 int len, start_pos, rel_pos;
8977f3c1
FB		 1559 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1560
baca51fa 1561 fdctrl = opaque;
b9b3d225 1562 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1563 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1564 return 0;
1565 }
baca51fa
FB		 1566 cur_drv = get_cur_drv(fdctrl);
1567 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1568 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1569 status2 = FD_SR2_SNS;
85571bc7
FB		 1570 if (dma_len > fdctrl->data_len)
1571 dma_len = fdctrl->data_len;
4be74634 1572 if (cur_drv->blk == NULL) {
4f431960 1573 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1574 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1575 else
9fea808a 1576 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1577 len = 0;
890fa6be
FB		 1578 goto transfer_error;
1579 }
baca51fa 1580 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1581 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1582 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1583 if (len + rel_pos > FD_SECTOR_LEN)
1584 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1585 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1586 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1587 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1588 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1589 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1590 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1591 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1592 /* READ & SCAN commands and realign to a sector for WRITE */
4be74634
MA		 1593 if (blk_read(cur_drv->blk, fd_sector(cur_drv),
1594 fdctrl->fifo, 1) < 0) {
8977f3c1
FB		 1595 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1596 fd_sector(cur_drv));
1597 /* Sure, image size is too small... */
baca51fa 1598 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1599 }
890fa6be 1600 }
4f431960
JM		 1601 switch (fdctrl->data_dir) {
1602 case FD_DIR_READ:
1603 /* READ commands */
85571bc7
FB		 1604 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1605 fdctrl->data_pos, len);
4f431960
JM		 1606 break;
1607 case FD_DIR_WRITE:
baca51fa 1608 /* WRITE commands */
8510854e
HP		 1609 if (cur_drv->ro) {
1610 /* Handle readonly medium early, no need to do DMA, touch the
1611 * LED or attempt any writes. A real floppy doesn't attempt
1612 * to write to readonly media either. */
1613 fdctrl_stop_transfer(fdctrl,
1614 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1615 0x00);
1616 goto transfer_error;
1617 }
1618
85571bc7
FB		 1619 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1620 fdctrl->data_pos, len);
4be74634
MA		 1621 if (blk_write(cur_drv->blk, fd_sector(cur_drv),
1622 fdctrl->fifo, 1) < 0) {
cced7a13
BS		 1623 FLOPPY_DPRINTF("error writing sector %d\n",
1624 fd_sector(cur_drv));
9fea808a 1625 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1626 goto transfer_error;
890fa6be 1627 }
4f431960 1628 break;
7ea004ed
HP		 1629 case FD_DIR_VERIFY:
1630 /* VERIFY commands */
1631 break;
4f431960
JM		 1632 default:
1633 /* SCAN commands */
baca51fa 1634 {
4f431960 1635 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1636 int ret;
85571bc7 1637 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
baca51fa 1638 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1639 if (ret == 0) {
77370520 1640 status2 = FD_SR2_SEH;
8977f3c1
FB		 1641 goto end_transfer;
1642 }
baca51fa
FB		 1643 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1644 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1645 status2 = 0x00;
1646 goto end_transfer;
1647 }
1648 }
4f431960 1649 break;
8977f3c1 1650 }
4f431960
JM		 1651 fdctrl->data_pos += len;
1652 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1653 if (rel_pos == 0) {
8977f3c1 1654 /* Seek to next sector */
746d6de7
BS		 1655 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1656 break;
8977f3c1
FB		 1657 }
1658 }
4f431960 1659 end_transfer:
baca51fa
FB		 1660 len = fdctrl->data_pos - start_pos;
1661 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1662 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1663 if (fdctrl->data_dir == FD_DIR_SCANE ||
1664 fdctrl->data_dir == FD_DIR_SCANL ||
1665 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1666 status2 = FD_SR2_SEH;
baca51fa 1667 fdctrl->data_len -= len;
890fa6be 1668 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1669 transfer_error:
8977f3c1 1670
baca51fa 1671 return len;
8977f3c1
FB		 1672}
1673
8977f3c1 1674/* Data register : 0x05 */
5c02c033 1675static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1676{
5c02c033 1677 FDrive *cur_drv;
8977f3c1 1678 uint32_t retval = 0;
e9077462 1679 uint32_t pos;
8977f3c1 1680
baca51fa 1681 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1682 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1683 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1684 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1685 return 0;
1686 }
f6c2d1d8
KW		 1687
1688 /* If data_len spans multiple sectors, the current position in the FIFO
1689 * wraps around while fdctrl->data_pos is the real position in the whole
1690 * request. */
baca51fa 1691 pos = fdctrl->data_pos;
e9077462 1692 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1693
1694 switch (fdctrl->phase) {
1695 case FD_PHASE_EXECUTION:
1696 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1697 if (pos == 0) {
746d6de7
BS		 1698 if (fdctrl->data_pos != 0)
1699 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1700 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1701 fd_sector(cur_drv));
1702 return 0;
1703 }
4be74634
MA		 1704 if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
1705 < 0) {
77370520
BS		 1706 FLOPPY_DPRINTF("error getting sector %d\n",
1707 fd_sector(cur_drv));
1708 /* Sure, image size is too small... */
1709 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1710 }
8977f3c1 1711 }
f6c2d1d8
KW		 1712
1713 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1714 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1715 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1716 }
1717 break;
1718
1719 case FD_PHASE_RESULT:
1720 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1721 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1722 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1723 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1724 fdctrl_reset_irq(fdctrl);
1725 }
f6c2d1d8
KW		 1726 break;
1727
1728 case FD_PHASE_COMMAND:
1729 default:
1730 abort();
8977f3c1 1731 }
f6c2d1d8
KW		 1732
1733 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1734 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1735
1736 return retval;
1737}
1738
5c02c033 1739static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1740{
5c02c033 1741 FDrive *cur_drv;
baca51fa 1742 uint8_t kh, kt, ks;
8977f3c1 1743
cefec4f5 1744 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1745 cur_drv = get_cur_drv(fdctrl);
1746 kt = fdctrl->fifo[6];
1747 kh = fdctrl->fifo[7];
1748 ks = fdctrl->fifo[8];
1749 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1750 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1751 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1752 NUM_SIDES(cur_drv)));
9fea808a 1753 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1754 case 2:
1755 /* sect too big */
9fea808a 1756 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1757 fdctrl->fifo[3] = kt;
1758 fdctrl->fifo[4] = kh;
1759 fdctrl->fifo[5] = ks;
1760 return;
1761 case 3:
1762 /* track too big */
77370520 1763 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1764 fdctrl->fifo[3] = kt;
1765 fdctrl->fifo[4] = kh;
1766 fdctrl->fifo[5] = ks;
1767 return;
1768 case 4:
1769 /* No seek enabled */
9fea808a 1770 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1771 fdctrl->fifo[3] = kt;
1772 fdctrl->fifo[4] = kh;
1773 fdctrl->fifo[5] = ks;
1774 return;
1775 case 1:
cd30b53d 1776 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 1777 break;
1778 default:
1779 break;
1780 }
1781 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634
MA		 1782 if (cur_drv->blk == NULL ||
1783 blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
cced7a13 1784 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 1785 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1786 } else {
4f431960
JM		 1787 if (cur_drv->sect == cur_drv->last_sect) {
1788 fdctrl->data_state &= ~FD_STATE_FORMAT;
1789 /* Last sector done */
cd30b53d 1790 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 1791 } else {
1792 /* More to do */
1793 fdctrl->data_pos = 0;
1794 fdctrl->data_len = 4;
1795 }
baca51fa
FB		 1796 }
1797}
1798
5c02c033 1799static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 1800{
1801 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1802 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 1803 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1804}
1805
5c02c033 1806static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 1807{
5c02c033 1808 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1809
1810 /* Drives position */
1811 fdctrl->fifo[0] = drv0(fdctrl)->track;
1812 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 1813#if MAX_FD == 4
1814 fdctrl->fifo[2] = drv2(fdctrl)->track;
1815 fdctrl->fifo[3] = drv3(fdctrl)->track;
1816#else
65cef780
BS		 1817 fdctrl->fifo[2] = 0;
1818 fdctrl->fifo[3] = 0;
78ae820c 1819#endif
65cef780
BS		 1820 /* timers */
1821 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 1822 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 1823 fdctrl->fifo[6] = cur_drv->last_sect;
1824 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1825 (cur_drv->perpendicular << 2);
1826 fdctrl->fifo[8] = fdctrl->config;
1827 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 1828 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 1829}
1830
5c02c033 1831static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 1832{
1833 /* Controller's version */
1834 fdctrl->fifo[0] = fdctrl->version;
83a26013 1835 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1836}
1837
5c02c033 1838static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 1839{
1840 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 1841 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1842}
1843
5c02c033 1844static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 1845{
5c02c033 1846 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1847
1848 /* Drives position */
1849 drv0(fdctrl)->track = fdctrl->fifo[3];
1850 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 1851#if MAX_FD == 4
1852 drv2(fdctrl)->track = fdctrl->fifo[5];
1853 drv3(fdctrl)->track = fdctrl->fifo[6];
1854#endif
65cef780
BS		 1855 /* timers */
1856 fdctrl->timer0 = fdctrl->fifo[7];
1857 fdctrl->timer1 = fdctrl->fifo[8];
1858 cur_drv->last_sect = fdctrl->fifo[9];
1859 fdctrl->lock = fdctrl->fifo[10] >> 7;
1860 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1861 fdctrl->config = fdctrl->fifo[11];
1862 fdctrl->precomp_trk = fdctrl->fifo[12];
1863 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 1864 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1865}
1866
5c02c033 1867static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 1868{
5c02c033 1869 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1870
1871 fdctrl->fifo[0] = 0;
1872 fdctrl->fifo[1] = 0;
1873 /* Drives position */
1874 fdctrl->fifo[2] = drv0(fdctrl)->track;
1875 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 1876#if MAX_FD == 4
1877 fdctrl->fifo[4] = drv2(fdctrl)->track;
1878 fdctrl->fifo[5] = drv3(fdctrl)->track;
1879#else
65cef780
BS		 1880 fdctrl->fifo[4] = 0;
1881 fdctrl->fifo[5] = 0;
78ae820c 1882#endif
65cef780
BS		 1883 /* timers */
1884 fdctrl->fifo[6] = fdctrl->timer0;
1885 fdctrl->fifo[7] = fdctrl->timer1;
1886 fdctrl->fifo[8] = cur_drv->last_sect;
1887 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1888 (cur_drv->perpendicular << 2);
1889 fdctrl->fifo[10] = fdctrl->config;
1890 fdctrl->fifo[11] = fdctrl->precomp_trk;
1891 fdctrl->fifo[12] = fdctrl->pwrd;
1892 fdctrl->fifo[13] = 0;
1893 fdctrl->fifo[14] = 0;
83a26013 1894 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 1895}
1896
5c02c033 1897static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 1898{
5c02c033 1899 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1900
65cef780 1901 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
bc72ad67
AB		 1902 timer_mod(fdctrl->result_timer,
1903 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50));
65cef780
BS		 1904}
1905
5c02c033 1906static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 1907{
5c02c033 1908 FDrive *cur_drv;
65cef780 1909
cefec4f5 1910 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1911 cur_drv = get_cur_drv(fdctrl);
1912 fdctrl->data_state |= FD_STATE_FORMAT;
1913 if (fdctrl->fifo[0] & 0x80)
1914 fdctrl->data_state |= FD_STATE_MULTI;
1915 else
1916 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 1917 cur_drv->bps =
1918 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1919#if 0
1920 cur_drv->last_sect =
1921 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1922 fdctrl->fifo[3] / 2;
1923#else
1924 cur_drv->last_sect = fdctrl->fifo[3];
1925#endif
1926 /* TODO: implement format using DMA expected by the Bochs BIOS
1927 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1928 * the sector with the specified fill byte
1929 */
1930 fdctrl->data_state &= ~FD_STATE_FORMAT;
1931 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1932}
1933
5c02c033 1934static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 1935{
1936 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1937 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 1938 if (fdctrl->fifo[2] & 1)
1939 fdctrl->dor &= ~FD_DOR_DMAEN;
1940 else
1941 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 1942 /* No result back */
07e415f2 1943 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1944}
1945
5c02c033 1946static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 1947{
5c02c033 1948 FDrive *cur_drv;
65cef780 1949
cefec4f5 1950 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1951 cur_drv = get_cur_drv(fdctrl);
1952 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1953 /* 1 Byte status back */
1954 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1955 (cur_drv->track == 0 ? 0x10 : 0x00) |
1956 (cur_drv->head << 2) |
cefec4f5 1957 GET_CUR_DRV(fdctrl) |
65cef780 1958 0x28;
83a26013 1959 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1960}
1961
5c02c033 1962static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 1963{
5c02c033 1964 FDrive *cur_drv;
65cef780 1965
cefec4f5 1966 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1967 cur_drv = get_cur_drv(fdctrl);
1968 fd_recalibrate(cur_drv);
07e415f2 1969 fdctrl_to_command_phase(fdctrl);
65cef780 1970 /* Raise Interrupt */
d497d534
HP		 1971 fdctrl->status0 |= FD_SR0_SEEK;
1972 fdctrl_raise_irq(fdctrl);
65cef780
BS		 1973}
1974
5c02c033 1975static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 1976{
5c02c033 1977 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1978
2fee0088 1979 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 1980 fdctrl->fifo[0] =
1981 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1982 fdctrl->reset_sensei--;
2fee0088
PH		 1983 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1984 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1985 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 1986 return;
f2d81b33 1987 } else {
f2d81b33 1988 fdctrl->fifo[0] =
2fee0088
PH		 1989 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1990 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 1991 }
1992
65cef780 1993 fdctrl->fifo[1] = cur_drv->track;
83a26013 1994 fdctrl_to_result_phase(fdctrl, 2);
65cef780 1995 fdctrl_reset_irq(fdctrl);
77370520 1996 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 1997}
1998
5c02c033 1999static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2000{
5c02c033 2001 FDrive *cur_drv;
65cef780 2002
cefec4f5 2003 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2004 cur_drv = get_cur_drv(fdctrl);
07e415f2 2005 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2006 /* The seek command just sends step pulses to the drive and doesn't care if
2007 * there is a medium inserted of if it's banging the head against the drive.
2008 */
6be01b1e 2009 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2010 /* Raise Interrupt */
d497d534
HP		 2011 fdctrl->status0 |= FD_SR0_SEEK;
2012 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2013}
2014
5c02c033 2015static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2016{
5c02c033 2017 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2018
2019 if (fdctrl->fifo[1] & 0x80)
2020 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2021 /* No result back */
07e415f2 2022 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2023}
2024
5c02c033 2025static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2026{
2027 fdctrl->config = fdctrl->fifo[2];
2028 fdctrl->precomp_trk = fdctrl->fifo[3];
2029 /* No result back */
07e415f2 2030 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2031}
2032
5c02c033 2033static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2034{
2035 fdctrl->pwrd = fdctrl->fifo[1];
2036 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2037 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2038}
2039
5c02c033 2040static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2041{
2042 /* No result back */
07e415f2 2043 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2044}
2045
5c02c033 2046static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2047{
5c02c033 2048 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2049 uint32_t pos;
65cef780 2050
e9077462
PM		 2051 pos = fdctrl->data_pos - 1;
2052 pos %= FD_SECTOR_LEN;
2053 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2054 /* Command parameters done */
e9077462 2055 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2056 fdctrl->fifo[0] = fdctrl->fifo[1];
2057 fdctrl->fifo[2] = 0;
2058 fdctrl->fifo[3] = 0;
83a26013 2059 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2060 } else {
07e415f2 2061 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2062 }
2063 } else if (fdctrl->data_len > 7) {
2064 /* ERROR */
2065 fdctrl->fifo[0] = 0x80 |
cefec4f5 2066 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2067 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2068 }
2069}
2070
6d013772 2071static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2072{
5c02c033 2073 FDrive *cur_drv;
65cef780 2074
cefec4f5 2075 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2076 cur_drv = get_cur_drv(fdctrl);
65cef780 2077 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2078 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2079 cur_drv->sect, 1);
65cef780 2080 } else {
6d013772
PH		 2081 fd_seek(cur_drv, cur_drv->head,
2082 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2083 }
07e415f2 2084 fdctrl_to_command_phase(fdctrl);
77370520 2085 /* Raise Interrupt */
d497d534
HP		 2086 fdctrl->status0 |= FD_SR0_SEEK;
2087 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2088}
2089
6d013772 2090static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2091{
5c02c033 2092 FDrive *cur_drv;
65cef780 2093
cefec4f5 2094 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2095 cur_drv = get_cur_drv(fdctrl);
65cef780 2096 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2097 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2098 } else {
6d013772
PH		 2099 fd_seek(cur_drv, cur_drv->head,
2100 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2101 }
07e415f2 2102 fdctrl_to_command_phase(fdctrl);
65cef780 2103 /* Raise Interrupt */
d497d534
HP		 2104 fdctrl->status0 |= FD_SR0_SEEK;
2105 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2106}
2107
85d291a0
KW		 2108/*
2109 * Handlers for the execution phase of each command
2110 */
d275b33d 2111typedef struct FDCtrlCommand {
678803ab
BS		 2112 uint8_t value;
2113 uint8_t mask;
2114 const char* name;
2115 int parameters;
5c02c033 2116 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2117 int direction;
d275b33d
KW		 2118} FDCtrlCommand;
2119
2120static const FDCtrlCommand handlers[] = {
678803ab
BS		 2121 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2122 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2123 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2124 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2125 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2126 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2127 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2128 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2129 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2130 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2131 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2132 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2133 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2134 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2135 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2136 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2137 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2138 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2139 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2140 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2141 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2142 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2143 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2144 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2145 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2146 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2147 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2148 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2149 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2150 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2151 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2152 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2153};
2154/* Associate command to an index in the 'handlers' array */
2155static uint8_t command_to_handler[256];
2156
d275b33d
KW		 2157static const FDCtrlCommand *get_command(uint8_t cmd)
2158{
2159 int idx;
2160
2161 idx = command_to_handler[cmd];
2162 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2163 return &handlers[idx];
2164}
2165
5c02c033 2166static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2167{
5c02c033 2168 FDrive *cur_drv;
d275b33d 2169 const FDCtrlCommand *cmd;
e9077462 2170 uint32_t pos;
baca51fa 2171
8977f3c1 2172 /* Reset mode */
1c346df2 2173 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2174 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2175 return;
2176 }
b9b3d225 2177 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2178 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2179 return;
2180 }
b9b3d225 2181 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2182
d275b33d
KW		 2183 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2184
2185 /* If data_len spans multiple sectors, the current position in the FIFO
2186 * wraps around while fdctrl->data_pos is the real position in the whole
2187 * request. */
2188 pos = fdctrl->data_pos++;
2189 pos %= FD_SECTOR_LEN;
2190 fdctrl->fifo[pos] = value;
2191
6cc8a11c
KW		 2192 if (fdctrl->data_pos == fdctrl->data_len) {
2193 fdctrl->msr &= ~FD_MSR_RQM;
2194 }
2195
5b0a25e8
KW		 2196 switch (fdctrl->phase) {
2197 case FD_PHASE_EXECUTION:
2198 /* For DMA requests, RQM should be cleared during execution phase, so
2199 * we would have errored out above. */
2200 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2201
8977f3c1 2202 /* FIFO data write */
b3bc1540 2203 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2204 fdctrl->data_pos == fdctrl->data_len) {
77370520 2205 cur_drv = get_cur_drv(fdctrl);
4be74634
MA		 2206 if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1)
2207 < 0) {
cced7a13
BS		 2208 FLOPPY_DPRINTF("error writing sector %d\n",
2209 fd_sector(cur_drv));
5b0a25e8 2210 break;
77370520 2211 }
746d6de7
BS		 2212 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2213 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2214 fd_sector(cur_drv));
5b0a25e8 2215 break;
746d6de7 2216 }
8977f3c1 2217 }
d275b33d
KW		 2218
2219 /* Switch to result phase when done with the transfer */
2220 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2221 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2222 }
5b0a25e8 2223 break;
678803ab 2224
5b0a25e8
KW		 2225 case FD_PHASE_COMMAND:
2226 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2227 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2228
d275b33d
KW		 2229 if (pos == 0) {
2230 /* The first byte specifies the command. Now we start reading
2231 * as many parameters as this command requires. */
2232 cmd = get_command(value);
2233 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2234 if (cmd->parameters) {
2235 fdctrl->msr |= FD_MSR_RQM;
2236 }
5b0a25e8 2237 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2238 }
65cef780 2239
5b0a25e8 2240 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2241 /* We have all parameters now, execute the command */
5b0a25e8 2242 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2243
5b0a25e8
KW		 2244 if (fdctrl->data_state & FD_STATE_FORMAT) {
2245 fdctrl_format_sector(fdctrl);
2246 break;
2247 }
2248
d275b33d
KW		 2249 cmd = get_command(fdctrl->fifo[0]);
2250 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2251 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2252 }
2253 break;
2254
2255 case FD_PHASE_RESULT:
2256 default:
2257 abort();
8977f3c1
FB		 2258 }
2259}
ed5fd2cc
FB		 2260
2261static void fdctrl_result_timer(void *opaque)
2262{
5c02c033
BS		 2263 FDCtrl *fdctrl = opaque;
2264 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2265
b7ffa3b1
TS		 2266 /* Pretend we are spinning.
2267 * This is needed for Coherent, which uses READ ID to check for
2268 * sector interleaving.
2269 */
2270 if (cur_drv->last_sect != 0) {
2271 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2272 }
844f65d6
HP		 2273 /* READ_ID can't automatically succeed! */
2274 if (fdctrl->check_media_rate &&
2275 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2276 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2277 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2278 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2279 } else {
2280 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2281 }
ed5fd2cc 2282}
678803ab 2283
7d4b4ba5 2284static void fdctrl_change_cb(void *opaque, bool load)
8e49ca46
MA		 2285{
2286 FDrive *drive = opaque;
2287
2e1280e8
HR		 2288 drive->media_inserted = load && drive->blk && blk_is_inserted(drive->blk);
2289
8e49ca46 2290 drive->media_changed = 1;
d5d47efc 2291 drive->media_validated = false;
21fcf360 2292 fd_revalidate(drive);
8e49ca46
MA		 2293}
2294
2e1280e8
HR		 2295static bool fdctrl_is_tray_open(void *opaque)
2296{
2297 FDrive *drive = opaque;
2298 return !drive->media_inserted;
2299}
2300
8e49ca46
MA		 2301static const BlockDevOps fdctrl_block_ops = {
2302 .change_media_cb = fdctrl_change_cb,
2e1280e8 2303 .is_tray_open = fdctrl_is_tray_open,
8e49ca46
MA		 2304};
2305
678803ab 2306/* Init functions */
a3ef7a61 2307static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
678803ab 2308{
12a71a02 2309 unsigned int i;
7d0d6950 2310 FDrive *drive;
678803ab 2311
678803ab 2312 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2313 drive = &fdctrl->drives[i];
844f65d6 2314 drive->fdctrl = fdctrl;
7d0d6950 2315
4be74634
MA		 2316 if (drive->blk) {
2317 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
a3ef7a61
AF		 2318 error_setg(errp, "fdc doesn't support drive option werror");
2319 return;
b47b3525 2320 }
4be74634 2321 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
a3ef7a61
AF		 2322 error_setg(errp, "fdc doesn't support drive option rerror");
2323 return;
b47b3525
MA		 2324 }
2325 }
2326
7d0d6950 2327 fd_init(drive);
4be74634
MA		 2328 if (drive->blk) {
2329 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2e1280e8 2330 drive->media_inserted = blk_is_inserted(drive->blk);
d5d47efc 2331 pick_drive_type(drive);
7d0d6950 2332 }
d5d47efc 2333 fd_revalidate(drive);
678803ab 2334 }
678803ab
BS		 2335}
2336
dfc65f1f
MA		 2337ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2338{
4a17cc4f
AF		 2339 DeviceState *dev;
2340 ISADevice *isadev;
dfc65f1f 2341
4a17cc4f
AF		 2342 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2343 if (!isadev) {
dfc65f1f
MA		 2344 return NULL;
2345 }
4a17cc4f 2346 dev = DEVICE(isadev);
dfc65f1f
MA		 2347
2348 if (fds[0]) {
6231a6da
MA		 2349 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2350 &error_fatal);
dfc65f1f
MA		 2351 }
2352 if (fds[1]) {
6231a6da
MA		 2353 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2354 &error_fatal);
dfc65f1f 2355 }
4a17cc4f 2356 qdev_init_nofail(dev);
dfc65f1f 2357
4a17cc4f 2358 return isadev;
dfc65f1f
MA		 2359}
2360
63ffb564 2361void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2362 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2363{
5c02c033 2364 FDCtrl *fdctrl;
2091ba23 2365 DeviceState *dev;
dd3be742 2366 SysBusDevice *sbd;
5c02c033 2367 FDCtrlSysBus *sys;
2091ba23 2368
19d46d71 2369 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2370 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2371 fdctrl = &sys->state;
2372 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2373 if (fds[0]) {
6231a6da
MA		 2374 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2375 &error_fatal);
995bf0ca
GH		 2376 }
2377 if (fds[1]) {
6231a6da
MA		 2378 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2379 &error_fatal);
995bf0ca 2380 }
e23a1b33 2381 qdev_init_nofail(dev);
dd3be742
HT		 2382 sbd = SYS_BUS_DEVICE(dev);
2383 sysbus_connect_irq(sbd, 0, irq);
2384 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2385}
2386
a8170e5e 2387void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2388 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2389{
f64ab228 2390 DeviceState *dev;
5c02c033 2391 FDCtrlSysBus *sys;
678803ab 2392
12a71a02 2393 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2394 if (fds[0]) {
6231a6da
MA		 2395 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2396 &error_fatal);
995bf0ca 2397 }
e23a1b33 2398 qdev_init_nofail(dev);
dd3be742
HT		 2399 sys = SYSBUS_FDC(dev);
2400 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2401 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2402 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2403}
f64ab228 2404
a3ef7a61 2405static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
f64ab228 2406{
12a71a02
BS		 2407 int i, j;
2408 static int command_tables_inited = 0;
f64ab228 2409
a73275dd
JS		 2410 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2411 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2412 }
2413
12a71a02
BS		 2414 /* Fill 'command_to_handler' lookup table */
2415 if (!command_tables_inited) {
2416 command_tables_inited = 1;
2417 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2418 for (j = 0; j < sizeof(command_to_handler); j++) {
2419 if ((j & handlers[i].mask) == handlers[i].value) {
2420 command_to_handler[j] = i;
2421 }
2422 }
2423 }
2424 }
2425
2426 FLOPPY_DPRINTF("init controller\n");
2427 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 2428 fdctrl->fifo_size = 512;
bc72ad67 2429 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2430 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2431
2432 fdctrl->version = 0x90; /* Intel 82078 controller */
2433 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2434 fdctrl->num_floppies = MAX_FD;
12a71a02 2435
a3ef7a61 2436 if (fdctrl->dma_chann != -1) {
99244fa1 2437 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
a3ef7a61
AF		 2438 }
2439 fdctrl_connect_drives(fdctrl, errp);
f64ab228
BS		 2440}
2441
212ec7ba 2442static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2443 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2444 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2445 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2446};
2447
db895a1e 2448static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2449{
db895a1e 2450 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2451 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2452 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2453 Error *err = NULL;
8baf73ad 2454
db895a1e
AF		 2455 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2456 "fdc");
dee41d58 2457
db895a1e 2458 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2459 fdctrl->dma_chann = isa->dma;
8baf73ad 2460
db895a1e 2461 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
a3ef7a61
AF		 2462 fdctrl_realize_common(fdctrl, &err);
2463 if (err != NULL) {
2464 error_propagate(errp, err);
db895a1e
AF		 2465 return;
2466 }
8baf73ad
GH		 2467}
2468
940194c2 2469static void sysbus_fdc_initfn(Object *obj)
12a71a02 2470{
19d46d71 2471 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2472 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2473 FDCtrl *fdctrl = &sys->state;
12a71a02 2474
19d46d71
AF		 2475 fdctrl->dma_chann = -1;
2476
940194c2 2477 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2478 "fdc", 0x08);
19d46d71 2479 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2480}
2481
19d46d71 2482static void sun4m_fdc_initfn(Object *obj)
940194c2 2483{
19d46d71
AF		 2484 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2485 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2486 FDCtrl *fdctrl = &sys->state;
940194c2 2487
19d46d71
AF		 2488 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2489 fdctrl, "fdctrl", 0x08);
2490 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2491}
2be37833 2492
19d46d71 2493static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2494{
19d46d71
AF		 2495 DeviceState *dev = DEVICE(obj);
2496 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2497 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2498 FDCtrl *fdctrl = &sys->state;
2499
19d46d71
AF		 2500 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2501
2502 sysbus_init_irq(sbd, &fdctrl->irq);
2503 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2504}
2505
19d46d71 2506static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2507{
dd3be742
HT		 2508 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2509 FDCtrl *fdctrl = &sys->state;
12a71a02 2510
19d46d71 2511 fdctrl_realize_common(fdctrl, errp);
12a71a02 2512}
f64ab228 2513
2da44dd0 2514FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2515{
020c8e76 2516 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2517
61a8d649 2518 return isa->state.drives[i].drive;
34d4260e
KW		 2519}
2520
a64405d1
JK		 2521static const VMStateDescription vmstate_isa_fdc ={
2522 .name = "fdc",
2523 .version_id = 2,
2524 .minimum_version_id = 2,
d49805ae 2525 .fields = (VMStateField[]) {
a64405d1
JK		 2526 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2527 VMSTATE_END_OF_LIST()
2528 }
2529};
2530
39bffca2 2531static Property isa_fdc_properties[] = {
c7bcc85d 2532 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2533 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2534 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
4be74634
MA		 2535 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2536 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
09c6d585
HP		 2537 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2538 0, true),
fff4687b
JS		 2539 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2540 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2541 FloppyDriveType),
2542 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2543 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2544 FloppyDriveType),
a73275dd
JS		 2545 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2546 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2547 FloppyDriveType),
39bffca2
AL		 2548 DEFINE_PROP_END_OF_LIST(),
2549};
2550
020c8e76 2551static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2552{
39bffca2 2553 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2554
2555 dc->realize = isabus_fdc_realize;
39bffca2 2556 dc->fw_name = "fdc";
39bffca2
AL		 2557 dc->reset = fdctrl_external_reset_isa;
2558 dc->vmsd = &vmstate_isa_fdc;
2559 dc->props = isa_fdc_properties;
125ee0ed 2560 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2561}
2562
81782b6a
GA		 2563static void isabus_fdc_instance_init(Object *obj)
2564{
2565 FDCtrlISABus *isa = ISA_FDC(obj);
2566
2567 device_add_bootindex_property(obj, &isa->bootindexA,
2568 "bootindexA", "/floppy@0",
2569 DEVICE(obj), NULL);
2570 device_add_bootindex_property(obj, &isa->bootindexB,
2571 "bootindexB", "/floppy@1",
2572 DEVICE(obj), NULL);
2573}
2574
8c43a6f0 2575static const TypeInfo isa_fdc_info = {
020c8e76 2576 .name = TYPE_ISA_FDC,
39bffca2
AL		 2577 .parent = TYPE_ISA_DEVICE,
2578 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2579 .class_init = isabus_fdc_class_init,
81782b6a 2580 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2581};
2582
a64405d1
JK		 2583static const VMStateDescription vmstate_sysbus_fdc ={
2584 .name = "fdc",
2585 .version_id = 2,
2586 .minimum_version_id = 2,
d49805ae 2587 .fields = (VMStateField[]) {
a64405d1
JK		 2588 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2589 VMSTATE_END_OF_LIST()
2590 }
2591};
2592
999e12bb 2593static Property sysbus_fdc_properties[] = {
4be74634
MA		 2594 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2595 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
fff4687b
JS		 2596 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2597 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2598 FloppyDriveType),
2599 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2600 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2601 FloppyDriveType),
a73275dd
JS		 2602 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2603 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2604 FloppyDriveType),
999e12bb 2605 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2606};
2607
999e12bb
AL		 2608static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2609{
39bffca2 2610 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2611
39bffca2 2612 dc->props = sysbus_fdc_properties;
125ee0ed 2613 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2614}
2615
8c43a6f0 2616static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2617 .name = "sysbus-fdc",
2618 .parent = TYPE_SYSBUS_FDC,
940194c2 2619 .instance_init = sysbus_fdc_initfn,
39bffca2 2620 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2621};
2622
2623static Property sun4m_fdc_properties[] = {
4be74634 2624 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
fff4687b
JS		 2625 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2626 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2627 FloppyDriveType),
a73275dd
JS		 2628 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2629 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2630 FloppyDriveType),
999e12bb
AL		 2631 DEFINE_PROP_END_OF_LIST(),
2632};
2633
2634static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2635{
39bffca2 2636 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2637
39bffca2 2638 dc->props = sun4m_fdc_properties;
125ee0ed 2639 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2640}
2641
8c43a6f0 2642static const TypeInfo sun4m_fdc_info = {
39bffca2 2643 .name = "SUNW,fdtwo",
19d46d71 2644 .parent = TYPE_SYSBUS_FDC,
940194c2 2645 .instance_init = sun4m_fdc_initfn,
39bffca2 2646 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2647};
2648
19d46d71
AF		 2649static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2650{
2651 DeviceClass *dc = DEVICE_CLASS(klass);
2652
2653 dc->realize = sysbus_fdc_common_realize;
2654 dc->reset = fdctrl_external_reset_sysbus;
2655 dc->vmsd = &vmstate_sysbus_fdc;
2656}
2657
2658static const TypeInfo sysbus_fdc_type_info = {
2659 .name = TYPE_SYSBUS_FDC,
2660 .parent = TYPE_SYS_BUS_DEVICE,
2661 .instance_size = sizeof(FDCtrlSysBus),
2662 .instance_init = sysbus_fdc_common_initfn,
2663 .abstract = true,
2664 .class_init = sysbus_fdc_common_class_init,
2665};
2666
83f7d43a 2667static void fdc_register_types(void)
f64ab228 2668{
39bffca2 2669 type_register_static(&isa_fdc_info);
19d46d71 2670 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2671 type_register_static(&sysbus_fdc_info);
2672 type_register_static(&sun4m_fdc_info);
f64ab228
BS		 2673}
2674
83f7d43a 2675type_init(fdc_register_types)
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