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Commit | Line | Data |
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8977f3c1 | 1 | /* |
890fa6be | 2 | * QEMU Floppy disk emulator (Intel 82078) |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003, 2007 Jocelyn Mayer |
bcc4e41f | 5 | * Copyright (c) 2008 Hervé Poussineau |
5fafdf24 | 6 | * |
8977f3c1 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
e80cfcfc FB |
25 | /* |
26 | * The controller is used in Sun4m systems in a slightly different | |
27 | * way. There are changes in DOR register and DMA is not available. | |
28 | */ | |
f64ab228 | 29 | |
80c71a24 | 30 | #include "qemu/osdep.h" |
0d09e41a | 31 | #include "hw/block/fdc.h" |
da34e65c | 32 | #include "qapi/error.h" |
1de7afc9 PB |
33 | #include "qemu/error-report.h" |
34 | #include "qemu/timer.h" | |
5df022cf | 35 | #include "qemu/memalign.h" |
64552b6b | 36 | #include "hw/irq.h" |
0d09e41a | 37 | #include "hw/isa/isa.h" |
a27bd6c7 | 38 | #include "hw/qdev-properties.h" |
ce35e229 | 39 | #include "hw/qdev-properties-system.h" |
d6454270 | 40 | #include "migration/vmstate.h" |
a92bd191 | 41 | #include "hw/block/block.h" |
fa1d36df | 42 | #include "sysemu/block-backend.h" |
9c17d615 PB |
43 | #include "sysemu/blockdev.h" |
44 | #include "sysemu/sysemu.h" | |
1de7afc9 | 45 | #include "qemu/log.h" |
db725815 | 46 | #include "qemu/main-loop.h" |
0b8fa32f | 47 | #include "qemu/module.h" |
1a5396d9 | 48 | #include "trace.h" |
db1015e9 | 49 | #include "qom/object.h" |
5a5d2f3d | 50 | #include "fdc-internal.h" |
8977f3c1 FB |
51 | |
52 | /********************************************************/ | |
53 | /* debug Floppy devices */ | |
8977f3c1 | 54 | |
c691320f JS |
55 | #define DEBUG_FLOPPY 0 |
56 | ||
001faf32 | 57 | #define FLOPPY_DPRINTF(fmt, ...) \ |
c691320f JS |
58 | do { \ |
59 | if (DEBUG_FLOPPY) { \ | |
60 | fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \ | |
61 | } \ | |
62 | } while (0) | |
8977f3c1 | 63 | |
51e6e90e | 64 | |
b154791e PMD |
65 | /* Anonymous BlockBackend for empty drive */ |
66 | static BlockBackend *blk_create_empty_drive(void) | |
67 | { | |
68 | return blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); | |
69 | } | |
70 | ||
51e6e90e KW |
71 | /********************************************************/ |
72 | /* qdev floppy bus */ | |
73 | ||
74 | #define TYPE_FLOPPY_BUS "floppy-bus" | |
8063396b | 75 | OBJECT_DECLARE_SIMPLE_TYPE(FloppyBus, FLOPPY_BUS) |
51e6e90e | 76 | |
394ea2ca | 77 | static FDrive *get_drv(FDCtrl *fdctrl, int unit); |
51e6e90e | 78 | |
51e6e90e KW |
79 | static const TypeInfo floppy_bus_info = { |
80 | .name = TYPE_FLOPPY_BUS, | |
81 | .parent = TYPE_BUS, | |
82 | .instance_size = sizeof(FloppyBus), | |
83 | }; | |
84 | ||
85 | static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev) | |
86 | { | |
d637e1dc | 87 | qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); |
51e6e90e KW |
88 | bus->fdc = fdc; |
89 | } | |
90 | ||
91 | ||
8977f3c1 FB |
92 | /********************************************************/ |
93 | /* Floppy drive emulation */ | |
94 | ||
109c17bc JS |
95 | /* In many cases, the total sector size of a format is enough to uniquely |
96 | * identify it. However, there are some total sector collisions between | |
97 | * formats of different physical size, and these are noted below by | |
98 | * highlighting the total sector size for entries with collisions. */ | |
5a5d2f3d | 99 | const FDFormat fd_formats[] = { |
61a8d649 MA |
100 | /* First entry is default format */ |
101 | /* 1.44 MB 3"1/2 floppy disks */ | |
109c17bc JS |
102 | { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */ |
103 | { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */ | |
2da44dd0 JS |
104 | { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, |
105 | { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, | |
106 | { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, | |
107 | { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, | |
108 | { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, | |
109 | { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, | |
61a8d649 | 110 | /* 2.88 MB 3"1/2 floppy disks */ |
2da44dd0 JS |
111 | { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, |
112 | { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, | |
113 | { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, | |
114 | { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, | |
115 | { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, | |
61a8d649 | 116 | /* 720 kB 3"1/2 floppy disks */ |
109c17bc | 117 | { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */ |
2da44dd0 JS |
118 | { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, |
119 | { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, | |
120 | { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, | |
121 | { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, | |
122 | { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, | |
61a8d649 | 123 | /* 1.2 MB 5"1/4 floppy disks */ |
2da44dd0 | 124 | { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, |
109c17bc | 125 | { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */ |
2da44dd0 JS |
126 | { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, |
127 | { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, | |
109c17bc | 128 | { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */ |
61a8d649 | 129 | /* 720 kB 5"1/4 floppy disks */ |
109c17bc | 130 | { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */ |
2da44dd0 | 131 | { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, |
61a8d649 | 132 | /* 360 kB 5"1/4 floppy disks */ |
109c17bc | 133 | { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */ |
2da44dd0 JS |
134 | { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, |
135 | { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, | |
136 | { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, | |
61a8d649 | 137 | /* 320 kB 5"1/4 floppy disks */ |
2da44dd0 JS |
138 | { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, |
139 | { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, | |
61a8d649 | 140 | /* 360 kB must match 5"1/4 better than 3"1/2... */ |
109c17bc | 141 | { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */ |
61a8d649 | 142 | /* end */ |
2da44dd0 | 143 | { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, |
61a8d649 MA |
144 | }; |
145 | ||
109c17bc JS |
146 | static FDriveSize drive_size(FloppyDriveType drive) |
147 | { | |
148 | switch (drive) { | |
149 | case FLOPPY_DRIVE_TYPE_120: | |
150 | return FDRIVE_SIZE_525; | |
151 | case FLOPPY_DRIVE_TYPE_144: | |
152 | case FLOPPY_DRIVE_TYPE_288: | |
153 | return FDRIVE_SIZE_350; | |
154 | default: | |
155 | return FDRIVE_SIZE_UNKNOWN; | |
156 | } | |
157 | } | |
158 | ||
cefec4f5 BS |
159 | #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) |
160 | #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) | |
161 | ||
8977f3c1 | 162 | /* Will always be a fixed parameter for us */ |
f2d81b33 BS |
163 | #define FD_SECTOR_LEN 512 |
164 | #define FD_SECTOR_SC 2 /* Sector size code */ | |
165 | #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ | |
8977f3c1 | 166 | |
a73275dd JS |
167 | |
168 | static FloppyDriveType get_fallback_drive_type(FDrive *drv); | |
169 | ||
fd9bdbd3 JS |
170 | /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU |
171 | * currently goes through some pains to keep seeks within the bounds | |
172 | * established by last_sect and max_track. Correcting this is difficult, | |
173 | * as refactoring FDC code tends to expose nasty bugs in the Linux kernel. | |
174 | * | |
175 | * For now: allow empty drives to have large bounds so we can seek around, | |
176 | * with the understanding that when a diskette is inserted, the bounds will | |
177 | * properly tighten to match the geometry of that inserted medium. | |
178 | */ | |
179 | static void fd_empty_seek_hack(FDrive *drv) | |
180 | { | |
181 | drv->last_sect = 0xFF; | |
182 | drv->max_track = 0xFF; | |
183 | } | |
184 | ||
5c02c033 | 185 | static void fd_init(FDrive *drv) |
8977f3c1 FB |
186 | { |
187 | /* Drive */ | |
8977f3c1 | 188 | drv->perpendicular = 0; |
8977f3c1 | 189 | /* Disk */ |
16c1e3ec | 190 | drv->disk = FLOPPY_DRIVE_TYPE_NONE; |
baca51fa | 191 | drv->last_sect = 0; |
8977f3c1 | 192 | drv->max_track = 0; |
d5d47efc JS |
193 | drv->ro = true; |
194 | drv->media_changed = 1; | |
8977f3c1 FB |
195 | } |
196 | ||
08388273 HP |
197 | #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) |
198 | ||
7859cb98 | 199 | static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, |
08388273 | 200 | uint8_t last_sect, uint8_t num_sides) |
8977f3c1 | 201 | { |
08388273 | 202 | return (((track * num_sides) + head) * last_sect) + sect - 1; |
8977f3c1 FB |
203 | } |
204 | ||
205 | /* Returns current position, in sectors, for given drive */ | |
5c02c033 | 206 | static int fd_sector(FDrive *drv) |
8977f3c1 | 207 | { |
08388273 HP |
208 | return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, |
209 | NUM_SIDES(drv)); | |
8977f3c1 FB |
210 | } |
211 | ||
a7a5b7c0 EB |
212 | /* Returns current position, in bytes, for given drive */ |
213 | static int fd_offset(FDrive *drv) | |
214 | { | |
215 | g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS); | |
216 | return fd_sector(drv) << BDRV_SECTOR_BITS; | |
217 | } | |
218 | ||
77370520 BS |
219 | /* Seek to a new position: |
220 | * returns 0 if already on right track | |
221 | * returns 1 if track changed | |
222 | * returns 2 if track is invalid | |
223 | * returns 3 if sector is invalid | |
224 | * returns 4 if seek is disabled | |
225 | */ | |
5c02c033 BS |
226 | static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, |
227 | int enable_seek) | |
8977f3c1 FB |
228 | { |
229 | uint32_t sector; | |
baca51fa FB |
230 | int ret; |
231 | ||
232 | if (track > drv->max_track || | |
4f431960 | 233 | (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
ed5fd2cc FB |
234 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
235 | head, track, sect, 1, | |
236 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
237 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
238 | return 2; |
239 | } | |
240 | if (sect > drv->last_sect) { | |
ed5fd2cc FB |
241 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
242 | head, track, sect, 1, | |
243 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
244 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
245 | return 3; |
246 | } | |
08388273 | 247 | sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); |
baca51fa | 248 | ret = 0; |
8977f3c1 FB |
249 | if (sector != fd_sector(drv)) { |
250 | #if 0 | |
251 | if (!enable_seek) { | |
cced7a13 BS |
252 | FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" |
253 | " (max=%d %02x %02x)\n", | |
254 | head, track, sect, 1, drv->max_track, | |
255 | drv->last_sect); | |
8977f3c1 FB |
256 | return 4; |
257 | } | |
258 | #endif | |
259 | drv->head = head; | |
6be01b1e | 260 | if (drv->track != track) { |
abb3e55b | 261 | if (drv->blk != NULL && blk_is_inserted(drv->blk)) { |
6be01b1e PH |
262 | drv->media_changed = 0; |
263 | } | |
4f431960 | 264 | ret = 1; |
6be01b1e | 265 | } |
8977f3c1 FB |
266 | drv->track = track; |
267 | drv->sect = sect; | |
8977f3c1 FB |
268 | } |
269 | ||
abb3e55b | 270 | if (drv->blk == NULL || !blk_is_inserted(drv->blk)) { |
c52acf60 PH |
271 | ret = 2; |
272 | } | |
273 | ||
baca51fa | 274 | return ret; |
8977f3c1 FB |
275 | } |
276 | ||
277 | /* Set drive back to track 0 */ | |
5c02c033 | 278 | static void fd_recalibrate(FDrive *drv) |
8977f3c1 FB |
279 | { |
280 | FLOPPY_DPRINTF("recalibrate\n"); | |
6be01b1e | 281 | fd_seek(drv, 0, 0, 1, 1); |
8977f3c1 FB |
282 | } |
283 | ||
d5d47efc JS |
284 | /** |
285 | * Determine geometry based on inserted diskette. | |
286 | * Will not operate on an empty drive. | |
287 | * | |
288 | * @return: 0 on success, -1 if the drive is empty. | |
289 | */ | |
290 | static int pick_geometry(FDrive *drv) | |
9a972233 | 291 | { |
21862658 | 292 | BlockBackend *blk = drv->blk; |
9a972233 JS |
293 | const FDFormat *parse; |
294 | uint64_t nb_sectors, size; | |
f31937aa JS |
295 | int i; |
296 | int match, size_match, type_match; | |
297 | bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO; | |
9a972233 | 298 | |
d5d47efc | 299 | /* We can only pick a geometry if we have a diskette. */ |
abb3e55b HR |
300 | if (!drv->blk || !blk_is_inserted(drv->blk) || |
301 | drv->drive == FLOPPY_DRIVE_TYPE_NONE) | |
302 | { | |
d5d47efc JS |
303 | return -1; |
304 | } | |
305 | ||
f31937aa JS |
306 | /* We need to determine the likely geometry of the inserted medium. |
307 | * In order of preference, we look for: | |
308 | * (1) The same drive type and number of sectors, | |
309 | * (2) The same diskette size and number of sectors, | |
310 | * (3) The same drive type. | |
311 | * | |
312 | * In all cases, matches that occur higher in the drive table will take | |
313 | * precedence over matches that occur later in the table. | |
314 | */ | |
9a972233 | 315 | blk_get_geometry(blk, &nb_sectors); |
f31937aa | 316 | match = size_match = type_match = -1; |
9a972233 JS |
317 | for (i = 0; ; i++) { |
318 | parse = &fd_formats[i]; | |
2da44dd0 | 319 | if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { |
9a972233 JS |
320 | break; |
321 | } | |
f31937aa JS |
322 | size = (parse->max_head + 1) * parse->max_track * parse->last_sect; |
323 | if (nb_sectors == size) { | |
324 | if (magic || parse->drive == drv->drive) { | |
325 | /* (1) perfect match -- nb_sectors and drive type */ | |
326 | goto out; | |
327 | } else if (drive_size(parse->drive) == drive_size(drv->drive)) { | |
328 | /* (2) size match -- nb_sectors and physical medium size */ | |
329 | match = (match == -1) ? i : match; | |
330 | } else { | |
331 | /* This is suspicious -- Did the user misconfigure? */ | |
332 | size_match = (size_match == -1) ? i : size_match; | |
9a972233 | 333 | } |
f31937aa JS |
334 | } else if (type_match == -1) { |
335 | if ((parse->drive == drv->drive) || | |
336 | (magic && (parse->drive == get_fallback_drive_type(drv)))) { | |
337 | /* (3) type match -- nb_sectors mismatch, but matches the type | |
338 | * specified explicitly by the user, or matches the fallback | |
339 | * default type when using the drive autodetect mechanism */ | |
340 | type_match = i; | |
9a972233 JS |
341 | } |
342 | } | |
343 | } | |
f31937aa JS |
344 | |
345 | /* No exact match found */ | |
9a972233 | 346 | if (match == -1) { |
f31937aa JS |
347 | if (size_match != -1) { |
348 | parse = &fd_formats[size_match]; | |
349 | FLOPPY_DPRINTF("User requested floppy drive type '%s', " | |
350 | "but inserted medium appears to be a " | |
c691320f | 351 | "%"PRId64" sector '%s' type\n", |
977c736f | 352 | FloppyDriveType_str(drv->drive), |
f31937aa | 353 | nb_sectors, |
977c736f | 354 | FloppyDriveType_str(parse->drive)); |
9a972233 | 355 | } |
329b7291 | 356 | assert(type_match != -1 && "misconfigured fd_format"); |
f31937aa | 357 | match = type_match; |
9a972233 | 358 | } |
f31937aa JS |
359 | parse = &(fd_formats[match]); |
360 | ||
361 | out: | |
21862658 JS |
362 | if (parse->max_head == 0) { |
363 | drv->flags &= ~FDISK_DBL_SIDES; | |
364 | } else { | |
365 | drv->flags |= FDISK_DBL_SIDES; | |
366 | } | |
367 | drv->max_track = parse->max_track; | |
368 | drv->last_sect = parse->last_sect; | |
d5d47efc | 369 | drv->disk = parse->drive; |
21862658 | 370 | drv->media_rate = parse->rate; |
d5d47efc JS |
371 | return 0; |
372 | } | |
373 | ||
374 | static void pick_drive_type(FDrive *drv) | |
375 | { | |
fff4687b JS |
376 | if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) { |
377 | return; | |
378 | } | |
379 | ||
d5d47efc JS |
380 | if (pick_geometry(drv) == 0) { |
381 | drv->drive = drv->disk; | |
382 | } else { | |
a73275dd | 383 | drv->drive = get_fallback_drive_type(drv); |
d5d47efc | 384 | } |
fff4687b JS |
385 | |
386 | g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO); | |
9a972233 JS |
387 | } |
388 | ||
8977f3c1 | 389 | /* Revalidate a disk drive after a disk change */ |
5c02c033 | 390 | static void fd_revalidate(FDrive *drv) |
8977f3c1 | 391 | { |
d5d47efc JS |
392 | int rc; |
393 | ||
8977f3c1 | 394 | FLOPPY_DPRINTF("revalidate\n"); |
4be74634 | 395 | if (drv->blk != NULL) { |
86b1cf32 | 396 | drv->ro = !blk_is_writable(drv->blk); |
abb3e55b | 397 | if (!blk_is_inserted(drv->blk)) { |
cfb08fba | 398 | FLOPPY_DPRINTF("No disk in drive\n"); |
d5d47efc | 399 | drv->disk = FLOPPY_DRIVE_TYPE_NONE; |
fd9bdbd3 | 400 | fd_empty_seek_hack(drv); |
d5d47efc JS |
401 | } else if (!drv->media_validated) { |
402 | rc = pick_geometry(drv); | |
403 | if (rc) { | |
404 | FLOPPY_DPRINTF("Could not validate floppy drive media"); | |
405 | } else { | |
406 | drv->media_validated = true; | |
407 | FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", | |
408 | (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, | |
409 | drv->max_track, drv->last_sect, | |
410 | drv->ro ? "ro" : "rw"); | |
411 | } | |
4f431960 | 412 | } |
8977f3c1 | 413 | } else { |
cfb08fba | 414 | FLOPPY_DPRINTF("No drive connected\n"); |
baca51fa | 415 | drv->last_sect = 0; |
4f431960 JM |
416 | drv->max_track = 0; |
417 | drv->flags &= ~FDISK_DBL_SIDES; | |
d5d47efc JS |
418 | drv->drive = FLOPPY_DRIVE_TYPE_NONE; |
419 | drv->disk = FLOPPY_DRIVE_TYPE_NONE; | |
8977f3c1 | 420 | } |
caed8802 FB |
421 | } |
422 | ||
39829a01 | 423 | static void fd_change_cb(void *opaque, bool load, Error **errp) |
394ea2ca KW |
424 | { |
425 | FDrive *drive = opaque; | |
a17c17a2 KW |
426 | |
427 | if (!load) { | |
428 | blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort); | |
429 | } else { | |
ceff3e1f | 430 | if (!blkconf_apply_backend_options(drive->conf, |
86b1cf32 KW |
431 | !blk_supports_write_perm(drive->blk), |
432 | false, errp)) { | |
a17c17a2 KW |
433 | return; |
434 | } | |
435 | } | |
394ea2ca KW |
436 | |
437 | drive->media_changed = 1; | |
438 | drive->media_validated = false; | |
439 | fd_revalidate(drive); | |
440 | } | |
441 | ||
442 | static const BlockDevOps fd_block_ops = { | |
443 | .change_media_cb = fd_change_cb, | |
444 | }; | |
445 | ||
446 | ||
447 | #define TYPE_FLOPPY_DRIVE "floppy" | |
8063396b | 448 | OBJECT_DECLARE_SIMPLE_TYPE(FloppyDrive, FLOPPY_DRIVE) |
394ea2ca | 449 | |
db1015e9 | 450 | struct FloppyDrive { |
a92bd191 KW |
451 | DeviceState qdev; |
452 | uint32_t unit; | |
453 | BlockConf conf; | |
454 | FloppyDriveType type; | |
db1015e9 | 455 | }; |
394ea2ca KW |
456 | |
457 | static Property floppy_drive_properties[] = { | |
458 | DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1), | |
a92bd191 | 459 | DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf), |
85bbd1e7 | 460 | DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type, |
a92bd191 KW |
461 | FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, |
462 | FloppyDriveType), | |
394ea2ca KW |
463 | DEFINE_PROP_END_OF_LIST(), |
464 | }; | |
465 | ||
ae34fce5 | 466 | static void floppy_drive_realize(DeviceState *qdev, Error **errp) |
394ea2ca KW |
467 | { |
468 | FloppyDrive *dev = FLOPPY_DRIVE(qdev); | |
469 | FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus); | |
470 | FDrive *drive; | |
0b9e918f | 471 | bool read_only; |
a92bd191 | 472 | int ret; |
394ea2ca KW |
473 | |
474 | if (dev->unit == -1) { | |
475 | for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) { | |
476 | drive = get_drv(bus->fdc, dev->unit); | |
477 | if (!drive->blk) { | |
478 | break; | |
479 | } | |
480 | } | |
481 | } | |
482 | ||
483 | if (dev->unit >= MAX_FD) { | |
ae34fce5 MZ |
484 | error_setg(errp, "Can't create floppy unit %d, bus supports " |
485 | "only %d units", dev->unit, MAX_FD); | |
486 | return; | |
394ea2ca KW |
487 | } |
488 | ||
394ea2ca | 489 | drive = get_drv(bus->fdc, dev->unit); |
394ea2ca | 490 | if (drive->blk) { |
ae34fce5 MZ |
491 | error_setg(errp, "Floppy unit %d is in use", dev->unit); |
492 | return; | |
a92bd191 KW |
493 | } |
494 | ||
495 | if (!dev->conf.blk) { | |
b154791e | 496 | dev->conf.blk = blk_create_empty_drive(); |
a92bd191 KW |
497 | ret = blk_attach_dev(dev->conf.blk, qdev); |
498 | assert(ret == 0); | |
0b9e918f KW |
499 | |
500 | /* Don't take write permissions on an empty drive to allow attaching a | |
501 | * read-only node later */ | |
502 | read_only = true; | |
503 | } else { | |
86b1cf32 KW |
504 | read_only = !blk_bs(dev->conf.blk) || |
505 | !blk_supports_write_perm(dev->conf.blk); | |
394ea2ca KW |
506 | } |
507 | ||
c56ee92f RK |
508 | if (!blkconf_blocksizes(&dev->conf, errp)) { |
509 | return; | |
510 | } | |
511 | ||
a92bd191 KW |
512 | if (dev->conf.logical_block_size != 512 || |
513 | dev->conf.physical_block_size != 512) | |
514 | { | |
ae34fce5 MZ |
515 | error_setg(errp, "Physical and logical block size must " |
516 | "be 512 for floppy"); | |
517 | return; | |
a92bd191 KW |
518 | } |
519 | ||
520 | /* rerror/werror aren't supported by fdc and therefore not even registered | |
521 | * with qdev. So set the defaults manually before they are used in | |
522 | * blkconf_apply_backend_options(). */ | |
523 | dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO; | |
524 | dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO; | |
a17c17a2 | 525 | |
0b9e918f | 526 | if (!blkconf_apply_backend_options(&dev->conf, read_only, false, errp)) { |
ae34fce5 | 527 | return; |
a17c17a2 | 528 | } |
a92bd191 KW |
529 | |
530 | /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us | |
531 | * for empty drives. */ | |
532 | if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC && | |
533 | blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) { | |
ae34fce5 MZ |
534 | error_setg(errp, "fdc doesn't support drive option werror"); |
535 | return; | |
394ea2ca | 536 | } |
a92bd191 | 537 | if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { |
ae34fce5 MZ |
538 | error_setg(errp, "fdc doesn't support drive option rerror"); |
539 | return; | |
a92bd191 KW |
540 | } |
541 | ||
a17c17a2 | 542 | drive->conf = &dev->conf; |
a92bd191 KW |
543 | drive->blk = dev->conf.blk; |
544 | drive->fdctrl = bus->fdc; | |
545 | ||
546 | fd_init(drive); | |
547 | blk_set_dev_ops(drive->blk, &fd_block_ops, drive); | |
548 | ||
549 | /* Keep 'type' qdev property and FDrive->drive in sync */ | |
550 | drive->drive = dev->type; | |
551 | pick_drive_type(drive); | |
552 | dev->type = drive->drive; | |
553 | ||
394ea2ca | 554 | fd_revalidate(drive); |
394ea2ca KW |
555 | } |
556 | ||
557 | static void floppy_drive_class_init(ObjectClass *klass, void *data) | |
558 | { | |
559 | DeviceClass *k = DEVICE_CLASS(klass); | |
ae34fce5 | 560 | k->realize = floppy_drive_realize; |
394ea2ca KW |
561 | set_bit(DEVICE_CATEGORY_STORAGE, k->categories); |
562 | k->bus_type = TYPE_FLOPPY_BUS; | |
4f67d30b | 563 | device_class_set_props(k, floppy_drive_properties); |
394ea2ca KW |
564 | k->desc = "virtual floppy drive"; |
565 | } | |
566 | ||
567 | static const TypeInfo floppy_drive_info = { | |
568 | .name = TYPE_FLOPPY_DRIVE, | |
569 | .parent = TYPE_DEVICE, | |
570 | .instance_size = sizeof(FloppyDrive), | |
571 | .class_init = floppy_drive_class_init, | |
572 | }; | |
573 | ||
8977f3c1 | 574 | /********************************************************/ |
4b19ec0c | 575 | /* Intel 82078 floppy disk controller emulation */ |
8977f3c1 | 576 | |
07e415f2 | 577 | static void fdctrl_to_command_phase(FDCtrl *fdctrl); |
d497d534 | 578 | static void fdctrl_raise_irq(FDCtrl *fdctrl); |
a2df5fa3 | 579 | static FDrive *get_cur_drv(FDCtrl *fdctrl); |
5c02c033 BS |
580 | |
581 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); | |
582 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); | |
583 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); | |
584 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); | |
585 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); | |
586 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); | |
587 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); | |
588 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); | |
589 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl); | |
590 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); | |
591 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); | |
a758f8f4 | 592 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); |
8977f3c1 | 593 | |
8977f3c1 FB |
594 | enum { |
595 | FD_DIR_WRITE = 0, | |
596 | FD_DIR_READ = 1, | |
597 | FD_DIR_SCANE = 2, | |
598 | FD_DIR_SCANL = 3, | |
599 | FD_DIR_SCANH = 4, | |
7ea004ed | 600 | FD_DIR_VERIFY = 5, |
8977f3c1 FB |
601 | }; |
602 | ||
603 | enum { | |
b9b3d225 BS |
604 | FD_STATE_MULTI = 0x01, /* multi track flag */ |
605 | FD_STATE_FORMAT = 0x02, /* format flag */ | |
8977f3c1 FB |
606 | }; |
607 | ||
9fea808a | 608 | enum { |
8c6a4d77 BS |
609 | FD_REG_SRA = 0x00, |
610 | FD_REG_SRB = 0x01, | |
9fea808a BS |
611 | FD_REG_DOR = 0x02, |
612 | FD_REG_TDR = 0x03, | |
613 | FD_REG_MSR = 0x04, | |
614 | FD_REG_DSR = 0x04, | |
615 | FD_REG_FIFO = 0x05, | |
616 | FD_REG_DIR = 0x07, | |
a758f8f4 | 617 | FD_REG_CCR = 0x07, |
9fea808a BS |
618 | }; |
619 | ||
620 | enum { | |
65cef780 | 621 | FD_CMD_READ_TRACK = 0x02, |
9fea808a BS |
622 | FD_CMD_SPECIFY = 0x03, |
623 | FD_CMD_SENSE_DRIVE_STATUS = 0x04, | |
65cef780 BS |
624 | FD_CMD_WRITE = 0x05, |
625 | FD_CMD_READ = 0x06, | |
9fea808a BS |
626 | FD_CMD_RECALIBRATE = 0x07, |
627 | FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, | |
65cef780 BS |
628 | FD_CMD_WRITE_DELETED = 0x09, |
629 | FD_CMD_READ_ID = 0x0a, | |
630 | FD_CMD_READ_DELETED = 0x0c, | |
631 | FD_CMD_FORMAT_TRACK = 0x0d, | |
9fea808a BS |
632 | FD_CMD_DUMPREG = 0x0e, |
633 | FD_CMD_SEEK = 0x0f, | |
634 | FD_CMD_VERSION = 0x10, | |
65cef780 | 635 | FD_CMD_SCAN_EQUAL = 0x11, |
9fea808a BS |
636 | FD_CMD_PERPENDICULAR_MODE = 0x12, |
637 | FD_CMD_CONFIGURE = 0x13, | |
65cef780 BS |
638 | FD_CMD_LOCK = 0x14, |
639 | FD_CMD_VERIFY = 0x16, | |
9fea808a BS |
640 | FD_CMD_POWERDOWN_MODE = 0x17, |
641 | FD_CMD_PART_ID = 0x18, | |
65cef780 BS |
642 | FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, |
643 | FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, | |
bb350a5e | 644 | FD_CMD_SAVE = 0x2e, |
9fea808a | 645 | FD_CMD_OPTION = 0x33, |
bb350a5e | 646 | FD_CMD_RESTORE = 0x4e, |
9fea808a BS |
647 | FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, |
648 | FD_CMD_RELATIVE_SEEK_OUT = 0x8f, | |
9fea808a BS |
649 | FD_CMD_FORMAT_AND_WRITE = 0xcd, |
650 | FD_CMD_RELATIVE_SEEK_IN = 0xcf, | |
651 | }; | |
652 | ||
653 | enum { | |
654 | FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ | |
655 | FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ | |
656 | FD_CONFIG_POLL = 0x10, /* Poll enabled */ | |
657 | FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ | |
658 | FD_CONFIG_EIS = 0x40, /* No implied seeks */ | |
659 | }; | |
660 | ||
661 | enum { | |
2fee0088 PH |
662 | FD_SR0_DS0 = 0x01, |
663 | FD_SR0_DS1 = 0x02, | |
664 | FD_SR0_HEAD = 0x04, | |
9fea808a BS |
665 | FD_SR0_EQPMT = 0x10, |
666 | FD_SR0_SEEK = 0x20, | |
667 | FD_SR0_ABNTERM = 0x40, | |
668 | FD_SR0_INVCMD = 0x80, | |
669 | FD_SR0_RDYCHG = 0xc0, | |
670 | }; | |
671 | ||
77370520 | 672 | enum { |
844f65d6 | 673 | FD_SR1_MA = 0x01, /* Missing address mark */ |
8510854e | 674 | FD_SR1_NW = 0x02, /* Not writable */ |
77370520 BS |
675 | FD_SR1_EC = 0x80, /* End of cylinder */ |
676 | }; | |
677 | ||
678 | enum { | |
679 | FD_SR2_SNS = 0x04, /* Scan not satisfied */ | |
680 | FD_SR2_SEH = 0x08, /* Scan equal hit */ | |
681 | }; | |
682 | ||
8c6a4d77 BS |
683 | enum { |
684 | FD_SRA_DIR = 0x01, | |
685 | FD_SRA_nWP = 0x02, | |
686 | FD_SRA_nINDX = 0x04, | |
687 | FD_SRA_HDSEL = 0x08, | |
688 | FD_SRA_nTRK0 = 0x10, | |
689 | FD_SRA_STEP = 0x20, | |
690 | FD_SRA_nDRV2 = 0x40, | |
691 | FD_SRA_INTPEND = 0x80, | |
692 | }; | |
693 | ||
694 | enum { | |
695 | FD_SRB_MTR0 = 0x01, | |
696 | FD_SRB_MTR1 = 0x02, | |
697 | FD_SRB_WGATE = 0x04, | |
698 | FD_SRB_RDATA = 0x08, | |
699 | FD_SRB_WDATA = 0x10, | |
700 | FD_SRB_DR0 = 0x20, | |
701 | }; | |
702 | ||
9fea808a | 703 | enum { |
78ae820c BS |
704 | #if MAX_FD == 4 |
705 | FD_DOR_SELMASK = 0x03, | |
706 | #else | |
9fea808a | 707 | FD_DOR_SELMASK = 0x01, |
78ae820c | 708 | #endif |
9fea808a BS |
709 | FD_DOR_nRESET = 0x04, |
710 | FD_DOR_DMAEN = 0x08, | |
711 | FD_DOR_MOTEN0 = 0x10, | |
712 | FD_DOR_MOTEN1 = 0x20, | |
713 | FD_DOR_MOTEN2 = 0x40, | |
714 | FD_DOR_MOTEN3 = 0x80, | |
715 | }; | |
716 | ||
717 | enum { | |
78ae820c | 718 | #if MAX_FD == 4 |
9fea808a | 719 | FD_TDR_BOOTSEL = 0x0c, |
78ae820c BS |
720 | #else |
721 | FD_TDR_BOOTSEL = 0x04, | |
722 | #endif | |
9fea808a BS |
723 | }; |
724 | ||
725 | enum { | |
726 | FD_DSR_DRATEMASK= 0x03, | |
727 | FD_DSR_PWRDOWN = 0x40, | |
728 | FD_DSR_SWRESET = 0x80, | |
729 | }; | |
730 | ||
731 | enum { | |
732 | FD_MSR_DRV0BUSY = 0x01, | |
733 | FD_MSR_DRV1BUSY = 0x02, | |
734 | FD_MSR_DRV2BUSY = 0x04, | |
735 | FD_MSR_DRV3BUSY = 0x08, | |
736 | FD_MSR_CMDBUSY = 0x10, | |
737 | FD_MSR_NONDMA = 0x20, | |
738 | FD_MSR_DIO = 0x40, | |
739 | FD_MSR_RQM = 0x80, | |
740 | }; | |
741 | ||
742 | enum { | |
743 | FD_DIR_DSKCHG = 0x80, | |
744 | }; | |
745 | ||
85d291a0 KW |
746 | /* |
747 | * See chapter 5.0 "Controller phases" of the spec: | |
748 | * | |
749 | * Command phase: | |
750 | * The host writes a command and its parameters into the FIFO. The command | |
751 | * phase is completed when all parameters for the command have been supplied, | |
752 | * and execution phase is entered. | |
753 | * | |
754 | * Execution phase: | |
755 | * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO | |
756 | * contains the payload now, otherwise it's unused. When all bytes of the | |
757 | * required data have been transferred, the state is switched to either result | |
758 | * phase (if the command produces status bytes) or directly back into the | |
759 | * command phase for the next command. | |
760 | * | |
761 | * Result phase: | |
762 | * The host reads out the FIFO, which contains one or more result bytes now. | |
763 | */ | |
764 | enum { | |
765 | /* Only for migration: reconstruct phase from registers like qemu 2.3 */ | |
766 | FD_PHASE_RECONSTRUCT = 0, | |
767 | ||
768 | FD_PHASE_COMMAND = 1, | |
769 | FD_PHASE_EXECUTION = 2, | |
770 | FD_PHASE_RESULT = 3, | |
771 | }; | |
772 | ||
8977f3c1 | 773 | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) |
baca51fa | 774 | #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) |
8977f3c1 | 775 | |
a73275dd JS |
776 | static FloppyDriveType get_fallback_drive_type(FDrive *drv) |
777 | { | |
778 | return drv->fdctrl->fallback; | |
779 | } | |
780 | ||
5a5d2f3d | 781 | uint32_t fdctrl_read(void *opaque, uint32_t reg) |
baca51fa | 782 | { |
5c02c033 | 783 | FDCtrl *fdctrl = opaque; |
baca51fa FB |
784 | uint32_t retval; |
785 | ||
a18e67f5 | 786 | reg &= 7; |
e64d7d59 | 787 | switch (reg) { |
8c6a4d77 BS |
788 | case FD_REG_SRA: |
789 | retval = fdctrl_read_statusA(fdctrl); | |
4f431960 | 790 | break; |
8c6a4d77 | 791 | case FD_REG_SRB: |
4f431960 JM |
792 | retval = fdctrl_read_statusB(fdctrl); |
793 | break; | |
9fea808a | 794 | case FD_REG_DOR: |
4f431960 JM |
795 | retval = fdctrl_read_dor(fdctrl); |
796 | break; | |
9fea808a | 797 | case FD_REG_TDR: |
baca51fa | 798 | retval = fdctrl_read_tape(fdctrl); |
4f431960 | 799 | break; |
9fea808a | 800 | case FD_REG_MSR: |
baca51fa | 801 | retval = fdctrl_read_main_status(fdctrl); |
4f431960 | 802 | break; |
9fea808a | 803 | case FD_REG_FIFO: |
baca51fa | 804 | retval = fdctrl_read_data(fdctrl); |
4f431960 | 805 | break; |
9fea808a | 806 | case FD_REG_DIR: |
baca51fa | 807 | retval = fdctrl_read_dir(fdctrl); |
4f431960 | 808 | break; |
a541f297 | 809 | default: |
4f431960 JM |
810 | retval = (uint32_t)(-1); |
811 | break; | |
a541f297 | 812 | } |
1a5396d9 | 813 | trace_fdc_ioport_read(reg, retval); |
baca51fa FB |
814 | |
815 | return retval; | |
816 | } | |
817 | ||
5a5d2f3d | 818 | void fdctrl_write(void *opaque, uint32_t reg, uint32_t value) |
baca51fa | 819 | { |
5c02c033 | 820 | FDCtrl *fdctrl = opaque; |
baca51fa | 821 | |
a18e67f5 | 822 | reg &= 7; |
1a5396d9 | 823 | trace_fdc_ioport_write(reg, value); |
e64d7d59 | 824 | switch (reg) { |
9fea808a | 825 | case FD_REG_DOR: |
4f431960 JM |
826 | fdctrl_write_dor(fdctrl, value); |
827 | break; | |
9fea808a | 828 | case FD_REG_TDR: |
baca51fa | 829 | fdctrl_write_tape(fdctrl, value); |
4f431960 | 830 | break; |
9fea808a | 831 | case FD_REG_DSR: |
baca51fa | 832 | fdctrl_write_rate(fdctrl, value); |
4f431960 | 833 | break; |
9fea808a | 834 | case FD_REG_FIFO: |
baca51fa | 835 | fdctrl_write_data(fdctrl, value); |
4f431960 | 836 | break; |
a758f8f4 HP |
837 | case FD_REG_CCR: |
838 | fdctrl_write_ccr(fdctrl, value); | |
839 | break; | |
a541f297 | 840 | default: |
4f431960 | 841 | break; |
a541f297 | 842 | } |
baca51fa FB |
843 | } |
844 | ||
7d905f71 JW |
845 | static bool fdrive_media_changed_needed(void *opaque) |
846 | { | |
847 | FDrive *drive = opaque; | |
848 | ||
abb3e55b | 849 | return (drive->blk != NULL && drive->media_changed != 1); |
7d905f71 JW |
850 | } |
851 | ||
852 | static const VMStateDescription vmstate_fdrive_media_changed = { | |
853 | .name = "fdrive/media_changed", | |
854 | .version_id = 1, | |
855 | .minimum_version_id = 1, | |
5cd8cada | 856 | .needed = fdrive_media_changed_needed, |
d49805ae | 857 | .fields = (VMStateField[]) { |
7d905f71 JW |
858 | VMSTATE_UINT8(media_changed, FDrive), |
859 | VMSTATE_END_OF_LIST() | |
860 | } | |
861 | }; | |
862 | ||
844f65d6 HP |
863 | static const VMStateDescription vmstate_fdrive_media_rate = { |
864 | .name = "fdrive/media_rate", | |
865 | .version_id = 1, | |
866 | .minimum_version_id = 1, | |
d49805ae | 867 | .fields = (VMStateField[]) { |
844f65d6 HP |
868 | VMSTATE_UINT8(media_rate, FDrive), |
869 | VMSTATE_END_OF_LIST() | |
870 | } | |
871 | }; | |
872 | ||
c0b92f30 PD |
873 | static bool fdrive_perpendicular_needed(void *opaque) |
874 | { | |
875 | FDrive *drive = opaque; | |
876 | ||
877 | return drive->perpendicular != 0; | |
878 | } | |
879 | ||
880 | static const VMStateDescription vmstate_fdrive_perpendicular = { | |
881 | .name = "fdrive/perpendicular", | |
882 | .version_id = 1, | |
883 | .minimum_version_id = 1, | |
5cd8cada | 884 | .needed = fdrive_perpendicular_needed, |
c0b92f30 PD |
885 | .fields = (VMStateField[]) { |
886 | VMSTATE_UINT8(perpendicular, FDrive), | |
887 | VMSTATE_END_OF_LIST() | |
888 | } | |
889 | }; | |
890 | ||
891 | static int fdrive_post_load(void *opaque, int version_id) | |
892 | { | |
893 | fd_revalidate(opaque); | |
894 | return 0; | |
895 | } | |
896 | ||
d7a6c270 JQ |
897 | static const VMStateDescription vmstate_fdrive = { |
898 | .name = "fdrive", | |
899 | .version_id = 1, | |
900 | .minimum_version_id = 1, | |
c0b92f30 | 901 | .post_load = fdrive_post_load, |
d49805ae | 902 | .fields = (VMStateField[]) { |
5c02c033 BS |
903 | VMSTATE_UINT8(head, FDrive), |
904 | VMSTATE_UINT8(track, FDrive), | |
905 | VMSTATE_UINT8(sect, FDrive), | |
d7a6c270 | 906 | VMSTATE_END_OF_LIST() |
7d905f71 | 907 | }, |
5cd8cada JQ |
908 | .subsections = (const VMStateDescription*[]) { |
909 | &vmstate_fdrive_media_changed, | |
910 | &vmstate_fdrive_media_rate, | |
911 | &vmstate_fdrive_perpendicular, | |
912 | NULL | |
d7a6c270 JQ |
913 | } |
914 | }; | |
3ccacc4a | 915 | |
85d291a0 KW |
916 | /* |
917 | * Reconstructs the phase from register values according to the logic that was | |
918 | * implemented in qemu 2.3. This is the default value that is used if the phase | |
919 | * subsection is not present on migration. | |
920 | * | |
921 | * Don't change this function to reflect newer qemu versions, it is part of | |
922 | * the migration ABI. | |
923 | */ | |
924 | static int reconstruct_phase(FDCtrl *fdctrl) | |
925 | { | |
926 | if (fdctrl->msr & FD_MSR_NONDMA) { | |
927 | return FD_PHASE_EXECUTION; | |
928 | } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { | |
929 | /* qemu 2.3 disabled RQM only during DMA transfers */ | |
930 | return FD_PHASE_EXECUTION; | |
931 | } else if (fdctrl->msr & FD_MSR_DIO) { | |
932 | return FD_PHASE_RESULT; | |
933 | } else { | |
934 | return FD_PHASE_COMMAND; | |
935 | } | |
936 | } | |
937 | ||
44b1ff31 | 938 | static int fdc_pre_save(void *opaque) |
3ccacc4a | 939 | { |
5c02c033 | 940 | FDCtrl *s = opaque; |
3ccacc4a | 941 | |
d7a6c270 | 942 | s->dor_vmstate = s->dor | GET_CUR_DRV(s); |
44b1ff31 DDAG |
943 | |
944 | return 0; | |
3ccacc4a BS |
945 | } |
946 | ||
85d291a0 KW |
947 | static int fdc_pre_load(void *opaque) |
948 | { | |
949 | FDCtrl *s = opaque; | |
950 | s->phase = FD_PHASE_RECONSTRUCT; | |
951 | return 0; | |
952 | } | |
953 | ||
e59fb374 | 954 | static int fdc_post_load(void *opaque, int version_id) |
3ccacc4a | 955 | { |
5c02c033 | 956 | FDCtrl *s = opaque; |
3ccacc4a | 957 | |
d7a6c270 JQ |
958 | SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); |
959 | s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; | |
85d291a0 KW |
960 | |
961 | if (s->phase == FD_PHASE_RECONSTRUCT) { | |
962 | s->phase = reconstruct_phase(s); | |
963 | } | |
964 | ||
3ccacc4a BS |
965 | return 0; |
966 | } | |
967 | ||
c0b92f30 PD |
968 | static bool fdc_reset_sensei_needed(void *opaque) |
969 | { | |
970 | FDCtrl *s = opaque; | |
971 | ||
972 | return s->reset_sensei != 0; | |
973 | } | |
974 | ||
975 | static const VMStateDescription vmstate_fdc_reset_sensei = { | |
976 | .name = "fdc/reset_sensei", | |
977 | .version_id = 1, | |
978 | .minimum_version_id = 1, | |
5cd8cada | 979 | .needed = fdc_reset_sensei_needed, |
c0b92f30 PD |
980 | .fields = (VMStateField[]) { |
981 | VMSTATE_INT32(reset_sensei, FDCtrl), | |
982 | VMSTATE_END_OF_LIST() | |
983 | } | |
984 | }; | |
985 | ||
986 | static bool fdc_result_timer_needed(void *opaque) | |
987 | { | |
988 | FDCtrl *s = opaque; | |
989 | ||
990 | return timer_pending(s->result_timer); | |
991 | } | |
992 | ||
993 | static const VMStateDescription vmstate_fdc_result_timer = { | |
994 | .name = "fdc/result_timer", | |
995 | .version_id = 1, | |
996 | .minimum_version_id = 1, | |
5cd8cada | 997 | .needed = fdc_result_timer_needed, |
c0b92f30 | 998 | .fields = (VMStateField[]) { |
e720677e | 999 | VMSTATE_TIMER_PTR(result_timer, FDCtrl), |
c0b92f30 PD |
1000 | VMSTATE_END_OF_LIST() |
1001 | } | |
1002 | }; | |
1003 | ||
85d291a0 KW |
1004 | static bool fdc_phase_needed(void *opaque) |
1005 | { | |
1006 | FDCtrl *fdctrl = opaque; | |
1007 | ||
1008 | return reconstruct_phase(fdctrl) != fdctrl->phase; | |
1009 | } | |
1010 | ||
1011 | static const VMStateDescription vmstate_fdc_phase = { | |
1012 | .name = "fdc/phase", | |
1013 | .version_id = 1, | |
1014 | .minimum_version_id = 1, | |
5cd8cada | 1015 | .needed = fdc_phase_needed, |
85d291a0 KW |
1016 | .fields = (VMStateField[]) { |
1017 | VMSTATE_UINT8(phase, FDCtrl), | |
1018 | VMSTATE_END_OF_LIST() | |
1019 | } | |
1020 | }; | |
1021 | ||
5a5d2f3d | 1022 | const VMStateDescription vmstate_fdc = { |
aef30c3c | 1023 | .name = "fdc", |
d7a6c270 JQ |
1024 | .version_id = 2, |
1025 | .minimum_version_id = 2, | |
d7a6c270 | 1026 | .pre_save = fdc_pre_save, |
85d291a0 | 1027 | .pre_load = fdc_pre_load, |
d7a6c270 | 1028 | .post_load = fdc_post_load, |
d49805ae | 1029 | .fields = (VMStateField[]) { |
d7a6c270 | 1030 | /* Controller State */ |
5c02c033 BS |
1031 | VMSTATE_UINT8(sra, FDCtrl), |
1032 | VMSTATE_UINT8(srb, FDCtrl), | |
1033 | VMSTATE_UINT8(dor_vmstate, FDCtrl), | |
1034 | VMSTATE_UINT8(tdr, FDCtrl), | |
1035 | VMSTATE_UINT8(dsr, FDCtrl), | |
1036 | VMSTATE_UINT8(msr, FDCtrl), | |
1037 | VMSTATE_UINT8(status0, FDCtrl), | |
1038 | VMSTATE_UINT8(status1, FDCtrl), | |
1039 | VMSTATE_UINT8(status2, FDCtrl), | |
d7a6c270 | 1040 | /* Command FIFO */ |
8ec68b06 BS |
1041 | VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, |
1042 | uint8_t), | |
5c02c033 BS |
1043 | VMSTATE_UINT32(data_pos, FDCtrl), |
1044 | VMSTATE_UINT32(data_len, FDCtrl), | |
1045 | VMSTATE_UINT8(data_state, FDCtrl), | |
1046 | VMSTATE_UINT8(data_dir, FDCtrl), | |
1047 | VMSTATE_UINT8(eot, FDCtrl), | |
d7a6c270 | 1048 | /* States kept only to be returned back */ |
5c02c033 BS |
1049 | VMSTATE_UINT8(timer0, FDCtrl), |
1050 | VMSTATE_UINT8(timer1, FDCtrl), | |
1051 | VMSTATE_UINT8(precomp_trk, FDCtrl), | |
1052 | VMSTATE_UINT8(config, FDCtrl), | |
1053 | VMSTATE_UINT8(lock, FDCtrl), | |
1054 | VMSTATE_UINT8(pwrd, FDCtrl), | |
d2164ad3 | 1055 | VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL), |
5c02c033 BS |
1056 | VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, |
1057 | vmstate_fdrive, FDrive), | |
d7a6c270 | 1058 | VMSTATE_END_OF_LIST() |
c0b92f30 | 1059 | }, |
5cd8cada JQ |
1060 | .subsections = (const VMStateDescription*[]) { |
1061 | &vmstate_fdc_reset_sensei, | |
1062 | &vmstate_fdc_result_timer, | |
1063 | &vmstate_fdc_phase, | |
1064 | NULL | |
78ae820c | 1065 | } |
d7a6c270 | 1066 | }; |
3ccacc4a | 1067 | |
8977f3c1 | 1068 | /* Change IRQ state */ |
5c02c033 | 1069 | static void fdctrl_reset_irq(FDCtrl *fdctrl) |
8977f3c1 | 1070 | { |
d497d534 | 1071 | fdctrl->status0 = 0; |
8c6a4d77 BS |
1072 | if (!(fdctrl->sra & FD_SRA_INTPEND)) |
1073 | return; | |
ed5fd2cc | 1074 | FLOPPY_DPRINTF("Reset interrupt\n"); |
d537cf6c | 1075 | qemu_set_irq(fdctrl->irq, 0); |
8c6a4d77 | 1076 | fdctrl->sra &= ~FD_SRA_INTPEND; |
8977f3c1 FB |
1077 | } |
1078 | ||
d497d534 | 1079 | static void fdctrl_raise_irq(FDCtrl *fdctrl) |
8977f3c1 | 1080 | { |
8c6a4d77 | 1081 | if (!(fdctrl->sra & FD_SRA_INTPEND)) { |
d537cf6c | 1082 | qemu_set_irq(fdctrl->irq, 1); |
8c6a4d77 | 1083 | fdctrl->sra |= FD_SRA_INTPEND; |
8977f3c1 | 1084 | } |
21fcf360 | 1085 | |
f2d81b33 | 1086 | fdctrl->reset_sensei = 0; |
77370520 | 1087 | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); |
8977f3c1 FB |
1088 | } |
1089 | ||
4b19ec0c | 1090 | /* Reset controller */ |
5a5d2f3d | 1091 | void fdctrl_reset(FDCtrl *fdctrl, int do_irq) |
8977f3c1 FB |
1092 | { |
1093 | int i; | |
1094 | ||
4b19ec0c | 1095 | FLOPPY_DPRINTF("reset controller\n"); |
baca51fa | 1096 | fdctrl_reset_irq(fdctrl); |
4b19ec0c | 1097 | /* Initialise controller */ |
8c6a4d77 BS |
1098 | fdctrl->sra = 0; |
1099 | fdctrl->srb = 0xc0; | |
4be74634 | 1100 | if (!fdctrl->drives[1].blk) { |
8c6a4d77 | 1101 | fdctrl->sra |= FD_SRA_nDRV2; |
4be74634 | 1102 | } |
baca51fa | 1103 | fdctrl->cur_drv = 0; |
1c346df2 | 1104 | fdctrl->dor = FD_DOR_nRESET; |
368df94d | 1105 | fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
b9b3d225 | 1106 | fdctrl->msr = FD_MSR_RQM; |
c0b92f30 PD |
1107 | fdctrl->reset_sensei = 0; |
1108 | timer_del(fdctrl->result_timer); | |
8977f3c1 | 1109 | /* FIFO state */ |
baca51fa FB |
1110 | fdctrl->data_pos = 0; |
1111 | fdctrl->data_len = 0; | |
b9b3d225 | 1112 | fdctrl->data_state = 0; |
baca51fa | 1113 | fdctrl->data_dir = FD_DIR_WRITE; |
8977f3c1 | 1114 | for (i = 0; i < MAX_FD; i++) |
1c346df2 | 1115 | fd_recalibrate(&fdctrl->drives[i]); |
07e415f2 | 1116 | fdctrl_to_command_phase(fdctrl); |
77370520 | 1117 | if (do_irq) { |
d497d534 HP |
1118 | fdctrl->status0 |= FD_SR0_RDYCHG; |
1119 | fdctrl_raise_irq(fdctrl); | |
f2d81b33 | 1120 | fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
77370520 | 1121 | } |
baca51fa FB |
1122 | } |
1123 | ||
5c02c033 | 1124 | static inline FDrive *drv0(FDCtrl *fdctrl) |
baca51fa | 1125 | { |
46d3233b | 1126 | return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
baca51fa FB |
1127 | } |
1128 | ||
5c02c033 | 1129 | static inline FDrive *drv1(FDCtrl *fdctrl) |
baca51fa | 1130 | { |
46d3233b BS |
1131 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
1132 | return &fdctrl->drives[1]; | |
1133 | else | |
1134 | return &fdctrl->drives[0]; | |
baca51fa FB |
1135 | } |
1136 | ||
78ae820c | 1137 | #if MAX_FD == 4 |
5c02c033 | 1138 | static inline FDrive *drv2(FDCtrl *fdctrl) |
78ae820c BS |
1139 | { |
1140 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) | |
1141 | return &fdctrl->drives[2]; | |
1142 | else | |
1143 | return &fdctrl->drives[1]; | |
1144 | } | |
1145 | ||
5c02c033 | 1146 | static inline FDrive *drv3(FDCtrl *fdctrl) |
78ae820c BS |
1147 | { |
1148 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) | |
1149 | return &fdctrl->drives[3]; | |
1150 | else | |
1151 | return &fdctrl->drives[2]; | |
1152 | } | |
1153 | #endif | |
1154 | ||
394ea2ca | 1155 | static FDrive *get_drv(FDCtrl *fdctrl, int unit) |
baca51fa | 1156 | { |
394ea2ca | 1157 | switch (unit) { |
78ae820c BS |
1158 | case 0: return drv0(fdctrl); |
1159 | case 1: return drv1(fdctrl); | |
1160 | #if MAX_FD == 4 | |
1161 | case 2: return drv2(fdctrl); | |
1162 | case 3: return drv3(fdctrl); | |
1163 | #endif | |
1164 | default: return NULL; | |
1165 | } | |
8977f3c1 FB |
1166 | } |
1167 | ||
394ea2ca KW |
1168 | static FDrive *get_cur_drv(FDCtrl *fdctrl) |
1169 | { | |
1ab95af0 PMD |
1170 | FDrive *cur_drv = get_drv(fdctrl, fdctrl->cur_drv); |
1171 | ||
1172 | if (!cur_drv->blk) { | |
1173 | /* | |
1174 | * Kludge: empty drive line selected. Create an anonymous | |
1175 | * BlockBackend to avoid NULL deref with various BlockBackend | |
1176 | * API calls within this model (CVE-2021-20196). | |
1177 | * Due to the controller QOM model limitations, we don't | |
1178 | * attach the created to the controller device. | |
1179 | */ | |
1180 | cur_drv->blk = blk_create_empty_drive(); | |
1181 | } | |
1182 | return cur_drv; | |
394ea2ca KW |
1183 | } |
1184 | ||
8c6a4d77 | 1185 | /* Status A register : 0x00 (read-only) */ |
5c02c033 | 1186 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) |
8c6a4d77 BS |
1187 | { |
1188 | uint32_t retval = fdctrl->sra; | |
1189 | ||
1190 | FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); | |
1191 | ||
1192 | return retval; | |
1193 | } | |
1194 | ||
8977f3c1 | 1195 | /* Status B register : 0x01 (read-only) */ |
5c02c033 | 1196 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) |
8977f3c1 | 1197 | { |
8c6a4d77 BS |
1198 | uint32_t retval = fdctrl->srb; |
1199 | ||
1200 | FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); | |
1201 | ||
1202 | return retval; | |
8977f3c1 FB |
1203 | } |
1204 | ||
1205 | /* Digital output register : 0x02 */ | |
5c02c033 | 1206 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) |
8977f3c1 | 1207 | { |
1c346df2 | 1208 | uint32_t retval = fdctrl->dor; |
8977f3c1 | 1209 | |
8977f3c1 | 1210 | /* Selected drive */ |
baca51fa | 1211 | retval |= fdctrl->cur_drv; |
8977f3c1 FB |
1212 | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); |
1213 | ||
1214 | return retval; | |
1215 | } | |
1216 | ||
5c02c033 | 1217 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1218 | { |
8977f3c1 | 1219 | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); |
8c6a4d77 BS |
1220 | |
1221 | /* Motors */ | |
1222 | if (value & FD_DOR_MOTEN0) | |
1223 | fdctrl->srb |= FD_SRB_MTR0; | |
1224 | else | |
1225 | fdctrl->srb &= ~FD_SRB_MTR0; | |
1226 | if (value & FD_DOR_MOTEN1) | |
1227 | fdctrl->srb |= FD_SRB_MTR1; | |
1228 | else | |
1229 | fdctrl->srb &= ~FD_SRB_MTR1; | |
1230 | ||
1231 | /* Drive */ | |
1232 | if (value & 1) | |
1233 | fdctrl->srb |= FD_SRB_DR0; | |
1234 | else | |
1235 | fdctrl->srb &= ~FD_SRB_DR0; | |
1236 | ||
8977f3c1 | 1237 | /* Reset */ |
9fea808a | 1238 | if (!(value & FD_DOR_nRESET)) { |
1c346df2 | 1239 | if (fdctrl->dor & FD_DOR_nRESET) { |
4b19ec0c | 1240 | FLOPPY_DPRINTF("controller enter RESET state\n"); |
8977f3c1 FB |
1241 | } |
1242 | } else { | |
1c346df2 | 1243 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 1244 | FLOPPY_DPRINTF("controller out of RESET state\n"); |
fb6cf1d0 | 1245 | fdctrl_reset(fdctrl, 1); |
b9b3d225 | 1246 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
8977f3c1 FB |
1247 | } |
1248 | } | |
1249 | /* Selected drive */ | |
9fea808a | 1250 | fdctrl->cur_drv = value & FD_DOR_SELMASK; |
368df94d BS |
1251 | |
1252 | fdctrl->dor = value; | |
8977f3c1 FB |
1253 | } |
1254 | ||
1255 | /* Tape drive register : 0x03 */ | |
5c02c033 | 1256 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) |
8977f3c1 | 1257 | { |
46d3233b | 1258 | uint32_t retval = fdctrl->tdr; |
8977f3c1 | 1259 | |
8977f3c1 FB |
1260 | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); |
1261 | ||
1262 | return retval; | |
1263 | } | |
1264 | ||
5c02c033 | 1265 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1266 | { |
8977f3c1 | 1267 | /* Reset mode */ |
1c346df2 | 1268 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 1269 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
1270 | return; |
1271 | } | |
1272 | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); | |
1273 | /* Disk boot selection indicator */ | |
46d3233b | 1274 | fdctrl->tdr = value & FD_TDR_BOOTSEL; |
8977f3c1 FB |
1275 | /* Tape indicators: never allow */ |
1276 | } | |
1277 | ||
1278 | /* Main status register : 0x04 (read) */ | |
5c02c033 | 1279 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) |
8977f3c1 | 1280 | { |
b9b3d225 | 1281 | uint32_t retval = fdctrl->msr; |
8977f3c1 | 1282 | |
b9b3d225 | 1283 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1c346df2 | 1284 | fdctrl->dor |= FD_DOR_nRESET; |
b9b3d225 | 1285 | |
8977f3c1 FB |
1286 | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); |
1287 | ||
1288 | return retval; | |
1289 | } | |
1290 | ||
1291 | /* Data select rate register : 0x04 (write) */ | |
5c02c033 | 1292 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1293 | { |
8977f3c1 | 1294 | /* Reset mode */ |
1c346df2 | 1295 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4f431960 JM |
1296 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
1297 | return; | |
1298 | } | |
8977f3c1 FB |
1299 | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); |
1300 | /* Reset: autoclear */ | |
9fea808a | 1301 | if (value & FD_DSR_SWRESET) { |
1c346df2 | 1302 | fdctrl->dor &= ~FD_DOR_nRESET; |
baca51fa | 1303 | fdctrl_reset(fdctrl, 1); |
1c346df2 | 1304 | fdctrl->dor |= FD_DOR_nRESET; |
8977f3c1 | 1305 | } |
9fea808a | 1306 | if (value & FD_DSR_PWRDOWN) { |
baca51fa | 1307 | fdctrl_reset(fdctrl, 1); |
8977f3c1 | 1308 | } |
b9b3d225 | 1309 | fdctrl->dsr = value; |
8977f3c1 FB |
1310 | } |
1311 | ||
a758f8f4 HP |
1312 | /* Configuration control register: 0x07 (write) */ |
1313 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) | |
1314 | { | |
1315 | /* Reset mode */ | |
1316 | if (!(fdctrl->dor & FD_DOR_nRESET)) { | |
1317 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); | |
1318 | return; | |
1319 | } | |
1320 | FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); | |
1321 | ||
1322 | /* Only the rate selection bits used in AT mode, and we | |
1323 | * store those in the DSR. | |
1324 | */ | |
1325 | fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | | |
1326 | (value & FD_DSR_DRATEMASK); | |
1327 | } | |
1328 | ||
5c02c033 | 1329 | static int fdctrl_media_changed(FDrive *drv) |
ea185bbd | 1330 | { |
21fcf360 | 1331 | return drv->media_changed; |
ea185bbd FB |
1332 | } |
1333 | ||
8977f3c1 | 1334 | /* Digital input register : 0x07 (read-only) */ |
5c02c033 | 1335 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) |
8977f3c1 | 1336 | { |
8977f3c1 FB |
1337 | uint32_t retval = 0; |
1338 | ||
a2df5fa3 | 1339 | if (fdctrl_media_changed(get_cur_drv(fdctrl))) { |
9fea808a | 1340 | retval |= FD_DIR_DSKCHG; |
a2df5fa3 | 1341 | } |
3c83eb4f | 1342 | if (retval != 0) { |
baca51fa | 1343 | FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); |
3c83eb4f | 1344 | } |
8977f3c1 FB |
1345 | |
1346 | return retval; | |
1347 | } | |
1348 | ||
07e415f2 KW |
1349 | /* Clear the FIFO and update the state for receiving the next command */ |
1350 | static void fdctrl_to_command_phase(FDCtrl *fdctrl) | |
8977f3c1 | 1351 | { |
85d291a0 | 1352 | fdctrl->phase = FD_PHASE_COMMAND; |
baca51fa FB |
1353 | fdctrl->data_dir = FD_DIR_WRITE; |
1354 | fdctrl->data_pos = 0; | |
6cc8a11c | 1355 | fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ |
b9b3d225 | 1356 | fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
6cc8a11c | 1357 | fdctrl->msr |= FD_MSR_RQM; |
8977f3c1 FB |
1358 | } |
1359 | ||
83a26013 KW |
1360 | /* Update the state to allow the guest to read out the command status. |
1361 | * @fifo_len is the number of result bytes to be read out. */ | |
1362 | static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) | |
8977f3c1 | 1363 | { |
85d291a0 | 1364 | fdctrl->phase = FD_PHASE_RESULT; |
baca51fa FB |
1365 | fdctrl->data_dir = FD_DIR_READ; |
1366 | fdctrl->data_len = fifo_len; | |
1367 | fdctrl->data_pos = 0; | |
b9b3d225 | 1368 | fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
8977f3c1 FB |
1369 | } |
1370 | ||
1371 | /* Set an error: unimplemented/unknown command */ | |
5c02c033 | 1372 | static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1373 | { |
cced7a13 BS |
1374 | qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", |
1375 | fdctrl->fifo[0]); | |
9fea808a | 1376 | fdctrl->fifo[0] = FD_SR0_INVCMD; |
83a26013 | 1377 | fdctrl_to_result_phase(fdctrl, 1); |
8977f3c1 FB |
1378 | } |
1379 | ||
6be01b1e PH |
1380 | /* Seek to next sector |
1381 | * returns 0 when end of track reached (for DBL_SIDES on head 1) | |
1382 | * otherwise returns 1 | |
1383 | */ | |
5c02c033 | 1384 | static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) |
746d6de7 BS |
1385 | { |
1386 | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", | |
1387 | cur_drv->head, cur_drv->track, cur_drv->sect, | |
1388 | fd_sector(cur_drv)); | |
1389 | /* XXX: cur_drv->sect >= cur_drv->last_sect should be an | |
1390 | error in fact */ | |
6be01b1e PH |
1391 | uint8_t new_head = cur_drv->head; |
1392 | uint8_t new_track = cur_drv->track; | |
1393 | uint8_t new_sect = cur_drv->sect; | |
1394 | ||
1395 | int ret = 1; | |
1396 | ||
1397 | if (new_sect >= cur_drv->last_sect || | |
1398 | new_sect == fdctrl->eot) { | |
1399 | new_sect = 1; | |
746d6de7 | 1400 | if (FD_MULTI_TRACK(fdctrl->data_state)) { |
6be01b1e | 1401 | if (new_head == 0 && |
746d6de7 | 1402 | (cur_drv->flags & FDISK_DBL_SIDES) != 0) { |
6be01b1e | 1403 | new_head = 1; |
746d6de7 | 1404 | } else { |
6be01b1e PH |
1405 | new_head = 0; |
1406 | new_track++; | |
c5139bd9 | 1407 | fdctrl->status0 |= FD_SR0_SEEK; |
6be01b1e PH |
1408 | if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { |
1409 | ret = 0; | |
1410 | } | |
746d6de7 BS |
1411 | } |
1412 | } else { | |
c5139bd9 | 1413 | fdctrl->status0 |= FD_SR0_SEEK; |
6be01b1e PH |
1414 | new_track++; |
1415 | ret = 0; | |
1416 | } | |
1417 | if (ret == 1) { | |
1418 | FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", | |
1419 | new_head, new_track, new_sect, fd_sector(cur_drv)); | |
746d6de7 | 1420 | } |
746d6de7 | 1421 | } else { |
6be01b1e | 1422 | new_sect++; |
746d6de7 | 1423 | } |
6be01b1e PH |
1424 | fd_seek(cur_drv, new_head, new_track, new_sect, 1); |
1425 | return ret; | |
746d6de7 BS |
1426 | } |
1427 | ||
8977f3c1 | 1428 | /* Callback for transfer end (stop or abort) */ |
5c02c033 BS |
1429 | static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, |
1430 | uint8_t status1, uint8_t status2) | |
8977f3c1 | 1431 | { |
5c02c033 | 1432 | FDrive *cur_drv; |
baca51fa | 1433 | cur_drv = get_cur_drv(fdctrl); |
075f5532 HP |
1434 | |
1435 | fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); | |
1436 | fdctrl->status0 |= GET_CUR_DRV(fdctrl); | |
1437 | if (cur_drv->head) { | |
1438 | fdctrl->status0 |= FD_SR0_HEAD; | |
1439 | } | |
1440 | fdctrl->status0 |= status0; | |
2fee0088 | 1441 | |
8977f3c1 | 1442 | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", |
2fee0088 PH |
1443 | status0, status1, status2, fdctrl->status0); |
1444 | fdctrl->fifo[0] = fdctrl->status0; | |
baca51fa FB |
1445 | fdctrl->fifo[1] = status1; |
1446 | fdctrl->fifo[2] = status2; | |
1447 | fdctrl->fifo[3] = cur_drv->track; | |
1448 | fdctrl->fifo[4] = cur_drv->head; | |
1449 | fdctrl->fifo[5] = cur_drv->sect; | |
1450 | fdctrl->fifo[6] = FD_SECTOR_SC; | |
1451 | fdctrl->data_dir = FD_DIR_READ; | |
441f6692 | 1452 | if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) { |
c8a35f1c HP |
1453 | IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); |
1454 | k->release_DREQ(fdctrl->dma, fdctrl->dma_chann); | |
ed5fd2cc | 1455 | } |
b9b3d225 | 1456 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
368df94d | 1457 | fdctrl->msr &= ~FD_MSR_NONDMA; |
34abf9a7 | 1458 | |
83a26013 | 1459 | fdctrl_to_result_phase(fdctrl, 7); |
d497d534 | 1460 | fdctrl_raise_irq(fdctrl); |
8977f3c1 FB |
1461 | } |
1462 | ||
1463 | /* Prepare a data transfer (either DMA or FIFO) */ | |
5c02c033 | 1464 | static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1465 | { |
5c02c033 | 1466 | FDrive *cur_drv; |
8977f3c1 | 1467 | uint8_t kh, kt, ks; |
8977f3c1 | 1468 | |
cefec4f5 | 1469 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1470 | cur_drv = get_cur_drv(fdctrl); |
1471 | kt = fdctrl->fifo[2]; | |
1472 | kh = fdctrl->fifo[3]; | |
1473 | ks = fdctrl->fifo[4]; | |
4b19ec0c | 1474 | FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", |
cefec4f5 | 1475 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1476 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1477 | NUM_SIDES(cur_drv))); | |
77370520 | 1478 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
8977f3c1 FB |
1479 | case 2: |
1480 | /* sect too big */ | |
9fea808a | 1481 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1482 | fdctrl->fifo[3] = kt; |
1483 | fdctrl->fifo[4] = kh; | |
1484 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1485 | return; |
1486 | case 3: | |
1487 | /* track too big */ | |
77370520 | 1488 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1489 | fdctrl->fifo[3] = kt; |
1490 | fdctrl->fifo[4] = kh; | |
1491 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1492 | return; |
1493 | case 4: | |
1494 | /* No seek enabled */ | |
9fea808a | 1495 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1496 | fdctrl->fifo[3] = kt; |
1497 | fdctrl->fifo[4] = kh; | |
1498 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1499 | return; |
1500 | case 1: | |
d6ed4e21 | 1501 | fdctrl->status0 |= FD_SR0_SEEK; |
8977f3c1 FB |
1502 | break; |
1503 | default: | |
1504 | break; | |
1505 | } | |
b9b3d225 | 1506 | |
844f65d6 HP |
1507 | /* Check the data rate. If the programmed data rate does not match |
1508 | * the currently inserted medium, the operation has to fail. */ | |
f5d33dd5 | 1509 | if ((fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { |
844f65d6 HP |
1510 | FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", |
1511 | fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); | |
1512 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); | |
1513 | fdctrl->fifo[3] = kt; | |
1514 | fdctrl->fifo[4] = kh; | |
1515 | fdctrl->fifo[5] = ks; | |
1516 | return; | |
1517 | } | |
1518 | ||
8977f3c1 | 1519 | /* Set the FIFO state */ |
baca51fa FB |
1520 | fdctrl->data_dir = direction; |
1521 | fdctrl->data_pos = 0; | |
27c86e24 | 1522 | assert(fdctrl->msr & FD_MSR_CMDBUSY); |
baca51fa FB |
1523 | if (fdctrl->fifo[0] & 0x80) |
1524 | fdctrl->data_state |= FD_STATE_MULTI; | |
1525 | else | |
1526 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
c83f97b5 | 1527 | if (fdctrl->fifo[5] == 0) { |
baca51fa FB |
1528 | fdctrl->data_len = fdctrl->fifo[8]; |
1529 | } else { | |
4f431960 | 1530 | int tmp; |
3bcb80f1 | 1531 | fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
771effeb | 1532 | tmp = (fdctrl->fifo[6] - ks + 1); |
defac5e2 PMD |
1533 | if (tmp < 0) { |
1534 | FLOPPY_DPRINTF("invalid EOT: %d\n", tmp); | |
1535 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); | |
1536 | fdctrl->fifo[3] = kt; | |
1537 | fdctrl->fifo[4] = kh; | |
1538 | fdctrl->fifo[5] = ks; | |
1539 | return; | |
1540 | } | |
baca51fa | 1541 | if (fdctrl->fifo[0] & 0x80) |
771effeb | 1542 | tmp += fdctrl->fifo[6]; |
4f431960 | 1543 | fdctrl->data_len *= tmp; |
baca51fa | 1544 | } |
890fa6be | 1545 | fdctrl->eot = fdctrl->fifo[6]; |
368df94d | 1546 | if (fdctrl->dor & FD_DOR_DMAEN) { |
9e58f172 | 1547 | /* DMA transfer is enabled. */ |
c8a35f1c | 1548 | IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma); |
9e58f172 SS |
1549 | |
1550 | FLOPPY_DPRINTF("direction=%d (%d - %d)\n", | |
1551 | direction, (128 << fdctrl->fifo[5]) * | |
4f431960 | 1552 | (cur_drv->last_sect - ks + 1), fdctrl->data_len); |
9e58f172 SS |
1553 | |
1554 | /* No access is allowed until DMA transfer has completed */ | |
1555 | fdctrl->msr &= ~FD_MSR_RQM; | |
1556 | if (direction != FD_DIR_VERIFY) { | |
1557 | /* | |
1558 | * Now, we just have to wait for the DMA controller to | |
1559 | * recall us... | |
1560 | */ | |
1561 | k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann); | |
1562 | k->schedule(fdctrl->dma); | |
baca51fa | 1563 | } else { |
9e58f172 SS |
1564 | /* Start transfer */ |
1565 | fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, | |
1566 | fdctrl->data_len); | |
8977f3c1 | 1567 | } |
9e58f172 | 1568 | return; |
8977f3c1 FB |
1569 | } |
1570 | FLOPPY_DPRINTF("start non-DMA transfer\n"); | |
6cc8a11c | 1571 | fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; |
b9b3d225 BS |
1572 | if (direction != FD_DIR_WRITE) |
1573 | fdctrl->msr |= FD_MSR_DIO; | |
8977f3c1 | 1574 | /* IO based transfer: calculate len */ |
d497d534 | 1575 | fdctrl_raise_irq(fdctrl); |
8977f3c1 FB |
1576 | } |
1577 | ||
1578 | /* Prepare a transfer of deleted data */ | |
5c02c033 | 1579 | static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1580 | { |
cced7a13 | 1581 | qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); |
77370520 | 1582 | |
8977f3c1 FB |
1583 | /* We don't handle deleted data, |
1584 | * so we don't return *ANYTHING* | |
1585 | */ | |
9fea808a | 1586 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
8977f3c1 FB |
1587 | } |
1588 | ||
1589 | /* handlers for DMA transfers */ | |
5a5d2f3d | 1590 | int fdctrl_transfer_handler(void *opaque, int nchan, int dma_pos, int dma_len) |
8977f3c1 | 1591 | { |
5c02c033 BS |
1592 | FDCtrl *fdctrl; |
1593 | FDrive *cur_drv; | |
baca51fa | 1594 | int len, start_pos, rel_pos; |
8977f3c1 | 1595 | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
c8a35f1c | 1596 | IsaDmaClass *k; |
8977f3c1 | 1597 | |
baca51fa | 1598 | fdctrl = opaque; |
b9b3d225 | 1599 | if (fdctrl->msr & FD_MSR_RQM) { |
8977f3c1 FB |
1600 | FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); |
1601 | return 0; | |
1602 | } | |
c8a35f1c | 1603 | k = ISADMA_GET_CLASS(fdctrl->dma); |
baca51fa FB |
1604 | cur_drv = get_cur_drv(fdctrl); |
1605 | if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || | |
1606 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1607 | status2 = FD_SR2_SNS; |
85571bc7 FB |
1608 | if (dma_len > fdctrl->data_len) |
1609 | dma_len = fdctrl->data_len; | |
4be74634 | 1610 | if (cur_drv->blk == NULL) { |
4f431960 | 1611 | if (fdctrl->data_dir == FD_DIR_WRITE) |
9fea808a | 1612 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
4f431960 | 1613 | else |
9fea808a | 1614 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
4f431960 | 1615 | len = 0; |
890fa6be FB |
1616 | goto transfer_error; |
1617 | } | |
baca51fa | 1618 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
85571bc7 FB |
1619 | for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { |
1620 | len = dma_len - fdctrl->data_pos; | |
baca51fa FB |
1621 | if (len + rel_pos > FD_SECTOR_LEN) |
1622 | len = FD_SECTOR_LEN - rel_pos; | |
6f7e9aec FB |
1623 | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " |
1624 | "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, | |
cefec4f5 | 1625 | fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
baca51fa | 1626 | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
9fea808a | 1627 | fd_sector(cur_drv) * FD_SECTOR_LEN); |
baca51fa | 1628 | if (fdctrl->data_dir != FD_DIR_WRITE || |
4f431960 | 1629 | len < FD_SECTOR_LEN || rel_pos != 0) { |
baca51fa | 1630 | /* READ & SCAN commands and realign to a sector for WRITE */ |
a9262f55 AF |
1631 | if (blk_pread(cur_drv->blk, fd_offset(cur_drv), BDRV_SECTOR_SIZE, |
1632 | fdctrl->fifo, 0) < 0) { | |
8977f3c1 FB |
1633 | FLOPPY_DPRINTF("Floppy: error getting sector %d\n", |
1634 | fd_sector(cur_drv)); | |
1635 | /* Sure, image size is too small... */ | |
baca51fa | 1636 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); |
8977f3c1 | 1637 | } |
890fa6be | 1638 | } |
4f431960 JM |
1639 | switch (fdctrl->data_dir) { |
1640 | case FD_DIR_READ: | |
1641 | /* READ commands */ | |
c8a35f1c HP |
1642 | k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, |
1643 | fdctrl->data_pos, len); | |
4f431960 JM |
1644 | break; |
1645 | case FD_DIR_WRITE: | |
baca51fa | 1646 | /* WRITE commands */ |
8510854e HP |
1647 | if (cur_drv->ro) { |
1648 | /* Handle readonly medium early, no need to do DMA, touch the | |
1649 | * LED or attempt any writes. A real floppy doesn't attempt | |
1650 | * to write to readonly media either. */ | |
1651 | fdctrl_stop_transfer(fdctrl, | |
1652 | FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, | |
1653 | 0x00); | |
1654 | goto transfer_error; | |
1655 | } | |
1656 | ||
c8a35f1c HP |
1657 | k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, |
1658 | fdctrl->data_pos, len); | |
a9262f55 AF |
1659 | if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), BDRV_SECTOR_SIZE, |
1660 | fdctrl->fifo, 0) < 0) { | |
cced7a13 BS |
1661 | FLOPPY_DPRINTF("error writing sector %d\n", |
1662 | fd_sector(cur_drv)); | |
9fea808a | 1663 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1664 | goto transfer_error; |
890fa6be | 1665 | } |
4f431960 | 1666 | break; |
7ea004ed HP |
1667 | case FD_DIR_VERIFY: |
1668 | /* VERIFY commands */ | |
1669 | break; | |
4f431960 JM |
1670 | default: |
1671 | /* SCAN commands */ | |
baca51fa | 1672 | { |
4f431960 | 1673 | uint8_t tmpbuf[FD_SECTOR_LEN]; |
baca51fa | 1674 | int ret; |
c8a35f1c HP |
1675 | k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos, |
1676 | len); | |
baca51fa | 1677 | ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
8977f3c1 | 1678 | if (ret == 0) { |
77370520 | 1679 | status2 = FD_SR2_SEH; |
8977f3c1 FB |
1680 | goto end_transfer; |
1681 | } | |
baca51fa FB |
1682 | if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1683 | (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { | |
8977f3c1 FB |
1684 | status2 = 0x00; |
1685 | goto end_transfer; | |
1686 | } | |
1687 | } | |
4f431960 | 1688 | break; |
8977f3c1 | 1689 | } |
4f431960 JM |
1690 | fdctrl->data_pos += len; |
1691 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; | |
baca51fa | 1692 | if (rel_pos == 0) { |
8977f3c1 | 1693 | /* Seek to next sector */ |
746d6de7 BS |
1694 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) |
1695 | break; | |
8977f3c1 FB |
1696 | } |
1697 | } | |
4f431960 | 1698 | end_transfer: |
baca51fa FB |
1699 | len = fdctrl->data_pos - start_pos; |
1700 | FLOPPY_DPRINTF("end transfer %d %d %d\n", | |
4f431960 | 1701 | fdctrl->data_pos, len, fdctrl->data_len); |
baca51fa FB |
1702 | if (fdctrl->data_dir == FD_DIR_SCANE || |
1703 | fdctrl->data_dir == FD_DIR_SCANL || | |
1704 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1705 | status2 = FD_SR2_SEH; |
baca51fa | 1706 | fdctrl->data_len -= len; |
890fa6be | 1707 | fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
4f431960 | 1708 | transfer_error: |
8977f3c1 | 1709 | |
baca51fa | 1710 | return len; |
8977f3c1 FB |
1711 | } |
1712 | ||
8977f3c1 | 1713 | /* Data register : 0x05 */ |
5c02c033 | 1714 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl) |
8977f3c1 | 1715 | { |
5c02c033 | 1716 | FDrive *cur_drv; |
8977f3c1 | 1717 | uint32_t retval = 0; |
e9077462 | 1718 | uint32_t pos; |
8977f3c1 | 1719 | |
baca51fa | 1720 | cur_drv = get_cur_drv(fdctrl); |
b9b3d225 BS |
1721 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1722 | if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { | |
cced7a13 | 1723 | FLOPPY_DPRINTF("error: controller not ready for reading\n"); |
8977f3c1 FB |
1724 | return 0; |
1725 | } | |
f6c2d1d8 KW |
1726 | |
1727 | /* If data_len spans multiple sectors, the current position in the FIFO | |
1728 | * wraps around while fdctrl->data_pos is the real position in the whole | |
1729 | * request. */ | |
baca51fa | 1730 | pos = fdctrl->data_pos; |
e9077462 | 1731 | pos %= FD_SECTOR_LEN; |
f6c2d1d8 KW |
1732 | |
1733 | switch (fdctrl->phase) { | |
1734 | case FD_PHASE_EXECUTION: | |
1735 | assert(fdctrl->msr & FD_MSR_NONDMA); | |
8977f3c1 | 1736 | if (pos == 0) { |
746d6de7 BS |
1737 | if (fdctrl->data_pos != 0) |
1738 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { | |
1739 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
1740 | fd_sector(cur_drv)); | |
1741 | return 0; | |
1742 | } | |
a9262f55 AF |
1743 | if (blk_pread(cur_drv->blk, fd_offset(cur_drv), BDRV_SECTOR_SIZE, |
1744 | fdctrl->fifo, 0) | |
4be74634 | 1745 | < 0) { |
77370520 BS |
1746 | FLOPPY_DPRINTF("error getting sector %d\n", |
1747 | fd_sector(cur_drv)); | |
1748 | /* Sure, image size is too small... */ | |
1749 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
1750 | } | |
8977f3c1 | 1751 | } |
f6c2d1d8 KW |
1752 | |
1753 | if (++fdctrl->data_pos == fdctrl->data_len) { | |
6cc8a11c | 1754 | fdctrl->msr &= ~FD_MSR_RQM; |
c5139bd9 | 1755 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
f6c2d1d8 KW |
1756 | } |
1757 | break; | |
1758 | ||
1759 | case FD_PHASE_RESULT: | |
1760 | assert(!(fdctrl->msr & FD_MSR_NONDMA)); | |
1761 | if (++fdctrl->data_pos == fdctrl->data_len) { | |
6cc8a11c | 1762 | fdctrl->msr &= ~FD_MSR_RQM; |
07e415f2 | 1763 | fdctrl_to_command_phase(fdctrl); |
ed5fd2cc FB |
1764 | fdctrl_reset_irq(fdctrl); |
1765 | } | |
f6c2d1d8 KW |
1766 | break; |
1767 | ||
1768 | case FD_PHASE_COMMAND: | |
1769 | default: | |
1770 | abort(); | |
8977f3c1 | 1771 | } |
f6c2d1d8 KW |
1772 | |
1773 | retval = fdctrl->fifo[pos]; | |
8977f3c1 FB |
1774 | FLOPPY_DPRINTF("data register: 0x%02x\n", retval); |
1775 | ||
1776 | return retval; | |
1777 | } | |
1778 | ||
5c02c033 | 1779 | static void fdctrl_format_sector(FDCtrl *fdctrl) |
8977f3c1 | 1780 | { |
5c02c033 | 1781 | FDrive *cur_drv; |
baca51fa | 1782 | uint8_t kh, kt, ks; |
8977f3c1 | 1783 | |
cefec4f5 | 1784 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1785 | cur_drv = get_cur_drv(fdctrl); |
1786 | kt = fdctrl->fifo[6]; | |
1787 | kh = fdctrl->fifo[7]; | |
1788 | ks = fdctrl->fifo[8]; | |
1789 | FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", | |
cefec4f5 | 1790 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1791 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1792 | NUM_SIDES(cur_drv))); | |
9fea808a | 1793 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
baca51fa FB |
1794 | case 2: |
1795 | /* sect too big */ | |
9fea808a | 1796 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1797 | fdctrl->fifo[3] = kt; |
1798 | fdctrl->fifo[4] = kh; | |
1799 | fdctrl->fifo[5] = ks; | |
1800 | return; | |
1801 | case 3: | |
1802 | /* track too big */ | |
77370520 | 1803 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1804 | fdctrl->fifo[3] = kt; |
1805 | fdctrl->fifo[4] = kh; | |
1806 | fdctrl->fifo[5] = ks; | |
1807 | return; | |
1808 | case 4: | |
1809 | /* No seek enabled */ | |
9fea808a | 1810 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1811 | fdctrl->fifo[3] = kt; |
1812 | fdctrl->fifo[4] = kh; | |
1813 | fdctrl->fifo[5] = ks; | |
1814 | return; | |
1815 | case 1: | |
cd30b53d | 1816 | fdctrl->status0 |= FD_SR0_SEEK; |
baca51fa FB |
1817 | break; |
1818 | default: | |
1819 | break; | |
1820 | } | |
1821 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
4be74634 | 1822 | if (cur_drv->blk == NULL || |
a9262f55 AF |
1823 | blk_pwrite(cur_drv->blk, fd_offset(cur_drv), BDRV_SECTOR_SIZE, |
1824 | fdctrl->fifo, 0) < 0) { | |
cced7a13 | 1825 | FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); |
9fea808a | 1826 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1827 | } else { |
4f431960 JM |
1828 | if (cur_drv->sect == cur_drv->last_sect) { |
1829 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1830 | /* Last sector done */ | |
cd30b53d | 1831 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
4f431960 JM |
1832 | } else { |
1833 | /* More to do */ | |
1834 | fdctrl->data_pos = 0; | |
1835 | fdctrl->data_len = 4; | |
1836 | } | |
baca51fa FB |
1837 | } |
1838 | } | |
1839 | ||
5c02c033 | 1840 | static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1841 | { |
1842 | fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; | |
1843 | fdctrl->fifo[0] = fdctrl->lock << 4; | |
83a26013 | 1844 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1845 | } |
1846 | ||
5c02c033 | 1847 | static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) |
65cef780 | 1848 | { |
5c02c033 | 1849 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1850 | |
1851 | /* Drives position */ | |
1852 | fdctrl->fifo[0] = drv0(fdctrl)->track; | |
1853 | fdctrl->fifo[1] = drv1(fdctrl)->track; | |
78ae820c BS |
1854 | #if MAX_FD == 4 |
1855 | fdctrl->fifo[2] = drv2(fdctrl)->track; | |
1856 | fdctrl->fifo[3] = drv3(fdctrl)->track; | |
1857 | #else | |
65cef780 BS |
1858 | fdctrl->fifo[2] = 0; |
1859 | fdctrl->fifo[3] = 0; | |
78ae820c | 1860 | #endif |
65cef780 BS |
1861 | /* timers */ |
1862 | fdctrl->fifo[4] = fdctrl->timer0; | |
368df94d | 1863 | fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
65cef780 BS |
1864 | fdctrl->fifo[6] = cur_drv->last_sect; |
1865 | fdctrl->fifo[7] = (fdctrl->lock << 7) | | |
1866 | (cur_drv->perpendicular << 2); | |
1867 | fdctrl->fifo[8] = fdctrl->config; | |
1868 | fdctrl->fifo[9] = fdctrl->precomp_trk; | |
83a26013 | 1869 | fdctrl_to_result_phase(fdctrl, 10); |
65cef780 BS |
1870 | } |
1871 | ||
5c02c033 | 1872 | static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1873 | { |
1874 | /* Controller's version */ | |
1875 | fdctrl->fifo[0] = fdctrl->version; | |
83a26013 | 1876 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1877 | } |
1878 | ||
5c02c033 | 1879 | static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1880 | { |
1881 | fdctrl->fifo[0] = 0x41; /* Stepping 1 */ | |
83a26013 | 1882 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1883 | } |
1884 | ||
5c02c033 | 1885 | static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) |
65cef780 | 1886 | { |
5c02c033 | 1887 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1888 | |
1889 | /* Drives position */ | |
1890 | drv0(fdctrl)->track = fdctrl->fifo[3]; | |
1891 | drv1(fdctrl)->track = fdctrl->fifo[4]; | |
78ae820c BS |
1892 | #if MAX_FD == 4 |
1893 | drv2(fdctrl)->track = fdctrl->fifo[5]; | |
1894 | drv3(fdctrl)->track = fdctrl->fifo[6]; | |
1895 | #endif | |
65cef780 BS |
1896 | /* timers */ |
1897 | fdctrl->timer0 = fdctrl->fifo[7]; | |
1898 | fdctrl->timer1 = fdctrl->fifo[8]; | |
1899 | cur_drv->last_sect = fdctrl->fifo[9]; | |
1900 | fdctrl->lock = fdctrl->fifo[10] >> 7; | |
1901 | cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; | |
1902 | fdctrl->config = fdctrl->fifo[11]; | |
1903 | fdctrl->precomp_trk = fdctrl->fifo[12]; | |
1904 | fdctrl->pwrd = fdctrl->fifo[13]; | |
07e415f2 | 1905 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1906 | } |
1907 | ||
5c02c033 | 1908 | static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) |
65cef780 | 1909 | { |
5c02c033 | 1910 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1911 | |
1912 | fdctrl->fifo[0] = 0; | |
1913 | fdctrl->fifo[1] = 0; | |
1914 | /* Drives position */ | |
1915 | fdctrl->fifo[2] = drv0(fdctrl)->track; | |
1916 | fdctrl->fifo[3] = drv1(fdctrl)->track; | |
78ae820c BS |
1917 | #if MAX_FD == 4 |
1918 | fdctrl->fifo[4] = drv2(fdctrl)->track; | |
1919 | fdctrl->fifo[5] = drv3(fdctrl)->track; | |
1920 | #else | |
65cef780 BS |
1921 | fdctrl->fifo[4] = 0; |
1922 | fdctrl->fifo[5] = 0; | |
78ae820c | 1923 | #endif |
65cef780 BS |
1924 | /* timers */ |
1925 | fdctrl->fifo[6] = fdctrl->timer0; | |
1926 | fdctrl->fifo[7] = fdctrl->timer1; | |
1927 | fdctrl->fifo[8] = cur_drv->last_sect; | |
1928 | fdctrl->fifo[9] = (fdctrl->lock << 7) | | |
1929 | (cur_drv->perpendicular << 2); | |
1930 | fdctrl->fifo[10] = fdctrl->config; | |
1931 | fdctrl->fifo[11] = fdctrl->precomp_trk; | |
1932 | fdctrl->fifo[12] = fdctrl->pwrd; | |
1933 | fdctrl->fifo[13] = 0; | |
1934 | fdctrl->fifo[14] = 0; | |
83a26013 | 1935 | fdctrl_to_result_phase(fdctrl, 15); |
65cef780 BS |
1936 | } |
1937 | ||
5c02c033 | 1938 | static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) |
65cef780 | 1939 | { |
5c02c033 | 1940 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1941 | |
65cef780 | 1942 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
73bcb24d RS |
1943 | timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
1944 | (NANOSECONDS_PER_SECOND / 50)); | |
65cef780 BS |
1945 | } |
1946 | ||
5c02c033 | 1947 | static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) |
65cef780 | 1948 | { |
5c02c033 | 1949 | FDrive *cur_drv; |
65cef780 | 1950 | |
cefec4f5 | 1951 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1952 | cur_drv = get_cur_drv(fdctrl); |
1953 | fdctrl->data_state |= FD_STATE_FORMAT; | |
1954 | if (fdctrl->fifo[0] & 0x80) | |
1955 | fdctrl->data_state |= FD_STATE_MULTI; | |
1956 | else | |
1957 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
65cef780 BS |
1958 | cur_drv->bps = |
1959 | fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; | |
1960 | #if 0 | |
1961 | cur_drv->last_sect = | |
1962 | cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : | |
1963 | fdctrl->fifo[3] / 2; | |
1964 | #else | |
1965 | cur_drv->last_sect = fdctrl->fifo[3]; | |
1966 | #endif | |
1967 | /* TODO: implement format using DMA expected by the Bochs BIOS | |
1968 | * and Linux fdformat (read 3 bytes per sector via DMA and fill | |
1969 | * the sector with the specified fill byte | |
1970 | */ | |
1971 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1972 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
1973 | } | |
1974 | ||
5c02c033 | 1975 | static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1976 | { |
1977 | fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; | |
1978 | fdctrl->timer1 = fdctrl->fifo[2] >> 1; | |
368df94d BS |
1979 | if (fdctrl->fifo[2] & 1) |
1980 | fdctrl->dor &= ~FD_DOR_DMAEN; | |
1981 | else | |
1982 | fdctrl->dor |= FD_DOR_DMAEN; | |
65cef780 | 1983 | /* No result back */ |
07e415f2 | 1984 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1985 | } |
1986 | ||
5c02c033 | 1987 | static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) |
65cef780 | 1988 | { |
5c02c033 | 1989 | FDrive *cur_drv; |
65cef780 | 1990 | |
cefec4f5 | 1991 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1992 | cur_drv = get_cur_drv(fdctrl); |
1993 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; | |
1994 | /* 1 Byte status back */ | |
1995 | fdctrl->fifo[0] = (cur_drv->ro << 6) | | |
1996 | (cur_drv->track == 0 ? 0x10 : 0x00) | | |
1997 | (cur_drv->head << 2) | | |
cefec4f5 | 1998 | GET_CUR_DRV(fdctrl) | |
65cef780 | 1999 | 0x28; |
83a26013 | 2000 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
2001 | } |
2002 | ||
5c02c033 | 2003 | static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) |
65cef780 | 2004 | { |
5c02c033 | 2005 | FDrive *cur_drv; |
65cef780 | 2006 | |
cefec4f5 | 2007 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
2008 | cur_drv = get_cur_drv(fdctrl); |
2009 | fd_recalibrate(cur_drv); | |
07e415f2 | 2010 | fdctrl_to_command_phase(fdctrl); |
65cef780 | 2011 | /* Raise Interrupt */ |
d497d534 HP |
2012 | fdctrl->status0 |= FD_SR0_SEEK; |
2013 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
2014 | } |
2015 | ||
5c02c033 | 2016 | static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) |
65cef780 | 2017 | { |
5c02c033 | 2018 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 2019 | |
2fee0088 | 2020 | if (fdctrl->reset_sensei > 0) { |
f2d81b33 BS |
2021 | fdctrl->fifo[0] = |
2022 | FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; | |
2023 | fdctrl->reset_sensei--; | |
2fee0088 PH |
2024 | } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { |
2025 | fdctrl->fifo[0] = FD_SR0_INVCMD; | |
83a26013 | 2026 | fdctrl_to_result_phase(fdctrl, 1); |
2fee0088 | 2027 | return; |
f2d81b33 | 2028 | } else { |
f2d81b33 | 2029 | fdctrl->fifo[0] = |
2fee0088 PH |
2030 | (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) |
2031 | | GET_CUR_DRV(fdctrl); | |
f2d81b33 BS |
2032 | } |
2033 | ||
65cef780 | 2034 | fdctrl->fifo[1] = cur_drv->track; |
83a26013 | 2035 | fdctrl_to_result_phase(fdctrl, 2); |
65cef780 | 2036 | fdctrl_reset_irq(fdctrl); |
77370520 | 2037 | fdctrl->status0 = FD_SR0_RDYCHG; |
65cef780 BS |
2038 | } |
2039 | ||
5c02c033 | 2040 | static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) |
65cef780 | 2041 | { |
5c02c033 | 2042 | FDrive *cur_drv; |
65cef780 | 2043 | |
cefec4f5 | 2044 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 2045 | cur_drv = get_cur_drv(fdctrl); |
07e415f2 | 2046 | fdctrl_to_command_phase(fdctrl); |
b072a3c8 HP |
2047 | /* The seek command just sends step pulses to the drive and doesn't care if |
2048 | * there is a medium inserted of if it's banging the head against the drive. | |
2049 | */ | |
6be01b1e | 2050 | fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); |
b072a3c8 | 2051 | /* Raise Interrupt */ |
d497d534 HP |
2052 | fdctrl->status0 |= FD_SR0_SEEK; |
2053 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
2054 | } |
2055 | ||
5c02c033 | 2056 | static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) |
65cef780 | 2057 | { |
5c02c033 | 2058 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
2059 | |
2060 | if (fdctrl->fifo[1] & 0x80) | |
2061 | cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; | |
2062 | /* No result back */ | |
07e415f2 | 2063 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
2064 | } |
2065 | ||
5c02c033 | 2066 | static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) |
65cef780 BS |
2067 | { |
2068 | fdctrl->config = fdctrl->fifo[2]; | |
2069 | fdctrl->precomp_trk = fdctrl->fifo[3]; | |
2070 | /* No result back */ | |
07e415f2 | 2071 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
2072 | } |
2073 | ||
5c02c033 | 2074 | static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) |
65cef780 BS |
2075 | { |
2076 | fdctrl->pwrd = fdctrl->fifo[1]; | |
2077 | fdctrl->fifo[0] = fdctrl->fifo[1]; | |
83a26013 | 2078 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
2079 | } |
2080 | ||
5c02c033 | 2081 | static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) |
65cef780 BS |
2082 | { |
2083 | /* No result back */ | |
07e415f2 | 2084 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
2085 | } |
2086 | ||
5c02c033 | 2087 | static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) |
65cef780 | 2088 | { |
5c02c033 | 2089 | FDrive *cur_drv = get_cur_drv(fdctrl); |
e9077462 | 2090 | uint32_t pos; |
65cef780 | 2091 | |
e9077462 PM |
2092 | pos = fdctrl->data_pos - 1; |
2093 | pos %= FD_SECTOR_LEN; | |
2094 | if (fdctrl->fifo[pos] & 0x80) { | |
65cef780 | 2095 | /* Command parameters done */ |
e9077462 | 2096 | if (fdctrl->fifo[pos] & 0x40) { |
65cef780 BS |
2097 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
2098 | fdctrl->fifo[2] = 0; | |
2099 | fdctrl->fifo[3] = 0; | |
83a26013 | 2100 | fdctrl_to_result_phase(fdctrl, 4); |
65cef780 | 2101 | } else { |
07e415f2 | 2102 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
2103 | } |
2104 | } else if (fdctrl->data_len > 7) { | |
2105 | /* ERROR */ | |
2106 | fdctrl->fifo[0] = 0x80 | | |
cefec4f5 | 2107 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
83a26013 | 2108 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
2109 | } |
2110 | } | |
2111 | ||
6d013772 | 2112 | static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) |
65cef780 | 2113 | { |
5c02c033 | 2114 | FDrive *cur_drv; |
65cef780 | 2115 | |
cefec4f5 | 2116 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 2117 | cur_drv = get_cur_drv(fdctrl); |
65cef780 | 2118 | if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
6be01b1e PH |
2119 | fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, |
2120 | cur_drv->sect, 1); | |
65cef780 | 2121 | } else { |
6d013772 PH |
2122 | fd_seek(cur_drv, cur_drv->head, |
2123 | cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); | |
65cef780 | 2124 | } |
07e415f2 | 2125 | fdctrl_to_command_phase(fdctrl); |
77370520 | 2126 | /* Raise Interrupt */ |
d497d534 HP |
2127 | fdctrl->status0 |= FD_SR0_SEEK; |
2128 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
2129 | } |
2130 | ||
6d013772 | 2131 | static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) |
65cef780 | 2132 | { |
5c02c033 | 2133 | FDrive *cur_drv; |
65cef780 | 2134 | |
cefec4f5 | 2135 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 2136 | cur_drv = get_cur_drv(fdctrl); |
65cef780 | 2137 | if (fdctrl->fifo[2] > cur_drv->track) { |
6be01b1e | 2138 | fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); |
65cef780 | 2139 | } else { |
6d013772 PH |
2140 | fd_seek(cur_drv, cur_drv->head, |
2141 | cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); | |
65cef780 | 2142 | } |
07e415f2 | 2143 | fdctrl_to_command_phase(fdctrl); |
65cef780 | 2144 | /* Raise Interrupt */ |
d497d534 HP |
2145 | fdctrl->status0 |= FD_SR0_SEEK; |
2146 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
2147 | } |
2148 | ||
85d291a0 KW |
2149 | /* |
2150 | * Handlers for the execution phase of each command | |
2151 | */ | |
d275b33d | 2152 | typedef struct FDCtrlCommand { |
678803ab BS |
2153 | uint8_t value; |
2154 | uint8_t mask; | |
2155 | const char* name; | |
2156 | int parameters; | |
5c02c033 | 2157 | void (*handler)(FDCtrl *fdctrl, int direction); |
678803ab | 2158 | int direction; |
d275b33d KW |
2159 | } FDCtrlCommand; |
2160 | ||
2161 | static const FDCtrlCommand handlers[] = { | |
678803ab BS |
2162 | { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, |
2163 | { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, | |
2164 | { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, | |
2165 | { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, | |
2166 | { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, | |
2167 | { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, | |
2168 | { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, | |
2169 | { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ | |
2170 | { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ | |
2171 | { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, | |
2172 | { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, | |
7ea004ed | 2173 | { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, |
678803ab BS |
2174 | { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, |
2175 | { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, | |
2176 | { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, | |
2177 | { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, | |
2178 | { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, | |
2179 | { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, | |
2180 | { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, | |
2181 | { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, | |
2182 | { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, | |
2183 | { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, | |
2184 | { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, | |
2185 | { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, | |
2186 | { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, | |
2187 | { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, | |
2188 | { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, | |
2189 | { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, | |
2190 | { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, | |
2191 | { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, | |
2192 | { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ | |
2193 | { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ | |
2194 | }; | |
2195 | /* Associate command to an index in the 'handlers' array */ | |
2196 | static uint8_t command_to_handler[256]; | |
2197 | ||
d275b33d KW |
2198 | static const FDCtrlCommand *get_command(uint8_t cmd) |
2199 | { | |
2200 | int idx; | |
2201 | ||
2202 | idx = command_to_handler[cmd]; | |
2203 | FLOPPY_DPRINTF("%s command\n", handlers[idx].name); | |
2204 | return &handlers[idx]; | |
2205 | } | |
2206 | ||
5c02c033 | 2207 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) |
baca51fa | 2208 | { |
5c02c033 | 2209 | FDrive *cur_drv; |
d275b33d | 2210 | const FDCtrlCommand *cmd; |
e9077462 | 2211 | uint32_t pos; |
baca51fa | 2212 | |
8977f3c1 | 2213 | /* Reset mode */ |
1c346df2 | 2214 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 2215 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
2216 | return; |
2217 | } | |
b9b3d225 | 2218 | if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { |
cced7a13 | 2219 | FLOPPY_DPRINTF("error: controller not ready for writing\n"); |
8977f3c1 FB |
2220 | return; |
2221 | } | |
b9b3d225 | 2222 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
5b0a25e8 | 2223 | |
d275b33d KW |
2224 | FLOPPY_DPRINTF("%s: %02x\n", __func__, value); |
2225 | ||
2226 | /* If data_len spans multiple sectors, the current position in the FIFO | |
2227 | * wraps around while fdctrl->data_pos is the real position in the whole | |
2228 | * request. */ | |
2229 | pos = fdctrl->data_pos++; | |
2230 | pos %= FD_SECTOR_LEN; | |
2231 | fdctrl->fifo[pos] = value; | |
2232 | ||
6cc8a11c KW |
2233 | if (fdctrl->data_pos == fdctrl->data_len) { |
2234 | fdctrl->msr &= ~FD_MSR_RQM; | |
2235 | } | |
2236 | ||
5b0a25e8 KW |
2237 | switch (fdctrl->phase) { |
2238 | case FD_PHASE_EXECUTION: | |
2239 | /* For DMA requests, RQM should be cleared during execution phase, so | |
2240 | * we would have errored out above. */ | |
2241 | assert(fdctrl->msr & FD_MSR_NONDMA); | |
d275b33d | 2242 | |
8977f3c1 | 2243 | /* FIFO data write */ |
b3bc1540 | 2244 | if (pos == FD_SECTOR_LEN - 1 || |
baca51fa | 2245 | fdctrl->data_pos == fdctrl->data_len) { |
77370520 | 2246 | cur_drv = get_cur_drv(fdctrl); |
a9262f55 AF |
2247 | if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), BDRV_SECTOR_SIZE, |
2248 | fdctrl->fifo, 0) < 0) { | |
cced7a13 BS |
2249 | FLOPPY_DPRINTF("error writing sector %d\n", |
2250 | fd_sector(cur_drv)); | |
5b0a25e8 | 2251 | break; |
77370520 | 2252 | } |
746d6de7 BS |
2253 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { |
2254 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
2255 | fd_sector(cur_drv)); | |
5b0a25e8 | 2256 | break; |
746d6de7 | 2257 | } |
8977f3c1 | 2258 | } |
d275b33d KW |
2259 | |
2260 | /* Switch to result phase when done with the transfer */ | |
2261 | if (fdctrl->data_pos == fdctrl->data_len) { | |
c5139bd9 | 2262 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
d275b33d | 2263 | } |
5b0a25e8 | 2264 | break; |
678803ab | 2265 | |
5b0a25e8 KW |
2266 | case FD_PHASE_COMMAND: |
2267 | assert(!(fdctrl->msr & FD_MSR_NONDMA)); | |
d275b33d | 2268 | assert(fdctrl->data_pos < FD_SECTOR_LEN); |
5b0a25e8 | 2269 | |
d275b33d KW |
2270 | if (pos == 0) { |
2271 | /* The first byte specifies the command. Now we start reading | |
2272 | * as many parameters as this command requires. */ | |
2273 | cmd = get_command(value); | |
2274 | fdctrl->data_len = cmd->parameters + 1; | |
6cc8a11c KW |
2275 | if (cmd->parameters) { |
2276 | fdctrl->msr |= FD_MSR_RQM; | |
2277 | } | |
5b0a25e8 | 2278 | fdctrl->msr |= FD_MSR_CMDBUSY; |
8977f3c1 | 2279 | } |
65cef780 | 2280 | |
5b0a25e8 | 2281 | if (fdctrl->data_pos == fdctrl->data_len) { |
d275b33d | 2282 | /* We have all parameters now, execute the command */ |
5b0a25e8 | 2283 | fdctrl->phase = FD_PHASE_EXECUTION; |
d275b33d | 2284 | |
5b0a25e8 KW |
2285 | if (fdctrl->data_state & FD_STATE_FORMAT) { |
2286 | fdctrl_format_sector(fdctrl); | |
2287 | break; | |
2288 | } | |
2289 | ||
d275b33d KW |
2290 | cmd = get_command(fdctrl->fifo[0]); |
2291 | FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); | |
2292 | cmd->handler(fdctrl, cmd->direction); | |
5b0a25e8 KW |
2293 | } |
2294 | break; | |
2295 | ||
2296 | case FD_PHASE_RESULT: | |
2297 | default: | |
2298 | abort(); | |
8977f3c1 FB |
2299 | } |
2300 | } | |
ed5fd2cc FB |
2301 | |
2302 | static void fdctrl_result_timer(void *opaque) | |
2303 | { | |
5c02c033 BS |
2304 | FDCtrl *fdctrl = opaque; |
2305 | FDrive *cur_drv = get_cur_drv(fdctrl); | |
4f431960 | 2306 | |
b7ffa3b1 TS |
2307 | /* Pretend we are spinning. |
2308 | * This is needed for Coherent, which uses READ ID to check for | |
2309 | * sector interleaving. | |
2310 | */ | |
2311 | if (cur_drv->last_sect != 0) { | |
2312 | cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; | |
2313 | } | |
844f65d6 | 2314 | /* READ_ID can't automatically succeed! */ |
f5d33dd5 | 2315 | if ((fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { |
844f65d6 HP |
2316 | FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", |
2317 | fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); | |
2318 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); | |
2319 | } else { | |
2320 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
2321 | } | |
ed5fd2cc | 2322 | } |
678803ab BS |
2323 | |
2324 | /* Init functions */ | |
6172e067 | 2325 | |
5a5d2f3d | 2326 | void fdctrl_init_drives(FloppyBus *bus, DriveInfo **fds) |
6172e067 MA |
2327 | { |
2328 | DeviceState *dev; | |
2329 | int i; | |
2330 | ||
2331 | for (i = 0; i < MAX_FD; i++) { | |
2332 | if (fds[i]) { | |
2333 | dev = qdev_new("floppy"); | |
2334 | qdev_prop_set_uint32(dev, "unit", i); | |
2335 | qdev_prop_set_enum(dev, "drive-type", FLOPPY_DRIVE_TYPE_AUTO); | |
934df912 MA |
2336 | qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(fds[i]), |
2337 | &error_fatal); | |
6172e067 MA |
2338 | qdev_realize_and_unref(dev, &bus->bus, &error_fatal); |
2339 | } | |
2340 | } | |
2341 | } | |
2342 | ||
5a5d2f3d | 2343 | void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl, Error **errp) |
f64ab228 | 2344 | { |
12a71a02 | 2345 | int i, j; |
f2a9a6c2 | 2346 | FDrive *drive; |
12a71a02 | 2347 | static int command_tables_inited = 0; |
f64ab228 | 2348 | |
a73275dd JS |
2349 | if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) { |
2350 | error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'"); | |
07a978ef | 2351 | return; |
a73275dd JS |
2352 | } |
2353 | ||
12a71a02 BS |
2354 | /* Fill 'command_to_handler' lookup table */ |
2355 | if (!command_tables_inited) { | |
2356 | command_tables_inited = 1; | |
2357 | for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { | |
2358 | for (j = 0; j < sizeof(command_to_handler); j++) { | |
2359 | if ((j & handlers[i].mask) == handlers[i].value) { | |
2360 | command_to_handler[j] = i; | |
2361 | } | |
2362 | } | |
2363 | } | |
2364 | } | |
2365 | ||
2366 | FLOPPY_DPRINTF("init controller\n"); | |
2367 | fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); | |
6653d131 | 2368 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); |
d7a6c270 | 2369 | fdctrl->fifo_size = 512; |
bc72ad67 | 2370 | fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
a3ef7a61 | 2371 | fdctrl_result_timer, fdctrl); |
12a71a02 BS |
2372 | |
2373 | fdctrl->version = 0x90; /* Intel 82078 controller */ | |
2374 | fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ | |
d7a6c270 | 2375 | fdctrl->num_floppies = MAX_FD; |
12a71a02 | 2376 | |
51e6e90e | 2377 | floppy_bus_create(fdctrl, &fdctrl->bus, dev); |
f2a9a6c2 MA |
2378 | |
2379 | for (i = 0; i < MAX_FD; i++) { | |
2380 | drive = &fdctrl->drives[i]; | |
2381 | drive->fdctrl = fdctrl; | |
2382 | fd_init(drive); | |
2383 | fd_revalidate(drive); | |
2384 | } | |
f64ab228 BS |
2385 | } |
2386 | ||
83f7d43a | 2387 | static void fdc_register_types(void) |
f64ab228 | 2388 | { |
51e6e90e | 2389 | type_register_static(&floppy_bus_info); |
394ea2ca | 2390 | type_register_static(&floppy_drive_info); |
f64ab228 BS |
2391 | } |
2392 | ||
83f7d43a | 2393 | type_init(fdc_register_types) |